1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 * Microsemi Ocelot Switch driver 3 * Copyright (c) 2019 Microsemi Corporation 4 */ 5 6 #ifndef _OCELOT_VCAP_H_ 7 #define _OCELOT_VCAP_H_ 8 9 #include <soc/mscc/ocelot.h> 10 11 /* Cookie definitions for private VCAP filters installed by the driver. 12 * Must be unique per VCAP block. 13 */ 14 #define OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port) (port) 15 #define OCELOT_VCAP_IS1_TAG_8021Q_TXVLAN(ocelot, port) (port) 16 #define OCELOT_VCAP_IS1_TAG_8021Q_PTP_MMIO(ocelot) ((ocelot)->num_phys_ports) 17 #define OCELOT_VCAP_IS2_TAG_8021Q_TXVLAN(ocelot, port) (port) 18 #define OCELOT_VCAP_IS2_MRP_REDIRECT(ocelot, port) ((ocelot)->num_phys_ports + (port)) 19 #define OCELOT_VCAP_IS2_TAG_8021Q_PTP_MMIO(ocelot) ((ocelot)->num_phys_ports * 2) 20 #define OCELOT_VCAP_IS2_L2_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 1) 21 #define OCELOT_VCAP_IS2_IPV4_GEN_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 2) 22 #define OCELOT_VCAP_IS2_IPV4_EV_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 3) 23 #define OCELOT_VCAP_IS2_IPV6_GEN_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 4) 24 #define OCELOT_VCAP_IS2_IPV6_EV_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 5) 25 #define OCELOT_VCAP_IS2_MRP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 6) 26 27 /* ================================================================= 28 * VCAP Common 29 * ================================================================= 30 */ 31 32 enum { 33 VCAP_ES0, 34 VCAP_IS1, 35 VCAP_IS2, 36 __VCAP_COUNT, 37 }; 38 39 #define OCELOT_NUM_VCAP_BLOCKS __VCAP_COUNT 40 41 struct vcap_props { 42 u16 tg_width; /* Type-group width (in bits) */ 43 u16 sw_count; /* Sub word count */ 44 u16 entry_count; /* Entry count */ 45 u16 entry_words; /* Number of entry words */ 46 u16 entry_width; /* Entry width (in bits) */ 47 u16 action_count; /* Action count */ 48 u16 action_words; /* Number of action words */ 49 u16 action_width; /* Action width (in bits) */ 50 u16 action_type_width; /* Action type width (in bits) */ 51 struct { 52 u16 width; /* Action type width (in bits) */ 53 u16 count; /* Action type sub word count */ 54 } action_table[2]; 55 u16 counter_words; /* Number of counter words */ 56 u16 counter_width; /* Counter width (in bits) */ 57 58 enum ocelot_target target; 59 60 const struct vcap_field *keys; 61 const struct vcap_field *actions; 62 }; 63 64 /* VCAP Type-Group values */ 65 #define VCAP_TG_NONE 0 /* Entry is invalid */ 66 #define VCAP_TG_FULL 1 /* Full entry */ 67 #define VCAP_TG_HALF 2 /* Half entry */ 68 #define VCAP_TG_QUARTER 3 /* Quarter entry */ 69 70 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD(x) (((x) << 22) & GENMASK(24, 22)) 71 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_M GENMASK(24, 22) 72 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_X(x) (((x) & GENMASK(24, 22)) >> 22) 73 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21) 74 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20) 75 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19) 76 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR(x) (((x) << 3) & GENMASK(18, 3)) 77 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_M GENMASK(18, 3) 78 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_X(x) (((x) & GENMASK(18, 3)) >> 3) 79 #define VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT BIT(2) 80 #define VCAP_CORE_UPDATE_CTRL_CLEAR_CACHE BIT(1) 81 #define VCAP_CORE_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0) 82 83 #define VCAP_CORE_MV_CFG_MV_NUM_POS(x) (((x) << 16) & GENMASK(31, 16)) 84 #define VCAP_CORE_MV_CFG_MV_NUM_POS_M GENMASK(31, 16) 85 #define VCAP_CORE_MV_CFG_MV_NUM_POS_X(x) (((x) & GENMASK(31, 16)) >> 16) 86 #define VCAP_CORE_MV_CFG_MV_SIZE(x) ((x) & GENMASK(15, 0)) 87 #define VCAP_CORE_MV_CFG_MV_SIZE_M GENMASK(15, 0) 88 89 #define VCAP_CACHE_ENTRY_DAT_RSZ 0x4 90 91 #define VCAP_CACHE_MASK_DAT_RSZ 0x4 92 93 #define VCAP_CACHE_ACTION_DAT_RSZ 0x4 94 95 #define VCAP_CACHE_CNT_DAT_RSZ 0x4 96 97 #define VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) 98 99 #define TCAM_BIST_CTRL_TCAM_BIST BIT(1) 100 #define TCAM_BIST_CTRL_TCAM_INIT BIT(0) 101 102 #define TCAM_BIST_CFG_TCAM_BIST_SOE_ENA BIT(8) 103 #define TCAM_BIST_CFG_TCAM_HCG_DIS BIT(7) 104 #define TCAM_BIST_CFG_TCAM_CG_DIS BIT(6) 105 #define TCAM_BIST_CFG_TCAM_BIAS(x) ((x) & GENMASK(5, 0)) 106 #define TCAM_BIST_CFG_TCAM_BIAS_M GENMASK(5, 0) 107 108 #define TCAM_BIST_STAT_BIST_RT_ERR BIT(15) 109 #define TCAM_BIST_STAT_BIST_PENC_ERR BIT(14) 110 #define TCAM_BIST_STAT_BIST_COMP_ERR BIT(13) 111 #define TCAM_BIST_STAT_BIST_ADDR_ERR BIT(12) 112 #define TCAM_BIST_STAT_BIST_BL1E_ERR BIT(11) 113 #define TCAM_BIST_STAT_BIST_BL1_ERR BIT(10) 114 #define TCAM_BIST_STAT_BIST_BL0E_ERR BIT(9) 115 #define TCAM_BIST_STAT_BIST_BL0_ERR BIT(8) 116 #define TCAM_BIST_STAT_BIST_PH1_ERR BIT(7) 117 #define TCAM_BIST_STAT_BIST_PH0_ERR BIT(6) 118 #define TCAM_BIST_STAT_BIST_PV1_ERR BIT(5) 119 #define TCAM_BIST_STAT_BIST_PV0_ERR BIT(4) 120 #define TCAM_BIST_STAT_BIST_RUN BIT(3) 121 #define TCAM_BIST_STAT_BIST_ERR BIT(2) 122 #define TCAM_BIST_STAT_BIST_BUSY BIT(1) 123 #define TCAM_BIST_STAT_TCAM_RDY BIT(0) 124 125 /* ================================================================= 126 * VCAP IS2 127 * ================================================================= 128 */ 129 130 /* IS2 half key types */ 131 #define IS2_TYPE_ETYPE 0 132 #define IS2_TYPE_LLC 1 133 #define IS2_TYPE_SNAP 2 134 #define IS2_TYPE_ARP 3 135 #define IS2_TYPE_IP_UDP_TCP 4 136 #define IS2_TYPE_IP_OTHER 5 137 #define IS2_TYPE_IPV6 6 138 #define IS2_TYPE_OAM 7 139 #define IS2_TYPE_SMAC_SIP6 8 140 #define IS2_TYPE_ANY 100 /* Pseudo type */ 141 142 /* IS2 half key type mask for matching any IP */ 143 #define IS2_TYPE_MASK_IP_ANY 0xe 144 145 enum { 146 IS2_ACTION_TYPE_NORMAL, 147 IS2_ACTION_TYPE_SMAC_SIP, 148 IS2_ACTION_TYPE_MAX, 149 }; 150 151 /* IS2 MASK_MODE values */ 152 #define IS2_ACT_MASK_MODE_NONE 0 153 #define IS2_ACT_MASK_MODE_FILTER 1 154 #define IS2_ACT_MASK_MODE_POLICY 2 155 #define IS2_ACT_MASK_MODE_REDIR 3 156 157 /* IS2 REW_OP values */ 158 #define IS2_ACT_REW_OP_NONE 0 159 #define IS2_ACT_REW_OP_PTP_ONE 2 160 #define IS2_ACT_REW_OP_PTP_TWO 3 161 #define IS2_ACT_REW_OP_SPECIAL 8 162 #define IS2_ACT_REW_OP_PTP_ORG 9 163 #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_1 (IS2_ACT_REW_OP_PTP_ONE | (1 << 3)) 164 #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_2 (IS2_ACT_REW_OP_PTP_ONE | (2 << 3)) 165 #define IS2_ACT_REW_OP_PTP_ONE_ADD_DELAY (IS2_ACT_REW_OP_PTP_ONE | (1 << 5)) 166 #define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7) 167 168 #define VCAP_PORT_WIDTH 4 169 170 /* IS2 quarter key - SMAC_SIP4 */ 171 #define IS2_QKO_IGR_PORT 0 172 #define IS2_QKL_IGR_PORT VCAP_PORT_WIDTH 173 #define IS2_QKO_L2_SMAC (IS2_QKO_IGR_PORT + IS2_QKL_IGR_PORT) 174 #define IS2_QKL_L2_SMAC 48 175 #define IS2_QKO_L3_IP4_SIP (IS2_QKO_L2_SMAC + IS2_QKL_L2_SMAC) 176 #define IS2_QKL_L3_IP4_SIP 32 177 178 enum vcap_is2_half_key_field { 179 /* Common */ 180 VCAP_IS2_TYPE, 181 VCAP_IS2_HK_FIRST, 182 VCAP_IS2_HK_PAG, 183 VCAP_IS2_HK_RSV1, 184 VCAP_IS2_HK_IGR_PORT_MASK, 185 VCAP_IS2_HK_RSV2, 186 VCAP_IS2_HK_HOST_MATCH, 187 VCAP_IS2_HK_L2_MC, 188 VCAP_IS2_HK_L2_BC, 189 VCAP_IS2_HK_VLAN_TAGGED, 190 VCAP_IS2_HK_VID, 191 VCAP_IS2_HK_DEI, 192 VCAP_IS2_HK_PCP, 193 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 194 VCAP_IS2_HK_L2_DMAC, 195 VCAP_IS2_HK_L2_SMAC, 196 /* MAC_ETYPE (TYPE=000) */ 197 VCAP_IS2_HK_MAC_ETYPE_ETYPE, 198 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0, 199 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1, 200 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2, 201 /* MAC_LLC (TYPE=001) */ 202 VCAP_IS2_HK_MAC_LLC_DMAC, 203 VCAP_IS2_HK_MAC_LLC_SMAC, 204 VCAP_IS2_HK_MAC_LLC_L2_LLC, 205 /* MAC_SNAP (TYPE=010) */ 206 VCAP_IS2_HK_MAC_SNAP_SMAC, 207 VCAP_IS2_HK_MAC_SNAP_DMAC, 208 VCAP_IS2_HK_MAC_SNAP_L2_SNAP, 209 /* MAC_ARP (TYPE=011) */ 210 VCAP_IS2_HK_MAC_ARP_SMAC, 211 VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK, 212 VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK, 213 VCAP_IS2_HK_MAC_ARP_LEN_OK, 214 VCAP_IS2_HK_MAC_ARP_TARGET_MATCH, 215 VCAP_IS2_HK_MAC_ARP_SENDER_MATCH, 216 VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN, 217 VCAP_IS2_HK_MAC_ARP_OPCODE, 218 VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP, 219 VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP, 220 VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP, 221 /* IP4_TCP_UDP / IP4_OTHER common */ 222 VCAP_IS2_HK_IP4, 223 VCAP_IS2_HK_L3_FRAGMENT, 224 VCAP_IS2_HK_L3_FRAG_OFS_GT0, 225 VCAP_IS2_HK_L3_OPTIONS, 226 VCAP_IS2_HK_IP4_L3_TTL_GT0, 227 VCAP_IS2_HK_L3_TOS, 228 VCAP_IS2_HK_L3_IP4_DIP, 229 VCAP_IS2_HK_L3_IP4_SIP, 230 VCAP_IS2_HK_DIP_EQ_SIP, 231 /* IP4_TCP_UDP (TYPE=100) */ 232 VCAP_IS2_HK_TCP, 233 VCAP_IS2_HK_L4_SPORT, 234 VCAP_IS2_HK_L4_DPORT, 235 VCAP_IS2_HK_L4_RNG, 236 VCAP_IS2_HK_L4_SPORT_EQ_DPORT, 237 VCAP_IS2_HK_L4_SEQUENCE_EQ0, 238 VCAP_IS2_HK_L4_URG, 239 VCAP_IS2_HK_L4_ACK, 240 VCAP_IS2_HK_L4_PSH, 241 VCAP_IS2_HK_L4_RST, 242 VCAP_IS2_HK_L4_SYN, 243 VCAP_IS2_HK_L4_FIN, 244 VCAP_IS2_HK_L4_1588_DOM, 245 VCAP_IS2_HK_L4_1588_VER, 246 /* IP4_OTHER (TYPE=101) */ 247 VCAP_IS2_HK_IP4_L3_PROTO, 248 VCAP_IS2_HK_L3_PAYLOAD, 249 /* IP6_STD (TYPE=110) */ 250 VCAP_IS2_HK_IP6_L3_TTL_GT0, 251 VCAP_IS2_HK_IP6_L3_PROTO, 252 VCAP_IS2_HK_L3_IP6_SIP, 253 /* OAM (TYPE=111) */ 254 VCAP_IS2_HK_OAM_MEL_FLAGS, 255 VCAP_IS2_HK_OAM_VER, 256 VCAP_IS2_HK_OAM_OPCODE, 257 VCAP_IS2_HK_OAM_FLAGS, 258 VCAP_IS2_HK_OAM_MEPID, 259 VCAP_IS2_HK_OAM_CCM_CNTS_EQ0, 260 VCAP_IS2_HK_OAM_IS_Y1731, 261 }; 262 263 struct vcap_field { 264 int offset; 265 int length; 266 }; 267 268 enum vcap_is2_action_field { 269 VCAP_IS2_ACT_HIT_ME_ONCE, 270 VCAP_IS2_ACT_CPU_COPY_ENA, 271 VCAP_IS2_ACT_CPU_QU_NUM, 272 VCAP_IS2_ACT_MASK_MODE, 273 VCAP_IS2_ACT_MIRROR_ENA, 274 VCAP_IS2_ACT_LRN_DIS, 275 VCAP_IS2_ACT_POLICE_ENA, 276 VCAP_IS2_ACT_POLICE_IDX, 277 VCAP_IS2_ACT_POLICE_VCAP_ONLY, 278 VCAP_IS2_ACT_PORT_MASK, 279 VCAP_IS2_ACT_REW_OP, 280 VCAP_IS2_ACT_SMAC_REPLACE_ENA, 281 VCAP_IS2_ACT_RSV, 282 VCAP_IS2_ACT_ACL_ID, 283 VCAP_IS2_ACT_HIT_CNT, 284 }; 285 286 /* ================================================================= 287 * VCAP IS1 288 * ================================================================= 289 */ 290 291 /* IS1 half key types */ 292 #define IS1_TYPE_S1_NORMAL 0 293 #define IS1_TYPE_S1_5TUPLE_IP4 1 294 295 /* IS1 full key types */ 296 #define IS1_TYPE_S1_NORMAL_IP6 0 297 #define IS1_TYPE_S1_7TUPLE 1 298 #define IS2_TYPE_S1_5TUPLE_IP6 2 299 300 enum { 301 IS1_ACTION_TYPE_NORMAL, 302 IS1_ACTION_TYPE_MAX, 303 }; 304 305 enum vcap_is1_half_key_field { 306 VCAP_IS1_HK_TYPE, 307 VCAP_IS1_HK_LOOKUP, 308 VCAP_IS1_HK_IGR_PORT_MASK, 309 VCAP_IS1_HK_RSV, 310 VCAP_IS1_HK_OAM_Y1731, 311 VCAP_IS1_HK_L2_MC, 312 VCAP_IS1_HK_L2_BC, 313 VCAP_IS1_HK_IP_MC, 314 VCAP_IS1_HK_VLAN_TAGGED, 315 VCAP_IS1_HK_VLAN_DBL_TAGGED, 316 VCAP_IS1_HK_TPID, 317 VCAP_IS1_HK_VID, 318 VCAP_IS1_HK_DEI, 319 VCAP_IS1_HK_PCP, 320 /* Specific Fields for IS1 Half Key S1_NORMAL */ 321 VCAP_IS1_HK_L2_SMAC, 322 VCAP_IS1_HK_ETYPE_LEN, 323 VCAP_IS1_HK_ETYPE, 324 VCAP_IS1_HK_IP_SNAP, 325 VCAP_IS1_HK_IP4, 326 VCAP_IS1_HK_L3_FRAGMENT, 327 VCAP_IS1_HK_L3_FRAG_OFS_GT0, 328 VCAP_IS1_HK_L3_OPTIONS, 329 VCAP_IS1_HK_L3_DSCP, 330 VCAP_IS1_HK_L3_IP4_SIP, 331 VCAP_IS1_HK_TCP_UDP, 332 VCAP_IS1_HK_TCP, 333 VCAP_IS1_HK_L4_SPORT, 334 VCAP_IS1_HK_L4_RNG, 335 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 336 VCAP_IS1_HK_IP4_INNER_TPID, 337 VCAP_IS1_HK_IP4_INNER_VID, 338 VCAP_IS1_HK_IP4_INNER_DEI, 339 VCAP_IS1_HK_IP4_INNER_PCP, 340 VCAP_IS1_HK_IP4_IP4, 341 VCAP_IS1_HK_IP4_L3_FRAGMENT, 342 VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0, 343 VCAP_IS1_HK_IP4_L3_OPTIONS, 344 VCAP_IS1_HK_IP4_L3_DSCP, 345 VCAP_IS1_HK_IP4_L3_IP4_DIP, 346 VCAP_IS1_HK_IP4_L3_IP4_SIP, 347 VCAP_IS1_HK_IP4_L3_PROTO, 348 VCAP_IS1_HK_IP4_TCP_UDP, 349 VCAP_IS1_HK_IP4_TCP, 350 VCAP_IS1_HK_IP4_L4_RNG, 351 VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE, 352 }; 353 354 enum vcap_is1_action_field { 355 VCAP_IS1_ACT_DSCP_ENA, 356 VCAP_IS1_ACT_DSCP_VAL, 357 VCAP_IS1_ACT_QOS_ENA, 358 VCAP_IS1_ACT_QOS_VAL, 359 VCAP_IS1_ACT_DP_ENA, 360 VCAP_IS1_ACT_DP_VAL, 361 VCAP_IS1_ACT_PAG_OVERRIDE_MASK, 362 VCAP_IS1_ACT_PAG_VAL, 363 VCAP_IS1_ACT_RSV, 364 VCAP_IS1_ACT_VID_REPLACE_ENA, 365 VCAP_IS1_ACT_VID_ADD_VAL, 366 VCAP_IS1_ACT_FID_SEL, 367 VCAP_IS1_ACT_FID_VAL, 368 VCAP_IS1_ACT_PCP_DEI_ENA, 369 VCAP_IS1_ACT_PCP_VAL, 370 VCAP_IS1_ACT_DEI_VAL, 371 VCAP_IS1_ACT_VLAN_POP_CNT_ENA, 372 VCAP_IS1_ACT_VLAN_POP_CNT, 373 VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA, 374 VCAP_IS1_ACT_HIT_STICKY, 375 }; 376 377 /* ================================================================= 378 * VCAP ES0 379 * ================================================================= 380 */ 381 382 enum { 383 ES0_ACTION_TYPE_NORMAL, 384 ES0_ACTION_TYPE_MAX, 385 }; 386 387 enum vcap_es0_key_field { 388 VCAP_ES0_EGR_PORT, 389 VCAP_ES0_IGR_PORT, 390 VCAP_ES0_RSV, 391 VCAP_ES0_L2_MC, 392 VCAP_ES0_L2_BC, 393 VCAP_ES0_VID, 394 VCAP_ES0_DP, 395 VCAP_ES0_PCP, 396 }; 397 398 enum vcap_es0_action_field { 399 VCAP_ES0_ACT_PUSH_OUTER_TAG, 400 VCAP_ES0_ACT_PUSH_INNER_TAG, 401 VCAP_ES0_ACT_TAG_A_TPID_SEL, 402 VCAP_ES0_ACT_TAG_A_VID_SEL, 403 VCAP_ES0_ACT_TAG_A_PCP_SEL, 404 VCAP_ES0_ACT_TAG_A_DEI_SEL, 405 VCAP_ES0_ACT_TAG_B_TPID_SEL, 406 VCAP_ES0_ACT_TAG_B_VID_SEL, 407 VCAP_ES0_ACT_TAG_B_PCP_SEL, 408 VCAP_ES0_ACT_TAG_B_DEI_SEL, 409 VCAP_ES0_ACT_VID_A_VAL, 410 VCAP_ES0_ACT_PCP_A_VAL, 411 VCAP_ES0_ACT_DEI_A_VAL, 412 VCAP_ES0_ACT_VID_B_VAL, 413 VCAP_ES0_ACT_PCP_B_VAL, 414 VCAP_ES0_ACT_DEI_B_VAL, 415 VCAP_ES0_ACT_RSV, 416 VCAP_ES0_ACT_HIT_STICKY, 417 }; 418 419 struct ocelot_ipv4 { 420 u8 addr[4]; 421 }; 422 423 enum ocelot_vcap_bit { 424 OCELOT_VCAP_BIT_ANY, 425 OCELOT_VCAP_BIT_0, 426 OCELOT_VCAP_BIT_1 427 }; 428 429 struct ocelot_vcap_u8 { 430 u8 value[1]; 431 u8 mask[1]; 432 }; 433 434 struct ocelot_vcap_u16 { 435 u8 value[2]; 436 u8 mask[2]; 437 }; 438 439 struct ocelot_vcap_u24 { 440 u8 value[3]; 441 u8 mask[3]; 442 }; 443 444 struct ocelot_vcap_u32 { 445 u8 value[4]; 446 u8 mask[4]; 447 }; 448 449 struct ocelot_vcap_u40 { 450 u8 value[5]; 451 u8 mask[5]; 452 }; 453 454 struct ocelot_vcap_u48 { 455 u8 value[6]; 456 u8 mask[6]; 457 }; 458 459 struct ocelot_vcap_u64 { 460 u8 value[8]; 461 u8 mask[8]; 462 }; 463 464 struct ocelot_vcap_u128 { 465 u8 value[16]; 466 u8 mask[16]; 467 }; 468 469 struct ocelot_vcap_vid { 470 u16 value; 471 u16 mask; 472 }; 473 474 struct ocelot_vcap_ipv4 { 475 struct ocelot_ipv4 value; 476 struct ocelot_ipv4 mask; 477 }; 478 479 struct ocelot_vcap_udp_tcp { 480 u16 value; 481 u16 mask; 482 }; 483 484 struct ocelot_vcap_port { 485 u8 value; 486 u8 mask; 487 }; 488 489 enum ocelot_vcap_key_type { 490 OCELOT_VCAP_KEY_ANY, 491 OCELOT_VCAP_KEY_ETYPE, 492 OCELOT_VCAP_KEY_LLC, 493 OCELOT_VCAP_KEY_SNAP, 494 OCELOT_VCAP_KEY_ARP, 495 OCELOT_VCAP_KEY_IPV4, 496 OCELOT_VCAP_KEY_IPV6 497 }; 498 499 struct ocelot_vcap_key_vlan { 500 struct ocelot_vcap_vid vid; /* VLAN ID (12 bit) */ 501 struct ocelot_vcap_u8 pcp; /* PCP (3 bit) */ 502 enum ocelot_vcap_bit dei; /* DEI */ 503 enum ocelot_vcap_bit tagged; /* Tagged/untagged frame */ 504 }; 505 506 struct ocelot_vcap_key_etype { 507 struct ocelot_vcap_u48 dmac; 508 struct ocelot_vcap_u48 smac; 509 struct ocelot_vcap_u16 etype; 510 struct ocelot_vcap_u16 data; /* MAC data */ 511 }; 512 513 struct ocelot_vcap_key_llc { 514 struct ocelot_vcap_u48 dmac; 515 struct ocelot_vcap_u48 smac; 516 517 /* LLC header: DSAP at byte 0, SSAP at byte 1, Control at byte 2 */ 518 struct ocelot_vcap_u32 llc; 519 }; 520 521 struct ocelot_vcap_key_snap { 522 struct ocelot_vcap_u48 dmac; 523 struct ocelot_vcap_u48 smac; 524 525 /* SNAP header: Organization Code at byte 0, Type at byte 3 */ 526 struct ocelot_vcap_u40 snap; 527 }; 528 529 struct ocelot_vcap_key_arp { 530 struct ocelot_vcap_u48 smac; 531 enum ocelot_vcap_bit arp; /* Opcode ARP/RARP */ 532 enum ocelot_vcap_bit req; /* Opcode request/reply */ 533 enum ocelot_vcap_bit unknown; /* Opcode unknown */ 534 enum ocelot_vcap_bit smac_match; /* Sender MAC matches SMAC */ 535 enum ocelot_vcap_bit dmac_match; /* Target MAC matches DMAC */ 536 537 /**< Protocol addr. length 4, hardware length 6 */ 538 enum ocelot_vcap_bit length; 539 540 enum ocelot_vcap_bit ip; /* Protocol address type IP */ 541 enum ocelot_vcap_bit ethernet; /* Hardware address type Ethernet */ 542 struct ocelot_vcap_ipv4 sip; /* Sender IP address */ 543 struct ocelot_vcap_ipv4 dip; /* Target IP address */ 544 }; 545 546 struct ocelot_vcap_key_ipv4 { 547 enum ocelot_vcap_bit ttl; /* TTL zero */ 548 enum ocelot_vcap_bit fragment; /* Fragment */ 549 enum ocelot_vcap_bit options; /* Header options */ 550 struct ocelot_vcap_u8 ds; 551 struct ocelot_vcap_u8 proto; /* Protocol */ 552 struct ocelot_vcap_ipv4 sip; /* Source IP address */ 553 struct ocelot_vcap_ipv4 dip; /* Destination IP address */ 554 struct ocelot_vcap_u48 data; /* Not UDP/TCP: IP data */ 555 struct ocelot_vcap_udp_tcp sport; /* UDP/TCP: Source port */ 556 struct ocelot_vcap_udp_tcp dport; /* UDP/TCP: Destination port */ 557 enum ocelot_vcap_bit tcp_fin; 558 enum ocelot_vcap_bit tcp_syn; 559 enum ocelot_vcap_bit tcp_rst; 560 enum ocelot_vcap_bit tcp_psh; 561 enum ocelot_vcap_bit tcp_ack; 562 enum ocelot_vcap_bit tcp_urg; 563 enum ocelot_vcap_bit sip_eq_dip; /* SIP equals DIP */ 564 enum ocelot_vcap_bit sport_eq_dport; /* SPORT equals DPORT */ 565 enum ocelot_vcap_bit seq_zero; /* TCP sequence number is zero */ 566 }; 567 568 struct ocelot_vcap_key_ipv6 { 569 struct ocelot_vcap_u8 proto; /* IPv6 protocol */ 570 struct ocelot_vcap_u128 sip; /* IPv6 source (byte 0-7 ignored) */ 571 struct ocelot_vcap_u128 dip; /* IPv6 destination (byte 0-7 ignored) */ 572 enum ocelot_vcap_bit ttl; /* TTL zero */ 573 struct ocelot_vcap_u8 ds; 574 struct ocelot_vcap_u48 data; /* Not UDP/TCP: IP data */ 575 struct ocelot_vcap_udp_tcp sport; 576 struct ocelot_vcap_udp_tcp dport; 577 enum ocelot_vcap_bit tcp_fin; 578 enum ocelot_vcap_bit tcp_syn; 579 enum ocelot_vcap_bit tcp_rst; 580 enum ocelot_vcap_bit tcp_psh; 581 enum ocelot_vcap_bit tcp_ack; 582 enum ocelot_vcap_bit tcp_urg; 583 enum ocelot_vcap_bit sip_eq_dip; /* SIP equals DIP */ 584 enum ocelot_vcap_bit sport_eq_dport; /* SPORT equals DPORT */ 585 enum ocelot_vcap_bit seq_zero; /* TCP sequence number is zero */ 586 }; 587 588 enum ocelot_mask_mode { 589 OCELOT_MASK_MODE_NONE, 590 OCELOT_MASK_MODE_PERMIT_DENY, 591 OCELOT_MASK_MODE_POLICY, 592 OCELOT_MASK_MODE_REDIRECT, 593 }; 594 595 enum ocelot_es0_vid_sel { 596 OCELOT_ES0_VID_PLUS_CLASSIFIED_VID = 0, 597 OCELOT_ES0_VID = 1, 598 }; 599 600 enum ocelot_es0_pcp_sel { 601 OCELOT_CLASSIFIED_PCP = 0, 602 OCELOT_ES0_PCP = 1, 603 }; 604 605 enum ocelot_es0_tag { 606 OCELOT_NO_ES0_TAG, 607 OCELOT_ES0_TAG, 608 OCELOT_FORCE_PORT_TAG, 609 OCELOT_FORCE_UNTAG, 610 }; 611 612 enum ocelot_tag_tpid_sel { 613 OCELOT_TAG_TPID_SEL_8021Q, 614 OCELOT_TAG_TPID_SEL_8021AD, 615 }; 616 617 struct ocelot_vcap_action { 618 union { 619 /* VCAP ES0 */ 620 struct { 621 enum ocelot_es0_tag push_outer_tag; 622 enum ocelot_es0_tag push_inner_tag; 623 enum ocelot_tag_tpid_sel tag_a_tpid_sel; 624 int tag_a_vid_sel; 625 int tag_a_pcp_sel; 626 u16 vid_a_val; 627 u8 pcp_a_val; 628 u8 dei_a_val; 629 enum ocelot_tag_tpid_sel tag_b_tpid_sel; 630 int tag_b_vid_sel; 631 int tag_b_pcp_sel; 632 u16 vid_b_val; 633 u8 pcp_b_val; 634 u8 dei_b_val; 635 }; 636 637 /* VCAP IS1 */ 638 struct { 639 bool vid_replace_ena; 640 u16 vid; 641 bool vlan_pop_cnt_ena; 642 int vlan_pop_cnt; 643 bool pcp_dei_ena; 644 u8 pcp; 645 u8 dei; 646 bool qos_ena; 647 u8 qos_val; 648 u8 pag_override_mask; 649 u8 pag_val; 650 }; 651 652 /* VCAP IS2 */ 653 struct { 654 bool cpu_copy_ena; 655 u8 cpu_qu_num; 656 enum ocelot_mask_mode mask_mode; 657 unsigned long port_mask; 658 bool police_ena; 659 struct ocelot_policer pol; 660 u32 pol_ix; 661 }; 662 }; 663 }; 664 665 struct ocelot_vcap_stats { 666 u64 bytes; 667 u64 pkts; 668 u64 used; 669 }; 670 671 enum ocelot_vcap_filter_type { 672 OCELOT_VCAP_FILTER_DUMMY, 673 OCELOT_VCAP_FILTER_PAG, 674 OCELOT_VCAP_FILTER_OFFLOAD, 675 OCELOT_PSFP_FILTER_OFFLOAD, 676 }; 677 678 struct ocelot_vcap_id { 679 unsigned long cookie; 680 bool tc_offload; 681 }; 682 683 struct ocelot_vcap_filter { 684 struct list_head list; 685 struct list_head trap_list; 686 687 enum ocelot_vcap_filter_type type; 688 int block_id; 689 int goto_target; 690 int lookup; 691 u8 pag; 692 u16 prio; 693 struct ocelot_vcap_id id; 694 695 struct ocelot_vcap_action action; 696 struct ocelot_vcap_stats stats; 697 /* For VCAP IS1 and IS2 */ 698 bool take_ts; 699 unsigned long ingress_port_mask; 700 /* For VCAP ES0 */ 701 struct ocelot_vcap_port ingress_port; 702 struct ocelot_vcap_port egress_port; 703 704 enum ocelot_vcap_bit dmac_mc; 705 enum ocelot_vcap_bit dmac_bc; 706 struct ocelot_vcap_key_vlan vlan; 707 708 enum ocelot_vcap_key_type key_type; 709 union { 710 /* OCELOT_VCAP_KEY_ANY: No specific fields */ 711 struct ocelot_vcap_key_etype etype; 712 struct ocelot_vcap_key_llc llc; 713 struct ocelot_vcap_key_snap snap; 714 struct ocelot_vcap_key_arp arp; 715 struct ocelot_vcap_key_ipv4 ipv4; 716 struct ocelot_vcap_key_ipv6 ipv6; 717 } key; 718 }; 719 720 int ocelot_vcap_filter_add(struct ocelot *ocelot, 721 struct ocelot_vcap_filter *rule, 722 struct netlink_ext_ack *extack); 723 int ocelot_vcap_filter_del(struct ocelot *ocelot, 724 struct ocelot_vcap_filter *rule); 725 int ocelot_vcap_filter_replace(struct ocelot *ocelot, 726 struct ocelot_vcap_filter *filter); 727 struct ocelot_vcap_filter * 728 ocelot_vcap_block_find_filter_by_id(struct ocelot_vcap_block *block, 729 unsigned long cookie, bool tc_offload); 730 731 #endif /* _OCELOT_VCAP_H_ */ 732