1e0632940SVladimir Oltean /* SPDX-License-Identifier: (GPL-2.0 OR MIT) 2e0632940SVladimir Oltean * Microsemi Ocelot Switch driver 3e0632940SVladimir Oltean * Copyright (c) 2019 Microsemi Corporation 4e0632940SVladimir Oltean */ 5e0632940SVladimir Oltean 6e0632940SVladimir Oltean #ifndef _OCELOT_VCAP_H_ 7e0632940SVladimir Oltean #define _OCELOT_VCAP_H_ 8e0632940SVladimir Oltean 9c1c3993eSVladimir Oltean #include <soc/mscc/ocelot.h> 10c1c3993eSVladimir Oltean 11e0632940SVladimir Oltean /* ================================================================= 12e0632940SVladimir Oltean * VCAP Common 13e0632940SVladimir Oltean * ================================================================= 14e0632940SVladimir Oltean */ 15e0632940SVladimir Oltean 168551cdebSVladimir Oltean enum { 17e3aea296SVladimir Oltean VCAP_ES0, 18a61e365dSVladimir Oltean VCAP_IS1, 198551cdebSVladimir Oltean VCAP_IS2, 208551cdebSVladimir Oltean }; 218551cdebSVladimir Oltean 228551cdebSVladimir Oltean struct vcap_props { 238551cdebSVladimir Oltean u16 tg_width; /* Type-group width (in bits) */ 248551cdebSVladimir Oltean u16 sw_count; /* Sub word count */ 258551cdebSVladimir Oltean u16 entry_count; /* Entry count */ 268551cdebSVladimir Oltean u16 entry_words; /* Number of entry words */ 278551cdebSVladimir Oltean u16 entry_width; /* Entry width (in bits) */ 288551cdebSVladimir Oltean u16 action_count; /* Action count */ 298551cdebSVladimir Oltean u16 action_words; /* Number of action words */ 308551cdebSVladimir Oltean u16 action_width; /* Action width (in bits) */ 318551cdebSVladimir Oltean u16 action_type_width; /* Action type width (in bits) */ 328551cdebSVladimir Oltean struct { 338551cdebSVladimir Oltean u16 width; /* Action type width (in bits) */ 348551cdebSVladimir Oltean u16 count; /* Action type sub word count */ 358551cdebSVladimir Oltean } action_table[2]; 368551cdebSVladimir Oltean u16 counter_words; /* Number of counter words */ 378551cdebSVladimir Oltean u16 counter_width; /* Counter width (in bits) */ 38c1c3993eSVladimir Oltean 39c1c3993eSVladimir Oltean enum ocelot_target target; 40c1c3993eSVladimir Oltean 41c1c3993eSVladimir Oltean const struct vcap_field *keys; 42c1c3993eSVladimir Oltean const struct vcap_field *actions; 438551cdebSVladimir Oltean }; 448551cdebSVladimir Oltean 45e0632940SVladimir Oltean /* VCAP Type-Group values */ 46e0632940SVladimir Oltean #define VCAP_TG_NONE 0 /* Entry is invalid */ 47e0632940SVladimir Oltean #define VCAP_TG_FULL 1 /* Full entry */ 48e0632940SVladimir Oltean #define VCAP_TG_HALF 2 /* Half entry */ 49e0632940SVladimir Oltean #define VCAP_TG_QUARTER 3 /* Quarter entry */ 50e0632940SVladimir Oltean 51c1c3993eSVladimir Oltean #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD(x) (((x) << 22) & GENMASK(24, 22)) 52c1c3993eSVladimir Oltean #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_M GENMASK(24, 22) 53c1c3993eSVladimir Oltean #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_X(x) (((x) & GENMASK(24, 22)) >> 22) 54c1c3993eSVladimir Oltean #define VCAP_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21) 55c1c3993eSVladimir Oltean #define VCAP_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20) 56c1c3993eSVladimir Oltean #define VCAP_CORE_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19) 57c1c3993eSVladimir Oltean #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR(x) (((x) << 3) & GENMASK(18, 3)) 58c1c3993eSVladimir Oltean #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_M GENMASK(18, 3) 59c1c3993eSVladimir Oltean #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_X(x) (((x) & GENMASK(18, 3)) >> 3) 60c1c3993eSVladimir Oltean #define VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT BIT(2) 61c1c3993eSVladimir Oltean #define VCAP_CORE_UPDATE_CTRL_CLEAR_CACHE BIT(1) 62c1c3993eSVladimir Oltean #define VCAP_CORE_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0) 63c1c3993eSVladimir Oltean 64c1c3993eSVladimir Oltean #define VCAP_CORE_MV_CFG_MV_NUM_POS(x) (((x) << 16) & GENMASK(31, 16)) 65c1c3993eSVladimir Oltean #define VCAP_CORE_MV_CFG_MV_NUM_POS_M GENMASK(31, 16) 66c1c3993eSVladimir Oltean #define VCAP_CORE_MV_CFG_MV_NUM_POS_X(x) (((x) & GENMASK(31, 16)) >> 16) 67c1c3993eSVladimir Oltean #define VCAP_CORE_MV_CFG_MV_SIZE(x) ((x) & GENMASK(15, 0)) 68c1c3993eSVladimir Oltean #define VCAP_CORE_MV_CFG_MV_SIZE_M GENMASK(15, 0) 69c1c3993eSVladimir Oltean 70c1c3993eSVladimir Oltean #define VCAP_CACHE_ENTRY_DAT_RSZ 0x4 71c1c3993eSVladimir Oltean 72c1c3993eSVladimir Oltean #define VCAP_CACHE_MASK_DAT_RSZ 0x4 73c1c3993eSVladimir Oltean 74c1c3993eSVladimir Oltean #define VCAP_CACHE_ACTION_DAT_RSZ 0x4 75c1c3993eSVladimir Oltean 76c1c3993eSVladimir Oltean #define VCAP_CACHE_CNT_DAT_RSZ 0x4 77c1c3993eSVladimir Oltean 78c1c3993eSVladimir Oltean #define VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) 79c1c3993eSVladimir Oltean 80c1c3993eSVladimir Oltean #define TCAM_BIST_CTRL_TCAM_BIST BIT(1) 81c1c3993eSVladimir Oltean #define TCAM_BIST_CTRL_TCAM_INIT BIT(0) 82c1c3993eSVladimir Oltean 83c1c3993eSVladimir Oltean #define TCAM_BIST_CFG_TCAM_BIST_SOE_ENA BIT(8) 84c1c3993eSVladimir Oltean #define TCAM_BIST_CFG_TCAM_HCG_DIS BIT(7) 85c1c3993eSVladimir Oltean #define TCAM_BIST_CFG_TCAM_CG_DIS BIT(6) 86c1c3993eSVladimir Oltean #define TCAM_BIST_CFG_TCAM_BIAS(x) ((x) & GENMASK(5, 0)) 87c1c3993eSVladimir Oltean #define TCAM_BIST_CFG_TCAM_BIAS_M GENMASK(5, 0) 88c1c3993eSVladimir Oltean 89c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_BIST_RT_ERR BIT(15) 90c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_BIST_PENC_ERR BIT(14) 91c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_BIST_COMP_ERR BIT(13) 92c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_BIST_ADDR_ERR BIT(12) 93c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_BIST_BL1E_ERR BIT(11) 94c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_BIST_BL1_ERR BIT(10) 95c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_BIST_BL0E_ERR BIT(9) 96c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_BIST_BL0_ERR BIT(8) 97c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_BIST_PH1_ERR BIT(7) 98c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_BIST_PH0_ERR BIT(6) 99c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_BIST_PV1_ERR BIT(5) 100c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_BIST_PV0_ERR BIT(4) 101c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_BIST_RUN BIT(3) 102c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_BIST_ERR BIT(2) 103c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_BIST_BUSY BIT(1) 104c1c3993eSVladimir Oltean #define TCAM_BIST_STAT_TCAM_RDY BIT(0) 105c1c3993eSVladimir Oltean 106e0632940SVladimir Oltean /* ================================================================= 107e0632940SVladimir Oltean * VCAP IS2 108e0632940SVladimir Oltean * ================================================================= 109e0632940SVladimir Oltean */ 110e0632940SVladimir Oltean 111e0632940SVladimir Oltean /* IS2 half key types */ 112e0632940SVladimir Oltean #define IS2_TYPE_ETYPE 0 113e0632940SVladimir Oltean #define IS2_TYPE_LLC 1 114e0632940SVladimir Oltean #define IS2_TYPE_SNAP 2 115e0632940SVladimir Oltean #define IS2_TYPE_ARP 3 116e0632940SVladimir Oltean #define IS2_TYPE_IP_UDP_TCP 4 117e0632940SVladimir Oltean #define IS2_TYPE_IP_OTHER 5 118e0632940SVladimir Oltean #define IS2_TYPE_IPV6 6 119e0632940SVladimir Oltean #define IS2_TYPE_OAM 7 120e0632940SVladimir Oltean #define IS2_TYPE_SMAC_SIP6 8 121e0632940SVladimir Oltean #define IS2_TYPE_ANY 100 /* Pseudo type */ 122e0632940SVladimir Oltean 123e0632940SVladimir Oltean /* IS2 half key type mask for matching any IP */ 124e0632940SVladimir Oltean #define IS2_TYPE_MASK_IP_ANY 0xe 125e0632940SVladimir Oltean 1268551cdebSVladimir Oltean enum { 1278551cdebSVladimir Oltean IS2_ACTION_TYPE_NORMAL, 1288551cdebSVladimir Oltean IS2_ACTION_TYPE_SMAC_SIP, 1298551cdebSVladimir Oltean IS2_ACTION_TYPE_MAX, 1308551cdebSVladimir Oltean }; 131e0632940SVladimir Oltean 132e0632940SVladimir Oltean /* IS2 MASK_MODE values */ 133e0632940SVladimir Oltean #define IS2_ACT_MASK_MODE_NONE 0 134e0632940SVladimir Oltean #define IS2_ACT_MASK_MODE_FILTER 1 135e0632940SVladimir Oltean #define IS2_ACT_MASK_MODE_POLICY 2 136e0632940SVladimir Oltean #define IS2_ACT_MASK_MODE_REDIR 3 137e0632940SVladimir Oltean 138e0632940SVladimir Oltean /* IS2 REW_OP values */ 139e0632940SVladimir Oltean #define IS2_ACT_REW_OP_NONE 0 140e0632940SVladimir Oltean #define IS2_ACT_REW_OP_PTP_ONE 2 141e0632940SVladimir Oltean #define IS2_ACT_REW_OP_PTP_TWO 3 142e0632940SVladimir Oltean #define IS2_ACT_REW_OP_SPECIAL 8 143e0632940SVladimir Oltean #define IS2_ACT_REW_OP_PTP_ORG 9 144e0632940SVladimir Oltean #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_1 (IS2_ACT_REW_OP_PTP_ONE | (1 << 3)) 145e0632940SVladimir Oltean #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_2 (IS2_ACT_REW_OP_PTP_ONE | (2 << 3)) 146e0632940SVladimir Oltean #define IS2_ACT_REW_OP_PTP_ONE_ADD_DELAY (IS2_ACT_REW_OP_PTP_ONE | (1 << 5)) 147e0632940SVladimir Oltean #define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7) 148e0632940SVladimir Oltean 149e0632940SVladimir Oltean #define VCAP_PORT_WIDTH 4 150e0632940SVladimir Oltean 151e0632940SVladimir Oltean /* IS2 quarter key - SMAC_SIP4 */ 152e0632940SVladimir Oltean #define IS2_QKO_IGR_PORT 0 153e0632940SVladimir Oltean #define IS2_QKL_IGR_PORT VCAP_PORT_WIDTH 154e0632940SVladimir Oltean #define IS2_QKO_L2_SMAC (IS2_QKO_IGR_PORT + IS2_QKL_IGR_PORT) 155e0632940SVladimir Oltean #define IS2_QKL_L2_SMAC 48 156e0632940SVladimir Oltean #define IS2_QKO_L3_IP4_SIP (IS2_QKO_L2_SMAC + IS2_QKL_L2_SMAC) 157e0632940SVladimir Oltean #define IS2_QKL_L3_IP4_SIP 32 158e0632940SVladimir Oltean 159e0632940SVladimir Oltean enum vcap_is2_half_key_field { 160e0632940SVladimir Oltean /* Common */ 161e0632940SVladimir Oltean VCAP_IS2_TYPE, 162e0632940SVladimir Oltean VCAP_IS2_HK_FIRST, 163e0632940SVladimir Oltean VCAP_IS2_HK_PAG, 164e0632940SVladimir Oltean VCAP_IS2_HK_RSV1, 165e0632940SVladimir Oltean VCAP_IS2_HK_IGR_PORT_MASK, 166e0632940SVladimir Oltean VCAP_IS2_HK_RSV2, 167e0632940SVladimir Oltean VCAP_IS2_HK_HOST_MATCH, 168e0632940SVladimir Oltean VCAP_IS2_HK_L2_MC, 169e0632940SVladimir Oltean VCAP_IS2_HK_L2_BC, 170e0632940SVladimir Oltean VCAP_IS2_HK_VLAN_TAGGED, 171e0632940SVladimir Oltean VCAP_IS2_HK_VID, 172e0632940SVladimir Oltean VCAP_IS2_HK_DEI, 173e0632940SVladimir Oltean VCAP_IS2_HK_PCP, 174e0632940SVladimir Oltean /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 175e0632940SVladimir Oltean VCAP_IS2_HK_L2_DMAC, 176e0632940SVladimir Oltean VCAP_IS2_HK_L2_SMAC, 177e0632940SVladimir Oltean /* MAC_ETYPE (TYPE=000) */ 178e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ETYPE_ETYPE, 179e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0, 180e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1, 181e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2, 182e0632940SVladimir Oltean /* MAC_LLC (TYPE=001) */ 183e0632940SVladimir Oltean VCAP_IS2_HK_MAC_LLC_DMAC, 184e0632940SVladimir Oltean VCAP_IS2_HK_MAC_LLC_SMAC, 185e0632940SVladimir Oltean VCAP_IS2_HK_MAC_LLC_L2_LLC, 186e0632940SVladimir Oltean /* MAC_SNAP (TYPE=010) */ 187e0632940SVladimir Oltean VCAP_IS2_HK_MAC_SNAP_SMAC, 188e0632940SVladimir Oltean VCAP_IS2_HK_MAC_SNAP_DMAC, 189e0632940SVladimir Oltean VCAP_IS2_HK_MAC_SNAP_L2_SNAP, 190e0632940SVladimir Oltean /* MAC_ARP (TYPE=011) */ 191e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_SMAC, 192e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK, 193e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK, 194e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_LEN_OK, 195e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_TARGET_MATCH, 196e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_SENDER_MATCH, 197e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN, 198e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_OPCODE, 199e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP, 200e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP, 201e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP, 202e0632940SVladimir Oltean /* IP4_TCP_UDP / IP4_OTHER common */ 203e0632940SVladimir Oltean VCAP_IS2_HK_IP4, 204e0632940SVladimir Oltean VCAP_IS2_HK_L3_FRAGMENT, 205e0632940SVladimir Oltean VCAP_IS2_HK_L3_FRAG_OFS_GT0, 206e0632940SVladimir Oltean VCAP_IS2_HK_L3_OPTIONS, 207e0632940SVladimir Oltean VCAP_IS2_HK_IP4_L3_TTL_GT0, 208e0632940SVladimir Oltean VCAP_IS2_HK_L3_TOS, 209e0632940SVladimir Oltean VCAP_IS2_HK_L3_IP4_DIP, 210e0632940SVladimir Oltean VCAP_IS2_HK_L3_IP4_SIP, 211e0632940SVladimir Oltean VCAP_IS2_HK_DIP_EQ_SIP, 212e0632940SVladimir Oltean /* IP4_TCP_UDP (TYPE=100) */ 213e0632940SVladimir Oltean VCAP_IS2_HK_TCP, 214e0632940SVladimir Oltean VCAP_IS2_HK_L4_SPORT, 215e0632940SVladimir Oltean VCAP_IS2_HK_L4_DPORT, 216e0632940SVladimir Oltean VCAP_IS2_HK_L4_RNG, 217e0632940SVladimir Oltean VCAP_IS2_HK_L4_SPORT_EQ_DPORT, 218e0632940SVladimir Oltean VCAP_IS2_HK_L4_SEQUENCE_EQ0, 219e0632940SVladimir Oltean VCAP_IS2_HK_L4_URG, 220e0632940SVladimir Oltean VCAP_IS2_HK_L4_ACK, 221e0632940SVladimir Oltean VCAP_IS2_HK_L4_PSH, 222e0632940SVladimir Oltean VCAP_IS2_HK_L4_RST, 223e0632940SVladimir Oltean VCAP_IS2_HK_L4_SYN, 224e0632940SVladimir Oltean VCAP_IS2_HK_L4_FIN, 225e0632940SVladimir Oltean VCAP_IS2_HK_L4_1588_DOM, 226e0632940SVladimir Oltean VCAP_IS2_HK_L4_1588_VER, 227e0632940SVladimir Oltean /* IP4_OTHER (TYPE=101) */ 228e0632940SVladimir Oltean VCAP_IS2_HK_IP4_L3_PROTO, 229e0632940SVladimir Oltean VCAP_IS2_HK_L3_PAYLOAD, 230e0632940SVladimir Oltean /* IP6_STD (TYPE=110) */ 231e0632940SVladimir Oltean VCAP_IS2_HK_IP6_L3_TTL_GT0, 232e0632940SVladimir Oltean VCAP_IS2_HK_IP6_L3_PROTO, 233e0632940SVladimir Oltean VCAP_IS2_HK_L3_IP6_SIP, 234e0632940SVladimir Oltean /* OAM (TYPE=111) */ 235e0632940SVladimir Oltean VCAP_IS2_HK_OAM_MEL_FLAGS, 236e0632940SVladimir Oltean VCAP_IS2_HK_OAM_VER, 237e0632940SVladimir Oltean VCAP_IS2_HK_OAM_OPCODE, 238e0632940SVladimir Oltean VCAP_IS2_HK_OAM_FLAGS, 239e0632940SVladimir Oltean VCAP_IS2_HK_OAM_MEPID, 240e0632940SVladimir Oltean VCAP_IS2_HK_OAM_CCM_CNTS_EQ0, 241e0632940SVladimir Oltean VCAP_IS2_HK_OAM_IS_Y1731, 242e0632940SVladimir Oltean }; 243e0632940SVladimir Oltean 244e0632940SVladimir Oltean struct vcap_field { 245e0632940SVladimir Oltean int offset; 246e0632940SVladimir Oltean int length; 247e0632940SVladimir Oltean }; 248e0632940SVladimir Oltean 249e0632940SVladimir Oltean enum vcap_is2_action_field { 250e0632940SVladimir Oltean VCAP_IS2_ACT_HIT_ME_ONCE, 251e0632940SVladimir Oltean VCAP_IS2_ACT_CPU_COPY_ENA, 252e0632940SVladimir Oltean VCAP_IS2_ACT_CPU_QU_NUM, 253e0632940SVladimir Oltean VCAP_IS2_ACT_MASK_MODE, 254e0632940SVladimir Oltean VCAP_IS2_ACT_MIRROR_ENA, 255e0632940SVladimir Oltean VCAP_IS2_ACT_LRN_DIS, 256e0632940SVladimir Oltean VCAP_IS2_ACT_POLICE_ENA, 257e0632940SVladimir Oltean VCAP_IS2_ACT_POLICE_IDX, 258e0632940SVladimir Oltean VCAP_IS2_ACT_POLICE_VCAP_ONLY, 259e0632940SVladimir Oltean VCAP_IS2_ACT_PORT_MASK, 260e0632940SVladimir Oltean VCAP_IS2_ACT_REW_OP, 261e0632940SVladimir Oltean VCAP_IS2_ACT_SMAC_REPLACE_ENA, 262e0632940SVladimir Oltean VCAP_IS2_ACT_RSV, 263e0632940SVladimir Oltean VCAP_IS2_ACT_ACL_ID, 264e0632940SVladimir Oltean VCAP_IS2_ACT_HIT_CNT, 265e0632940SVladimir Oltean }; 266e0632940SVladimir Oltean 267a61e365dSVladimir Oltean /* ================================================================= 268a61e365dSVladimir Oltean * VCAP IS1 269a61e365dSVladimir Oltean * ================================================================= 270a61e365dSVladimir Oltean */ 271a61e365dSVladimir Oltean 272a61e365dSVladimir Oltean /* IS1 half key types */ 273a61e365dSVladimir Oltean #define IS1_TYPE_S1_NORMAL 0 274a61e365dSVladimir Oltean #define IS1_TYPE_S1_5TUPLE_IP4 1 275a61e365dSVladimir Oltean 276a61e365dSVladimir Oltean /* IS1 full key types */ 277a61e365dSVladimir Oltean #define IS1_TYPE_S1_NORMAL_IP6 0 278a61e365dSVladimir Oltean #define IS1_TYPE_S1_7TUPLE 1 279a61e365dSVladimir Oltean #define IS2_TYPE_S1_5TUPLE_IP6 2 280a61e365dSVladimir Oltean 281a61e365dSVladimir Oltean enum { 282a61e365dSVladimir Oltean IS1_ACTION_TYPE_NORMAL, 283a61e365dSVladimir Oltean IS1_ACTION_TYPE_MAX, 284a61e365dSVladimir Oltean }; 285a61e365dSVladimir Oltean 286a61e365dSVladimir Oltean enum vcap_is1_half_key_field { 287a61e365dSVladimir Oltean VCAP_IS1_HK_TYPE, 288a61e365dSVladimir Oltean VCAP_IS1_HK_LOOKUP, 289a61e365dSVladimir Oltean VCAP_IS1_HK_IGR_PORT_MASK, 290a61e365dSVladimir Oltean VCAP_IS1_HK_RSV, 291a61e365dSVladimir Oltean VCAP_IS1_HK_OAM_Y1731, 292a61e365dSVladimir Oltean VCAP_IS1_HK_L2_MC, 293a61e365dSVladimir Oltean VCAP_IS1_HK_L2_BC, 294a61e365dSVladimir Oltean VCAP_IS1_HK_IP_MC, 295a61e365dSVladimir Oltean VCAP_IS1_HK_VLAN_TAGGED, 296a61e365dSVladimir Oltean VCAP_IS1_HK_VLAN_DBL_TAGGED, 297a61e365dSVladimir Oltean VCAP_IS1_HK_TPID, 298a61e365dSVladimir Oltean VCAP_IS1_HK_VID, 299a61e365dSVladimir Oltean VCAP_IS1_HK_DEI, 300a61e365dSVladimir Oltean VCAP_IS1_HK_PCP, 301a61e365dSVladimir Oltean /* Specific Fields for IS1 Half Key S1_NORMAL */ 302a61e365dSVladimir Oltean VCAP_IS1_HK_L2_SMAC, 303a61e365dSVladimir Oltean VCAP_IS1_HK_ETYPE_LEN, 304a61e365dSVladimir Oltean VCAP_IS1_HK_ETYPE, 305a61e365dSVladimir Oltean VCAP_IS1_HK_IP_SNAP, 306a61e365dSVladimir Oltean VCAP_IS1_HK_IP4, 307a61e365dSVladimir Oltean VCAP_IS1_HK_L3_FRAGMENT, 308a61e365dSVladimir Oltean VCAP_IS1_HK_L3_FRAG_OFS_GT0, 309a61e365dSVladimir Oltean VCAP_IS1_HK_L3_OPTIONS, 310a61e365dSVladimir Oltean VCAP_IS1_HK_L3_DSCP, 311a61e365dSVladimir Oltean VCAP_IS1_HK_L3_IP4_SIP, 312a61e365dSVladimir Oltean VCAP_IS1_HK_TCP_UDP, 313a61e365dSVladimir Oltean VCAP_IS1_HK_TCP, 314a61e365dSVladimir Oltean VCAP_IS1_HK_L4_SPORT, 315a61e365dSVladimir Oltean VCAP_IS1_HK_L4_RNG, 316a61e365dSVladimir Oltean /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 317a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_INNER_TPID, 318a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_INNER_VID, 319a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_INNER_DEI, 320a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_INNER_PCP, 321a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_IP4, 322a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_L3_FRAGMENT, 323a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0, 324a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_L3_OPTIONS, 325a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_L3_DSCP, 326a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_L3_IP4_DIP, 327a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_L3_IP4_SIP, 328a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_L3_PROTO, 329a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_TCP_UDP, 330a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_TCP, 331a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_L4_RNG, 332a61e365dSVladimir Oltean VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE, 333a61e365dSVladimir Oltean }; 334a61e365dSVladimir Oltean 335a61e365dSVladimir Oltean enum vcap_is1_action_field { 336a61e365dSVladimir Oltean VCAP_IS1_ACT_DSCP_ENA, 337a61e365dSVladimir Oltean VCAP_IS1_ACT_DSCP_VAL, 338a61e365dSVladimir Oltean VCAP_IS1_ACT_QOS_ENA, 339a61e365dSVladimir Oltean VCAP_IS1_ACT_QOS_VAL, 340a61e365dSVladimir Oltean VCAP_IS1_ACT_DP_ENA, 341a61e365dSVladimir Oltean VCAP_IS1_ACT_DP_VAL, 342a61e365dSVladimir Oltean VCAP_IS1_ACT_PAG_OVERRIDE_MASK, 343a61e365dSVladimir Oltean VCAP_IS1_ACT_PAG_VAL, 344a61e365dSVladimir Oltean VCAP_IS1_ACT_RSV, 345a61e365dSVladimir Oltean VCAP_IS1_ACT_VID_REPLACE_ENA, 346a61e365dSVladimir Oltean VCAP_IS1_ACT_VID_ADD_VAL, 347a61e365dSVladimir Oltean VCAP_IS1_ACT_FID_SEL, 348a61e365dSVladimir Oltean VCAP_IS1_ACT_FID_VAL, 349a61e365dSVladimir Oltean VCAP_IS1_ACT_PCP_DEI_ENA, 350a61e365dSVladimir Oltean VCAP_IS1_ACT_PCP_VAL, 351a61e365dSVladimir Oltean VCAP_IS1_ACT_DEI_VAL, 352a61e365dSVladimir Oltean VCAP_IS1_ACT_VLAN_POP_CNT_ENA, 353a61e365dSVladimir Oltean VCAP_IS1_ACT_VLAN_POP_CNT, 354a61e365dSVladimir Oltean VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA, 355a61e365dSVladimir Oltean VCAP_IS1_ACT_HIT_STICKY, 356a61e365dSVladimir Oltean }; 357a61e365dSVladimir Oltean 358e3aea296SVladimir Oltean /* ================================================================= 359e3aea296SVladimir Oltean * VCAP ES0 360e3aea296SVladimir Oltean * ================================================================= 361e3aea296SVladimir Oltean */ 362e3aea296SVladimir Oltean 363e3aea296SVladimir Oltean enum { 364e3aea296SVladimir Oltean ES0_ACTION_TYPE_NORMAL, 365e3aea296SVladimir Oltean ES0_ACTION_TYPE_MAX, 366e3aea296SVladimir Oltean }; 367e3aea296SVladimir Oltean 368e3aea296SVladimir Oltean enum vcap_es0_key_field { 369e3aea296SVladimir Oltean VCAP_ES0_EGR_PORT, 370e3aea296SVladimir Oltean VCAP_ES0_IGR_PORT, 371e3aea296SVladimir Oltean VCAP_ES0_RSV, 372e3aea296SVladimir Oltean VCAP_ES0_L2_MC, 373e3aea296SVladimir Oltean VCAP_ES0_L2_BC, 374e3aea296SVladimir Oltean VCAP_ES0_VID, 375e3aea296SVladimir Oltean VCAP_ES0_DP, 376e3aea296SVladimir Oltean VCAP_ES0_PCP, 377e3aea296SVladimir Oltean }; 378e3aea296SVladimir Oltean 379e3aea296SVladimir Oltean enum vcap_es0_action_field { 380e3aea296SVladimir Oltean VCAP_ES0_ACT_PUSH_OUTER_TAG, 381e3aea296SVladimir Oltean VCAP_ES0_ACT_PUSH_INNER_TAG, 382e3aea296SVladimir Oltean VCAP_ES0_ACT_TAG_A_TPID_SEL, 383e3aea296SVladimir Oltean VCAP_ES0_ACT_TAG_A_VID_SEL, 384e3aea296SVladimir Oltean VCAP_ES0_ACT_TAG_A_PCP_SEL, 385e3aea296SVladimir Oltean VCAP_ES0_ACT_TAG_A_DEI_SEL, 386e3aea296SVladimir Oltean VCAP_ES0_ACT_TAG_B_TPID_SEL, 387e3aea296SVladimir Oltean VCAP_ES0_ACT_TAG_B_VID_SEL, 388e3aea296SVladimir Oltean VCAP_ES0_ACT_TAG_B_PCP_SEL, 389e3aea296SVladimir Oltean VCAP_ES0_ACT_TAG_B_DEI_SEL, 390e3aea296SVladimir Oltean VCAP_ES0_ACT_VID_A_VAL, 391e3aea296SVladimir Oltean VCAP_ES0_ACT_PCP_A_VAL, 392e3aea296SVladimir Oltean VCAP_ES0_ACT_DEI_A_VAL, 393e3aea296SVladimir Oltean VCAP_ES0_ACT_VID_B_VAL, 394e3aea296SVladimir Oltean VCAP_ES0_ACT_PCP_B_VAL, 395e3aea296SVladimir Oltean VCAP_ES0_ACT_DEI_B_VAL, 396e3aea296SVladimir Oltean VCAP_ES0_ACT_RSV, 397e3aea296SVladimir Oltean VCAP_ES0_ACT_HIT_STICKY, 398e3aea296SVladimir Oltean }; 399e3aea296SVladimir Oltean 400e0632940SVladimir Oltean #endif /* _OCELOT_VCAP_H_ */ 401