1e0632940SVladimir Oltean /* SPDX-License-Identifier: (GPL-2.0 OR MIT) 2e0632940SVladimir Oltean * Microsemi Ocelot Switch driver 3e0632940SVladimir Oltean * Copyright (c) 2019 Microsemi Corporation 4e0632940SVladimir Oltean */ 5e0632940SVladimir Oltean 6e0632940SVladimir Oltean #ifndef _OCELOT_VCAP_H_ 7e0632940SVladimir Oltean #define _OCELOT_VCAP_H_ 8e0632940SVladimir Oltean 9e0632940SVladimir Oltean /* ================================================================= 10e0632940SVladimir Oltean * VCAP Common 11e0632940SVladimir Oltean * ================================================================= 12e0632940SVladimir Oltean */ 13e0632940SVladimir Oltean 148551cdebSVladimir Oltean enum { 158551cdebSVladimir Oltean /* VCAP_IS1, */ 168551cdebSVladimir Oltean VCAP_IS2, 178551cdebSVladimir Oltean /* VCAP_ES0, */ 188551cdebSVladimir Oltean }; 198551cdebSVladimir Oltean 208551cdebSVladimir Oltean struct vcap_props { 218551cdebSVladimir Oltean u16 tg_width; /* Type-group width (in bits) */ 228551cdebSVladimir Oltean u16 sw_count; /* Sub word count */ 238551cdebSVladimir Oltean u16 entry_count; /* Entry count */ 248551cdebSVladimir Oltean u16 entry_words; /* Number of entry words */ 258551cdebSVladimir Oltean u16 entry_width; /* Entry width (in bits) */ 268551cdebSVladimir Oltean u16 action_count; /* Action count */ 278551cdebSVladimir Oltean u16 action_words; /* Number of action words */ 288551cdebSVladimir Oltean u16 action_width; /* Action width (in bits) */ 298551cdebSVladimir Oltean u16 action_type_width; /* Action type width (in bits) */ 308551cdebSVladimir Oltean struct { 318551cdebSVladimir Oltean u16 width; /* Action type width (in bits) */ 328551cdebSVladimir Oltean u16 count; /* Action type sub word count */ 338551cdebSVladimir Oltean } action_table[2]; 348551cdebSVladimir Oltean u16 counter_words; /* Number of counter words */ 358551cdebSVladimir Oltean u16 counter_width; /* Counter width (in bits) */ 368551cdebSVladimir Oltean }; 378551cdebSVladimir Oltean 38e0632940SVladimir Oltean /* VCAP Type-Group values */ 39e0632940SVladimir Oltean #define VCAP_TG_NONE 0 /* Entry is invalid */ 40e0632940SVladimir Oltean #define VCAP_TG_FULL 1 /* Full entry */ 41e0632940SVladimir Oltean #define VCAP_TG_HALF 2 /* Half entry */ 42e0632940SVladimir Oltean #define VCAP_TG_QUARTER 3 /* Quarter entry */ 43e0632940SVladimir Oltean 44e0632940SVladimir Oltean /* ================================================================= 45e0632940SVladimir Oltean * VCAP IS2 46e0632940SVladimir Oltean * ================================================================= 47e0632940SVladimir Oltean */ 48e0632940SVladimir Oltean 49e0632940SVladimir Oltean /* IS2 half key types */ 50e0632940SVladimir Oltean #define IS2_TYPE_ETYPE 0 51e0632940SVladimir Oltean #define IS2_TYPE_LLC 1 52e0632940SVladimir Oltean #define IS2_TYPE_SNAP 2 53e0632940SVladimir Oltean #define IS2_TYPE_ARP 3 54e0632940SVladimir Oltean #define IS2_TYPE_IP_UDP_TCP 4 55e0632940SVladimir Oltean #define IS2_TYPE_IP_OTHER 5 56e0632940SVladimir Oltean #define IS2_TYPE_IPV6 6 57e0632940SVladimir Oltean #define IS2_TYPE_OAM 7 58e0632940SVladimir Oltean #define IS2_TYPE_SMAC_SIP6 8 59e0632940SVladimir Oltean #define IS2_TYPE_ANY 100 /* Pseudo type */ 60e0632940SVladimir Oltean 61e0632940SVladimir Oltean /* IS2 half key type mask for matching any IP */ 62e0632940SVladimir Oltean #define IS2_TYPE_MASK_IP_ANY 0xe 63e0632940SVladimir Oltean 648551cdebSVladimir Oltean enum { 658551cdebSVladimir Oltean IS2_ACTION_TYPE_NORMAL, 668551cdebSVladimir Oltean IS2_ACTION_TYPE_SMAC_SIP, 678551cdebSVladimir Oltean IS2_ACTION_TYPE_MAX, 688551cdebSVladimir Oltean }; 69e0632940SVladimir Oltean 70e0632940SVladimir Oltean /* IS2 MASK_MODE values */ 71e0632940SVladimir Oltean #define IS2_ACT_MASK_MODE_NONE 0 72e0632940SVladimir Oltean #define IS2_ACT_MASK_MODE_FILTER 1 73e0632940SVladimir Oltean #define IS2_ACT_MASK_MODE_POLICY 2 74e0632940SVladimir Oltean #define IS2_ACT_MASK_MODE_REDIR 3 75e0632940SVladimir Oltean 76e0632940SVladimir Oltean /* IS2 REW_OP values */ 77e0632940SVladimir Oltean #define IS2_ACT_REW_OP_NONE 0 78e0632940SVladimir Oltean #define IS2_ACT_REW_OP_PTP_ONE 2 79e0632940SVladimir Oltean #define IS2_ACT_REW_OP_PTP_TWO 3 80e0632940SVladimir Oltean #define IS2_ACT_REW_OP_SPECIAL 8 81e0632940SVladimir Oltean #define IS2_ACT_REW_OP_PTP_ORG 9 82e0632940SVladimir Oltean #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_1 (IS2_ACT_REW_OP_PTP_ONE | (1 << 3)) 83e0632940SVladimir Oltean #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_2 (IS2_ACT_REW_OP_PTP_ONE | (2 << 3)) 84e0632940SVladimir Oltean #define IS2_ACT_REW_OP_PTP_ONE_ADD_DELAY (IS2_ACT_REW_OP_PTP_ONE | (1 << 5)) 85e0632940SVladimir Oltean #define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7) 86e0632940SVladimir Oltean 87e0632940SVladimir Oltean #define VCAP_PORT_WIDTH 4 88e0632940SVladimir Oltean 89e0632940SVladimir Oltean /* IS2 quarter key - SMAC_SIP4 */ 90e0632940SVladimir Oltean #define IS2_QKO_IGR_PORT 0 91e0632940SVladimir Oltean #define IS2_QKL_IGR_PORT VCAP_PORT_WIDTH 92e0632940SVladimir Oltean #define IS2_QKO_L2_SMAC (IS2_QKO_IGR_PORT + IS2_QKL_IGR_PORT) 93e0632940SVladimir Oltean #define IS2_QKL_L2_SMAC 48 94e0632940SVladimir Oltean #define IS2_QKO_L3_IP4_SIP (IS2_QKO_L2_SMAC + IS2_QKL_L2_SMAC) 95e0632940SVladimir Oltean #define IS2_QKL_L3_IP4_SIP 32 96e0632940SVladimir Oltean 97e0632940SVladimir Oltean enum vcap_is2_half_key_field { 98e0632940SVladimir Oltean /* Common */ 99e0632940SVladimir Oltean VCAP_IS2_TYPE, 100e0632940SVladimir Oltean VCAP_IS2_HK_FIRST, 101e0632940SVladimir Oltean VCAP_IS2_HK_PAG, 102e0632940SVladimir Oltean VCAP_IS2_HK_RSV1, 103e0632940SVladimir Oltean VCAP_IS2_HK_IGR_PORT_MASK, 104e0632940SVladimir Oltean VCAP_IS2_HK_RSV2, 105e0632940SVladimir Oltean VCAP_IS2_HK_HOST_MATCH, 106e0632940SVladimir Oltean VCAP_IS2_HK_L2_MC, 107e0632940SVladimir Oltean VCAP_IS2_HK_L2_BC, 108e0632940SVladimir Oltean VCAP_IS2_HK_VLAN_TAGGED, 109e0632940SVladimir Oltean VCAP_IS2_HK_VID, 110e0632940SVladimir Oltean VCAP_IS2_HK_DEI, 111e0632940SVladimir Oltean VCAP_IS2_HK_PCP, 112e0632940SVladimir Oltean /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 113e0632940SVladimir Oltean VCAP_IS2_HK_L2_DMAC, 114e0632940SVladimir Oltean VCAP_IS2_HK_L2_SMAC, 115e0632940SVladimir Oltean /* MAC_ETYPE (TYPE=000) */ 116e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ETYPE_ETYPE, 117e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0, 118e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1, 119e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2, 120e0632940SVladimir Oltean /* MAC_LLC (TYPE=001) */ 121e0632940SVladimir Oltean VCAP_IS2_HK_MAC_LLC_DMAC, 122e0632940SVladimir Oltean VCAP_IS2_HK_MAC_LLC_SMAC, 123e0632940SVladimir Oltean VCAP_IS2_HK_MAC_LLC_L2_LLC, 124e0632940SVladimir Oltean /* MAC_SNAP (TYPE=010) */ 125e0632940SVladimir Oltean VCAP_IS2_HK_MAC_SNAP_SMAC, 126e0632940SVladimir Oltean VCAP_IS2_HK_MAC_SNAP_DMAC, 127e0632940SVladimir Oltean VCAP_IS2_HK_MAC_SNAP_L2_SNAP, 128e0632940SVladimir Oltean /* MAC_ARP (TYPE=011) */ 129e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_SMAC, 130e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK, 131e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK, 132e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_LEN_OK, 133e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_TARGET_MATCH, 134e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_SENDER_MATCH, 135e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN, 136e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_OPCODE, 137e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP, 138e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP, 139e0632940SVladimir Oltean VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP, 140e0632940SVladimir Oltean /* IP4_TCP_UDP / IP4_OTHER common */ 141e0632940SVladimir Oltean VCAP_IS2_HK_IP4, 142e0632940SVladimir Oltean VCAP_IS2_HK_L3_FRAGMENT, 143e0632940SVladimir Oltean VCAP_IS2_HK_L3_FRAG_OFS_GT0, 144e0632940SVladimir Oltean VCAP_IS2_HK_L3_OPTIONS, 145e0632940SVladimir Oltean VCAP_IS2_HK_IP4_L3_TTL_GT0, 146e0632940SVladimir Oltean VCAP_IS2_HK_L3_TOS, 147e0632940SVladimir Oltean VCAP_IS2_HK_L3_IP4_DIP, 148e0632940SVladimir Oltean VCAP_IS2_HK_L3_IP4_SIP, 149e0632940SVladimir Oltean VCAP_IS2_HK_DIP_EQ_SIP, 150e0632940SVladimir Oltean /* IP4_TCP_UDP (TYPE=100) */ 151e0632940SVladimir Oltean VCAP_IS2_HK_TCP, 152e0632940SVladimir Oltean VCAP_IS2_HK_L4_SPORT, 153e0632940SVladimir Oltean VCAP_IS2_HK_L4_DPORT, 154e0632940SVladimir Oltean VCAP_IS2_HK_L4_RNG, 155e0632940SVladimir Oltean VCAP_IS2_HK_L4_SPORT_EQ_DPORT, 156e0632940SVladimir Oltean VCAP_IS2_HK_L4_SEQUENCE_EQ0, 157e0632940SVladimir Oltean VCAP_IS2_HK_L4_URG, 158e0632940SVladimir Oltean VCAP_IS2_HK_L4_ACK, 159e0632940SVladimir Oltean VCAP_IS2_HK_L4_PSH, 160e0632940SVladimir Oltean VCAP_IS2_HK_L4_RST, 161e0632940SVladimir Oltean VCAP_IS2_HK_L4_SYN, 162e0632940SVladimir Oltean VCAP_IS2_HK_L4_FIN, 163e0632940SVladimir Oltean VCAP_IS2_HK_L4_1588_DOM, 164e0632940SVladimir Oltean VCAP_IS2_HK_L4_1588_VER, 165e0632940SVladimir Oltean /* IP4_OTHER (TYPE=101) */ 166e0632940SVladimir Oltean VCAP_IS2_HK_IP4_L3_PROTO, 167e0632940SVladimir Oltean VCAP_IS2_HK_L3_PAYLOAD, 168e0632940SVladimir Oltean /* IP6_STD (TYPE=110) */ 169e0632940SVladimir Oltean VCAP_IS2_HK_IP6_L3_TTL_GT0, 170e0632940SVladimir Oltean VCAP_IS2_HK_IP6_L3_PROTO, 171e0632940SVladimir Oltean VCAP_IS2_HK_L3_IP6_SIP, 172e0632940SVladimir Oltean /* OAM (TYPE=111) */ 173e0632940SVladimir Oltean VCAP_IS2_HK_OAM_MEL_FLAGS, 174e0632940SVladimir Oltean VCAP_IS2_HK_OAM_VER, 175e0632940SVladimir Oltean VCAP_IS2_HK_OAM_OPCODE, 176e0632940SVladimir Oltean VCAP_IS2_HK_OAM_FLAGS, 177e0632940SVladimir Oltean VCAP_IS2_HK_OAM_MEPID, 178e0632940SVladimir Oltean VCAP_IS2_HK_OAM_CCM_CNTS_EQ0, 179e0632940SVladimir Oltean VCAP_IS2_HK_OAM_IS_Y1731, 180e0632940SVladimir Oltean }; 181e0632940SVladimir Oltean 182e0632940SVladimir Oltean struct vcap_field { 183e0632940SVladimir Oltean int offset; 184e0632940SVladimir Oltean int length; 185e0632940SVladimir Oltean }; 186e0632940SVladimir Oltean 187e0632940SVladimir Oltean enum vcap_is2_action_field { 188e0632940SVladimir Oltean VCAP_IS2_ACT_HIT_ME_ONCE, 189e0632940SVladimir Oltean VCAP_IS2_ACT_CPU_COPY_ENA, 190e0632940SVladimir Oltean VCAP_IS2_ACT_CPU_QU_NUM, 191e0632940SVladimir Oltean VCAP_IS2_ACT_MASK_MODE, 192e0632940SVladimir Oltean VCAP_IS2_ACT_MIRROR_ENA, 193e0632940SVladimir Oltean VCAP_IS2_ACT_LRN_DIS, 194e0632940SVladimir Oltean VCAP_IS2_ACT_POLICE_ENA, 195e0632940SVladimir Oltean VCAP_IS2_ACT_POLICE_IDX, 196e0632940SVladimir Oltean VCAP_IS2_ACT_POLICE_VCAP_ONLY, 197e0632940SVladimir Oltean VCAP_IS2_ACT_PORT_MASK, 198e0632940SVladimir Oltean VCAP_IS2_ACT_REW_OP, 199e0632940SVladimir Oltean VCAP_IS2_ACT_SMAC_REPLACE_ENA, 200e0632940SVladimir Oltean VCAP_IS2_ACT_RSV, 201e0632940SVladimir Oltean VCAP_IS2_ACT_ACL_ID, 202e0632940SVladimir Oltean VCAP_IS2_ACT_HIT_CNT, 203e0632940SVladimir Oltean }; 204e0632940SVladimir Oltean 205e0632940SVladimir Oltean #endif /* _OCELOT_VCAP_H_ */ 206