1a030dfe1SVladimir Oltean /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2a030dfe1SVladimir Oltean /* 3a030dfe1SVladimir Oltean * Microsemi Ocelot Switch driver 4a030dfe1SVladimir Oltean * 5a030dfe1SVladimir Oltean * Copyright (c) 2017 Microsemi Corporation 6a030dfe1SVladimir Oltean */ 7a030dfe1SVladimir Oltean 8a030dfe1SVladimir Oltean #ifndef _MSCC_OCELOT_SYS_H_ 9a030dfe1SVladimir Oltean #define _MSCC_OCELOT_SYS_H_ 10a030dfe1SVladimir Oltean 11a030dfe1SVladimir Oltean #define SYS_COUNT_RX_OCTETS_RSZ 0x4 12a030dfe1SVladimir Oltean 13a030dfe1SVladimir Oltean #define SYS_COUNT_TX_OCTETS_RSZ 0x4 14a030dfe1SVladimir Oltean 15a030dfe1SVladimir Oltean #define SYS_PORT_MODE_RSZ 0x4 16a030dfe1SVladimir Oltean 17a030dfe1SVladimir Oltean #define SYS_PORT_MODE_DATA_WO_TS(x) (((x) << 5) & GENMASK(6, 5)) 18a030dfe1SVladimir Oltean #define SYS_PORT_MODE_DATA_WO_TS_M GENMASK(6, 5) 19a030dfe1SVladimir Oltean #define SYS_PORT_MODE_DATA_WO_TS_X(x) (((x) & GENMASK(6, 5)) >> 5) 20a030dfe1SVladimir Oltean #define SYS_PORT_MODE_INCL_INJ_HDR(x) (((x) << 3) & GENMASK(4, 3)) 21a030dfe1SVladimir Oltean #define SYS_PORT_MODE_INCL_INJ_HDR_M GENMASK(4, 3) 22a030dfe1SVladimir Oltean #define SYS_PORT_MODE_INCL_INJ_HDR_X(x) (((x) & GENMASK(4, 3)) >> 3) 23a030dfe1SVladimir Oltean #define SYS_PORT_MODE_INCL_XTR_HDR(x) (((x) << 1) & GENMASK(2, 1)) 24a030dfe1SVladimir Oltean #define SYS_PORT_MODE_INCL_XTR_HDR_M GENMASK(2, 1) 25a030dfe1SVladimir Oltean #define SYS_PORT_MODE_INCL_XTR_HDR_X(x) (((x) & GENMASK(2, 1)) >> 1) 26a030dfe1SVladimir Oltean #define SYS_PORT_MODE_INJ_HDR_ERR BIT(0) 27a030dfe1SVladimir Oltean 28a030dfe1SVladimir Oltean #define SYS_FRONT_PORT_MODE_RSZ 0x4 29a030dfe1SVladimir Oltean 30a030dfe1SVladimir Oltean #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(0) 31a030dfe1SVladimir Oltean 32a030dfe1SVladimir Oltean #define SYS_FRM_AGING_AGE_TX_ENA BIT(20) 33a030dfe1SVladimir Oltean #define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0)) 34a030dfe1SVladimir Oltean #define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0) 35a030dfe1SVladimir Oltean 36a030dfe1SVladimir Oltean #define SYS_STAT_CFG_STAT_CLEAR_SHOT(x) (((x) << 10) & GENMASK(16, 10)) 37a030dfe1SVladimir Oltean #define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10) 38a030dfe1SVladimir Oltean #define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x) (((x) & GENMASK(16, 10)) >> 10) 39a030dfe1SVladimir Oltean #define SYS_STAT_CFG_STAT_VIEW(x) ((x) & GENMASK(9, 0)) 40a030dfe1SVladimir Oltean #define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0) 41a030dfe1SVladimir Oltean 42a030dfe1SVladimir Oltean #define SYS_SW_STATUS_RSZ 0x4 43a030dfe1SVladimir Oltean 44a030dfe1SVladimir Oltean #define SYS_SW_STATUS_PORT_RX_PAUSED BIT(0) 45a030dfe1SVladimir Oltean 46a030dfe1SVladimir Oltean #define SYS_MISC_CFG_PTP_RSRV_CLR BIT(1) 47a030dfe1SVladimir Oltean #define SYS_MISC_CFG_PTP_DIS_NEG_RO BIT(0) 48a030dfe1SVladimir Oltean 49a030dfe1SVladimir Oltean #define SYS_REW_MAC_HIGH_CFG_RSZ 0x4 50a030dfe1SVladimir Oltean 51a030dfe1SVladimir Oltean #define SYS_REW_MAC_LOW_CFG_RSZ 0x4 52a030dfe1SVladimir Oltean 53a030dfe1SVladimir Oltean #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x) (((x) << 6) & GENMASK(21, 6)) 54a030dfe1SVladimir Oltean #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6) 55a030dfe1SVladimir Oltean #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x) (((x) & GENMASK(21, 6)) >> 6) 56a030dfe1SVladimir Oltean #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET(x) ((x) & GENMASK(5, 0)) 57a030dfe1SVladimir Oltean #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET_M GENMASK(5, 0) 58a030dfe1SVladimir Oltean 59a030dfe1SVladimir Oltean #define SYS_PAUSE_CFG_RSZ 0x4 60a030dfe1SVladimir Oltean 61a030dfe1SVladimir Oltean #define SYS_PAUSE_CFG_PAUSE_START(x) (((x) << 10) & GENMASK(18, 10)) 62a030dfe1SVladimir Oltean #define SYS_PAUSE_CFG_PAUSE_START_M GENMASK(18, 10) 63a030dfe1SVladimir Oltean #define SYS_PAUSE_CFG_PAUSE_START_X(x) (((x) & GENMASK(18, 10)) >> 10) 64a030dfe1SVladimir Oltean #define SYS_PAUSE_CFG_PAUSE_STOP(x) (((x) << 1) & GENMASK(9, 1)) 65a030dfe1SVladimir Oltean #define SYS_PAUSE_CFG_PAUSE_STOP_M GENMASK(9, 1) 66a030dfe1SVladimir Oltean #define SYS_PAUSE_CFG_PAUSE_STOP_X(x) (((x) & GENMASK(9, 1)) >> 1) 67a030dfe1SVladimir Oltean #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0) 68a030dfe1SVladimir Oltean 69a030dfe1SVladimir Oltean #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START(x) (((x) << 9) & GENMASK(17, 9)) 70a030dfe1SVladimir Oltean #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_M GENMASK(17, 9) 71a030dfe1SVladimir Oltean #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_X(x) (((x) & GENMASK(17, 9)) >> 9) 72a030dfe1SVladimir Oltean #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP(x) ((x) & GENMASK(8, 0)) 73a030dfe1SVladimir Oltean #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP_M GENMASK(8, 0) 74a030dfe1SVladimir Oltean 75a030dfe1SVladimir Oltean #define SYS_ATOP_RSZ 0x4 76a030dfe1SVladimir Oltean 77a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_RSZ 0x4 78a030dfe1SVladimir Oltean 79a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_FC_LINK_SPEED(x) (((x) << 26) & GENMASK(27, 26)) 80a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_FC_LINK_SPEED_M GENMASK(27, 26) 81a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_FC_LINK_SPEED_X(x) (((x) & GENMASK(27, 26)) >> 26) 82a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_FC_LATENCY_CFG(x) (((x) << 20) & GENMASK(25, 20)) 83a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_M GENMASK(25, 20) 84a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_X(x) (((x) & GENMASK(25, 20)) >> 20) 85a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18) 86a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17) 87a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16) 88a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG(x) ((x) & GENMASK(15, 0)) 89a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_M GENMASK(15, 0) 90a030dfe1SVladimir Oltean 91a030dfe1SVladimir Oltean #define SYS_MMGT_RELCNT(x) (((x) << 16) & GENMASK(31, 16)) 92a030dfe1SVladimir Oltean #define SYS_MMGT_RELCNT_M GENMASK(31, 16) 93a030dfe1SVladimir Oltean #define SYS_MMGT_RELCNT_X(x) (((x) & GENMASK(31, 16)) >> 16) 94a030dfe1SVladimir Oltean #define SYS_MMGT_FREECNT(x) ((x) & GENMASK(15, 0)) 95a030dfe1SVladimir Oltean #define SYS_MMGT_FREECNT_M GENMASK(15, 0) 96a030dfe1SVladimir Oltean 97a030dfe1SVladimir Oltean #define SYS_MMGT_FAST_FREEVLD(x) (((x) << 4) & GENMASK(7, 4)) 98a030dfe1SVladimir Oltean #define SYS_MMGT_FAST_FREEVLD_M GENMASK(7, 4) 99a030dfe1SVladimir Oltean #define SYS_MMGT_FAST_FREEVLD_X(x) (((x) & GENMASK(7, 4)) >> 4) 100a030dfe1SVladimir Oltean #define SYS_MMGT_FAST_RELVLD(x) ((x) & GENMASK(3, 0)) 101a030dfe1SVladimir Oltean #define SYS_MMGT_FAST_RELVLD_M GENMASK(3, 0) 102a030dfe1SVladimir Oltean 103a030dfe1SVladimir Oltean #define SYS_EVENTS_DIF_RSZ 0x4 104a030dfe1SVladimir Oltean 105a030dfe1SVladimir Oltean #define SYS_EVENTS_DIF_EV_DRX(x) (((x) << 6) & GENMASK(8, 6)) 106a030dfe1SVladimir Oltean #define SYS_EVENTS_DIF_EV_DRX_M GENMASK(8, 6) 107a030dfe1SVladimir Oltean #define SYS_EVENTS_DIF_EV_DRX_X(x) (((x) & GENMASK(8, 6)) >> 6) 108a030dfe1SVladimir Oltean #define SYS_EVENTS_DIF_EV_DTX(x) ((x) & GENMASK(5, 0)) 109a030dfe1SVladimir Oltean #define SYS_EVENTS_DIF_EV_DTX_M GENMASK(5, 0) 110a030dfe1SVladimir Oltean 111a030dfe1SVladimir Oltean #define SYS_EVENTS_CORE_EV_FWR BIT(2) 112a030dfe1SVladimir Oltean #define SYS_EVENTS_CORE_EV_ANA(x) ((x) & GENMASK(1, 0)) 113a030dfe1SVladimir Oltean #define SYS_EVENTS_CORE_EV_ANA_M GENMASK(1, 0) 114a030dfe1SVladimir Oltean 115a030dfe1SVladimir Oltean #define SYS_CNT_GSZ 0x4 116a030dfe1SVladimir Oltean 117a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_TXSTAMP_OAM BIT(29) 118a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_OVFL BIT(28) 119a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_VLD BIT(27) 120a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_ID(x) (((x) << 21) & GENMASK(26, 21)) 121a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_ID_M GENMASK(26, 21) 122a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_ID_X(x) (((x) & GENMASK(26, 21)) >> 21) 123a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_TXPORT(x) (((x) << 16) & GENMASK(20, 16)) 124a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_TXPORT_M GENMASK(20, 16) 125a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_TXPORT_X(x) (((x) & GENMASK(20, 16)) >> 16) 126a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_SEQ_ID(x) ((x) & GENMASK(15, 0)) 127a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_SEQ_ID_M GENMASK(15, 0) 128a030dfe1SVladimir Oltean 129a030dfe1SVladimir Oltean #define SYS_PTP_TXSTAMP_PTP_TXSTAMP(x) ((x) & GENMASK(29, 0)) 130a030dfe1SVladimir Oltean #define SYS_PTP_TXSTAMP_PTP_TXSTAMP_M GENMASK(29, 0) 131a030dfe1SVladimir Oltean #define SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC BIT(31) 132a030dfe1SVladimir Oltean 133a030dfe1SVladimir Oltean #define SYS_PTP_NXT_PTP_NXT BIT(0) 134a030dfe1SVladimir Oltean 135a030dfe1SVladimir Oltean #define SYS_PTP_CFG_PTP_STAMP_WID(x) (((x) << 2) & GENMASK(7, 2)) 136a030dfe1SVladimir Oltean #define SYS_PTP_CFG_PTP_STAMP_WID_M GENMASK(7, 2) 137a030dfe1SVladimir Oltean #define SYS_PTP_CFG_PTP_STAMP_WID_X(x) (((x) & GENMASK(7, 2)) >> 2) 138a030dfe1SVladimir Oltean #define SYS_PTP_CFG_PTP_CF_ROLL_MODE(x) ((x) & GENMASK(1, 0)) 139a030dfe1SVladimir Oltean #define SYS_PTP_CFG_PTP_CF_ROLL_MODE_M GENMASK(1, 0) 140a030dfe1SVladimir Oltean 141a030dfe1SVladimir Oltean #define SYS_RAM_INIT_RAM_INIT BIT(1) 142a030dfe1SVladimir Oltean #define SYS_RAM_INIT_RAM_CFG_HOOK BIT(0) 143a030dfe1SVladimir Oltean 144a030dfe1SVladimir Oltean #endif 145