1a030dfe1SVladimir Oltean /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2a030dfe1SVladimir Oltean /* 3a030dfe1SVladimir Oltean * Microsemi Ocelot Switch driver 4a030dfe1SVladimir Oltean * 5a030dfe1SVladimir Oltean * Copyright (c) 2017 Microsemi Corporation 6a030dfe1SVladimir Oltean */ 7a030dfe1SVladimir Oltean 8a030dfe1SVladimir Oltean #ifndef _MSCC_OCELOT_SYS_H_ 9a030dfe1SVladimir Oltean #define _MSCC_OCELOT_SYS_H_ 10a030dfe1SVladimir Oltean 11a030dfe1SVladimir Oltean #define SYS_COUNT_RX_OCTETS_RSZ 0x4 12a030dfe1SVladimir Oltean 13a030dfe1SVladimir Oltean #define SYS_COUNT_TX_OCTETS_RSZ 0x4 14a030dfe1SVladimir Oltean 15a030dfe1SVladimir Oltean #define SYS_FRONT_PORT_MODE_RSZ 0x4 16a030dfe1SVladimir Oltean 17a030dfe1SVladimir Oltean #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(0) 18a030dfe1SVladimir Oltean 19a030dfe1SVladimir Oltean #define SYS_FRM_AGING_AGE_TX_ENA BIT(20) 20a030dfe1SVladimir Oltean #define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0)) 21a030dfe1SVladimir Oltean #define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0) 22a030dfe1SVladimir Oltean 23a030dfe1SVladimir Oltean #define SYS_STAT_CFG_STAT_CLEAR_SHOT(x) (((x) << 10) & GENMASK(16, 10)) 24a030dfe1SVladimir Oltean #define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10) 25a030dfe1SVladimir Oltean #define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x) (((x) & GENMASK(16, 10)) >> 10) 26a030dfe1SVladimir Oltean #define SYS_STAT_CFG_STAT_VIEW(x) ((x) & GENMASK(9, 0)) 27a030dfe1SVladimir Oltean #define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0) 28a030dfe1SVladimir Oltean 29a030dfe1SVladimir Oltean #define SYS_SW_STATUS_RSZ 0x4 30a030dfe1SVladimir Oltean 31a030dfe1SVladimir Oltean #define SYS_SW_STATUS_PORT_RX_PAUSED BIT(0) 32a030dfe1SVladimir Oltean 33a030dfe1SVladimir Oltean #define SYS_MISC_CFG_PTP_RSRV_CLR BIT(1) 34a030dfe1SVladimir Oltean #define SYS_MISC_CFG_PTP_DIS_NEG_RO BIT(0) 35a030dfe1SVladimir Oltean 36a030dfe1SVladimir Oltean #define SYS_REW_MAC_HIGH_CFG_RSZ 0x4 37a030dfe1SVladimir Oltean 38a030dfe1SVladimir Oltean #define SYS_REW_MAC_LOW_CFG_RSZ 0x4 39a030dfe1SVladimir Oltean 40a030dfe1SVladimir Oltean #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x) (((x) << 6) & GENMASK(21, 6)) 41a030dfe1SVladimir Oltean #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6) 42a030dfe1SVladimir Oltean #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x) (((x) & GENMASK(21, 6)) >> 6) 43a030dfe1SVladimir Oltean #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET(x) ((x) & GENMASK(5, 0)) 44a030dfe1SVladimir Oltean #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET_M GENMASK(5, 0) 45a030dfe1SVladimir Oltean 46a030dfe1SVladimir Oltean #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START(x) (((x) << 9) & GENMASK(17, 9)) 47a030dfe1SVladimir Oltean #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_M GENMASK(17, 9) 48a030dfe1SVladimir Oltean #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_X(x) (((x) & GENMASK(17, 9)) >> 9) 49a030dfe1SVladimir Oltean #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP(x) ((x) & GENMASK(8, 0)) 50a030dfe1SVladimir Oltean #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP_M GENMASK(8, 0) 51a030dfe1SVladimir Oltean 52a030dfe1SVladimir Oltean #define SYS_ATOP_RSZ 0x4 53a030dfe1SVladimir Oltean 54a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_RSZ 0x4 55a030dfe1SVladimir Oltean 56a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_FC_LINK_SPEED(x) (((x) << 26) & GENMASK(27, 26)) 57a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_FC_LINK_SPEED_M GENMASK(27, 26) 58a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_FC_LINK_SPEED_X(x) (((x) & GENMASK(27, 26)) >> 26) 59a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_FC_LATENCY_CFG(x) (((x) << 20) & GENMASK(25, 20)) 60a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_M GENMASK(25, 20) 61a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_X(x) (((x) & GENMASK(25, 20)) >> 20) 62a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18) 63a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17) 64a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16) 65a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG(x) ((x) & GENMASK(15, 0)) 66a030dfe1SVladimir Oltean #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_M GENMASK(15, 0) 67a030dfe1SVladimir Oltean 68a030dfe1SVladimir Oltean #define SYS_MMGT_RELCNT(x) (((x) << 16) & GENMASK(31, 16)) 69a030dfe1SVladimir Oltean #define SYS_MMGT_RELCNT_M GENMASK(31, 16) 70a030dfe1SVladimir Oltean #define SYS_MMGT_RELCNT_X(x) (((x) & GENMASK(31, 16)) >> 16) 71a030dfe1SVladimir Oltean #define SYS_MMGT_FREECNT(x) ((x) & GENMASK(15, 0)) 72a030dfe1SVladimir Oltean #define SYS_MMGT_FREECNT_M GENMASK(15, 0) 73a030dfe1SVladimir Oltean 74a030dfe1SVladimir Oltean #define SYS_MMGT_FAST_FREEVLD(x) (((x) << 4) & GENMASK(7, 4)) 75a030dfe1SVladimir Oltean #define SYS_MMGT_FAST_FREEVLD_M GENMASK(7, 4) 76a030dfe1SVladimir Oltean #define SYS_MMGT_FAST_FREEVLD_X(x) (((x) & GENMASK(7, 4)) >> 4) 77a030dfe1SVladimir Oltean #define SYS_MMGT_FAST_RELVLD(x) ((x) & GENMASK(3, 0)) 78a030dfe1SVladimir Oltean #define SYS_MMGT_FAST_RELVLD_M GENMASK(3, 0) 79a030dfe1SVladimir Oltean 80a030dfe1SVladimir Oltean #define SYS_EVENTS_DIF_RSZ 0x4 81a030dfe1SVladimir Oltean 82a030dfe1SVladimir Oltean #define SYS_EVENTS_DIF_EV_DRX(x) (((x) << 6) & GENMASK(8, 6)) 83a030dfe1SVladimir Oltean #define SYS_EVENTS_DIF_EV_DRX_M GENMASK(8, 6) 84a030dfe1SVladimir Oltean #define SYS_EVENTS_DIF_EV_DRX_X(x) (((x) & GENMASK(8, 6)) >> 6) 85a030dfe1SVladimir Oltean #define SYS_EVENTS_DIF_EV_DTX(x) ((x) & GENMASK(5, 0)) 86a030dfe1SVladimir Oltean #define SYS_EVENTS_DIF_EV_DTX_M GENMASK(5, 0) 87a030dfe1SVladimir Oltean 88a030dfe1SVladimir Oltean #define SYS_EVENTS_CORE_EV_FWR BIT(2) 89a030dfe1SVladimir Oltean #define SYS_EVENTS_CORE_EV_ANA(x) ((x) & GENMASK(1, 0)) 90a030dfe1SVladimir Oltean #define SYS_EVENTS_CORE_EV_ANA_M GENMASK(1, 0) 91a030dfe1SVladimir Oltean 92a030dfe1SVladimir Oltean #define SYS_CNT_GSZ 0x4 93a030dfe1SVladimir Oltean 94a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_TXSTAMP_OAM BIT(29) 95a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_OVFL BIT(28) 96a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_VLD BIT(27) 97a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_ID(x) (((x) << 21) & GENMASK(26, 21)) 98a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_ID_M GENMASK(26, 21) 99a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_ID_X(x) (((x) & GENMASK(26, 21)) >> 21) 100a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_TXPORT(x) (((x) << 16) & GENMASK(20, 16)) 101a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_TXPORT_M GENMASK(20, 16) 102a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_TXPORT_X(x) (((x) & GENMASK(20, 16)) >> 16) 103a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_SEQ_ID(x) ((x) & GENMASK(15, 0)) 104a030dfe1SVladimir Oltean #define SYS_PTP_STATUS_PTP_MESS_SEQ_ID_M GENMASK(15, 0) 105a030dfe1SVladimir Oltean 106a030dfe1SVladimir Oltean #define SYS_PTP_TXSTAMP_PTP_TXSTAMP(x) ((x) & GENMASK(29, 0)) 107a030dfe1SVladimir Oltean #define SYS_PTP_TXSTAMP_PTP_TXSTAMP_M GENMASK(29, 0) 108a030dfe1SVladimir Oltean #define SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC BIT(31) 109a030dfe1SVladimir Oltean 110a030dfe1SVladimir Oltean #define SYS_PTP_NXT_PTP_NXT BIT(0) 111a030dfe1SVladimir Oltean 112a030dfe1SVladimir Oltean #define SYS_PTP_CFG_PTP_STAMP_WID(x) (((x) << 2) & GENMASK(7, 2)) 113a030dfe1SVladimir Oltean #define SYS_PTP_CFG_PTP_STAMP_WID_M GENMASK(7, 2) 114a030dfe1SVladimir Oltean #define SYS_PTP_CFG_PTP_STAMP_WID_X(x) (((x) & GENMASK(7, 2)) >> 2) 115a030dfe1SVladimir Oltean #define SYS_PTP_CFG_PTP_CF_ROLL_MODE(x) ((x) & GENMASK(1, 0)) 116a030dfe1SVladimir Oltean #define SYS_PTP_CFG_PTP_CF_ROLL_MODE_M GENMASK(1, 0) 117a030dfe1SVladimir Oltean 118a030dfe1SVladimir Oltean #define SYS_RAM_INIT_RAM_INIT BIT(1) 119a030dfe1SVladimir Oltean #define SYS_RAM_INIT_RAM_CFG_HOOK BIT(0) 120a030dfe1SVladimir Oltean 121a030dfe1SVladimir Oltean #endif 122