1964ee5c8SVladimir Oltean /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2964ee5c8SVladimir Oltean /* 3964ee5c8SVladimir Oltean * Microsemi Ocelot Switch driver 4964ee5c8SVladimir Oltean * 5964ee5c8SVladimir Oltean * Copyright (c) 2017 Microsemi Corporation 6964ee5c8SVladimir Oltean */ 7964ee5c8SVladimir Oltean 8964ee5c8SVladimir Oltean #ifndef _MSCC_OCELOT_QSYS_H_ 9964ee5c8SVladimir Oltean #define _MSCC_OCELOT_QSYS_H_ 10964ee5c8SVladimir Oltean 11964ee5c8SVladimir Oltean #define QSYS_PORT_MODE_RSZ 0x4 12964ee5c8SVladimir Oltean 13964ee5c8SVladimir Oltean #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1) 14964ee5c8SVladimir Oltean #define QSYS_PORT_MODE_DEQUEUE_LATE BIT(0) 15964ee5c8SVladimir Oltean 16964ee5c8SVladimir Oltean #define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE BIT(5) 17964ee5c8SVladimir Oltean #define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4) 18964ee5c8SVladimir Oltean #define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3) 19964ee5c8SVladimir Oltean #define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE BIT(2) 20964ee5c8SVladimir Oltean #define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE BIT(1) 21964ee5c8SVladimir Oltean #define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS BIT(0) 22964ee5c8SVladimir Oltean 23964ee5c8SVladimir Oltean #define QSYS_EEE_CFG_RSZ 0x4 24964ee5c8SVladimir Oltean 25964ee5c8SVladimir Oltean #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8)) 26964ee5c8SVladimir Oltean #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8) 27964ee5c8SVladimir Oltean #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8) 28964ee5c8SVladimir Oltean #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0)) 29964ee5c8SVladimir Oltean #define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0) 30964ee5c8SVladimir Oltean 31964ee5c8SVladimir Oltean #define QSYS_SW_STATUS_RSZ 0x4 32964ee5c8SVladimir Oltean 33964ee5c8SVladimir Oltean #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8)) 34964ee5c8SVladimir Oltean #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8) 35964ee5c8SVladimir Oltean #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8) 36964ee5c8SVladimir Oltean #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0)) 37964ee5c8SVladimir Oltean #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0) 38964ee5c8SVladimir Oltean 39964ee5c8SVladimir Oltean #define QSYS_QMAP_GSZ 0x4 40964ee5c8SVladimir Oltean 41964ee5c8SVladimir Oltean #define QSYS_QMAP_SE_BASE(x) (((x) << 5) & GENMASK(12, 5)) 42964ee5c8SVladimir Oltean #define QSYS_QMAP_SE_BASE_M GENMASK(12, 5) 43964ee5c8SVladimir Oltean #define QSYS_QMAP_SE_BASE_X(x) (((x) & GENMASK(12, 5)) >> 5) 44964ee5c8SVladimir Oltean #define QSYS_QMAP_SE_IDX_SEL(x) (((x) << 2) & GENMASK(4, 2)) 45964ee5c8SVladimir Oltean #define QSYS_QMAP_SE_IDX_SEL_M GENMASK(4, 2) 46964ee5c8SVladimir Oltean #define QSYS_QMAP_SE_IDX_SEL_X(x) (((x) & GENMASK(4, 2)) >> 2) 47964ee5c8SVladimir Oltean #define QSYS_QMAP_SE_INP_SEL(x) ((x) & GENMASK(1, 0)) 48964ee5c8SVladimir Oltean #define QSYS_QMAP_SE_INP_SEL_M GENMASK(1, 0) 49964ee5c8SVladimir Oltean 50964ee5c8SVladimir Oltean #define QSYS_ISDX_SGRP_GSZ 0x4 51964ee5c8SVladimir Oltean 52964ee5c8SVladimir Oltean #define QSYS_TIMED_FRAME_ENTRY_GSZ 0x4 53964ee5c8SVladimir Oltean 54964ee5c8SVladimir Oltean #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x) (((x) << 9) & GENMASK(18, 9)) 55964ee5c8SVladimir Oltean #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M GENMASK(18, 9) 56964ee5c8SVladimir Oltean #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_X(x) (((x) & GENMASK(18, 9)) >> 9) 57964ee5c8SVladimir Oltean #define QSYS_TFRM_MISC_TIMED_CANCEL_1SHOT BIT(8) 58964ee5c8SVladimir Oltean #define QSYS_TFRM_MISC_TIMED_SLOT_MODE_MC BIT(7) 59964ee5c8SVladimir Oltean #define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT(x) ((x) & GENMASK(6, 0)) 60964ee5c8SVladimir Oltean #define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M GENMASK(6, 0) 61964ee5c8SVladimir Oltean 62964ee5c8SVladimir Oltean #define QSYS_RED_PROFILE_RSZ 0x4 63964ee5c8SVladimir Oltean 64964ee5c8SVladimir Oltean #define QSYS_RED_PROFILE_WM_RED_LOW(x) (((x) << 8) & GENMASK(15, 8)) 65964ee5c8SVladimir Oltean #define QSYS_RED_PROFILE_WM_RED_LOW_M GENMASK(15, 8) 66964ee5c8SVladimir Oltean #define QSYS_RED_PROFILE_WM_RED_LOW_X(x) (((x) & GENMASK(15, 8)) >> 8) 67964ee5c8SVladimir Oltean #define QSYS_RED_PROFILE_WM_RED_HIGH(x) ((x) & GENMASK(7, 0)) 68964ee5c8SVladimir Oltean #define QSYS_RED_PROFILE_WM_RED_HIGH_M GENMASK(7, 0) 69964ee5c8SVladimir Oltean 70964ee5c8SVladimir Oltean #define QSYS_RES_CFG_GSZ 0x8 71964ee5c8SVladimir Oltean 72964ee5c8SVladimir Oltean #define QSYS_RES_STAT_GSZ 0x8 73964ee5c8SVladimir Oltean 74964ee5c8SVladimir Oltean #define QSYS_RES_STAT_INUSE(x) (((x) << 12) & GENMASK(23, 12)) 75964ee5c8SVladimir Oltean #define QSYS_RES_STAT_INUSE_M GENMASK(23, 12) 76964ee5c8SVladimir Oltean #define QSYS_RES_STAT_INUSE_X(x) (((x) & GENMASK(23, 12)) >> 12) 77964ee5c8SVladimir Oltean #define QSYS_RES_STAT_MAXUSE(x) ((x) & GENMASK(11, 0)) 78964ee5c8SVladimir Oltean #define QSYS_RES_STAT_MAXUSE_M GENMASK(11, 0) 79964ee5c8SVladimir Oltean 80*f6fe01d6SVladimir Oltean #define QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(x) ((x) & GENMASK(15, 0)) 81*f6fe01d6SVladimir Oltean #define QSYS_MMGT_EQ_CTRL_FP_FREE_CNT_M GENMASK(15, 0) 82*f6fe01d6SVladimir Oltean 83964ee5c8SVladimir Oltean #define QSYS_EVENTS_CORE_EV_FDC(x) (((x) << 2) & GENMASK(4, 2)) 84964ee5c8SVladimir Oltean #define QSYS_EVENTS_CORE_EV_FDC_M GENMASK(4, 2) 85964ee5c8SVladimir Oltean #define QSYS_EVENTS_CORE_EV_FDC_X(x) (((x) & GENMASK(4, 2)) >> 2) 86964ee5c8SVladimir Oltean #define QSYS_EVENTS_CORE_EV_FRD(x) ((x) & GENMASK(1, 0)) 87964ee5c8SVladimir Oltean #define QSYS_EVENTS_CORE_EV_FRD_M GENMASK(1, 0) 88964ee5c8SVladimir Oltean 89964ee5c8SVladimir Oltean #define QSYS_QMAXSDU_CFG_0_RSZ 0x4 90964ee5c8SVladimir Oltean 91964ee5c8SVladimir Oltean #define QSYS_QMAXSDU_CFG_1_RSZ 0x4 92964ee5c8SVladimir Oltean 93964ee5c8SVladimir Oltean #define QSYS_QMAXSDU_CFG_2_RSZ 0x4 94964ee5c8SVladimir Oltean 95964ee5c8SVladimir Oltean #define QSYS_QMAXSDU_CFG_3_RSZ 0x4 96964ee5c8SVladimir Oltean 97964ee5c8SVladimir Oltean #define QSYS_QMAXSDU_CFG_4_RSZ 0x4 98964ee5c8SVladimir Oltean 99964ee5c8SVladimir Oltean #define QSYS_QMAXSDU_CFG_5_RSZ 0x4 100964ee5c8SVladimir Oltean 101964ee5c8SVladimir Oltean #define QSYS_QMAXSDU_CFG_6_RSZ 0x4 102964ee5c8SVladimir Oltean 103964ee5c8SVladimir Oltean #define QSYS_QMAXSDU_CFG_7_RSZ 0x4 104964ee5c8SVladimir Oltean 105964ee5c8SVladimir Oltean #define QSYS_PREEMPTION_CFG_RSZ 0x4 106964ee5c8SVladimir Oltean 107964ee5c8SVladimir Oltean #define QSYS_PREEMPTION_CFG_P_QUEUES(x) ((x) & GENMASK(7, 0)) 108964ee5c8SVladimir Oltean #define QSYS_PREEMPTION_CFG_P_QUEUES_M GENMASK(7, 0) 109964ee5c8SVladimir Oltean #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE(x) (((x) << 8) & GENMASK(9, 8)) 110964ee5c8SVladimir Oltean #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_M GENMASK(9, 8) 111964ee5c8SVladimir Oltean #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(x) (((x) & GENMASK(9, 8)) >> 8) 112964ee5c8SVladimir Oltean #define QSYS_PREEMPTION_CFG_STRICT_IPG(x) (((x) << 12) & GENMASK(13, 12)) 113964ee5c8SVladimir Oltean #define QSYS_PREEMPTION_CFG_STRICT_IPG_M GENMASK(13, 12) 114964ee5c8SVladimir Oltean #define QSYS_PREEMPTION_CFG_STRICT_IPG_X(x) (((x) & GENMASK(13, 12)) >> 12) 115964ee5c8SVladimir Oltean #define QSYS_PREEMPTION_CFG_HOLD_ADVANCE(x) (((x) << 16) & GENMASK(31, 16)) 116964ee5c8SVladimir Oltean #define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_M GENMASK(31, 16) 117964ee5c8SVladimir Oltean #define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_X(x) (((x) & GENMASK(31, 16)) >> 16) 118964ee5c8SVladimir Oltean 119964ee5c8SVladimir Oltean #define QSYS_CIR_CFG_GSZ 0x80 120964ee5c8SVladimir Oltean 121964ee5c8SVladimir Oltean #define QSYS_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6)) 122964ee5c8SVladimir Oltean #define QSYS_CIR_CFG_CIR_RATE_M GENMASK(20, 6) 123964ee5c8SVladimir Oltean #define QSYS_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6) 124964ee5c8SVladimir Oltean #define QSYS_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0)) 125964ee5c8SVladimir Oltean #define QSYS_CIR_CFG_CIR_BURST_M GENMASK(5, 0) 126964ee5c8SVladimir Oltean 127964ee5c8SVladimir Oltean #define QSYS_EIR_CFG_GSZ 0x80 128964ee5c8SVladimir Oltean 129964ee5c8SVladimir Oltean #define QSYS_EIR_CFG_EIR_RATE(x) (((x) << 7) & GENMASK(21, 7)) 130964ee5c8SVladimir Oltean #define QSYS_EIR_CFG_EIR_RATE_M GENMASK(21, 7) 131964ee5c8SVladimir Oltean #define QSYS_EIR_CFG_EIR_RATE_X(x) (((x) & GENMASK(21, 7)) >> 7) 132964ee5c8SVladimir Oltean #define QSYS_EIR_CFG_EIR_BURST(x) (((x) << 1) & GENMASK(6, 1)) 133964ee5c8SVladimir Oltean #define QSYS_EIR_CFG_EIR_BURST_M GENMASK(6, 1) 134964ee5c8SVladimir Oltean #define QSYS_EIR_CFG_EIR_BURST_X(x) (((x) & GENMASK(6, 1)) >> 1) 135964ee5c8SVladimir Oltean #define QSYS_EIR_CFG_EIR_MARK_ENA BIT(0) 136964ee5c8SVladimir Oltean 137964ee5c8SVladimir Oltean #define QSYS_SE_CFG_GSZ 0x80 138964ee5c8SVladimir Oltean 139964ee5c8SVladimir Oltean #define QSYS_SE_CFG_SE_DWRR_CNT(x) (((x) << 6) & GENMASK(9, 6)) 140964ee5c8SVladimir Oltean #define QSYS_SE_CFG_SE_DWRR_CNT_M GENMASK(9, 6) 141964ee5c8SVladimir Oltean #define QSYS_SE_CFG_SE_DWRR_CNT_X(x) (((x) & GENMASK(9, 6)) >> 6) 142964ee5c8SVladimir Oltean #define QSYS_SE_CFG_SE_RR_ENA BIT(5) 143964ee5c8SVladimir Oltean #define QSYS_SE_CFG_SE_AVB_ENA BIT(4) 144964ee5c8SVladimir Oltean #define QSYS_SE_CFG_SE_FRM_MODE(x) (((x) << 2) & GENMASK(3, 2)) 145964ee5c8SVladimir Oltean #define QSYS_SE_CFG_SE_FRM_MODE_M GENMASK(3, 2) 146964ee5c8SVladimir Oltean #define QSYS_SE_CFG_SE_FRM_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2) 147964ee5c8SVladimir Oltean #define QSYS_SE_CFG_SE_EXC_ENA BIT(1) 148964ee5c8SVladimir Oltean #define QSYS_SE_CFG_SE_EXC_FWD BIT(0) 149964ee5c8SVladimir Oltean 150964ee5c8SVladimir Oltean #define QSYS_SE_DWRR_CFG_GSZ 0x80 151964ee5c8SVladimir Oltean #define QSYS_SE_DWRR_CFG_RSZ 0x4 152964ee5c8SVladimir Oltean 153964ee5c8SVladimir Oltean #define QSYS_SE_CONNECT_GSZ 0x80 154964ee5c8SVladimir Oltean 155964ee5c8SVladimir Oltean #define QSYS_SE_CONNECT_SE_OUTP_IDX(x) (((x) << 17) & GENMASK(24, 17)) 156964ee5c8SVladimir Oltean #define QSYS_SE_CONNECT_SE_OUTP_IDX_M GENMASK(24, 17) 157964ee5c8SVladimir Oltean #define QSYS_SE_CONNECT_SE_OUTP_IDX_X(x) (((x) & GENMASK(24, 17)) >> 17) 158964ee5c8SVladimir Oltean #define QSYS_SE_CONNECT_SE_INP_IDX(x) (((x) << 9) & GENMASK(16, 9)) 159964ee5c8SVladimir Oltean #define QSYS_SE_CONNECT_SE_INP_IDX_M GENMASK(16, 9) 160964ee5c8SVladimir Oltean #define QSYS_SE_CONNECT_SE_INP_IDX_X(x) (((x) & GENMASK(16, 9)) >> 9) 161964ee5c8SVladimir Oltean #define QSYS_SE_CONNECT_SE_OUTP_CON(x) (((x) << 5) & GENMASK(8, 5)) 162964ee5c8SVladimir Oltean #define QSYS_SE_CONNECT_SE_OUTP_CON_M GENMASK(8, 5) 163964ee5c8SVladimir Oltean #define QSYS_SE_CONNECT_SE_OUTP_CON_X(x) (((x) & GENMASK(8, 5)) >> 5) 164964ee5c8SVladimir Oltean #define QSYS_SE_CONNECT_SE_INP_CNT(x) (((x) << 1) & GENMASK(4, 1)) 165964ee5c8SVladimir Oltean #define QSYS_SE_CONNECT_SE_INP_CNT_M GENMASK(4, 1) 166964ee5c8SVladimir Oltean #define QSYS_SE_CONNECT_SE_INP_CNT_X(x) (((x) & GENMASK(4, 1)) >> 1) 167964ee5c8SVladimir Oltean #define QSYS_SE_CONNECT_SE_TERMINAL BIT(0) 168964ee5c8SVladimir Oltean 169964ee5c8SVladimir Oltean #define QSYS_SE_DLB_SENSE_GSZ 0x80 170964ee5c8SVladimir Oltean 171964ee5c8SVladimir Oltean #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO(x) (((x) << 11) & GENMASK(13, 11)) 172964ee5c8SVladimir Oltean #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_M GENMASK(13, 11) 173964ee5c8SVladimir Oltean #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_X(x) (((x) & GENMASK(13, 11)) >> 11) 174964ee5c8SVladimir Oltean #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT(x) (((x) << 7) & GENMASK(10, 7)) 175964ee5c8SVladimir Oltean #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_M GENMASK(10, 7) 176964ee5c8SVladimir Oltean #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_X(x) (((x) & GENMASK(10, 7)) >> 7) 177964ee5c8SVladimir Oltean #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT(x) (((x) << 3) & GENMASK(6, 3)) 178964ee5c8SVladimir Oltean #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_M GENMASK(6, 3) 179964ee5c8SVladimir Oltean #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_X(x) (((x) & GENMASK(6, 3)) >> 3) 180964ee5c8SVladimir Oltean #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(2) 181964ee5c8SVladimir Oltean #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_ENA BIT(1) 182964ee5c8SVladimir Oltean #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0) 183964ee5c8SVladimir Oltean 184964ee5c8SVladimir Oltean #define QSYS_CIR_STATE_GSZ 0x80 185964ee5c8SVladimir Oltean 186964ee5c8SVladimir Oltean #define QSYS_CIR_STATE_CIR_LVL(x) (((x) << 4) & GENMASK(25, 4)) 187964ee5c8SVladimir Oltean #define QSYS_CIR_STATE_CIR_LVL_M GENMASK(25, 4) 188964ee5c8SVladimir Oltean #define QSYS_CIR_STATE_CIR_LVL_X(x) (((x) & GENMASK(25, 4)) >> 4) 189964ee5c8SVladimir Oltean #define QSYS_CIR_STATE_SHP_TIME(x) ((x) & GENMASK(3, 0)) 190964ee5c8SVladimir Oltean #define QSYS_CIR_STATE_SHP_TIME_M GENMASK(3, 0) 191964ee5c8SVladimir Oltean 192964ee5c8SVladimir Oltean #define QSYS_EIR_STATE_GSZ 0x80 193964ee5c8SVladimir Oltean 194964ee5c8SVladimir Oltean #define QSYS_SE_STATE_GSZ 0x80 195964ee5c8SVladimir Oltean 196964ee5c8SVladimir Oltean #define QSYS_SE_STATE_SE_OUTP_LVL(x) (((x) << 1) & GENMASK(2, 1)) 197964ee5c8SVladimir Oltean #define QSYS_SE_STATE_SE_OUTP_LVL_M GENMASK(2, 1) 198964ee5c8SVladimir Oltean #define QSYS_SE_STATE_SE_OUTP_LVL_X(x) (((x) & GENMASK(2, 1)) >> 1) 199964ee5c8SVladimir Oltean #define QSYS_SE_STATE_SE_WAS_YEL BIT(0) 200964ee5c8SVladimir Oltean 201964ee5c8SVladimir Oltean #define QSYS_HSCH_MISC_CFG_SE_CONNECT_VLD BIT(8) 202964ee5c8SVladimir Oltean #define QSYS_HSCH_MISC_CFG_FRM_ADJ(x) (((x) << 3) & GENMASK(7, 3)) 203964ee5c8SVladimir Oltean #define QSYS_HSCH_MISC_CFG_FRM_ADJ_M GENMASK(7, 3) 204964ee5c8SVladimir Oltean #define QSYS_HSCH_MISC_CFG_FRM_ADJ_X(x) (((x) & GENMASK(7, 3)) >> 3) 205964ee5c8SVladimir Oltean #define QSYS_HSCH_MISC_CFG_LEAK_DIS BIT(2) 206964ee5c8SVladimir Oltean #define QSYS_HSCH_MISC_CFG_QSHP_EXC_ENA BIT(1) 207964ee5c8SVladimir Oltean #define QSYS_HSCH_MISC_CFG_PFC_BYP_UPD BIT(0) 208964ee5c8SVladimir Oltean 209964ee5c8SVladimir Oltean #define QSYS_TAG_CONFIG_RSZ 0x4 210964ee5c8SVladimir Oltean 211964ee5c8SVladimir Oltean #define QSYS_TAG_CONFIG_ENABLE BIT(0) 212964ee5c8SVladimir Oltean #define QSYS_TAG_CONFIG_LINK_SPEED(x) (((x) << 4) & GENMASK(5, 4)) 213964ee5c8SVladimir Oltean #define QSYS_TAG_CONFIG_LINK_SPEED_M GENMASK(5, 4) 214964ee5c8SVladimir Oltean #define QSYS_TAG_CONFIG_LINK_SPEED_X(x) (((x) & GENMASK(5, 4)) >> 4) 215964ee5c8SVladimir Oltean #define QSYS_TAG_CONFIG_INIT_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8)) 216964ee5c8SVladimir Oltean #define QSYS_TAG_CONFIG_INIT_GATE_STATE_M GENMASK(15, 8) 217964ee5c8SVladimir Oltean #define QSYS_TAG_CONFIG_INIT_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8) 218964ee5c8SVladimir Oltean #define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(x) (((x) << 16) & GENMASK(23, 16)) 219964ee5c8SVladimir Oltean #define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M GENMASK(23, 16) 220964ee5c8SVladimir Oltean #define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_X(x) (((x) & GENMASK(23, 16)) >> 16) 221964ee5c8SVladimir Oltean 222964ee5c8SVladimir Oltean #define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(x) ((x) & GENMASK(7, 0)) 223964ee5c8SVladimir Oltean #define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M GENMASK(7, 0) 224964ee5c8SVladimir Oltean #define QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q BIT(8) 225964ee5c8SVladimir Oltean #define QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE BIT(16) 226964ee5c8SVladimir Oltean 227964ee5c8SVladimir Oltean #define QSYS_PORT_MAX_SDU_RSZ 0x4 228964ee5c8SVladimir Oltean 229964ee5c8SVladimir Oltean #define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) 230964ee5c8SVladimir Oltean #define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0) 231964ee5c8SVladimir Oltean #define QSYS_PARAM_CFG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16)) 232964ee5c8SVladimir Oltean #define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_M GENMASK(31, 16) 233964ee5c8SVladimir Oltean #define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16) 234964ee5c8SVladimir Oltean 235964ee5c8SVladimir Oltean #define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0)) 236964ee5c8SVladimir Oltean #define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0) 237964ee5c8SVladimir Oltean #define QSYS_GCL_CFG_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8)) 238964ee5c8SVladimir Oltean #define QSYS_GCL_CFG_REG_1_GATE_STATE_M GENMASK(15, 8) 239964ee5c8SVladimir Oltean #define QSYS_GCL_CFG_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8) 240964ee5c8SVladimir Oltean 241964ee5c8SVladimir Oltean #define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) 242964ee5c8SVladimir Oltean #define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0) 243964ee5c8SVladimir Oltean #define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16)) 244964ee5c8SVladimir Oltean #define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_M GENMASK(31, 16) 245964ee5c8SVladimir Oltean #define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16) 246964ee5c8SVladimir Oltean 247964ee5c8SVladimir Oltean #define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) 248964ee5c8SVladimir Oltean #define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0) 249964ee5c8SVladimir Oltean #define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE(x) (((x) << 16) & GENMASK(23, 16)) 250964ee5c8SVladimir Oltean #define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_M GENMASK(23, 16) 251964ee5c8SVladimir Oltean #define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_X(x) (((x) & GENMASK(23, 16)) >> 16) 252964ee5c8SVladimir Oltean #define QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING BIT(24) 253964ee5c8SVladimir Oltean 254964ee5c8SVladimir Oltean #define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0)) 255964ee5c8SVladimir Oltean #define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0) 256964ee5c8SVladimir Oltean #define QSYS_GCL_STATUS_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8)) 257964ee5c8SVladimir Oltean #define QSYS_GCL_STATUS_REG_1_GATE_STATE_M GENMASK(15, 8) 258964ee5c8SVladimir Oltean #define QSYS_GCL_STATUS_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8) 259964ee5c8SVladimir Oltean 260964ee5c8SVladimir Oltean #endif 261