1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* Copyright (c) 2017 Microsemi Corporation 3 */ 4 5 #ifndef _SOC_MSCC_OCELOT_H 6 #define _SOC_MSCC_OCELOT_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/net_tstamp.h> 10 #include <linux/if_vlan.h> 11 #include <linux/regmap.h> 12 #include <net/dsa.h> 13 14 /* Port Group IDs (PGID) are masks of destination ports. 15 * 16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each 17 * frame, and forwards the frame to the ports that are present in the logical 18 * AND of all 3 PGIDs. 19 * 20 * These PGID lookups are: 21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by 22 * which the switch selects a destination PGID: 23 * - The {DMAC, VID} is present in the MAC table. In that case, the 24 * destination PGID is given by the DEST_IDX field of the MAC table entry 25 * that matched. 26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The 27 * frame is disseminated as being either unicast, multicast or broadcast, 28 * and according to that, the destination PGID is chosen as being the 29 * value contained by ANA_FLOODING_FLD_UNICAST, 30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST. 31 * The destination PGID can be an unicast set: the first PGIDs, 0 to 32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from 33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to 34 * a physical port and has a single bit set in the destination ports mask: 35 * that corresponding to the port number itself. In contrast, a multicast 36 * PGID will have potentially more than one single bit set in the destination 37 * ports mask. 38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier 39 * dissects each frame and generates a 4-bit Link Aggregation Code which is 40 * used for this second PGID table lookup. The goal of link aggregation is to 41 * hash multiple flows within the same LAG on to different destination ports. 42 * The first lookup will result in a PGID with all the LAG members present in 43 * the destination ports mask, and the second lookup, by Link Aggregation 44 * Code, will ensure that each flow gets forwarded only to a single port out 45 * of that mask (there are no duplicates). 46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table 47 * is indexed with the ingress port (plus 80). These PGIDs answer the 48 * question "is port i allowed to forward traffic to port j?" If yes, then 49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used 50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge. 51 */ 52 53 /* Reserve some destination PGIDs at the end of the range: 54 * PGID_BLACKHOLE: used for not forwarding the frames 55 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses 56 * of the switch port net devices, towards the CPU port module. 57 * PGID_UC: the flooding destinations for unknown unicast traffic. 58 * PGID_MC: the flooding destinations for non-IP multicast traffic. 59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic. 60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic. 61 * PGID_BC: the flooding destinations for broadcast traffic. 62 */ 63 #define PGID_BLACKHOLE 57 64 #define PGID_CPU 58 65 #define PGID_UC 59 66 #define PGID_MC 60 67 #define PGID_MCIPV4 61 68 #define PGID_MCIPV6 62 69 #define PGID_BC 63 70 71 #define for_each_unicast_dest_pgid(ocelot, pgid) \ 72 for ((pgid) = 0; \ 73 (pgid) < (ocelot)->num_phys_ports; \ 74 (pgid)++) 75 76 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \ 77 for ((pgid) = (ocelot)->num_phys_ports + 1; \ 78 (pgid) < PGID_BLACKHOLE; \ 79 (pgid)++) 80 81 #define for_each_aggr_pgid(ocelot, pgid) \ 82 for ((pgid) = PGID_AGGR; \ 83 (pgid) < PGID_SRC; \ 84 (pgid)++) 85 86 /* Aggregation PGIDs, one per Link Aggregation Code */ 87 #define PGID_AGGR 64 88 89 /* Source PGIDs, one per physical port */ 90 #define PGID_SRC 80 91 92 #define OCELOT_NUM_TC 8 93 94 #define OCELOT_SPEED_2500 0 95 #define OCELOT_SPEED_1000 1 96 #define OCELOT_SPEED_100 2 97 #define OCELOT_SPEED_10 3 98 99 #define OCELOT_PTP_PINS_NUM 4 100 101 #define TARGET_OFFSET 24 102 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0) 103 #define REG(reg, offset) [reg & REG_MASK] = offset 104 105 #define REG_RESERVED_ADDR 0xffffffff 106 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR) 107 108 #define OCELOT_MRP_CPUQ 7 109 110 enum ocelot_target { 111 ANA = 1, 112 QS, 113 QSYS, 114 REW, 115 SYS, 116 S0, 117 S1, 118 S2, 119 HSIO, 120 PTP, 121 GCB, 122 DEV_GMII, 123 TARGET_MAX, 124 }; 125 126 enum ocelot_reg { 127 ANA_ADVLEARN = ANA << TARGET_OFFSET, 128 ANA_VLANMASK, 129 ANA_PORT_B_DOMAIN, 130 ANA_ANAGEFIL, 131 ANA_ANEVENTS, 132 ANA_STORMLIMIT_BURST, 133 ANA_STORMLIMIT_CFG, 134 ANA_ISOLATED_PORTS, 135 ANA_COMMUNITY_PORTS, 136 ANA_AUTOAGE, 137 ANA_MACTOPTIONS, 138 ANA_LEARNDISC, 139 ANA_AGENCTRL, 140 ANA_MIRRORPORTS, 141 ANA_EMIRRORPORTS, 142 ANA_FLOODING, 143 ANA_FLOODING_IPMC, 144 ANA_SFLOW_CFG, 145 ANA_PORT_MODE, 146 ANA_CUT_THRU_CFG, 147 ANA_PGID_PGID, 148 ANA_TABLES_ANMOVED, 149 ANA_TABLES_MACHDATA, 150 ANA_TABLES_MACLDATA, 151 ANA_TABLES_STREAMDATA, 152 ANA_TABLES_MACACCESS, 153 ANA_TABLES_MACTINDX, 154 ANA_TABLES_VLANACCESS, 155 ANA_TABLES_VLANTIDX, 156 ANA_TABLES_ISDXACCESS, 157 ANA_TABLES_ISDXTIDX, 158 ANA_TABLES_ENTRYLIM, 159 ANA_TABLES_PTP_ID_HIGH, 160 ANA_TABLES_PTP_ID_LOW, 161 ANA_TABLES_STREAMACCESS, 162 ANA_TABLES_STREAMTIDX, 163 ANA_TABLES_SEQ_HISTORY, 164 ANA_TABLES_SEQ_MASK, 165 ANA_TABLES_SFID_MASK, 166 ANA_TABLES_SFIDACCESS, 167 ANA_TABLES_SFIDTIDX, 168 ANA_MSTI_STATE, 169 ANA_OAM_UPM_LM_CNT, 170 ANA_SG_ACCESS_CTRL, 171 ANA_SG_CONFIG_REG_1, 172 ANA_SG_CONFIG_REG_2, 173 ANA_SG_CONFIG_REG_3, 174 ANA_SG_CONFIG_REG_4, 175 ANA_SG_CONFIG_REG_5, 176 ANA_SG_GCL_GS_CONFIG, 177 ANA_SG_GCL_TI_CONFIG, 178 ANA_SG_STATUS_REG_1, 179 ANA_SG_STATUS_REG_2, 180 ANA_SG_STATUS_REG_3, 181 ANA_PORT_VLAN_CFG, 182 ANA_PORT_DROP_CFG, 183 ANA_PORT_QOS_CFG, 184 ANA_PORT_VCAP_CFG, 185 ANA_PORT_VCAP_S1_KEY_CFG, 186 ANA_PORT_VCAP_S2_CFG, 187 ANA_PORT_PCP_DEI_MAP, 188 ANA_PORT_CPU_FWD_CFG, 189 ANA_PORT_CPU_FWD_BPDU_CFG, 190 ANA_PORT_CPU_FWD_GARP_CFG, 191 ANA_PORT_CPU_FWD_CCM_CFG, 192 ANA_PORT_PORT_CFG, 193 ANA_PORT_POL_CFG, 194 ANA_PORT_PTP_CFG, 195 ANA_PORT_PTP_DLY1_CFG, 196 ANA_PORT_PTP_DLY2_CFG, 197 ANA_PORT_SFID_CFG, 198 ANA_PFC_PFC_CFG, 199 ANA_PFC_PFC_TIMER, 200 ANA_IPT_OAM_MEP_CFG, 201 ANA_IPT_IPT, 202 ANA_PPT_PPT, 203 ANA_FID_MAP_FID_MAP, 204 ANA_AGGR_CFG, 205 ANA_CPUQ_CFG, 206 ANA_CPUQ_CFG2, 207 ANA_CPUQ_8021_CFG, 208 ANA_DSCP_CFG, 209 ANA_DSCP_REWR_CFG, 210 ANA_VCAP_RNG_TYPE_CFG, 211 ANA_VCAP_RNG_VAL_CFG, 212 ANA_VRAP_CFG, 213 ANA_VRAP_HDR_DATA, 214 ANA_VRAP_HDR_MASK, 215 ANA_DISCARD_CFG, 216 ANA_FID_CFG, 217 ANA_POL_PIR_CFG, 218 ANA_POL_CIR_CFG, 219 ANA_POL_MODE_CFG, 220 ANA_POL_PIR_STATE, 221 ANA_POL_CIR_STATE, 222 ANA_POL_STATE, 223 ANA_POL_FLOWC, 224 ANA_POL_HYST, 225 ANA_POL_MISC_CFG, 226 QS_XTR_GRP_CFG = QS << TARGET_OFFSET, 227 QS_XTR_RD, 228 QS_XTR_FRM_PRUNING, 229 QS_XTR_FLUSH, 230 QS_XTR_DATA_PRESENT, 231 QS_XTR_CFG, 232 QS_INJ_GRP_CFG, 233 QS_INJ_WR, 234 QS_INJ_CTRL, 235 QS_INJ_STATUS, 236 QS_INJ_ERR, 237 QS_INH_DBG, 238 QSYS_PORT_MODE = QSYS << TARGET_OFFSET, 239 QSYS_SWITCH_PORT_MODE, 240 QSYS_STAT_CNT_CFG, 241 QSYS_EEE_CFG, 242 QSYS_EEE_THRES, 243 QSYS_IGR_NO_SHARING, 244 QSYS_EGR_NO_SHARING, 245 QSYS_SW_STATUS, 246 QSYS_EXT_CPU_CFG, 247 QSYS_PAD_CFG, 248 QSYS_CPU_GROUP_MAP, 249 QSYS_QMAP, 250 QSYS_ISDX_SGRP, 251 QSYS_TIMED_FRAME_ENTRY, 252 QSYS_TFRM_MISC, 253 QSYS_TFRM_PORT_DLY, 254 QSYS_TFRM_TIMER_CFG_1, 255 QSYS_TFRM_TIMER_CFG_2, 256 QSYS_TFRM_TIMER_CFG_3, 257 QSYS_TFRM_TIMER_CFG_4, 258 QSYS_TFRM_TIMER_CFG_5, 259 QSYS_TFRM_TIMER_CFG_6, 260 QSYS_TFRM_TIMER_CFG_7, 261 QSYS_TFRM_TIMER_CFG_8, 262 QSYS_RED_PROFILE, 263 QSYS_RES_QOS_MODE, 264 QSYS_RES_CFG, 265 QSYS_RES_STAT, 266 QSYS_EGR_DROP_MODE, 267 QSYS_EQ_CTRL, 268 QSYS_EVENTS_CORE, 269 QSYS_QMAXSDU_CFG_0, 270 QSYS_QMAXSDU_CFG_1, 271 QSYS_QMAXSDU_CFG_2, 272 QSYS_QMAXSDU_CFG_3, 273 QSYS_QMAXSDU_CFG_4, 274 QSYS_QMAXSDU_CFG_5, 275 QSYS_QMAXSDU_CFG_6, 276 QSYS_QMAXSDU_CFG_7, 277 QSYS_PREEMPTION_CFG, 278 QSYS_CIR_CFG, 279 QSYS_EIR_CFG, 280 QSYS_SE_CFG, 281 QSYS_SE_DWRR_CFG, 282 QSYS_SE_CONNECT, 283 QSYS_SE_DLB_SENSE, 284 QSYS_CIR_STATE, 285 QSYS_EIR_STATE, 286 QSYS_SE_STATE, 287 QSYS_HSCH_MISC_CFG, 288 QSYS_TAG_CONFIG, 289 QSYS_TAS_PARAM_CFG_CTRL, 290 QSYS_PORT_MAX_SDU, 291 QSYS_PARAM_CFG_REG_1, 292 QSYS_PARAM_CFG_REG_2, 293 QSYS_PARAM_CFG_REG_3, 294 QSYS_PARAM_CFG_REG_4, 295 QSYS_PARAM_CFG_REG_5, 296 QSYS_GCL_CFG_REG_1, 297 QSYS_GCL_CFG_REG_2, 298 QSYS_PARAM_STATUS_REG_1, 299 QSYS_PARAM_STATUS_REG_2, 300 QSYS_PARAM_STATUS_REG_3, 301 QSYS_PARAM_STATUS_REG_4, 302 QSYS_PARAM_STATUS_REG_5, 303 QSYS_PARAM_STATUS_REG_6, 304 QSYS_PARAM_STATUS_REG_7, 305 QSYS_PARAM_STATUS_REG_8, 306 QSYS_PARAM_STATUS_REG_9, 307 QSYS_GCL_STATUS_REG_1, 308 QSYS_GCL_STATUS_REG_2, 309 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET, 310 REW_TAG_CFG, 311 REW_PORT_CFG, 312 REW_DSCP_CFG, 313 REW_PCP_DEI_QOS_MAP_CFG, 314 REW_PTP_CFG, 315 REW_PTP_DLY1_CFG, 316 REW_RED_TAG_CFG, 317 REW_DSCP_REMAP_DP1_CFG, 318 REW_DSCP_REMAP_CFG, 319 REW_STAT_CFG, 320 REW_REW_STICKY, 321 REW_PPT, 322 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET, 323 SYS_COUNT_RX_UNICAST, 324 SYS_COUNT_RX_MULTICAST, 325 SYS_COUNT_RX_BROADCAST, 326 SYS_COUNT_RX_SHORTS, 327 SYS_COUNT_RX_FRAGMENTS, 328 SYS_COUNT_RX_JABBERS, 329 SYS_COUNT_RX_CRC_ALIGN_ERRS, 330 SYS_COUNT_RX_SYM_ERRS, 331 SYS_COUNT_RX_64, 332 SYS_COUNT_RX_65_127, 333 SYS_COUNT_RX_128_255, 334 SYS_COUNT_RX_256_1023, 335 SYS_COUNT_RX_1024_1526, 336 SYS_COUNT_RX_1527_MAX, 337 SYS_COUNT_RX_PAUSE, 338 SYS_COUNT_RX_CONTROL, 339 SYS_COUNT_RX_LONGS, 340 SYS_COUNT_RX_CLASSIFIED_DROPS, 341 SYS_COUNT_TX_OCTETS, 342 SYS_COUNT_TX_UNICAST, 343 SYS_COUNT_TX_MULTICAST, 344 SYS_COUNT_TX_BROADCAST, 345 SYS_COUNT_TX_COLLISION, 346 SYS_COUNT_TX_DROPS, 347 SYS_COUNT_TX_PAUSE, 348 SYS_COUNT_TX_64, 349 SYS_COUNT_TX_65_127, 350 SYS_COUNT_TX_128_511, 351 SYS_COUNT_TX_512_1023, 352 SYS_COUNT_TX_1024_1526, 353 SYS_COUNT_TX_1527_MAX, 354 SYS_COUNT_TX_AGING, 355 SYS_RESET_CFG, 356 SYS_SR_ETYPE_CFG, 357 SYS_VLAN_ETYPE_CFG, 358 SYS_PORT_MODE, 359 SYS_FRONT_PORT_MODE, 360 SYS_FRM_AGING, 361 SYS_STAT_CFG, 362 SYS_SW_STATUS, 363 SYS_MISC_CFG, 364 SYS_REW_MAC_HIGH_CFG, 365 SYS_REW_MAC_LOW_CFG, 366 SYS_TIMESTAMP_OFFSET, 367 SYS_CMID, 368 SYS_PAUSE_CFG, 369 SYS_PAUSE_TOT_CFG, 370 SYS_ATOP, 371 SYS_ATOP_TOT_CFG, 372 SYS_MAC_FC_CFG, 373 SYS_MMGT, 374 SYS_MMGT_FAST, 375 SYS_EVENTS_DIF, 376 SYS_EVENTS_CORE, 377 SYS_CNT, 378 SYS_PTP_STATUS, 379 SYS_PTP_TXSTAMP, 380 SYS_PTP_NXT, 381 SYS_PTP_CFG, 382 SYS_RAM_INIT, 383 SYS_CM_ADDR, 384 SYS_CM_DATA_WR, 385 SYS_CM_DATA_RD, 386 SYS_CM_OP, 387 SYS_CM_DATA, 388 PTP_PIN_CFG = PTP << TARGET_OFFSET, 389 PTP_PIN_TOD_SEC_MSB, 390 PTP_PIN_TOD_SEC_LSB, 391 PTP_PIN_TOD_NSEC, 392 PTP_PIN_WF_HIGH_PERIOD, 393 PTP_PIN_WF_LOW_PERIOD, 394 PTP_CFG_MISC, 395 PTP_CLK_CFG_ADJ_CFG, 396 PTP_CLK_CFG_ADJ_FREQ, 397 GCB_SOFT_RST = GCB << TARGET_OFFSET, 398 GCB_MIIM_MII_STATUS, 399 GCB_MIIM_MII_CMD, 400 GCB_MIIM_MII_DATA, 401 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, 402 DEV_PORT_MISC, 403 DEV_EVENTS, 404 DEV_EEE_CFG, 405 DEV_RX_PATH_DELAY, 406 DEV_TX_PATH_DELAY, 407 DEV_PTP_PREDICT_CFG, 408 DEV_MAC_ENA_CFG, 409 DEV_MAC_MODE_CFG, 410 DEV_MAC_MAXLEN_CFG, 411 DEV_MAC_TAGS_CFG, 412 DEV_MAC_ADV_CHK_CFG, 413 DEV_MAC_IFG_CFG, 414 DEV_MAC_HDX_CFG, 415 DEV_MAC_DBG_CFG, 416 DEV_MAC_FC_MAC_LOW_CFG, 417 DEV_MAC_FC_MAC_HIGH_CFG, 418 DEV_MAC_STICKY, 419 PCS1G_CFG, 420 PCS1G_MODE_CFG, 421 PCS1G_SD_CFG, 422 PCS1G_ANEG_CFG, 423 PCS1G_ANEG_NP_CFG, 424 PCS1G_LB_CFG, 425 PCS1G_DBG_CFG, 426 PCS1G_CDET_CFG, 427 PCS1G_ANEG_STATUS, 428 PCS1G_ANEG_NP_STATUS, 429 PCS1G_LINK_STATUS, 430 PCS1G_LINK_DOWN_CNT, 431 PCS1G_STICKY, 432 PCS1G_DEBUG_STATUS, 433 PCS1G_LPI_CFG, 434 PCS1G_LPI_WAKE_ERROR_CNT, 435 PCS1G_LPI_STATUS, 436 PCS1G_TSTPAT_MODE_CFG, 437 PCS1G_TSTPAT_STATUS, 438 DEV_PCS_FX100_CFG, 439 DEV_PCS_FX100_STATUS, 440 }; 441 442 enum ocelot_regfield { 443 ANA_ADVLEARN_VLAN_CHK, 444 ANA_ADVLEARN_LEARN_MIRROR, 445 ANA_ANEVENTS_FLOOD_DISCARD, 446 ANA_ANEVENTS_MSTI_DROP, 447 ANA_ANEVENTS_ACLKILL, 448 ANA_ANEVENTS_ACLUSED, 449 ANA_ANEVENTS_AUTOAGE, 450 ANA_ANEVENTS_VS2TTL1, 451 ANA_ANEVENTS_STORM_DROP, 452 ANA_ANEVENTS_LEARN_DROP, 453 ANA_ANEVENTS_AGED_ENTRY, 454 ANA_ANEVENTS_CPU_LEARN_FAILED, 455 ANA_ANEVENTS_AUTO_LEARN_FAILED, 456 ANA_ANEVENTS_LEARN_REMOVE, 457 ANA_ANEVENTS_AUTO_LEARNED, 458 ANA_ANEVENTS_AUTO_MOVED, 459 ANA_ANEVENTS_DROPPED, 460 ANA_ANEVENTS_CLASSIFIED_DROP, 461 ANA_ANEVENTS_CLASSIFIED_COPY, 462 ANA_ANEVENTS_VLAN_DISCARD, 463 ANA_ANEVENTS_FWD_DISCARD, 464 ANA_ANEVENTS_MULTICAST_FLOOD, 465 ANA_ANEVENTS_UNICAST_FLOOD, 466 ANA_ANEVENTS_DEST_KNOWN, 467 ANA_ANEVENTS_BUCKET3_MATCH, 468 ANA_ANEVENTS_BUCKET2_MATCH, 469 ANA_ANEVENTS_BUCKET1_MATCH, 470 ANA_ANEVENTS_BUCKET0_MATCH, 471 ANA_ANEVENTS_CPU_OPERATION, 472 ANA_ANEVENTS_DMAC_LOOKUP, 473 ANA_ANEVENTS_SMAC_LOOKUP, 474 ANA_ANEVENTS_SEQ_GEN_ERR_0, 475 ANA_ANEVENTS_SEQ_GEN_ERR_1, 476 ANA_TABLES_MACACCESS_B_DOM, 477 ANA_TABLES_MACTINDX_BUCKET, 478 ANA_TABLES_MACTINDX_M_INDEX, 479 QSYS_SWITCH_PORT_MODE_PORT_ENA, 480 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG, 481 QSYS_SWITCH_PORT_MODE_YEL_RSRVD, 482 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE, 483 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 484 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE, 485 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD, 486 QSYS_TIMED_FRAME_ENTRY_TFRM_FP, 487 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO, 488 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL, 489 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T, 490 SYS_PORT_MODE_DATA_WO_TS, 491 SYS_PORT_MODE_INCL_INJ_HDR, 492 SYS_PORT_MODE_INCL_XTR_HDR, 493 SYS_PORT_MODE_INCL_HDR_ERR, 494 SYS_RESET_CFG_CORE_ENA, 495 SYS_RESET_CFG_MEM_ENA, 496 SYS_RESET_CFG_MEM_INIT, 497 GCB_SOFT_RST_SWC_RST, 498 GCB_MIIM_MII_STATUS_PENDING, 499 GCB_MIIM_MII_STATUS_BUSY, 500 SYS_PAUSE_CFG_PAUSE_START, 501 SYS_PAUSE_CFG_PAUSE_STOP, 502 SYS_PAUSE_CFG_PAUSE_ENA, 503 REGFIELD_MAX 504 }; 505 506 enum { 507 /* VCAP_CORE_CFG */ 508 VCAP_CORE_UPDATE_CTRL, 509 VCAP_CORE_MV_CFG, 510 /* VCAP_CORE_CACHE */ 511 VCAP_CACHE_ENTRY_DAT, 512 VCAP_CACHE_MASK_DAT, 513 VCAP_CACHE_ACTION_DAT, 514 VCAP_CACHE_CNT_DAT, 515 VCAP_CACHE_TG_DAT, 516 /* VCAP_CONST */ 517 VCAP_CONST_VCAP_VER, 518 VCAP_CONST_ENTRY_WIDTH, 519 VCAP_CONST_ENTRY_CNT, 520 VCAP_CONST_ENTRY_SWCNT, 521 VCAP_CONST_ENTRY_TG_WIDTH, 522 VCAP_CONST_ACTION_DEF_CNT, 523 VCAP_CONST_ACTION_WIDTH, 524 VCAP_CONST_CNT_WIDTH, 525 VCAP_CONST_CORE_CNT, 526 VCAP_CONST_IF_CNT, 527 }; 528 529 enum ocelot_ptp_pins { 530 PTP_PIN_0, 531 PTP_PIN_1, 532 PTP_PIN_2, 533 PTP_PIN_3, 534 TOD_ACC_PIN 535 }; 536 537 struct ocelot_stat_layout { 538 u32 offset; 539 char name[ETH_GSTRING_LEN]; 540 }; 541 542 enum ocelot_tag_prefix { 543 OCELOT_TAG_PREFIX_DISABLED = 0, 544 OCELOT_TAG_PREFIX_NONE, 545 OCELOT_TAG_PREFIX_SHORT, 546 OCELOT_TAG_PREFIX_LONG, 547 }; 548 549 struct ocelot; 550 551 struct ocelot_ops { 552 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port); 553 int (*netdev_to_port)(struct net_device *dev); 554 int (*reset)(struct ocelot *ocelot); 555 u16 (*wm_enc)(u16 value); 556 u16 (*wm_dec)(u16 value); 557 void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse); 558 }; 559 560 struct ocelot_vcap_block { 561 struct list_head rules; 562 int count; 563 int pol_lpr; 564 }; 565 566 struct ocelot_bridge_vlan { 567 u16 vid; 568 unsigned long portmask; 569 unsigned long untagged; 570 struct list_head list; 571 }; 572 573 enum ocelot_port_tag_config { 574 /* all VLANs are egress-untagged */ 575 OCELOT_PORT_TAG_DISABLED = 0, 576 /* all VLANs except the native VLAN and VID 0 are egress-tagged */ 577 OCELOT_PORT_TAG_NATIVE = 1, 578 /* all VLANs except VID 0 are egress-tagged */ 579 OCELOT_PORT_TAG_TRUNK_NO_VID0 = 2, 580 /* all VLANs are egress-tagged */ 581 OCELOT_PORT_TAG_TRUNK = 3, 582 }; 583 584 enum ocelot_sb { 585 OCELOT_SB_BUF, 586 OCELOT_SB_REF, 587 OCELOT_SB_NUM, 588 }; 589 590 enum ocelot_sb_pool { 591 OCELOT_SB_POOL_ING, 592 OCELOT_SB_POOL_EGR, 593 OCELOT_SB_POOL_NUM, 594 }; 595 596 #define OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION BIT(0) 597 #define OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP BIT(1) 598 599 struct ocelot_port { 600 struct ocelot *ocelot; 601 602 struct regmap *target; 603 604 bool vlan_aware; 605 /* VLAN that untagged frames are classified to, on ingress */ 606 const struct ocelot_bridge_vlan *pvid_vlan; 607 608 unsigned int ptp_skbs_in_flight; 609 u8 ptp_cmd; 610 struct sk_buff_head tx_skbs; 611 u8 ts_id; 612 613 phy_interface_t phy_mode; 614 615 u8 *xmit_template; 616 bool is_dsa_8021q_cpu; 617 bool learn_ena; 618 619 struct net_device *bond; 620 bool lag_tx_active; 621 622 u16 mrp_ring_id; 623 624 struct net_device *bridge; 625 u8 stp_state; 626 }; 627 628 struct ocelot { 629 struct device *dev; 630 struct devlink *devlink; 631 struct devlink_port *devlink_ports; 632 633 const struct ocelot_ops *ops; 634 struct regmap *targets[TARGET_MAX]; 635 struct regmap_field *regfields[REGFIELD_MAX]; 636 const u32 *const *map; 637 const struct ocelot_stat_layout *stats_layout; 638 unsigned int num_stats; 639 640 u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM]; 641 int packet_buffer_size; 642 int num_frame_refs; 643 int num_mact_rows; 644 645 struct ocelot_port **ports; 646 647 u8 base_mac[ETH_ALEN]; 648 649 struct list_head vlans; 650 651 /* Switches like VSC9959 have flooding per traffic class */ 652 int num_flooding_pgids; 653 654 /* In tables like ANA:PORT and the ANA:PGID:PGID mask, 655 * the CPU is located after the physical ports (at the 656 * num_phys_ports index). 657 */ 658 u8 num_phys_ports; 659 660 int npi; 661 662 enum ocelot_tag_prefix npi_inj_prefix; 663 enum ocelot_tag_prefix npi_xtr_prefix; 664 665 struct list_head multicast; 666 struct list_head pgids; 667 668 struct list_head dummy_rules; 669 struct ocelot_vcap_block block[3]; 670 struct vcap_props *vcap; 671 672 /* Workqueue to check statistics for overflow with its lock */ 673 struct mutex stats_lock; 674 u64 *stats; 675 struct delayed_work stats_work; 676 struct workqueue_struct *stats_queue; 677 678 /* Lock for serializing access to the MAC table */ 679 struct mutex mact_lock; 680 681 struct workqueue_struct *owq; 682 683 u8 ptp:1; 684 struct ptp_clock *ptp_clock; 685 struct ptp_clock_info ptp_info; 686 struct hwtstamp_config hwtstamp_config; 687 unsigned int ptp_skbs_in_flight; 688 /* Protects the 2-step TX timestamp ID logic */ 689 spinlock_t ts_id_lock; 690 /* Protects the PTP interface state */ 691 struct mutex ptp_lock; 692 /* Protects the PTP clock */ 693 spinlock_t ptp_clock_lock; 694 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM]; 695 }; 696 697 struct ocelot_policer { 698 u32 rate; /* kilobit per second */ 699 u32 burst; /* bytes */ 700 }; 701 702 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 703 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) 704 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) 705 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0) 706 707 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 708 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) 709 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) 710 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) 711 712 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 713 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) 714 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) 715 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) 716 717 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val)) 718 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val)) 719 #define ocelot_fields_write(ocelot, id, reg, val) regmap_fields_write((ocelot)->regfields[(reg)], (id), (val)) 720 #define ocelot_fields_read(ocelot, id, reg, val) regmap_fields_read((ocelot)->regfields[(reg)], (id), (val)) 721 722 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \ 723 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 724 #define ocelot_target_read_gix(ocelot, target, reg, gi) \ 725 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi)) 726 #define ocelot_target_read_rix(ocelot, target, reg, ri) \ 727 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri)) 728 #define ocelot_target_read(ocelot, target, reg) \ 729 __ocelot_target_read_ix(ocelot, target, reg, 0) 730 731 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \ 732 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 733 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \ 734 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi)) 735 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \ 736 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri)) 737 #define ocelot_target_write(ocelot, target, val, reg) \ 738 __ocelot_target_write_ix(ocelot, target, val, reg, 0) 739 740 /* I/O */ 741 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); 742 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); 743 void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, u32 reg); 744 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); 745 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); 746 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, 747 u32 offset); 748 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target, 749 u32 reg, u32 offset); 750 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target, 751 u32 val, u32 reg, u32 offset); 752 753 /* Packet I/O */ 754 bool ocelot_can_inject(struct ocelot *ocelot, int grp); 755 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 756 u32 rew_op, struct sk_buff *skb); 757 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb); 758 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp); 759 760 /* Hardware initialization */ 761 int ocelot_regfields_init(struct ocelot *ocelot, 762 const struct reg_field *const regfields); 763 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res); 764 int ocelot_init(struct ocelot *ocelot); 765 void ocelot_deinit(struct ocelot *ocelot); 766 void ocelot_init_port(struct ocelot *ocelot, int port); 767 void ocelot_deinit_port(struct ocelot *ocelot, int port); 768 769 /* DSA callbacks */ 770 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data); 771 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data); 772 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset); 773 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 774 struct ethtool_ts_info *info); 775 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs); 776 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled, 777 struct netlink_ext_ack *extack); 778 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state); 779 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot); 780 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 781 struct switchdev_brport_flags val); 782 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 783 struct switchdev_brport_flags val); 784 void ocelot_port_bridge_join(struct ocelot *ocelot, int port, 785 struct net_device *bridge); 786 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 787 struct net_device *bridge); 788 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 789 dsa_fdb_dump_cb_t *cb, void *data); 790 int ocelot_fdb_add(struct ocelot *ocelot, int port, 791 const unsigned char *addr, u16 vid); 792 int ocelot_fdb_del(struct ocelot *ocelot, int port, 793 const unsigned char *addr, u16 vid); 794 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 795 bool untagged, struct netlink_ext_ack *extack); 796 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 797 bool untagged); 798 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid); 799 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr); 800 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr); 801 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 802 struct sk_buff *skb, 803 struct sk_buff **clone); 804 void ocelot_get_txtstamp(struct ocelot *ocelot); 805 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu); 806 int ocelot_get_max_mtu(struct ocelot *ocelot, int port); 807 int ocelot_port_policer_add(struct ocelot *ocelot, int port, 808 struct ocelot_policer *pol); 809 int ocelot_port_policer_del(struct ocelot *ocelot, int port); 810 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port, 811 struct flow_cls_offload *f, bool ingress); 812 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port, 813 struct flow_cls_offload *f, bool ingress); 814 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port, 815 struct flow_cls_offload *f, bool ingress); 816 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 817 const struct switchdev_obj_port_mdb *mdb); 818 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 819 const struct switchdev_obj_port_mdb *mdb); 820 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 821 struct net_device *bond, 822 struct netdev_lag_upper_info *info); 823 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 824 struct net_device *bond); 825 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active); 826 827 int ocelot_devlink_sb_register(struct ocelot *ocelot); 828 void ocelot_devlink_sb_unregister(struct ocelot *ocelot); 829 int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index, 830 u16 pool_index, 831 struct devlink_sb_pool_info *pool_info); 832 int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index, 833 u16 pool_index, u32 size, 834 enum devlink_sb_threshold_type threshold_type, 835 struct netlink_ext_ack *extack); 836 int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port, 837 unsigned int sb_index, u16 pool_index, 838 u32 *p_threshold); 839 int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port, 840 unsigned int sb_index, u16 pool_index, 841 u32 threshold, struct netlink_ext_ack *extack); 842 int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port, 843 unsigned int sb_index, u16 tc_index, 844 enum devlink_sb_pool_type pool_type, 845 u16 *p_pool_index, u32 *p_threshold); 846 int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port, 847 unsigned int sb_index, u16 tc_index, 848 enum devlink_sb_pool_type pool_type, 849 u16 pool_index, u32 threshold, 850 struct netlink_ext_ack *extack); 851 int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index); 852 int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index); 853 int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port, 854 unsigned int sb_index, u16 pool_index, 855 u32 *p_cur, u32 *p_max); 856 int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port, 857 unsigned int sb_index, u16 tc_index, 858 enum devlink_sb_pool_type pool_type, 859 u32 *p_cur, u32 *p_max); 860 861 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 862 unsigned int link_an_mode, 863 phy_interface_t interface, 864 unsigned long quirks); 865 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 866 struct phy_device *phydev, 867 unsigned int link_an_mode, 868 phy_interface_t interface, 869 int speed, int duplex, 870 bool tx_pause, bool rx_pause, 871 unsigned long quirks); 872 873 #if IS_ENABLED(CONFIG_BRIDGE_MRP) 874 int ocelot_mrp_add(struct ocelot *ocelot, int port, 875 const struct switchdev_obj_mrp *mrp); 876 int ocelot_mrp_del(struct ocelot *ocelot, int port, 877 const struct switchdev_obj_mrp *mrp); 878 int ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port, 879 const struct switchdev_obj_ring_role_mrp *mrp); 880 int ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, 881 const struct switchdev_obj_ring_role_mrp *mrp); 882 #else 883 static inline int ocelot_mrp_add(struct ocelot *ocelot, int port, 884 const struct switchdev_obj_mrp *mrp) 885 { 886 return -EOPNOTSUPP; 887 } 888 889 static inline int ocelot_mrp_del(struct ocelot *ocelot, int port, 890 const struct switchdev_obj_mrp *mrp) 891 { 892 return -EOPNOTSUPP; 893 } 894 895 static inline int 896 ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port, 897 const struct switchdev_obj_ring_role_mrp *mrp) 898 { 899 return -EOPNOTSUPP; 900 } 901 902 static inline int 903 ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, 904 const struct switchdev_obj_ring_role_mrp *mrp) 905 { 906 return -EOPNOTSUPP; 907 } 908 #endif 909 910 #endif 911