1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* Copyright (c) 2017 Microsemi Corporation 3 */ 4 5 #ifndef _SOC_MSCC_OCELOT_H 6 #define _SOC_MSCC_OCELOT_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/net_tstamp.h> 10 #include <linux/if_vlan.h> 11 #include <linux/regmap.h> 12 #include <net/dsa.h> 13 14 /* Port Group IDs (PGID) are masks of destination ports. 15 * 16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each 17 * frame, and forwards the frame to the ports that are present in the logical 18 * AND of all 3 PGIDs. 19 * 20 * These PGID lookups are: 21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by 22 * which the switch selects a destination PGID: 23 * - The {DMAC, VID} is present in the MAC table. In that case, the 24 * destination PGID is given by the DEST_IDX field of the MAC table entry 25 * that matched. 26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The 27 * frame is disseminated as being either unicast, multicast or broadcast, 28 * and according to that, the destination PGID is chosen as being the 29 * value contained by ANA_FLOODING_FLD_UNICAST, 30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST. 31 * The destination PGID can be an unicast set: the first PGIDs, 0 to 32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from 33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to 34 * a physical port and has a single bit set in the destination ports mask: 35 * that corresponding to the port number itself. In contrast, a multicast 36 * PGID will have potentially more than one single bit set in the destination 37 * ports mask. 38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier 39 * dissects each frame and generates a 4-bit Link Aggregation Code which is 40 * used for this second PGID table lookup. The goal of link aggregation is to 41 * hash multiple flows within the same LAG on to different destination ports. 42 * The first lookup will result in a PGID with all the LAG members present in 43 * the destination ports mask, and the second lookup, by Link Aggregation 44 * Code, will ensure that each flow gets forwarded only to a single port out 45 * of that mask (there are no duplicates). 46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table 47 * is indexed with the ingress port (plus 80). These PGIDs answer the 48 * question "is port i allowed to forward traffic to port j?" If yes, then 49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used 50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge. 51 */ 52 53 /* Reserve some destination PGIDs at the end of the range: 54 * PGID_BLACKHOLE: used for not forwarding the frames 55 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses 56 * of the switch port net devices, towards the CPU port module. 57 * PGID_UC: the flooding destinations for unknown unicast traffic. 58 * PGID_MC: the flooding destinations for non-IP multicast traffic. 59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic. 60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic. 61 * PGID_BC: the flooding destinations for broadcast traffic. 62 */ 63 #define PGID_BLACKHOLE 57 64 #define PGID_CPU 58 65 #define PGID_UC 59 66 #define PGID_MC 60 67 #define PGID_MCIPV4 61 68 #define PGID_MCIPV6 62 69 #define PGID_BC 63 70 71 #define for_each_unicast_dest_pgid(ocelot, pgid) \ 72 for ((pgid) = 0; \ 73 (pgid) < (ocelot)->num_phys_ports; \ 74 (pgid)++) 75 76 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \ 77 for ((pgid) = (ocelot)->num_phys_ports + 1; \ 78 (pgid) < PGID_BLACKHOLE; \ 79 (pgid)++) 80 81 #define for_each_aggr_pgid(ocelot, pgid) \ 82 for ((pgid) = PGID_AGGR; \ 83 (pgid) < PGID_SRC; \ 84 (pgid)++) 85 86 /* Aggregation PGIDs, one per Link Aggregation Code */ 87 #define PGID_AGGR 64 88 89 /* Source PGIDs, one per physical port */ 90 #define PGID_SRC 80 91 92 #define OCELOT_NUM_TC 8 93 94 #define OCELOT_SPEED_2500 0 95 #define OCELOT_SPEED_1000 1 96 #define OCELOT_SPEED_100 2 97 #define OCELOT_SPEED_10 3 98 99 #define OCELOT_PTP_PINS_NUM 4 100 101 #define TARGET_OFFSET 24 102 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0) 103 #define REG(reg, offset) [reg & REG_MASK] = offset 104 105 #define REG_RESERVED_ADDR 0xffffffff 106 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR) 107 108 enum ocelot_target { 109 ANA = 1, 110 QS, 111 QSYS, 112 REW, 113 SYS, 114 S0, 115 S1, 116 S2, 117 HSIO, 118 PTP, 119 FDMA, 120 GCB, 121 DEV_GMII, 122 TARGET_MAX, 123 }; 124 125 enum ocelot_reg { 126 ANA_ADVLEARN = ANA << TARGET_OFFSET, 127 ANA_VLANMASK, 128 ANA_PORT_B_DOMAIN, 129 ANA_ANAGEFIL, 130 ANA_ANEVENTS, 131 ANA_STORMLIMIT_BURST, 132 ANA_STORMLIMIT_CFG, 133 ANA_ISOLATED_PORTS, 134 ANA_COMMUNITY_PORTS, 135 ANA_AUTOAGE, 136 ANA_MACTOPTIONS, 137 ANA_LEARNDISC, 138 ANA_AGENCTRL, 139 ANA_MIRRORPORTS, 140 ANA_EMIRRORPORTS, 141 ANA_FLOODING, 142 ANA_FLOODING_IPMC, 143 ANA_SFLOW_CFG, 144 ANA_PORT_MODE, 145 ANA_CUT_THRU_CFG, 146 ANA_PGID_PGID, 147 ANA_TABLES_ANMOVED, 148 ANA_TABLES_MACHDATA, 149 ANA_TABLES_MACLDATA, 150 ANA_TABLES_STREAMDATA, 151 ANA_TABLES_MACACCESS, 152 ANA_TABLES_MACTINDX, 153 ANA_TABLES_VLANACCESS, 154 ANA_TABLES_VLANTIDX, 155 ANA_TABLES_ISDXACCESS, 156 ANA_TABLES_ISDXTIDX, 157 ANA_TABLES_ENTRYLIM, 158 ANA_TABLES_PTP_ID_HIGH, 159 ANA_TABLES_PTP_ID_LOW, 160 ANA_TABLES_STREAMACCESS, 161 ANA_TABLES_STREAMTIDX, 162 ANA_TABLES_SEQ_HISTORY, 163 ANA_TABLES_SEQ_MASK, 164 ANA_TABLES_SFID_MASK, 165 ANA_TABLES_SFIDACCESS, 166 ANA_TABLES_SFIDTIDX, 167 ANA_MSTI_STATE, 168 ANA_OAM_UPM_LM_CNT, 169 ANA_SG_ACCESS_CTRL, 170 ANA_SG_CONFIG_REG_1, 171 ANA_SG_CONFIG_REG_2, 172 ANA_SG_CONFIG_REG_3, 173 ANA_SG_CONFIG_REG_4, 174 ANA_SG_CONFIG_REG_5, 175 ANA_SG_GCL_GS_CONFIG, 176 ANA_SG_GCL_TI_CONFIG, 177 ANA_SG_STATUS_REG_1, 178 ANA_SG_STATUS_REG_2, 179 ANA_SG_STATUS_REG_3, 180 ANA_PORT_VLAN_CFG, 181 ANA_PORT_DROP_CFG, 182 ANA_PORT_QOS_CFG, 183 ANA_PORT_VCAP_CFG, 184 ANA_PORT_VCAP_S1_KEY_CFG, 185 ANA_PORT_VCAP_S2_CFG, 186 ANA_PORT_PCP_DEI_MAP, 187 ANA_PORT_CPU_FWD_CFG, 188 ANA_PORT_CPU_FWD_BPDU_CFG, 189 ANA_PORT_CPU_FWD_GARP_CFG, 190 ANA_PORT_CPU_FWD_CCM_CFG, 191 ANA_PORT_PORT_CFG, 192 ANA_PORT_POL_CFG, 193 ANA_PORT_PTP_CFG, 194 ANA_PORT_PTP_DLY1_CFG, 195 ANA_PORT_PTP_DLY2_CFG, 196 ANA_PORT_SFID_CFG, 197 ANA_PFC_PFC_CFG, 198 ANA_PFC_PFC_TIMER, 199 ANA_IPT_OAM_MEP_CFG, 200 ANA_IPT_IPT, 201 ANA_PPT_PPT, 202 ANA_FID_MAP_FID_MAP, 203 ANA_AGGR_CFG, 204 ANA_CPUQ_CFG, 205 ANA_CPUQ_CFG2, 206 ANA_CPUQ_8021_CFG, 207 ANA_DSCP_CFG, 208 ANA_DSCP_REWR_CFG, 209 ANA_VCAP_RNG_TYPE_CFG, 210 ANA_VCAP_RNG_VAL_CFG, 211 ANA_VRAP_CFG, 212 ANA_VRAP_HDR_DATA, 213 ANA_VRAP_HDR_MASK, 214 ANA_DISCARD_CFG, 215 ANA_FID_CFG, 216 ANA_POL_PIR_CFG, 217 ANA_POL_CIR_CFG, 218 ANA_POL_MODE_CFG, 219 ANA_POL_PIR_STATE, 220 ANA_POL_CIR_STATE, 221 ANA_POL_STATE, 222 ANA_POL_FLOWC, 223 ANA_POL_HYST, 224 ANA_POL_MISC_CFG, 225 QS_XTR_GRP_CFG = QS << TARGET_OFFSET, 226 QS_XTR_RD, 227 QS_XTR_FRM_PRUNING, 228 QS_XTR_FLUSH, 229 QS_XTR_DATA_PRESENT, 230 QS_XTR_CFG, 231 QS_INJ_GRP_CFG, 232 QS_INJ_WR, 233 QS_INJ_CTRL, 234 QS_INJ_STATUS, 235 QS_INJ_ERR, 236 QS_INH_DBG, 237 QSYS_PORT_MODE = QSYS << TARGET_OFFSET, 238 QSYS_SWITCH_PORT_MODE, 239 QSYS_STAT_CNT_CFG, 240 QSYS_EEE_CFG, 241 QSYS_EEE_THRES, 242 QSYS_IGR_NO_SHARING, 243 QSYS_EGR_NO_SHARING, 244 QSYS_SW_STATUS, 245 QSYS_EXT_CPU_CFG, 246 QSYS_PAD_CFG, 247 QSYS_CPU_GROUP_MAP, 248 QSYS_QMAP, 249 QSYS_ISDX_SGRP, 250 QSYS_TIMED_FRAME_ENTRY, 251 QSYS_TFRM_MISC, 252 QSYS_TFRM_PORT_DLY, 253 QSYS_TFRM_TIMER_CFG_1, 254 QSYS_TFRM_TIMER_CFG_2, 255 QSYS_TFRM_TIMER_CFG_3, 256 QSYS_TFRM_TIMER_CFG_4, 257 QSYS_TFRM_TIMER_CFG_5, 258 QSYS_TFRM_TIMER_CFG_6, 259 QSYS_TFRM_TIMER_CFG_7, 260 QSYS_TFRM_TIMER_CFG_8, 261 QSYS_RED_PROFILE, 262 QSYS_RES_QOS_MODE, 263 QSYS_RES_CFG, 264 QSYS_RES_STAT, 265 QSYS_EGR_DROP_MODE, 266 QSYS_EQ_CTRL, 267 QSYS_EVENTS_CORE, 268 QSYS_QMAXSDU_CFG_0, 269 QSYS_QMAXSDU_CFG_1, 270 QSYS_QMAXSDU_CFG_2, 271 QSYS_QMAXSDU_CFG_3, 272 QSYS_QMAXSDU_CFG_4, 273 QSYS_QMAXSDU_CFG_5, 274 QSYS_QMAXSDU_CFG_6, 275 QSYS_QMAXSDU_CFG_7, 276 QSYS_PREEMPTION_CFG, 277 QSYS_CIR_CFG, 278 QSYS_EIR_CFG, 279 QSYS_SE_CFG, 280 QSYS_SE_DWRR_CFG, 281 QSYS_SE_CONNECT, 282 QSYS_SE_DLB_SENSE, 283 QSYS_CIR_STATE, 284 QSYS_EIR_STATE, 285 QSYS_SE_STATE, 286 QSYS_HSCH_MISC_CFG, 287 QSYS_TAG_CONFIG, 288 QSYS_TAS_PARAM_CFG_CTRL, 289 QSYS_PORT_MAX_SDU, 290 QSYS_PARAM_CFG_REG_1, 291 QSYS_PARAM_CFG_REG_2, 292 QSYS_PARAM_CFG_REG_3, 293 QSYS_PARAM_CFG_REG_4, 294 QSYS_PARAM_CFG_REG_5, 295 QSYS_GCL_CFG_REG_1, 296 QSYS_GCL_CFG_REG_2, 297 QSYS_PARAM_STATUS_REG_1, 298 QSYS_PARAM_STATUS_REG_2, 299 QSYS_PARAM_STATUS_REG_3, 300 QSYS_PARAM_STATUS_REG_4, 301 QSYS_PARAM_STATUS_REG_5, 302 QSYS_PARAM_STATUS_REG_6, 303 QSYS_PARAM_STATUS_REG_7, 304 QSYS_PARAM_STATUS_REG_8, 305 QSYS_PARAM_STATUS_REG_9, 306 QSYS_GCL_STATUS_REG_1, 307 QSYS_GCL_STATUS_REG_2, 308 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET, 309 REW_TAG_CFG, 310 REW_PORT_CFG, 311 REW_DSCP_CFG, 312 REW_PCP_DEI_QOS_MAP_CFG, 313 REW_PTP_CFG, 314 REW_PTP_DLY1_CFG, 315 REW_RED_TAG_CFG, 316 REW_DSCP_REMAP_DP1_CFG, 317 REW_DSCP_REMAP_CFG, 318 REW_STAT_CFG, 319 REW_REW_STICKY, 320 REW_PPT, 321 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET, 322 SYS_COUNT_RX_UNICAST, 323 SYS_COUNT_RX_MULTICAST, 324 SYS_COUNT_RX_BROADCAST, 325 SYS_COUNT_RX_SHORTS, 326 SYS_COUNT_RX_FRAGMENTS, 327 SYS_COUNT_RX_JABBERS, 328 SYS_COUNT_RX_CRC_ALIGN_ERRS, 329 SYS_COUNT_RX_SYM_ERRS, 330 SYS_COUNT_RX_64, 331 SYS_COUNT_RX_65_127, 332 SYS_COUNT_RX_128_255, 333 SYS_COUNT_RX_256_1023, 334 SYS_COUNT_RX_1024_1526, 335 SYS_COUNT_RX_1527_MAX, 336 SYS_COUNT_RX_PAUSE, 337 SYS_COUNT_RX_CONTROL, 338 SYS_COUNT_RX_LONGS, 339 SYS_COUNT_RX_CLASSIFIED_DROPS, 340 SYS_COUNT_TX_OCTETS, 341 SYS_COUNT_TX_UNICAST, 342 SYS_COUNT_TX_MULTICAST, 343 SYS_COUNT_TX_BROADCAST, 344 SYS_COUNT_TX_COLLISION, 345 SYS_COUNT_TX_DROPS, 346 SYS_COUNT_TX_PAUSE, 347 SYS_COUNT_TX_64, 348 SYS_COUNT_TX_65_127, 349 SYS_COUNT_TX_128_511, 350 SYS_COUNT_TX_512_1023, 351 SYS_COUNT_TX_1024_1526, 352 SYS_COUNT_TX_1527_MAX, 353 SYS_COUNT_TX_AGING, 354 SYS_RESET_CFG, 355 SYS_SR_ETYPE_CFG, 356 SYS_VLAN_ETYPE_CFG, 357 SYS_PORT_MODE, 358 SYS_FRONT_PORT_MODE, 359 SYS_FRM_AGING, 360 SYS_STAT_CFG, 361 SYS_SW_STATUS, 362 SYS_MISC_CFG, 363 SYS_REW_MAC_HIGH_CFG, 364 SYS_REW_MAC_LOW_CFG, 365 SYS_TIMESTAMP_OFFSET, 366 SYS_CMID, 367 SYS_PAUSE_CFG, 368 SYS_PAUSE_TOT_CFG, 369 SYS_ATOP, 370 SYS_ATOP_TOT_CFG, 371 SYS_MAC_FC_CFG, 372 SYS_MMGT, 373 SYS_MMGT_FAST, 374 SYS_EVENTS_DIF, 375 SYS_EVENTS_CORE, 376 SYS_CNT, 377 SYS_PTP_STATUS, 378 SYS_PTP_TXSTAMP, 379 SYS_PTP_NXT, 380 SYS_PTP_CFG, 381 SYS_RAM_INIT, 382 SYS_CM_ADDR, 383 SYS_CM_DATA_WR, 384 SYS_CM_DATA_RD, 385 SYS_CM_OP, 386 SYS_CM_DATA, 387 PTP_PIN_CFG = PTP << TARGET_OFFSET, 388 PTP_PIN_TOD_SEC_MSB, 389 PTP_PIN_TOD_SEC_LSB, 390 PTP_PIN_TOD_NSEC, 391 PTP_PIN_WF_HIGH_PERIOD, 392 PTP_PIN_WF_LOW_PERIOD, 393 PTP_CFG_MISC, 394 PTP_CLK_CFG_ADJ_CFG, 395 PTP_CLK_CFG_ADJ_FREQ, 396 GCB_SOFT_RST = GCB << TARGET_OFFSET, 397 GCB_MIIM_MII_STATUS, 398 GCB_MIIM_MII_CMD, 399 GCB_MIIM_MII_DATA, 400 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, 401 DEV_PORT_MISC, 402 DEV_EVENTS, 403 DEV_EEE_CFG, 404 DEV_RX_PATH_DELAY, 405 DEV_TX_PATH_DELAY, 406 DEV_PTP_PREDICT_CFG, 407 DEV_MAC_ENA_CFG, 408 DEV_MAC_MODE_CFG, 409 DEV_MAC_MAXLEN_CFG, 410 DEV_MAC_TAGS_CFG, 411 DEV_MAC_ADV_CHK_CFG, 412 DEV_MAC_IFG_CFG, 413 DEV_MAC_HDX_CFG, 414 DEV_MAC_DBG_CFG, 415 DEV_MAC_FC_MAC_LOW_CFG, 416 DEV_MAC_FC_MAC_HIGH_CFG, 417 DEV_MAC_STICKY, 418 PCS1G_CFG, 419 PCS1G_MODE_CFG, 420 PCS1G_SD_CFG, 421 PCS1G_ANEG_CFG, 422 PCS1G_ANEG_NP_CFG, 423 PCS1G_LB_CFG, 424 PCS1G_DBG_CFG, 425 PCS1G_CDET_CFG, 426 PCS1G_ANEG_STATUS, 427 PCS1G_ANEG_NP_STATUS, 428 PCS1G_LINK_STATUS, 429 PCS1G_LINK_DOWN_CNT, 430 PCS1G_STICKY, 431 PCS1G_DEBUG_STATUS, 432 PCS1G_LPI_CFG, 433 PCS1G_LPI_WAKE_ERROR_CNT, 434 PCS1G_LPI_STATUS, 435 PCS1G_TSTPAT_MODE_CFG, 436 PCS1G_TSTPAT_STATUS, 437 DEV_PCS_FX100_CFG, 438 DEV_PCS_FX100_STATUS, 439 }; 440 441 enum ocelot_regfield { 442 ANA_ADVLEARN_VLAN_CHK, 443 ANA_ADVLEARN_LEARN_MIRROR, 444 ANA_ANEVENTS_FLOOD_DISCARD, 445 ANA_ANEVENTS_MSTI_DROP, 446 ANA_ANEVENTS_ACLKILL, 447 ANA_ANEVENTS_ACLUSED, 448 ANA_ANEVENTS_AUTOAGE, 449 ANA_ANEVENTS_VS2TTL1, 450 ANA_ANEVENTS_STORM_DROP, 451 ANA_ANEVENTS_LEARN_DROP, 452 ANA_ANEVENTS_AGED_ENTRY, 453 ANA_ANEVENTS_CPU_LEARN_FAILED, 454 ANA_ANEVENTS_AUTO_LEARN_FAILED, 455 ANA_ANEVENTS_LEARN_REMOVE, 456 ANA_ANEVENTS_AUTO_LEARNED, 457 ANA_ANEVENTS_AUTO_MOVED, 458 ANA_ANEVENTS_DROPPED, 459 ANA_ANEVENTS_CLASSIFIED_DROP, 460 ANA_ANEVENTS_CLASSIFIED_COPY, 461 ANA_ANEVENTS_VLAN_DISCARD, 462 ANA_ANEVENTS_FWD_DISCARD, 463 ANA_ANEVENTS_MULTICAST_FLOOD, 464 ANA_ANEVENTS_UNICAST_FLOOD, 465 ANA_ANEVENTS_DEST_KNOWN, 466 ANA_ANEVENTS_BUCKET3_MATCH, 467 ANA_ANEVENTS_BUCKET2_MATCH, 468 ANA_ANEVENTS_BUCKET1_MATCH, 469 ANA_ANEVENTS_BUCKET0_MATCH, 470 ANA_ANEVENTS_CPU_OPERATION, 471 ANA_ANEVENTS_DMAC_LOOKUP, 472 ANA_ANEVENTS_SMAC_LOOKUP, 473 ANA_ANEVENTS_SEQ_GEN_ERR_0, 474 ANA_ANEVENTS_SEQ_GEN_ERR_1, 475 ANA_TABLES_MACACCESS_B_DOM, 476 ANA_TABLES_MACTINDX_BUCKET, 477 ANA_TABLES_MACTINDX_M_INDEX, 478 QSYS_SWITCH_PORT_MODE_PORT_ENA, 479 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG, 480 QSYS_SWITCH_PORT_MODE_YEL_RSRVD, 481 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE, 482 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 483 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE, 484 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD, 485 QSYS_TIMED_FRAME_ENTRY_TFRM_FP, 486 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO, 487 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL, 488 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T, 489 SYS_PORT_MODE_DATA_WO_TS, 490 SYS_PORT_MODE_INCL_INJ_HDR, 491 SYS_PORT_MODE_INCL_XTR_HDR, 492 SYS_PORT_MODE_INCL_HDR_ERR, 493 SYS_RESET_CFG_CORE_ENA, 494 SYS_RESET_CFG_MEM_ENA, 495 SYS_RESET_CFG_MEM_INIT, 496 GCB_SOFT_RST_SWC_RST, 497 GCB_MIIM_MII_STATUS_PENDING, 498 GCB_MIIM_MII_STATUS_BUSY, 499 SYS_PAUSE_CFG_PAUSE_START, 500 SYS_PAUSE_CFG_PAUSE_STOP, 501 SYS_PAUSE_CFG_PAUSE_ENA, 502 REGFIELD_MAX 503 }; 504 505 enum { 506 /* VCAP_CORE_CFG */ 507 VCAP_CORE_UPDATE_CTRL, 508 VCAP_CORE_MV_CFG, 509 /* VCAP_CORE_CACHE */ 510 VCAP_CACHE_ENTRY_DAT, 511 VCAP_CACHE_MASK_DAT, 512 VCAP_CACHE_ACTION_DAT, 513 VCAP_CACHE_CNT_DAT, 514 VCAP_CACHE_TG_DAT, 515 /* VCAP_CONST */ 516 VCAP_CONST_VCAP_VER, 517 VCAP_CONST_ENTRY_WIDTH, 518 VCAP_CONST_ENTRY_CNT, 519 VCAP_CONST_ENTRY_SWCNT, 520 VCAP_CONST_ENTRY_TG_WIDTH, 521 VCAP_CONST_ACTION_DEF_CNT, 522 VCAP_CONST_ACTION_WIDTH, 523 VCAP_CONST_CNT_WIDTH, 524 VCAP_CONST_CORE_CNT, 525 VCAP_CONST_IF_CNT, 526 }; 527 528 enum ocelot_ptp_pins { 529 PTP_PIN_0, 530 PTP_PIN_1, 531 PTP_PIN_2, 532 PTP_PIN_3, 533 TOD_ACC_PIN 534 }; 535 536 struct ocelot_stat_layout { 537 u32 offset; 538 char name[ETH_GSTRING_LEN]; 539 }; 540 541 struct ocelot_stats_region { 542 struct list_head node; 543 u32 offset; 544 int count; 545 u32 *buf; 546 }; 547 548 enum ocelot_tag_prefix { 549 OCELOT_TAG_PREFIX_DISABLED = 0, 550 OCELOT_TAG_PREFIX_NONE, 551 OCELOT_TAG_PREFIX_SHORT, 552 OCELOT_TAG_PREFIX_LONG, 553 }; 554 555 struct ocelot; 556 557 struct ocelot_ops { 558 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port); 559 int (*netdev_to_port)(struct net_device *dev); 560 int (*reset)(struct ocelot *ocelot); 561 u16 (*wm_enc)(u16 value); 562 u16 (*wm_dec)(u16 value); 563 void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse); 564 void (*psfp_init)(struct ocelot *ocelot); 565 int (*psfp_filter_add)(struct ocelot *ocelot, int port, 566 struct flow_cls_offload *f); 567 int (*psfp_filter_del)(struct ocelot *ocelot, struct flow_cls_offload *f); 568 int (*psfp_stats_get)(struct ocelot *ocelot, struct flow_cls_offload *f, 569 struct flow_stats *stats); 570 void (*cut_through_fwd)(struct ocelot *ocelot); 571 }; 572 573 struct ocelot_vcap_policer { 574 struct list_head pol_list; 575 u16 base; 576 u16 max; 577 u16 base2; 578 u16 max2; 579 }; 580 581 struct ocelot_vcap_block { 582 struct list_head rules; 583 int count; 584 }; 585 586 struct ocelot_bridge_vlan { 587 u16 vid; 588 unsigned long portmask; 589 unsigned long untagged; 590 struct list_head list; 591 }; 592 593 enum ocelot_port_tag_config { 594 /* all VLANs are egress-untagged */ 595 OCELOT_PORT_TAG_DISABLED = 0, 596 /* all VLANs except the native VLAN and VID 0 are egress-tagged */ 597 OCELOT_PORT_TAG_NATIVE = 1, 598 /* all VLANs except VID 0 are egress-tagged */ 599 OCELOT_PORT_TAG_TRUNK_NO_VID0 = 2, 600 /* all VLANs are egress-tagged */ 601 OCELOT_PORT_TAG_TRUNK = 3, 602 }; 603 604 struct ocelot_psfp_list { 605 struct list_head stream_list; 606 struct list_head sfi_list; 607 struct list_head sgi_list; 608 }; 609 610 enum ocelot_sb { 611 OCELOT_SB_BUF, 612 OCELOT_SB_REF, 613 OCELOT_SB_NUM, 614 }; 615 616 enum ocelot_sb_pool { 617 OCELOT_SB_POOL_ING, 618 OCELOT_SB_POOL_EGR, 619 OCELOT_SB_POOL_NUM, 620 }; 621 622 /* MAC table entry types. 623 * ENTRYTYPE_NORMAL is subject to aging. 624 * ENTRYTYPE_LOCKED is not subject to aging. 625 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 626 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 627 */ 628 enum macaccess_entry_type { 629 ENTRYTYPE_NORMAL = 0, 630 ENTRYTYPE_LOCKED, 631 ENTRYTYPE_MACv4, 632 ENTRYTYPE_MACv6, 633 }; 634 635 #define OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION BIT(0) 636 #define OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP BIT(1) 637 638 struct ocelot_lag_fdb { 639 unsigned char addr[ETH_ALEN]; 640 u16 vid; 641 struct net_device *bond; 642 struct list_head list; 643 }; 644 645 struct ocelot_mirror { 646 refcount_t refcount; 647 int to; 648 }; 649 650 struct ocelot_port { 651 struct ocelot *ocelot; 652 653 struct regmap *target; 654 655 bool vlan_aware; 656 /* VLAN that untagged frames are classified to, on ingress */ 657 const struct ocelot_bridge_vlan *pvid_vlan; 658 659 unsigned int ptp_skbs_in_flight; 660 u8 ptp_cmd; 661 struct sk_buff_head tx_skbs; 662 u8 ts_id; 663 664 phy_interface_t phy_mode; 665 666 u8 *xmit_template; 667 bool is_dsa_8021q_cpu; 668 bool learn_ena; 669 670 struct net_device *bond; 671 bool lag_tx_active; 672 673 u16 mrp_ring_id; 674 675 struct net_device *bridge; 676 int bridge_num; 677 u8 stp_state; 678 679 int speed; 680 }; 681 682 struct ocelot { 683 struct device *dev; 684 struct devlink *devlink; 685 struct devlink_port *devlink_ports; 686 687 const struct ocelot_ops *ops; 688 struct regmap *targets[TARGET_MAX]; 689 struct regmap_field *regfields[REGFIELD_MAX]; 690 const u32 *const *map; 691 const struct ocelot_stat_layout *stats_layout; 692 struct list_head stats_regions; 693 unsigned int num_stats; 694 695 u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM]; 696 int packet_buffer_size; 697 int num_frame_refs; 698 int num_mact_rows; 699 700 struct ocelot_port **ports; 701 702 u8 base_mac[ETH_ALEN]; 703 704 struct list_head vlans; 705 struct list_head traps; 706 struct list_head lag_fdbs; 707 708 /* Switches like VSC9959 have flooding per traffic class */ 709 int num_flooding_pgids; 710 711 /* In tables like ANA:PORT and the ANA:PGID:PGID mask, 712 * the CPU is located after the physical ports (at the 713 * num_phys_ports index). 714 */ 715 u8 num_phys_ports; 716 717 int npi; 718 719 enum ocelot_tag_prefix npi_inj_prefix; 720 enum ocelot_tag_prefix npi_xtr_prefix; 721 722 unsigned long bridges; 723 724 struct list_head multicast; 725 struct list_head pgids; 726 727 struct list_head dummy_rules; 728 struct ocelot_vcap_block block[3]; 729 struct ocelot_vcap_policer vcap_pol; 730 struct vcap_props *vcap; 731 struct ocelot_mirror *mirror; 732 733 struct ocelot_psfp_list psfp; 734 735 /* Workqueue to check statistics for overflow with its lock */ 736 struct mutex stats_lock; 737 u64 *stats; 738 struct delayed_work stats_work; 739 struct workqueue_struct *stats_queue; 740 741 /* Lock for serializing access to the MAC table */ 742 struct mutex mact_lock; 743 /* Lock for serializing forwarding domain changes */ 744 struct mutex fwd_domain_lock; 745 746 struct workqueue_struct *owq; 747 748 u8 ptp:1; 749 struct ptp_clock *ptp_clock; 750 struct ptp_clock_info ptp_info; 751 struct hwtstamp_config hwtstamp_config; 752 unsigned int ptp_skbs_in_flight; 753 /* Protects the 2-step TX timestamp ID logic */ 754 spinlock_t ts_id_lock; 755 /* Protects the PTP interface state */ 756 struct mutex ptp_lock; 757 /* Protects the PTP clock */ 758 spinlock_t ptp_clock_lock; 759 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM]; 760 761 struct ocelot_fdma *fdma; 762 }; 763 764 struct ocelot_policer { 765 u32 rate; /* kilobit per second */ 766 u32 burst; /* bytes */ 767 }; 768 769 #define ocelot_bulk_read_rix(ocelot, reg, ri, buf, count) \ 770 __ocelot_bulk_read_ix(ocelot, reg, reg##_RSZ * (ri), buf, count) 771 772 #define ocelot_read_ix(ocelot, reg, gi, ri) \ 773 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 774 #define ocelot_read_gix(ocelot, reg, gi) \ 775 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) 776 #define ocelot_read_rix(ocelot, reg, ri) \ 777 __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) 778 #define ocelot_read(ocelot, reg) \ 779 __ocelot_read_ix(ocelot, reg, 0) 780 781 #define ocelot_write_ix(ocelot, val, reg, gi, ri) \ 782 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 783 #define ocelot_write_gix(ocelot, val, reg, gi) \ 784 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) 785 #define ocelot_write_rix(ocelot, val, reg, ri) \ 786 __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) 787 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) 788 789 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) \ 790 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 791 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) \ 792 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) 793 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) \ 794 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) 795 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) 796 797 #define ocelot_field_write(ocelot, reg, val) \ 798 regmap_field_write((ocelot)->regfields[(reg)], (val)) 799 #define ocelot_field_read(ocelot, reg, val) \ 800 regmap_field_read((ocelot)->regfields[(reg)], (val)) 801 #define ocelot_fields_write(ocelot, id, reg, val) \ 802 regmap_fields_write((ocelot)->regfields[(reg)], (id), (val)) 803 #define ocelot_fields_read(ocelot, id, reg, val) \ 804 regmap_fields_read((ocelot)->regfields[(reg)], (id), (val)) 805 806 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \ 807 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 808 #define ocelot_target_read_gix(ocelot, target, reg, gi) \ 809 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi)) 810 #define ocelot_target_read_rix(ocelot, target, reg, ri) \ 811 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri)) 812 #define ocelot_target_read(ocelot, target, reg) \ 813 __ocelot_target_read_ix(ocelot, target, reg, 0) 814 815 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \ 816 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 817 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \ 818 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi)) 819 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \ 820 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri)) 821 #define ocelot_target_write(ocelot, target, val, reg) \ 822 __ocelot_target_write_ix(ocelot, target, val, reg, 0) 823 824 /* I/O */ 825 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); 826 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); 827 void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, u32 reg); 828 int __ocelot_bulk_read_ix(struct ocelot *ocelot, u32 reg, u32 offset, void *buf, 829 int count); 830 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); 831 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); 832 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, 833 u32 offset); 834 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target, 835 u32 reg, u32 offset); 836 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target, 837 u32 val, u32 reg, u32 offset); 838 839 /* Packet I/O */ 840 bool ocelot_can_inject(struct ocelot *ocelot, int grp); 841 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 842 u32 rew_op, struct sk_buff *skb); 843 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag); 844 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb); 845 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp); 846 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb, 847 u64 timestamp); 848 849 /* Hardware initialization */ 850 int ocelot_regfields_init(struct ocelot *ocelot, 851 const struct reg_field *const regfields); 852 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res); 853 int ocelot_init(struct ocelot *ocelot); 854 void ocelot_deinit(struct ocelot *ocelot); 855 void ocelot_init_port(struct ocelot *ocelot, int port); 856 void ocelot_deinit_port(struct ocelot *ocelot, int port); 857 858 void ocelot_port_set_dsa_8021q_cpu(struct ocelot *ocelot, int port); 859 void ocelot_port_unset_dsa_8021q_cpu(struct ocelot *ocelot, int port); 860 861 /* DSA callbacks */ 862 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data); 863 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data); 864 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset); 865 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 866 struct ethtool_ts_info *info); 867 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs); 868 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled, 869 struct netlink_ext_ack *extack); 870 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state); 871 u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot); 872 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port); 873 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining); 874 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 875 struct switchdev_brport_flags val); 876 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 877 struct switchdev_brport_flags val); 878 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port); 879 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio); 880 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp); 881 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio); 882 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio); 883 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 884 struct net_device *bridge, int bridge_num, 885 struct netlink_ext_ack *extack); 886 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 887 struct net_device *bridge); 888 int ocelot_mact_flush(struct ocelot *ocelot, int port); 889 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 890 dsa_fdb_dump_cb_t *cb, void *data); 891 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr, 892 u16 vid, const struct net_device *bridge); 893 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr, 894 u16 vid, const struct net_device *bridge); 895 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond, 896 const unsigned char *addr, u16 vid, 897 const struct net_device *bridge); 898 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond, 899 const unsigned char *addr, u16 vid, 900 const struct net_device *bridge); 901 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 902 bool untagged, struct netlink_ext_ack *extack); 903 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 904 bool untagged); 905 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid); 906 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr); 907 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr); 908 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 909 struct sk_buff *skb, 910 struct sk_buff **clone); 911 void ocelot_get_txtstamp(struct ocelot *ocelot); 912 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu); 913 int ocelot_get_max_mtu(struct ocelot *ocelot, int port); 914 int ocelot_port_policer_add(struct ocelot *ocelot, int port, 915 struct ocelot_policer *pol); 916 int ocelot_port_policer_del(struct ocelot *ocelot, int port); 917 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to, 918 bool ingress, struct netlink_ext_ack *extack); 919 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress); 920 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port, 921 struct flow_cls_offload *f, bool ingress); 922 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port, 923 struct flow_cls_offload *f, bool ingress); 924 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port, 925 struct flow_cls_offload *f, bool ingress); 926 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 927 const struct switchdev_obj_port_mdb *mdb, 928 const struct net_device *bridge); 929 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 930 const struct switchdev_obj_port_mdb *mdb, 931 const struct net_device *bridge); 932 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 933 struct net_device *bond, 934 struct netdev_lag_upper_info *info); 935 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 936 struct net_device *bond); 937 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active); 938 939 int ocelot_devlink_sb_register(struct ocelot *ocelot); 940 void ocelot_devlink_sb_unregister(struct ocelot *ocelot); 941 int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index, 942 u16 pool_index, 943 struct devlink_sb_pool_info *pool_info); 944 int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index, 945 u16 pool_index, u32 size, 946 enum devlink_sb_threshold_type threshold_type, 947 struct netlink_ext_ack *extack); 948 int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port, 949 unsigned int sb_index, u16 pool_index, 950 u32 *p_threshold); 951 int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port, 952 unsigned int sb_index, u16 pool_index, 953 u32 threshold, struct netlink_ext_ack *extack); 954 int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port, 955 unsigned int sb_index, u16 tc_index, 956 enum devlink_sb_pool_type pool_type, 957 u16 *p_pool_index, u32 *p_threshold); 958 int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port, 959 unsigned int sb_index, u16 tc_index, 960 enum devlink_sb_pool_type pool_type, 961 u16 pool_index, u32 threshold, 962 struct netlink_ext_ack *extack); 963 int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index); 964 int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index); 965 int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port, 966 unsigned int sb_index, u16 pool_index, 967 u32 *p_cur, u32 *p_max); 968 int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port, 969 unsigned int sb_index, u16 tc_index, 970 enum devlink_sb_pool_type pool_type, 971 u32 *p_cur, u32 *p_max); 972 973 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 974 unsigned int link_an_mode, 975 phy_interface_t interface, 976 unsigned long quirks); 977 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 978 struct phy_device *phydev, 979 unsigned int link_an_mode, 980 phy_interface_t interface, 981 int speed, int duplex, 982 bool tx_pause, bool rx_pause, 983 unsigned long quirks); 984 985 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx, 986 const unsigned char mac[ETH_ALEN], 987 unsigned int vid, enum macaccess_entry_type *type); 988 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx, 989 const unsigned char mac[ETH_ALEN], 990 unsigned int vid, 991 enum macaccess_entry_type type, 992 int sfid, int ssid); 993 994 int ocelot_vcap_policer_add(struct ocelot *ocelot, u32 pol_ix, 995 struct ocelot_policer *pol); 996 int ocelot_vcap_policer_del(struct ocelot *ocelot, u32 pol_ix); 997 998 #if IS_ENABLED(CONFIG_BRIDGE_MRP) 999 int ocelot_mrp_add(struct ocelot *ocelot, int port, 1000 const struct switchdev_obj_mrp *mrp); 1001 int ocelot_mrp_del(struct ocelot *ocelot, int port, 1002 const struct switchdev_obj_mrp *mrp); 1003 int ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port, 1004 const struct switchdev_obj_ring_role_mrp *mrp); 1005 int ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, 1006 const struct switchdev_obj_ring_role_mrp *mrp); 1007 #else 1008 static inline int ocelot_mrp_add(struct ocelot *ocelot, int port, 1009 const struct switchdev_obj_mrp *mrp) 1010 { 1011 return -EOPNOTSUPP; 1012 } 1013 1014 static inline int ocelot_mrp_del(struct ocelot *ocelot, int port, 1015 const struct switchdev_obj_mrp *mrp) 1016 { 1017 return -EOPNOTSUPP; 1018 } 1019 1020 static inline int 1021 ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port, 1022 const struct switchdev_obj_ring_role_mrp *mrp) 1023 { 1024 return -EOPNOTSUPP; 1025 } 1026 1027 static inline int 1028 ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, 1029 const struct switchdev_obj_ring_role_mrp *mrp) 1030 { 1031 return -EOPNOTSUPP; 1032 } 1033 #endif 1034 1035 #endif 1036