1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* Copyright (c) 2017 Microsemi Corporation 3 */ 4 5 #ifndef _SOC_MSCC_OCELOT_H 6 #define _SOC_MSCC_OCELOT_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/net_tstamp.h> 10 #include <linux/if_vlan.h> 11 #include <linux/regmap.h> 12 #include <net/dsa.h> 13 14 /* Port Group IDs (PGID) are masks of destination ports. 15 * 16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each 17 * frame, and forwards the frame to the ports that are present in the logical 18 * AND of all 3 PGIDs. 19 * 20 * These PGID lookups are: 21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by 22 * which the switch selects a destination PGID: 23 * - The {DMAC, VID} is present in the MAC table. In that case, the 24 * destination PGID is given by the DEST_IDX field of the MAC table entry 25 * that matched. 26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The 27 * frame is disseminated as being either unicast, multicast or broadcast, 28 * and according to that, the destination PGID is chosen as being the 29 * value contained by ANA_FLOODING_FLD_UNICAST, 30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST. 31 * The destination PGID can be an unicast set: the first PGIDs, 0 to 32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from 33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to 34 * a physical port and has a single bit set in the destination ports mask: 35 * that corresponding to the port number itself. In contrast, a multicast 36 * PGID will have potentially more than one single bit set in the destination 37 * ports mask. 38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier 39 * dissects each frame and generates a 4-bit Link Aggregation Code which is 40 * used for this second PGID table lookup. The goal of link aggregation is to 41 * hash multiple flows within the same LAG on to different destination ports. 42 * The first lookup will result in a PGID with all the LAG members present in 43 * the destination ports mask, and the second lookup, by Link Aggregation 44 * Code, will ensure that each flow gets forwarded only to a single port out 45 * of that mask (there are no duplicates). 46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table 47 * is indexed with the ingress port (plus 80). These PGIDs answer the 48 * question "is port i allowed to forward traffic to port j?" If yes, then 49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used 50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge. 51 */ 52 53 /* Reserve some destination PGIDs at the end of the range: 54 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses 55 * of the switch port net devices, towards the CPU port module. 56 * PGID_UC: the flooding destinations for unknown unicast traffic. 57 * PGID_MC: the flooding destinations for non-IP multicast traffic. 58 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic. 59 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic. 60 * PGID_BC: the flooding destinations for broadcast traffic. 61 */ 62 #define PGID_CPU 58 63 #define PGID_UC 59 64 #define PGID_MC 60 65 #define PGID_MCIPV4 61 66 #define PGID_MCIPV6 62 67 #define PGID_BC 63 68 69 #define for_each_unicast_dest_pgid(ocelot, pgid) \ 70 for ((pgid) = 0; \ 71 (pgid) < (ocelot)->num_phys_ports; \ 72 (pgid)++) 73 74 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \ 75 for ((pgid) = (ocelot)->num_phys_ports + 1; \ 76 (pgid) < PGID_CPU; \ 77 (pgid)++) 78 79 #define for_each_aggr_pgid(ocelot, pgid) \ 80 for ((pgid) = PGID_AGGR; \ 81 (pgid) < PGID_SRC; \ 82 (pgid)++) 83 84 /* Aggregation PGIDs, one per Link Aggregation Code */ 85 #define PGID_AGGR 64 86 87 /* Source PGIDs, one per physical port */ 88 #define PGID_SRC 80 89 90 #define IFH_TAG_TYPE_C 0 91 #define IFH_TAG_TYPE_S 1 92 93 #define IFH_REW_OP_NOOP 0x0 94 #define IFH_REW_OP_DSCP 0x1 95 #define IFH_REW_OP_ONE_STEP_PTP 0x2 96 #define IFH_REW_OP_TWO_STEP_PTP 0x3 97 #define IFH_REW_OP_ORIGIN_PTP 0x5 98 99 #define OCELOT_NUM_TC 8 100 101 #define OCELOT_SPEED_2500 0 102 #define OCELOT_SPEED_1000 1 103 #define OCELOT_SPEED_100 2 104 #define OCELOT_SPEED_10 3 105 106 #define OCELOT_PTP_PINS_NUM 4 107 108 #define TARGET_OFFSET 24 109 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0) 110 #define REG(reg, offset) [reg & REG_MASK] = offset 111 112 #define REG_RESERVED_ADDR 0xffffffff 113 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR) 114 115 #define OCELOT_MRP_CPUQ 7 116 117 enum ocelot_target { 118 ANA = 1, 119 QS, 120 QSYS, 121 REW, 122 SYS, 123 S0, 124 S1, 125 S2, 126 HSIO, 127 PTP, 128 GCB, 129 DEV_GMII, 130 TARGET_MAX, 131 }; 132 133 enum ocelot_reg { 134 ANA_ADVLEARN = ANA << TARGET_OFFSET, 135 ANA_VLANMASK, 136 ANA_PORT_B_DOMAIN, 137 ANA_ANAGEFIL, 138 ANA_ANEVENTS, 139 ANA_STORMLIMIT_BURST, 140 ANA_STORMLIMIT_CFG, 141 ANA_ISOLATED_PORTS, 142 ANA_COMMUNITY_PORTS, 143 ANA_AUTOAGE, 144 ANA_MACTOPTIONS, 145 ANA_LEARNDISC, 146 ANA_AGENCTRL, 147 ANA_MIRRORPORTS, 148 ANA_EMIRRORPORTS, 149 ANA_FLOODING, 150 ANA_FLOODING_IPMC, 151 ANA_SFLOW_CFG, 152 ANA_PORT_MODE, 153 ANA_CUT_THRU_CFG, 154 ANA_PGID_PGID, 155 ANA_TABLES_ANMOVED, 156 ANA_TABLES_MACHDATA, 157 ANA_TABLES_MACLDATA, 158 ANA_TABLES_STREAMDATA, 159 ANA_TABLES_MACACCESS, 160 ANA_TABLES_MACTINDX, 161 ANA_TABLES_VLANACCESS, 162 ANA_TABLES_VLANTIDX, 163 ANA_TABLES_ISDXACCESS, 164 ANA_TABLES_ISDXTIDX, 165 ANA_TABLES_ENTRYLIM, 166 ANA_TABLES_PTP_ID_HIGH, 167 ANA_TABLES_PTP_ID_LOW, 168 ANA_TABLES_STREAMACCESS, 169 ANA_TABLES_STREAMTIDX, 170 ANA_TABLES_SEQ_HISTORY, 171 ANA_TABLES_SEQ_MASK, 172 ANA_TABLES_SFID_MASK, 173 ANA_TABLES_SFIDACCESS, 174 ANA_TABLES_SFIDTIDX, 175 ANA_MSTI_STATE, 176 ANA_OAM_UPM_LM_CNT, 177 ANA_SG_ACCESS_CTRL, 178 ANA_SG_CONFIG_REG_1, 179 ANA_SG_CONFIG_REG_2, 180 ANA_SG_CONFIG_REG_3, 181 ANA_SG_CONFIG_REG_4, 182 ANA_SG_CONFIG_REG_5, 183 ANA_SG_GCL_GS_CONFIG, 184 ANA_SG_GCL_TI_CONFIG, 185 ANA_SG_STATUS_REG_1, 186 ANA_SG_STATUS_REG_2, 187 ANA_SG_STATUS_REG_3, 188 ANA_PORT_VLAN_CFG, 189 ANA_PORT_DROP_CFG, 190 ANA_PORT_QOS_CFG, 191 ANA_PORT_VCAP_CFG, 192 ANA_PORT_VCAP_S1_KEY_CFG, 193 ANA_PORT_VCAP_S2_CFG, 194 ANA_PORT_PCP_DEI_MAP, 195 ANA_PORT_CPU_FWD_CFG, 196 ANA_PORT_CPU_FWD_BPDU_CFG, 197 ANA_PORT_CPU_FWD_GARP_CFG, 198 ANA_PORT_CPU_FWD_CCM_CFG, 199 ANA_PORT_PORT_CFG, 200 ANA_PORT_POL_CFG, 201 ANA_PORT_PTP_CFG, 202 ANA_PORT_PTP_DLY1_CFG, 203 ANA_PORT_PTP_DLY2_CFG, 204 ANA_PORT_SFID_CFG, 205 ANA_PFC_PFC_CFG, 206 ANA_PFC_PFC_TIMER, 207 ANA_IPT_OAM_MEP_CFG, 208 ANA_IPT_IPT, 209 ANA_PPT_PPT, 210 ANA_FID_MAP_FID_MAP, 211 ANA_AGGR_CFG, 212 ANA_CPUQ_CFG, 213 ANA_CPUQ_CFG2, 214 ANA_CPUQ_8021_CFG, 215 ANA_DSCP_CFG, 216 ANA_DSCP_REWR_CFG, 217 ANA_VCAP_RNG_TYPE_CFG, 218 ANA_VCAP_RNG_VAL_CFG, 219 ANA_VRAP_CFG, 220 ANA_VRAP_HDR_DATA, 221 ANA_VRAP_HDR_MASK, 222 ANA_DISCARD_CFG, 223 ANA_FID_CFG, 224 ANA_POL_PIR_CFG, 225 ANA_POL_CIR_CFG, 226 ANA_POL_MODE_CFG, 227 ANA_POL_PIR_STATE, 228 ANA_POL_CIR_STATE, 229 ANA_POL_STATE, 230 ANA_POL_FLOWC, 231 ANA_POL_HYST, 232 ANA_POL_MISC_CFG, 233 QS_XTR_GRP_CFG = QS << TARGET_OFFSET, 234 QS_XTR_RD, 235 QS_XTR_FRM_PRUNING, 236 QS_XTR_FLUSH, 237 QS_XTR_DATA_PRESENT, 238 QS_XTR_CFG, 239 QS_INJ_GRP_CFG, 240 QS_INJ_WR, 241 QS_INJ_CTRL, 242 QS_INJ_STATUS, 243 QS_INJ_ERR, 244 QS_INH_DBG, 245 QSYS_PORT_MODE = QSYS << TARGET_OFFSET, 246 QSYS_SWITCH_PORT_MODE, 247 QSYS_STAT_CNT_CFG, 248 QSYS_EEE_CFG, 249 QSYS_EEE_THRES, 250 QSYS_IGR_NO_SHARING, 251 QSYS_EGR_NO_SHARING, 252 QSYS_SW_STATUS, 253 QSYS_EXT_CPU_CFG, 254 QSYS_PAD_CFG, 255 QSYS_CPU_GROUP_MAP, 256 QSYS_QMAP, 257 QSYS_ISDX_SGRP, 258 QSYS_TIMED_FRAME_ENTRY, 259 QSYS_TFRM_MISC, 260 QSYS_TFRM_PORT_DLY, 261 QSYS_TFRM_TIMER_CFG_1, 262 QSYS_TFRM_TIMER_CFG_2, 263 QSYS_TFRM_TIMER_CFG_3, 264 QSYS_TFRM_TIMER_CFG_4, 265 QSYS_TFRM_TIMER_CFG_5, 266 QSYS_TFRM_TIMER_CFG_6, 267 QSYS_TFRM_TIMER_CFG_7, 268 QSYS_TFRM_TIMER_CFG_8, 269 QSYS_RED_PROFILE, 270 QSYS_RES_QOS_MODE, 271 QSYS_RES_CFG, 272 QSYS_RES_STAT, 273 QSYS_EGR_DROP_MODE, 274 QSYS_EQ_CTRL, 275 QSYS_EVENTS_CORE, 276 QSYS_QMAXSDU_CFG_0, 277 QSYS_QMAXSDU_CFG_1, 278 QSYS_QMAXSDU_CFG_2, 279 QSYS_QMAXSDU_CFG_3, 280 QSYS_QMAXSDU_CFG_4, 281 QSYS_QMAXSDU_CFG_5, 282 QSYS_QMAXSDU_CFG_6, 283 QSYS_QMAXSDU_CFG_7, 284 QSYS_PREEMPTION_CFG, 285 QSYS_CIR_CFG, 286 QSYS_EIR_CFG, 287 QSYS_SE_CFG, 288 QSYS_SE_DWRR_CFG, 289 QSYS_SE_CONNECT, 290 QSYS_SE_DLB_SENSE, 291 QSYS_CIR_STATE, 292 QSYS_EIR_STATE, 293 QSYS_SE_STATE, 294 QSYS_HSCH_MISC_CFG, 295 QSYS_TAG_CONFIG, 296 QSYS_TAS_PARAM_CFG_CTRL, 297 QSYS_PORT_MAX_SDU, 298 QSYS_PARAM_CFG_REG_1, 299 QSYS_PARAM_CFG_REG_2, 300 QSYS_PARAM_CFG_REG_3, 301 QSYS_PARAM_CFG_REG_4, 302 QSYS_PARAM_CFG_REG_5, 303 QSYS_GCL_CFG_REG_1, 304 QSYS_GCL_CFG_REG_2, 305 QSYS_PARAM_STATUS_REG_1, 306 QSYS_PARAM_STATUS_REG_2, 307 QSYS_PARAM_STATUS_REG_3, 308 QSYS_PARAM_STATUS_REG_4, 309 QSYS_PARAM_STATUS_REG_5, 310 QSYS_PARAM_STATUS_REG_6, 311 QSYS_PARAM_STATUS_REG_7, 312 QSYS_PARAM_STATUS_REG_8, 313 QSYS_PARAM_STATUS_REG_9, 314 QSYS_GCL_STATUS_REG_1, 315 QSYS_GCL_STATUS_REG_2, 316 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET, 317 REW_TAG_CFG, 318 REW_PORT_CFG, 319 REW_DSCP_CFG, 320 REW_PCP_DEI_QOS_MAP_CFG, 321 REW_PTP_CFG, 322 REW_PTP_DLY1_CFG, 323 REW_RED_TAG_CFG, 324 REW_DSCP_REMAP_DP1_CFG, 325 REW_DSCP_REMAP_CFG, 326 REW_STAT_CFG, 327 REW_REW_STICKY, 328 REW_PPT, 329 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET, 330 SYS_COUNT_RX_UNICAST, 331 SYS_COUNT_RX_MULTICAST, 332 SYS_COUNT_RX_BROADCAST, 333 SYS_COUNT_RX_SHORTS, 334 SYS_COUNT_RX_FRAGMENTS, 335 SYS_COUNT_RX_JABBERS, 336 SYS_COUNT_RX_CRC_ALIGN_ERRS, 337 SYS_COUNT_RX_SYM_ERRS, 338 SYS_COUNT_RX_64, 339 SYS_COUNT_RX_65_127, 340 SYS_COUNT_RX_128_255, 341 SYS_COUNT_RX_256_1023, 342 SYS_COUNT_RX_1024_1526, 343 SYS_COUNT_RX_1527_MAX, 344 SYS_COUNT_RX_PAUSE, 345 SYS_COUNT_RX_CONTROL, 346 SYS_COUNT_RX_LONGS, 347 SYS_COUNT_RX_CLASSIFIED_DROPS, 348 SYS_COUNT_TX_OCTETS, 349 SYS_COUNT_TX_UNICAST, 350 SYS_COUNT_TX_MULTICAST, 351 SYS_COUNT_TX_BROADCAST, 352 SYS_COUNT_TX_COLLISION, 353 SYS_COUNT_TX_DROPS, 354 SYS_COUNT_TX_PAUSE, 355 SYS_COUNT_TX_64, 356 SYS_COUNT_TX_65_127, 357 SYS_COUNT_TX_128_511, 358 SYS_COUNT_TX_512_1023, 359 SYS_COUNT_TX_1024_1526, 360 SYS_COUNT_TX_1527_MAX, 361 SYS_COUNT_TX_AGING, 362 SYS_RESET_CFG, 363 SYS_SR_ETYPE_CFG, 364 SYS_VLAN_ETYPE_CFG, 365 SYS_PORT_MODE, 366 SYS_FRONT_PORT_MODE, 367 SYS_FRM_AGING, 368 SYS_STAT_CFG, 369 SYS_SW_STATUS, 370 SYS_MISC_CFG, 371 SYS_REW_MAC_HIGH_CFG, 372 SYS_REW_MAC_LOW_CFG, 373 SYS_TIMESTAMP_OFFSET, 374 SYS_CMID, 375 SYS_PAUSE_CFG, 376 SYS_PAUSE_TOT_CFG, 377 SYS_ATOP, 378 SYS_ATOP_TOT_CFG, 379 SYS_MAC_FC_CFG, 380 SYS_MMGT, 381 SYS_MMGT_FAST, 382 SYS_EVENTS_DIF, 383 SYS_EVENTS_CORE, 384 SYS_CNT, 385 SYS_PTP_STATUS, 386 SYS_PTP_TXSTAMP, 387 SYS_PTP_NXT, 388 SYS_PTP_CFG, 389 SYS_RAM_INIT, 390 SYS_CM_ADDR, 391 SYS_CM_DATA_WR, 392 SYS_CM_DATA_RD, 393 SYS_CM_OP, 394 SYS_CM_DATA, 395 PTP_PIN_CFG = PTP << TARGET_OFFSET, 396 PTP_PIN_TOD_SEC_MSB, 397 PTP_PIN_TOD_SEC_LSB, 398 PTP_PIN_TOD_NSEC, 399 PTP_PIN_WF_HIGH_PERIOD, 400 PTP_PIN_WF_LOW_PERIOD, 401 PTP_CFG_MISC, 402 PTP_CLK_CFG_ADJ_CFG, 403 PTP_CLK_CFG_ADJ_FREQ, 404 GCB_SOFT_RST = GCB << TARGET_OFFSET, 405 GCB_MIIM_MII_STATUS, 406 GCB_MIIM_MII_CMD, 407 GCB_MIIM_MII_DATA, 408 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, 409 DEV_PORT_MISC, 410 DEV_EVENTS, 411 DEV_EEE_CFG, 412 DEV_RX_PATH_DELAY, 413 DEV_TX_PATH_DELAY, 414 DEV_PTP_PREDICT_CFG, 415 DEV_MAC_ENA_CFG, 416 DEV_MAC_MODE_CFG, 417 DEV_MAC_MAXLEN_CFG, 418 DEV_MAC_TAGS_CFG, 419 DEV_MAC_ADV_CHK_CFG, 420 DEV_MAC_IFG_CFG, 421 DEV_MAC_HDX_CFG, 422 DEV_MAC_DBG_CFG, 423 DEV_MAC_FC_MAC_LOW_CFG, 424 DEV_MAC_FC_MAC_HIGH_CFG, 425 DEV_MAC_STICKY, 426 PCS1G_CFG, 427 PCS1G_MODE_CFG, 428 PCS1G_SD_CFG, 429 PCS1G_ANEG_CFG, 430 PCS1G_ANEG_NP_CFG, 431 PCS1G_LB_CFG, 432 PCS1G_DBG_CFG, 433 PCS1G_CDET_CFG, 434 PCS1G_ANEG_STATUS, 435 PCS1G_ANEG_NP_STATUS, 436 PCS1G_LINK_STATUS, 437 PCS1G_LINK_DOWN_CNT, 438 PCS1G_STICKY, 439 PCS1G_DEBUG_STATUS, 440 PCS1G_LPI_CFG, 441 PCS1G_LPI_WAKE_ERROR_CNT, 442 PCS1G_LPI_STATUS, 443 PCS1G_TSTPAT_MODE_CFG, 444 PCS1G_TSTPAT_STATUS, 445 DEV_PCS_FX100_CFG, 446 DEV_PCS_FX100_STATUS, 447 }; 448 449 enum ocelot_regfield { 450 ANA_ADVLEARN_VLAN_CHK, 451 ANA_ADVLEARN_LEARN_MIRROR, 452 ANA_ANEVENTS_FLOOD_DISCARD, 453 ANA_ANEVENTS_MSTI_DROP, 454 ANA_ANEVENTS_ACLKILL, 455 ANA_ANEVENTS_ACLUSED, 456 ANA_ANEVENTS_AUTOAGE, 457 ANA_ANEVENTS_VS2TTL1, 458 ANA_ANEVENTS_STORM_DROP, 459 ANA_ANEVENTS_LEARN_DROP, 460 ANA_ANEVENTS_AGED_ENTRY, 461 ANA_ANEVENTS_CPU_LEARN_FAILED, 462 ANA_ANEVENTS_AUTO_LEARN_FAILED, 463 ANA_ANEVENTS_LEARN_REMOVE, 464 ANA_ANEVENTS_AUTO_LEARNED, 465 ANA_ANEVENTS_AUTO_MOVED, 466 ANA_ANEVENTS_DROPPED, 467 ANA_ANEVENTS_CLASSIFIED_DROP, 468 ANA_ANEVENTS_CLASSIFIED_COPY, 469 ANA_ANEVENTS_VLAN_DISCARD, 470 ANA_ANEVENTS_FWD_DISCARD, 471 ANA_ANEVENTS_MULTICAST_FLOOD, 472 ANA_ANEVENTS_UNICAST_FLOOD, 473 ANA_ANEVENTS_DEST_KNOWN, 474 ANA_ANEVENTS_BUCKET3_MATCH, 475 ANA_ANEVENTS_BUCKET2_MATCH, 476 ANA_ANEVENTS_BUCKET1_MATCH, 477 ANA_ANEVENTS_BUCKET0_MATCH, 478 ANA_ANEVENTS_CPU_OPERATION, 479 ANA_ANEVENTS_DMAC_LOOKUP, 480 ANA_ANEVENTS_SMAC_LOOKUP, 481 ANA_ANEVENTS_SEQ_GEN_ERR_0, 482 ANA_ANEVENTS_SEQ_GEN_ERR_1, 483 ANA_TABLES_MACACCESS_B_DOM, 484 ANA_TABLES_MACTINDX_BUCKET, 485 ANA_TABLES_MACTINDX_M_INDEX, 486 QSYS_SWITCH_PORT_MODE_PORT_ENA, 487 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG, 488 QSYS_SWITCH_PORT_MODE_YEL_RSRVD, 489 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE, 490 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 491 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE, 492 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD, 493 QSYS_TIMED_FRAME_ENTRY_TFRM_FP, 494 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO, 495 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL, 496 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T, 497 SYS_PORT_MODE_DATA_WO_TS, 498 SYS_PORT_MODE_INCL_INJ_HDR, 499 SYS_PORT_MODE_INCL_XTR_HDR, 500 SYS_PORT_MODE_INCL_HDR_ERR, 501 SYS_RESET_CFG_CORE_ENA, 502 SYS_RESET_CFG_MEM_ENA, 503 SYS_RESET_CFG_MEM_INIT, 504 GCB_SOFT_RST_SWC_RST, 505 GCB_MIIM_MII_STATUS_PENDING, 506 GCB_MIIM_MII_STATUS_BUSY, 507 SYS_PAUSE_CFG_PAUSE_START, 508 SYS_PAUSE_CFG_PAUSE_STOP, 509 SYS_PAUSE_CFG_PAUSE_ENA, 510 REGFIELD_MAX 511 }; 512 513 enum { 514 /* VCAP_CORE_CFG */ 515 VCAP_CORE_UPDATE_CTRL, 516 VCAP_CORE_MV_CFG, 517 /* VCAP_CORE_CACHE */ 518 VCAP_CACHE_ENTRY_DAT, 519 VCAP_CACHE_MASK_DAT, 520 VCAP_CACHE_ACTION_DAT, 521 VCAP_CACHE_CNT_DAT, 522 VCAP_CACHE_TG_DAT, 523 /* VCAP_CONST */ 524 VCAP_CONST_VCAP_VER, 525 VCAP_CONST_ENTRY_WIDTH, 526 VCAP_CONST_ENTRY_CNT, 527 VCAP_CONST_ENTRY_SWCNT, 528 VCAP_CONST_ENTRY_TG_WIDTH, 529 VCAP_CONST_ACTION_DEF_CNT, 530 VCAP_CONST_ACTION_WIDTH, 531 VCAP_CONST_CNT_WIDTH, 532 VCAP_CONST_CORE_CNT, 533 VCAP_CONST_IF_CNT, 534 }; 535 536 enum ocelot_ptp_pins { 537 PTP_PIN_0, 538 PTP_PIN_1, 539 PTP_PIN_2, 540 PTP_PIN_3, 541 TOD_ACC_PIN 542 }; 543 544 struct ocelot_stat_layout { 545 u32 offset; 546 char name[ETH_GSTRING_LEN]; 547 }; 548 549 enum ocelot_tag_prefix { 550 OCELOT_TAG_PREFIX_DISABLED = 0, 551 OCELOT_TAG_PREFIX_NONE, 552 OCELOT_TAG_PREFIX_SHORT, 553 OCELOT_TAG_PREFIX_LONG, 554 }; 555 556 struct ocelot; 557 558 struct ocelot_ops { 559 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port); 560 int (*netdev_to_port)(struct net_device *dev); 561 int (*reset)(struct ocelot *ocelot); 562 u16 (*wm_enc)(u16 value); 563 u16 (*wm_dec)(u16 value); 564 void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse); 565 }; 566 567 struct ocelot_vcap_block { 568 struct list_head rules; 569 int count; 570 int pol_lpr; 571 }; 572 573 struct ocelot_vlan { 574 bool valid; 575 u16 vid; 576 }; 577 578 enum ocelot_sb { 579 OCELOT_SB_BUF, 580 OCELOT_SB_REF, 581 OCELOT_SB_NUM, 582 }; 583 584 enum ocelot_sb_pool { 585 OCELOT_SB_POOL_ING, 586 OCELOT_SB_POOL_EGR, 587 OCELOT_SB_POOL_NUM, 588 }; 589 590 struct ocelot_port { 591 struct ocelot *ocelot; 592 593 struct regmap *target; 594 595 bool vlan_aware; 596 /* VLAN that untagged frames are classified to, on ingress */ 597 struct ocelot_vlan pvid_vlan; 598 /* The VLAN ID that will be transmitted as untagged, on egress */ 599 struct ocelot_vlan native_vlan; 600 601 u8 ptp_cmd; 602 struct sk_buff_head tx_skbs; 603 u8 ts_id; 604 spinlock_t ts_id_lock; 605 606 phy_interface_t phy_mode; 607 608 u8 *xmit_template; 609 bool is_dsa_8021q_cpu; 610 bool learn_ena; 611 612 struct net_device *bond; 613 bool lag_tx_active; 614 }; 615 616 struct ocelot { 617 struct device *dev; 618 struct devlink *devlink; 619 struct devlink_port *devlink_ports; 620 621 const struct ocelot_ops *ops; 622 struct regmap *targets[TARGET_MAX]; 623 struct regmap_field *regfields[REGFIELD_MAX]; 624 const u32 *const *map; 625 const struct ocelot_stat_layout *stats_layout; 626 unsigned int num_stats; 627 628 u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM]; 629 int packet_buffer_size; 630 int num_frame_refs; 631 int num_mact_rows; 632 633 struct net_device *hw_bridge_dev; 634 u16 bridge_mask; 635 u16 bridge_fwd_mask; 636 637 struct ocelot_port **ports; 638 639 u8 base_mac[ETH_ALEN]; 640 641 /* Keep track of the vlan port masks */ 642 u32 vlan_mask[VLAN_N_VID]; 643 644 /* Switches like VSC9959 have flooding per traffic class */ 645 int num_flooding_pgids; 646 647 /* In tables like ANA:PORT and the ANA:PGID:PGID mask, 648 * the CPU is located after the physical ports (at the 649 * num_phys_ports index). 650 */ 651 u8 num_phys_ports; 652 653 int npi; 654 655 enum ocelot_tag_prefix npi_inj_prefix; 656 enum ocelot_tag_prefix npi_xtr_prefix; 657 658 struct list_head multicast; 659 struct list_head pgids; 660 661 struct list_head dummy_rules; 662 struct ocelot_vcap_block block[3]; 663 struct vcap_props *vcap; 664 665 /* Workqueue to check statistics for overflow with its lock */ 666 struct mutex stats_lock; 667 u64 *stats; 668 struct delayed_work stats_work; 669 struct workqueue_struct *stats_queue; 670 671 struct workqueue_struct *owq; 672 673 u8 ptp:1; 674 struct ptp_clock *ptp_clock; 675 struct ptp_clock_info ptp_info; 676 struct hwtstamp_config hwtstamp_config; 677 /* Protects the PTP interface state */ 678 struct mutex ptp_lock; 679 /* Protects the PTP clock */ 680 spinlock_t ptp_clock_lock; 681 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM]; 682 683 #if IS_ENABLED(CONFIG_BRIDGE_MRP) 684 u16 mrp_ring_id; 685 struct net_device *mrp_p_port; 686 struct net_device *mrp_s_port; 687 #endif 688 }; 689 690 struct ocelot_policer { 691 u32 rate; /* kilobit per second */ 692 u32 burst; /* bytes */ 693 }; 694 695 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 696 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) 697 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) 698 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0) 699 700 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 701 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) 702 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) 703 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) 704 705 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 706 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) 707 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) 708 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) 709 710 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val)) 711 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val)) 712 #define ocelot_fields_write(ocelot, id, reg, val) regmap_fields_write((ocelot)->regfields[(reg)], (id), (val)) 713 #define ocelot_fields_read(ocelot, id, reg, val) regmap_fields_read((ocelot)->regfields[(reg)], (id), (val)) 714 715 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \ 716 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 717 #define ocelot_target_read_gix(ocelot, target, reg, gi) \ 718 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi)) 719 #define ocelot_target_read_rix(ocelot, target, reg, ri) \ 720 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri)) 721 #define ocelot_target_read(ocelot, target, reg) \ 722 __ocelot_target_read_ix(ocelot, target, reg, 0) 723 724 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \ 725 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 726 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \ 727 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi)) 728 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \ 729 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri)) 730 #define ocelot_target_write(ocelot, target, val, reg) \ 731 __ocelot_target_write_ix(ocelot, target, val, reg, 0) 732 733 /* I/O */ 734 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); 735 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); 736 void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, u32 reg); 737 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); 738 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); 739 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, 740 u32 offset); 741 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target, 742 u32 reg, u32 offset); 743 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target, 744 u32 val, u32 reg, u32 offset); 745 746 /* Packet I/O */ 747 #if IS_ENABLED(CONFIG_MSCC_OCELOT_SWITCH_LIB) 748 749 bool ocelot_can_inject(struct ocelot *ocelot, int grp); 750 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 751 u32 rew_op, struct sk_buff *skb); 752 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb); 753 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp); 754 755 #else 756 757 static inline bool ocelot_can_inject(struct ocelot *ocelot, int grp) 758 { 759 return false; 760 } 761 762 static inline void ocelot_port_inject_frame(struct ocelot *ocelot, int port, 763 int grp, u32 rew_op, 764 struct sk_buff *skb) 765 { 766 } 767 768 static inline int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, 769 struct sk_buff **skb) 770 { 771 return -EIO; 772 } 773 774 static inline void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 775 { 776 } 777 778 #endif 779 780 /* Hardware initialization */ 781 int ocelot_regfields_init(struct ocelot *ocelot, 782 const struct reg_field *const regfields); 783 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res); 784 int ocelot_init(struct ocelot *ocelot); 785 void ocelot_deinit(struct ocelot *ocelot); 786 void ocelot_init_port(struct ocelot *ocelot, int port); 787 void ocelot_deinit_port(struct ocelot *ocelot, int port); 788 789 /* DSA callbacks */ 790 void ocelot_port_enable(struct ocelot *ocelot, int port, 791 struct phy_device *phy); 792 void ocelot_port_disable(struct ocelot *ocelot, int port); 793 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data); 794 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data); 795 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset); 796 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 797 struct ethtool_ts_info *info); 798 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs); 799 int ocelot_port_flush(struct ocelot *ocelot, int port); 800 void ocelot_adjust_link(struct ocelot *ocelot, int port, 801 struct phy_device *phydev); 802 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled); 803 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state); 804 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot); 805 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 806 struct switchdev_brport_flags val); 807 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 808 struct switchdev_brport_flags val); 809 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 810 struct net_device *bridge); 811 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 812 struct net_device *bridge); 813 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 814 dsa_fdb_dump_cb_t *cb, void *data); 815 int ocelot_fdb_add(struct ocelot *ocelot, int port, 816 const unsigned char *addr, u16 vid); 817 int ocelot_fdb_del(struct ocelot *ocelot, int port, 818 const unsigned char *addr, u16 vid); 819 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 820 bool untagged); 821 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 822 bool untagged); 823 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid); 824 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr); 825 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr); 826 void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 827 struct sk_buff *clone); 828 void ocelot_get_txtstamp(struct ocelot *ocelot); 829 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu); 830 int ocelot_get_max_mtu(struct ocelot *ocelot, int port); 831 int ocelot_port_policer_add(struct ocelot *ocelot, int port, 832 struct ocelot_policer *pol); 833 int ocelot_port_policer_del(struct ocelot *ocelot, int port); 834 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port, 835 struct flow_cls_offload *f, bool ingress); 836 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port, 837 struct flow_cls_offload *f, bool ingress); 838 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port, 839 struct flow_cls_offload *f, bool ingress); 840 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 841 const struct switchdev_obj_port_mdb *mdb); 842 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 843 const struct switchdev_obj_port_mdb *mdb); 844 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 845 struct net_device *bond, 846 struct netdev_lag_upper_info *info); 847 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 848 struct net_device *bond); 849 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active); 850 851 int ocelot_devlink_sb_register(struct ocelot *ocelot); 852 void ocelot_devlink_sb_unregister(struct ocelot *ocelot); 853 int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index, 854 u16 pool_index, 855 struct devlink_sb_pool_info *pool_info); 856 int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index, 857 u16 pool_index, u32 size, 858 enum devlink_sb_threshold_type threshold_type, 859 struct netlink_ext_ack *extack); 860 int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port, 861 unsigned int sb_index, u16 pool_index, 862 u32 *p_threshold); 863 int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port, 864 unsigned int sb_index, u16 pool_index, 865 u32 threshold, struct netlink_ext_ack *extack); 866 int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port, 867 unsigned int sb_index, u16 tc_index, 868 enum devlink_sb_pool_type pool_type, 869 u16 *p_pool_index, u32 *p_threshold); 870 int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port, 871 unsigned int sb_index, u16 tc_index, 872 enum devlink_sb_pool_type pool_type, 873 u16 pool_index, u32 threshold, 874 struct netlink_ext_ack *extack); 875 int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index); 876 int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index); 877 int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port, 878 unsigned int sb_index, u16 pool_index, 879 u32 *p_cur, u32 *p_max); 880 int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port, 881 unsigned int sb_index, u16 tc_index, 882 enum devlink_sb_pool_type pool_type, 883 u32 *p_cur, u32 *p_max); 884 885 #if IS_ENABLED(CONFIG_BRIDGE_MRP) 886 int ocelot_mrp_add(struct ocelot *ocelot, int port, 887 const struct switchdev_obj_mrp *mrp); 888 int ocelot_mrp_del(struct ocelot *ocelot, int port, 889 const struct switchdev_obj_mrp *mrp); 890 int ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port, 891 const struct switchdev_obj_ring_role_mrp *mrp); 892 int ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, 893 const struct switchdev_obj_ring_role_mrp *mrp); 894 #else 895 static inline int ocelot_mrp_add(struct ocelot *ocelot, int port, 896 const struct switchdev_obj_mrp *mrp) 897 { 898 return -EOPNOTSUPP; 899 } 900 901 static inline int ocelot_mrp_del(struct ocelot *ocelot, int port, 902 const struct switchdev_obj_mrp *mrp) 903 { 904 return -EOPNOTSUPP; 905 } 906 907 static inline int 908 ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port, 909 const struct switchdev_obj_ring_role_mrp *mrp) 910 { 911 return -EOPNOTSUPP; 912 } 913 914 static inline int 915 ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, 916 const struct switchdev_obj_ring_role_mrp *mrp) 917 { 918 return -EOPNOTSUPP; 919 } 920 #endif 921 922 #endif 923