xref: /openbmc/linux/include/soc/mscc/ocelot.h (revision b58c6630)
1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /* Copyright (c) 2017 Microsemi Corporation
3  */
4 
5 #ifndef _SOC_MSCC_OCELOT_H
6 #define _SOC_MSCC_OCELOT_H
7 
8 #include <linux/ptp_clock_kernel.h>
9 #include <linux/net_tstamp.h>
10 #include <linux/if_vlan.h>
11 #include <linux/regmap.h>
12 #include <net/dsa.h>
13 
14 /* Port Group IDs (PGID) are masks of destination ports.
15  *
16  * For L2 forwarding, the switch performs 3 lookups in the PGID table for each
17  * frame, and forwards the frame to the ports that are present in the logical
18  * AND of all 3 PGIDs.
19  *
20  * These PGID lookups are:
21  * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
22  *   which the switch selects a destination PGID:
23  *     - The {DMAC, VID} is present in the MAC table. In that case, the
24  *       destination PGID is given by the DEST_IDX field of the MAC table entry
25  *       that matched.
26  *     - The {DMAC, VID} is not present in the MAC table (it is unknown). The
27  *       frame is disseminated as being either unicast, multicast or broadcast,
28  *       and according to that, the destination PGID is chosen as being the
29  *       value contained by ANA_FLOODING_FLD_UNICAST,
30  *       ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
31  *   The destination PGID can be an unicast set: the first PGIDs, 0 to
32  *   ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
33  *   ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
34  *   a physical port and has a single bit set in the destination ports mask:
35  *   that corresponding to the port number itself. In contrast, a multicast
36  *   PGID will have potentially more than one single bit set in the destination
37  *   ports mask.
38  * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
39  *   dissects each frame and generates a 4-bit Link Aggregation Code which is
40  *   used for this second PGID table lookup. The goal of link aggregation is to
41  *   hash multiple flows within the same LAG on to different destination ports.
42  *   The first lookup will result in a PGID with all the LAG members present in
43  *   the destination ports mask, and the second lookup, by Link Aggregation
44  *   Code, will ensure that each flow gets forwarded only to a single port out
45  *   of that mask (there are no duplicates).
46  * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
47  *   is indexed with the ingress port (plus 80). These PGIDs answer the
48  *   question "is port i allowed to forward traffic to port j?" If yes, then
49  *   BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
50  *   to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
51  */
52 
53 /* Reserve some destination PGIDs at the end of the range:
54  * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
55  *           of the switch port net devices, towards the CPU port module.
56  * PGID_UC: the flooding destinations for unknown unicast traffic.
57  * PGID_MC: the flooding destinations for broadcast and non-IP multicast
58  *          traffic.
59  * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
60  * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
61  */
62 #define PGID_CPU			59
63 #define PGID_UC				60
64 #define PGID_MC				61
65 #define PGID_MCIPV4			62
66 #define PGID_MCIPV6			63
67 
68 /* Aggregation PGIDs, one per Link Aggregation Code */
69 #define PGID_AGGR			64
70 
71 /* Source PGIDs, one per physical port */
72 #define PGID_SRC			80
73 
74 #define IFH_INJ_BYPASS			BIT(31)
75 #define IFH_INJ_POP_CNT_DISABLE		(3 << 28)
76 
77 #define IFH_TAG_TYPE_C			0
78 #define IFH_TAG_TYPE_S			1
79 
80 #define IFH_REW_OP_NOOP			0x0
81 #define IFH_REW_OP_DSCP			0x1
82 #define IFH_REW_OP_ONE_STEP_PTP		0x2
83 #define IFH_REW_OP_TWO_STEP_PTP		0x3
84 #define IFH_REW_OP_ORIGIN_PTP		0x5
85 
86 #define OCELOT_TAG_LEN			16
87 #define OCELOT_SHORT_PREFIX_LEN		4
88 #define OCELOT_LONG_PREFIX_LEN		16
89 
90 #define OCELOT_SPEED_2500		0
91 #define OCELOT_SPEED_1000		1
92 #define OCELOT_SPEED_100		2
93 #define OCELOT_SPEED_10			3
94 
95 #define TARGET_OFFSET			24
96 #define REG_MASK			GENMASK(TARGET_OFFSET - 1, 0)
97 #define REG(reg, offset)		[reg & REG_MASK] = offset
98 
99 #define REG_RESERVED_ADDR		0xffffffff
100 #define REG_RESERVED(reg)		REG(reg, REG_RESERVED_ADDR)
101 
102 enum ocelot_target {
103 	ANA = 1,
104 	QS,
105 	QSYS,
106 	REW,
107 	SYS,
108 	S2,
109 	HSIO,
110 	PTP,
111 	GCB,
112 	TARGET_MAX,
113 };
114 
115 enum ocelot_reg {
116 	ANA_ADVLEARN = ANA << TARGET_OFFSET,
117 	ANA_VLANMASK,
118 	ANA_PORT_B_DOMAIN,
119 	ANA_ANAGEFIL,
120 	ANA_ANEVENTS,
121 	ANA_STORMLIMIT_BURST,
122 	ANA_STORMLIMIT_CFG,
123 	ANA_ISOLATED_PORTS,
124 	ANA_COMMUNITY_PORTS,
125 	ANA_AUTOAGE,
126 	ANA_MACTOPTIONS,
127 	ANA_LEARNDISC,
128 	ANA_AGENCTRL,
129 	ANA_MIRRORPORTS,
130 	ANA_EMIRRORPORTS,
131 	ANA_FLOODING,
132 	ANA_FLOODING_IPMC,
133 	ANA_SFLOW_CFG,
134 	ANA_PORT_MODE,
135 	ANA_CUT_THRU_CFG,
136 	ANA_PGID_PGID,
137 	ANA_TABLES_ANMOVED,
138 	ANA_TABLES_MACHDATA,
139 	ANA_TABLES_MACLDATA,
140 	ANA_TABLES_STREAMDATA,
141 	ANA_TABLES_MACACCESS,
142 	ANA_TABLES_MACTINDX,
143 	ANA_TABLES_VLANACCESS,
144 	ANA_TABLES_VLANTIDX,
145 	ANA_TABLES_ISDXACCESS,
146 	ANA_TABLES_ISDXTIDX,
147 	ANA_TABLES_ENTRYLIM,
148 	ANA_TABLES_PTP_ID_HIGH,
149 	ANA_TABLES_PTP_ID_LOW,
150 	ANA_TABLES_STREAMACCESS,
151 	ANA_TABLES_STREAMTIDX,
152 	ANA_TABLES_SEQ_HISTORY,
153 	ANA_TABLES_SEQ_MASK,
154 	ANA_TABLES_SFID_MASK,
155 	ANA_TABLES_SFIDACCESS,
156 	ANA_TABLES_SFIDTIDX,
157 	ANA_MSTI_STATE,
158 	ANA_OAM_UPM_LM_CNT,
159 	ANA_SG_ACCESS_CTRL,
160 	ANA_SG_CONFIG_REG_1,
161 	ANA_SG_CONFIG_REG_2,
162 	ANA_SG_CONFIG_REG_3,
163 	ANA_SG_CONFIG_REG_4,
164 	ANA_SG_CONFIG_REG_5,
165 	ANA_SG_GCL_GS_CONFIG,
166 	ANA_SG_GCL_TI_CONFIG,
167 	ANA_SG_STATUS_REG_1,
168 	ANA_SG_STATUS_REG_2,
169 	ANA_SG_STATUS_REG_3,
170 	ANA_PORT_VLAN_CFG,
171 	ANA_PORT_DROP_CFG,
172 	ANA_PORT_QOS_CFG,
173 	ANA_PORT_VCAP_CFG,
174 	ANA_PORT_VCAP_S1_KEY_CFG,
175 	ANA_PORT_VCAP_S2_CFG,
176 	ANA_PORT_PCP_DEI_MAP,
177 	ANA_PORT_CPU_FWD_CFG,
178 	ANA_PORT_CPU_FWD_BPDU_CFG,
179 	ANA_PORT_CPU_FWD_GARP_CFG,
180 	ANA_PORT_CPU_FWD_CCM_CFG,
181 	ANA_PORT_PORT_CFG,
182 	ANA_PORT_POL_CFG,
183 	ANA_PORT_PTP_CFG,
184 	ANA_PORT_PTP_DLY1_CFG,
185 	ANA_PORT_PTP_DLY2_CFG,
186 	ANA_PORT_SFID_CFG,
187 	ANA_PFC_PFC_CFG,
188 	ANA_PFC_PFC_TIMER,
189 	ANA_IPT_OAM_MEP_CFG,
190 	ANA_IPT_IPT,
191 	ANA_PPT_PPT,
192 	ANA_FID_MAP_FID_MAP,
193 	ANA_AGGR_CFG,
194 	ANA_CPUQ_CFG,
195 	ANA_CPUQ_CFG2,
196 	ANA_CPUQ_8021_CFG,
197 	ANA_DSCP_CFG,
198 	ANA_DSCP_REWR_CFG,
199 	ANA_VCAP_RNG_TYPE_CFG,
200 	ANA_VCAP_RNG_VAL_CFG,
201 	ANA_VRAP_CFG,
202 	ANA_VRAP_HDR_DATA,
203 	ANA_VRAP_HDR_MASK,
204 	ANA_DISCARD_CFG,
205 	ANA_FID_CFG,
206 	ANA_POL_PIR_CFG,
207 	ANA_POL_CIR_CFG,
208 	ANA_POL_MODE_CFG,
209 	ANA_POL_PIR_STATE,
210 	ANA_POL_CIR_STATE,
211 	ANA_POL_STATE,
212 	ANA_POL_FLOWC,
213 	ANA_POL_HYST,
214 	ANA_POL_MISC_CFG,
215 	QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
216 	QS_XTR_RD,
217 	QS_XTR_FRM_PRUNING,
218 	QS_XTR_FLUSH,
219 	QS_XTR_DATA_PRESENT,
220 	QS_XTR_CFG,
221 	QS_INJ_GRP_CFG,
222 	QS_INJ_WR,
223 	QS_INJ_CTRL,
224 	QS_INJ_STATUS,
225 	QS_INJ_ERR,
226 	QS_INH_DBG,
227 	QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
228 	QSYS_SWITCH_PORT_MODE,
229 	QSYS_STAT_CNT_CFG,
230 	QSYS_EEE_CFG,
231 	QSYS_EEE_THRES,
232 	QSYS_IGR_NO_SHARING,
233 	QSYS_EGR_NO_SHARING,
234 	QSYS_SW_STATUS,
235 	QSYS_EXT_CPU_CFG,
236 	QSYS_PAD_CFG,
237 	QSYS_CPU_GROUP_MAP,
238 	QSYS_QMAP,
239 	QSYS_ISDX_SGRP,
240 	QSYS_TIMED_FRAME_ENTRY,
241 	QSYS_TFRM_MISC,
242 	QSYS_TFRM_PORT_DLY,
243 	QSYS_TFRM_TIMER_CFG_1,
244 	QSYS_TFRM_TIMER_CFG_2,
245 	QSYS_TFRM_TIMER_CFG_3,
246 	QSYS_TFRM_TIMER_CFG_4,
247 	QSYS_TFRM_TIMER_CFG_5,
248 	QSYS_TFRM_TIMER_CFG_6,
249 	QSYS_TFRM_TIMER_CFG_7,
250 	QSYS_TFRM_TIMER_CFG_8,
251 	QSYS_RED_PROFILE,
252 	QSYS_RES_QOS_MODE,
253 	QSYS_RES_CFG,
254 	QSYS_RES_STAT,
255 	QSYS_EGR_DROP_MODE,
256 	QSYS_EQ_CTRL,
257 	QSYS_EVENTS_CORE,
258 	QSYS_QMAXSDU_CFG_0,
259 	QSYS_QMAXSDU_CFG_1,
260 	QSYS_QMAXSDU_CFG_2,
261 	QSYS_QMAXSDU_CFG_3,
262 	QSYS_QMAXSDU_CFG_4,
263 	QSYS_QMAXSDU_CFG_5,
264 	QSYS_QMAXSDU_CFG_6,
265 	QSYS_QMAXSDU_CFG_7,
266 	QSYS_PREEMPTION_CFG,
267 	QSYS_CIR_CFG,
268 	QSYS_EIR_CFG,
269 	QSYS_SE_CFG,
270 	QSYS_SE_DWRR_CFG,
271 	QSYS_SE_CONNECT,
272 	QSYS_SE_DLB_SENSE,
273 	QSYS_CIR_STATE,
274 	QSYS_EIR_STATE,
275 	QSYS_SE_STATE,
276 	QSYS_HSCH_MISC_CFG,
277 	QSYS_TAG_CONFIG,
278 	QSYS_TAS_PARAM_CFG_CTRL,
279 	QSYS_PORT_MAX_SDU,
280 	QSYS_PARAM_CFG_REG_1,
281 	QSYS_PARAM_CFG_REG_2,
282 	QSYS_PARAM_CFG_REG_3,
283 	QSYS_PARAM_CFG_REG_4,
284 	QSYS_PARAM_CFG_REG_5,
285 	QSYS_GCL_CFG_REG_1,
286 	QSYS_GCL_CFG_REG_2,
287 	QSYS_PARAM_STATUS_REG_1,
288 	QSYS_PARAM_STATUS_REG_2,
289 	QSYS_PARAM_STATUS_REG_3,
290 	QSYS_PARAM_STATUS_REG_4,
291 	QSYS_PARAM_STATUS_REG_5,
292 	QSYS_PARAM_STATUS_REG_6,
293 	QSYS_PARAM_STATUS_REG_7,
294 	QSYS_PARAM_STATUS_REG_8,
295 	QSYS_PARAM_STATUS_REG_9,
296 	QSYS_GCL_STATUS_REG_1,
297 	QSYS_GCL_STATUS_REG_2,
298 	REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
299 	REW_TAG_CFG,
300 	REW_PORT_CFG,
301 	REW_DSCP_CFG,
302 	REW_PCP_DEI_QOS_MAP_CFG,
303 	REW_PTP_CFG,
304 	REW_PTP_DLY1_CFG,
305 	REW_RED_TAG_CFG,
306 	REW_DSCP_REMAP_DP1_CFG,
307 	REW_DSCP_REMAP_CFG,
308 	REW_STAT_CFG,
309 	REW_REW_STICKY,
310 	REW_PPT,
311 	SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
312 	SYS_COUNT_RX_UNICAST,
313 	SYS_COUNT_RX_MULTICAST,
314 	SYS_COUNT_RX_BROADCAST,
315 	SYS_COUNT_RX_SHORTS,
316 	SYS_COUNT_RX_FRAGMENTS,
317 	SYS_COUNT_RX_JABBERS,
318 	SYS_COUNT_RX_CRC_ALIGN_ERRS,
319 	SYS_COUNT_RX_SYM_ERRS,
320 	SYS_COUNT_RX_64,
321 	SYS_COUNT_RX_65_127,
322 	SYS_COUNT_RX_128_255,
323 	SYS_COUNT_RX_256_1023,
324 	SYS_COUNT_RX_1024_1526,
325 	SYS_COUNT_RX_1527_MAX,
326 	SYS_COUNT_RX_PAUSE,
327 	SYS_COUNT_RX_CONTROL,
328 	SYS_COUNT_RX_LONGS,
329 	SYS_COUNT_RX_CLASSIFIED_DROPS,
330 	SYS_COUNT_TX_OCTETS,
331 	SYS_COUNT_TX_UNICAST,
332 	SYS_COUNT_TX_MULTICAST,
333 	SYS_COUNT_TX_BROADCAST,
334 	SYS_COUNT_TX_COLLISION,
335 	SYS_COUNT_TX_DROPS,
336 	SYS_COUNT_TX_PAUSE,
337 	SYS_COUNT_TX_64,
338 	SYS_COUNT_TX_65_127,
339 	SYS_COUNT_TX_128_511,
340 	SYS_COUNT_TX_512_1023,
341 	SYS_COUNT_TX_1024_1526,
342 	SYS_COUNT_TX_1527_MAX,
343 	SYS_COUNT_TX_AGING,
344 	SYS_RESET_CFG,
345 	SYS_SR_ETYPE_CFG,
346 	SYS_VLAN_ETYPE_CFG,
347 	SYS_PORT_MODE,
348 	SYS_FRONT_PORT_MODE,
349 	SYS_FRM_AGING,
350 	SYS_STAT_CFG,
351 	SYS_SW_STATUS,
352 	SYS_MISC_CFG,
353 	SYS_REW_MAC_HIGH_CFG,
354 	SYS_REW_MAC_LOW_CFG,
355 	SYS_TIMESTAMP_OFFSET,
356 	SYS_CMID,
357 	SYS_PAUSE_CFG,
358 	SYS_PAUSE_TOT_CFG,
359 	SYS_ATOP,
360 	SYS_ATOP_TOT_CFG,
361 	SYS_MAC_FC_CFG,
362 	SYS_MMGT,
363 	SYS_MMGT_FAST,
364 	SYS_EVENTS_DIF,
365 	SYS_EVENTS_CORE,
366 	SYS_CNT,
367 	SYS_PTP_STATUS,
368 	SYS_PTP_TXSTAMP,
369 	SYS_PTP_NXT,
370 	SYS_PTP_CFG,
371 	SYS_RAM_INIT,
372 	SYS_CM_ADDR,
373 	SYS_CM_DATA_WR,
374 	SYS_CM_DATA_RD,
375 	SYS_CM_OP,
376 	SYS_CM_DATA,
377 	S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
378 	S2_CORE_MV_CFG,
379 	S2_CACHE_ENTRY_DAT,
380 	S2_CACHE_MASK_DAT,
381 	S2_CACHE_ACTION_DAT,
382 	S2_CACHE_CNT_DAT,
383 	S2_CACHE_TG_DAT,
384 	PTP_PIN_CFG = PTP << TARGET_OFFSET,
385 	PTP_PIN_TOD_SEC_MSB,
386 	PTP_PIN_TOD_SEC_LSB,
387 	PTP_PIN_TOD_NSEC,
388 	PTP_CFG_MISC,
389 	PTP_CLK_CFG_ADJ_CFG,
390 	PTP_CLK_CFG_ADJ_FREQ,
391 	GCB_SOFT_RST = GCB << TARGET_OFFSET,
392 };
393 
394 enum ocelot_regfield {
395 	ANA_ADVLEARN_VLAN_CHK,
396 	ANA_ADVLEARN_LEARN_MIRROR,
397 	ANA_ANEVENTS_FLOOD_DISCARD,
398 	ANA_ANEVENTS_MSTI_DROP,
399 	ANA_ANEVENTS_ACLKILL,
400 	ANA_ANEVENTS_ACLUSED,
401 	ANA_ANEVENTS_AUTOAGE,
402 	ANA_ANEVENTS_VS2TTL1,
403 	ANA_ANEVENTS_STORM_DROP,
404 	ANA_ANEVENTS_LEARN_DROP,
405 	ANA_ANEVENTS_AGED_ENTRY,
406 	ANA_ANEVENTS_CPU_LEARN_FAILED,
407 	ANA_ANEVENTS_AUTO_LEARN_FAILED,
408 	ANA_ANEVENTS_LEARN_REMOVE,
409 	ANA_ANEVENTS_AUTO_LEARNED,
410 	ANA_ANEVENTS_AUTO_MOVED,
411 	ANA_ANEVENTS_DROPPED,
412 	ANA_ANEVENTS_CLASSIFIED_DROP,
413 	ANA_ANEVENTS_CLASSIFIED_COPY,
414 	ANA_ANEVENTS_VLAN_DISCARD,
415 	ANA_ANEVENTS_FWD_DISCARD,
416 	ANA_ANEVENTS_MULTICAST_FLOOD,
417 	ANA_ANEVENTS_UNICAST_FLOOD,
418 	ANA_ANEVENTS_DEST_KNOWN,
419 	ANA_ANEVENTS_BUCKET3_MATCH,
420 	ANA_ANEVENTS_BUCKET2_MATCH,
421 	ANA_ANEVENTS_BUCKET1_MATCH,
422 	ANA_ANEVENTS_BUCKET0_MATCH,
423 	ANA_ANEVENTS_CPU_OPERATION,
424 	ANA_ANEVENTS_DMAC_LOOKUP,
425 	ANA_ANEVENTS_SMAC_LOOKUP,
426 	ANA_ANEVENTS_SEQ_GEN_ERR_0,
427 	ANA_ANEVENTS_SEQ_GEN_ERR_1,
428 	ANA_TABLES_MACACCESS_B_DOM,
429 	ANA_TABLES_MACTINDX_BUCKET,
430 	ANA_TABLES_MACTINDX_M_INDEX,
431 	QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
432 	QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
433 	QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
434 	QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
435 	QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
436 	SYS_RESET_CFG_CORE_ENA,
437 	SYS_RESET_CFG_MEM_ENA,
438 	SYS_RESET_CFG_MEM_INIT,
439 	GCB_SOFT_RST_SWC_RST,
440 	REGFIELD_MAX
441 };
442 
443 enum ocelot_clk_pins {
444 	ALT_PPS_PIN	= 1,
445 	EXT_CLK_PIN,
446 	ALT_LDST_PIN,
447 	TOD_ACC_PIN
448 };
449 
450 struct ocelot_stat_layout {
451 	u32 offset;
452 	char name[ETH_GSTRING_LEN];
453 };
454 
455 enum ocelot_tag_prefix {
456 	OCELOT_TAG_PREFIX_DISABLED	= 0,
457 	OCELOT_TAG_PREFIX_NONE,
458 	OCELOT_TAG_PREFIX_SHORT,
459 	OCELOT_TAG_PREFIX_LONG,
460 };
461 
462 struct ocelot;
463 
464 struct ocelot_ops {
465 	int (*reset)(struct ocelot *ocelot);
466 };
467 
468 struct ocelot_acl_block {
469 	struct list_head rules;
470 	int count;
471 	int pol_lpr;
472 };
473 
474 struct ocelot_port {
475 	struct ocelot			*ocelot;
476 
477 	void __iomem			*regs;
478 
479 	bool				vlan_aware;
480 
481 	/* Ingress default VLAN (pvid) */
482 	u16				pvid;
483 
484 	/* Egress default VLAN (vid) */
485 	u16				vid;
486 
487 	u8				ptp_cmd;
488 	struct sk_buff_head		tx_skbs;
489 	u8				ts_id;
490 
491 	phy_interface_t			phy_mode;
492 };
493 
494 struct ocelot {
495 	struct device			*dev;
496 
497 	const struct ocelot_ops		*ops;
498 	struct regmap			*targets[TARGET_MAX];
499 	struct regmap_field		*regfields[REGFIELD_MAX];
500 	const u32 *const		*map;
501 	const struct ocelot_stat_layout	*stats_layout;
502 	unsigned int			num_stats;
503 
504 	int				shared_queue_sz;
505 
506 	struct net_device		*hw_bridge_dev;
507 	u16				bridge_mask;
508 	u16				bridge_fwd_mask;
509 
510 	struct ocelot_port		**ports;
511 
512 	u8				base_mac[ETH_ALEN];
513 
514 	/* Keep track of the vlan port masks */
515 	u32				vlan_mask[VLAN_N_VID];
516 
517 	/* In tables like ANA:PORT and the ANA:PGID:PGID mask,
518 	 * the CPU is located after the physical ports (at the
519 	 * num_phys_ports index).
520 	 */
521 	u8				num_phys_ports;
522 
523 	int				npi;
524 
525 	enum ocelot_tag_prefix		inj_prefix;
526 	enum ocelot_tag_prefix		xtr_prefix;
527 
528 	u32				*lags;
529 
530 	struct list_head		multicast;
531 
532 	struct ocelot_acl_block		acl_block;
533 
534 	const struct vcap_field		*vcap_is2_keys;
535 	const struct vcap_field		*vcap_is2_actions;
536 	const struct vcap_props		*vcap;
537 
538 	/* Workqueue to check statistics for overflow with its lock */
539 	struct mutex			stats_lock;
540 	u64				*stats;
541 	struct delayed_work		stats_work;
542 	struct workqueue_struct		*stats_queue;
543 
544 	u8				ptp:1;
545 	struct ptp_clock		*ptp_clock;
546 	struct ptp_clock_info		ptp_info;
547 	struct hwtstamp_config		hwtstamp_config;
548 	/* Protects the PTP interface state */
549 	struct mutex			ptp_lock;
550 	/* Protects the PTP clock */
551 	spinlock_t			ptp_clock_lock;
552 };
553 
554 struct ocelot_policer {
555 	u32 rate; /* kilobit per second */
556 	u32 burst; /* bytes */
557 };
558 
559 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
560 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
561 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
562 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
563 
564 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
565 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
566 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
567 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
568 
569 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
570 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
571 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
572 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
573 
574 /* I/O */
575 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
576 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
577 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
578 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
579 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
580 		     u32 offset);
581 
582 /* Hardware initialization */
583 int ocelot_regfields_init(struct ocelot *ocelot,
584 			  const struct reg_field *const regfields);
585 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
586 void ocelot_configure_cpu(struct ocelot *ocelot, int npi,
587 			  enum ocelot_tag_prefix injection,
588 			  enum ocelot_tag_prefix extraction);
589 int ocelot_init(struct ocelot *ocelot);
590 void ocelot_deinit(struct ocelot *ocelot);
591 void ocelot_init_port(struct ocelot *ocelot, int port);
592 
593 /* DSA callbacks */
594 void ocelot_port_enable(struct ocelot *ocelot, int port,
595 			struct phy_device *phy);
596 void ocelot_port_disable(struct ocelot *ocelot, int port);
597 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
598 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
599 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
600 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
601 		       struct ethtool_ts_info *info);
602 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
603 void ocelot_adjust_link(struct ocelot *ocelot, int port,
604 			struct phy_device *phydev);
605 void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
606 				bool vlan_aware);
607 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
608 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
609 			    struct net_device *bridge);
610 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
611 			     struct net_device *bridge);
612 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
613 		    dsa_fdb_dump_cb_t *cb, void *data);
614 int ocelot_fdb_add(struct ocelot *ocelot, int port,
615 		   const unsigned char *addr, u16 vid);
616 int ocelot_fdb_del(struct ocelot *ocelot, int port,
617 		   const unsigned char *addr, u16 vid);
618 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
619 		    bool untagged);
620 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
621 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
622 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
623 int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
624 int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port,
625 				 struct sk_buff *skb);
626 void ocelot_get_txtstamp(struct ocelot *ocelot);
627 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu);
628 int ocelot_get_max_mtu(struct ocelot *ocelot, int port);
629 int ocelot_port_policer_add(struct ocelot *ocelot, int port,
630 			    struct ocelot_policer *pol);
631 int ocelot_port_policer_del(struct ocelot *ocelot, int port);
632 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port,
633 			      struct flow_cls_offload *f, bool ingress);
634 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
635 			      struct flow_cls_offload *f, bool ingress);
636 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
637 			    struct flow_cls_offload *f, bool ingress);
638 
639 #endif
640