1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* Copyright (c) 2017 Microsemi Corporation 3 */ 4 5 #ifndef _SOC_MSCC_OCELOT_H 6 #define _SOC_MSCC_OCELOT_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/net_tstamp.h> 10 #include <linux/if_vlan.h> 11 #include <linux/regmap.h> 12 #include <net/dsa.h> 13 14 /* Port Group IDs (PGID) are masks of destination ports. 15 * 16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each 17 * frame, and forwards the frame to the ports that are present in the logical 18 * AND of all 3 PGIDs. 19 * 20 * These PGID lookups are: 21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by 22 * which the switch selects a destination PGID: 23 * - The {DMAC, VID} is present in the MAC table. In that case, the 24 * destination PGID is given by the DEST_IDX field of the MAC table entry 25 * that matched. 26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The 27 * frame is disseminated as being either unicast, multicast or broadcast, 28 * and according to that, the destination PGID is chosen as being the 29 * value contained by ANA_FLOODING_FLD_UNICAST, 30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST. 31 * The destination PGID can be an unicast set: the first PGIDs, 0 to 32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from 33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to 34 * a physical port and has a single bit set in the destination ports mask: 35 * that corresponding to the port number itself. In contrast, a multicast 36 * PGID will have potentially more than one single bit set in the destination 37 * ports mask. 38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier 39 * dissects each frame and generates a 4-bit Link Aggregation Code which is 40 * used for this second PGID table lookup. The goal of link aggregation is to 41 * hash multiple flows within the same LAG on to different destination ports. 42 * The first lookup will result in a PGID with all the LAG members present in 43 * the destination ports mask, and the second lookup, by Link Aggregation 44 * Code, will ensure that each flow gets forwarded only to a single port out 45 * of that mask (there are no duplicates). 46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table 47 * is indexed with the ingress port (plus 80). These PGIDs answer the 48 * question "is port i allowed to forward traffic to port j?" If yes, then 49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used 50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge. 51 */ 52 53 /* Reserve some destination PGIDs at the end of the range: 54 * PGID_BLACKHOLE: used for not forwarding the frames 55 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses 56 * of the switch port net devices, towards the CPU port module. 57 * PGID_UC: the flooding destinations for unknown unicast traffic. 58 * PGID_MC: the flooding destinations for non-IP multicast traffic. 59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic. 60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic. 61 * PGID_BC: the flooding destinations for broadcast traffic. 62 */ 63 #define PGID_BLACKHOLE 57 64 #define PGID_CPU 58 65 #define PGID_UC 59 66 #define PGID_MC 60 67 #define PGID_MCIPV4 61 68 #define PGID_MCIPV6 62 69 #define PGID_BC 63 70 71 #define for_each_unicast_dest_pgid(ocelot, pgid) \ 72 for ((pgid) = 0; \ 73 (pgid) < (ocelot)->num_phys_ports; \ 74 (pgid)++) 75 76 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \ 77 for ((pgid) = (ocelot)->num_phys_ports + 1; \ 78 (pgid) < PGID_BLACKHOLE; \ 79 (pgid)++) 80 81 #define for_each_aggr_pgid(ocelot, pgid) \ 82 for ((pgid) = PGID_AGGR; \ 83 (pgid) < PGID_SRC; \ 84 (pgid)++) 85 86 /* Aggregation PGIDs, one per Link Aggregation Code */ 87 #define PGID_AGGR 64 88 89 /* Source PGIDs, one per physical port */ 90 #define PGID_SRC 80 91 92 #define OCELOT_NUM_TC 8 93 94 #define OCELOT_SPEED_2500 0 95 #define OCELOT_SPEED_1000 1 96 #define OCELOT_SPEED_100 2 97 #define OCELOT_SPEED_10 3 98 99 #define OCELOT_PTP_PINS_NUM 4 100 101 #define TARGET_OFFSET 24 102 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0) 103 #define REG(reg, offset) [reg & REG_MASK] = offset 104 105 #define REG_RESERVED_ADDR 0xffffffff 106 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR) 107 108 enum ocelot_target { 109 ANA = 1, 110 QS, 111 QSYS, 112 REW, 113 SYS, 114 S0, 115 S1, 116 S2, 117 HSIO, 118 PTP, 119 FDMA, 120 GCB, 121 DEV_GMII, 122 TARGET_MAX, 123 }; 124 125 enum ocelot_reg { 126 ANA_ADVLEARN = ANA << TARGET_OFFSET, 127 ANA_VLANMASK, 128 ANA_PORT_B_DOMAIN, 129 ANA_ANAGEFIL, 130 ANA_ANEVENTS, 131 ANA_STORMLIMIT_BURST, 132 ANA_STORMLIMIT_CFG, 133 ANA_ISOLATED_PORTS, 134 ANA_COMMUNITY_PORTS, 135 ANA_AUTOAGE, 136 ANA_MACTOPTIONS, 137 ANA_LEARNDISC, 138 ANA_AGENCTRL, 139 ANA_MIRRORPORTS, 140 ANA_EMIRRORPORTS, 141 ANA_FLOODING, 142 ANA_FLOODING_IPMC, 143 ANA_SFLOW_CFG, 144 ANA_PORT_MODE, 145 ANA_CUT_THRU_CFG, 146 ANA_PGID_PGID, 147 ANA_TABLES_ANMOVED, 148 ANA_TABLES_MACHDATA, 149 ANA_TABLES_MACLDATA, 150 ANA_TABLES_STREAMDATA, 151 ANA_TABLES_MACACCESS, 152 ANA_TABLES_MACTINDX, 153 ANA_TABLES_VLANACCESS, 154 ANA_TABLES_VLANTIDX, 155 ANA_TABLES_ISDXACCESS, 156 ANA_TABLES_ISDXTIDX, 157 ANA_TABLES_ENTRYLIM, 158 ANA_TABLES_PTP_ID_HIGH, 159 ANA_TABLES_PTP_ID_LOW, 160 ANA_TABLES_STREAMACCESS, 161 ANA_TABLES_STREAMTIDX, 162 ANA_TABLES_SEQ_HISTORY, 163 ANA_TABLES_SEQ_MASK, 164 ANA_TABLES_SFID_MASK, 165 ANA_TABLES_SFIDACCESS, 166 ANA_TABLES_SFIDTIDX, 167 ANA_MSTI_STATE, 168 ANA_OAM_UPM_LM_CNT, 169 ANA_SG_ACCESS_CTRL, 170 ANA_SG_CONFIG_REG_1, 171 ANA_SG_CONFIG_REG_2, 172 ANA_SG_CONFIG_REG_3, 173 ANA_SG_CONFIG_REG_4, 174 ANA_SG_CONFIG_REG_5, 175 ANA_SG_GCL_GS_CONFIG, 176 ANA_SG_GCL_TI_CONFIG, 177 ANA_SG_STATUS_REG_1, 178 ANA_SG_STATUS_REG_2, 179 ANA_SG_STATUS_REG_3, 180 ANA_PORT_VLAN_CFG, 181 ANA_PORT_DROP_CFG, 182 ANA_PORT_QOS_CFG, 183 ANA_PORT_VCAP_CFG, 184 ANA_PORT_VCAP_S1_KEY_CFG, 185 ANA_PORT_VCAP_S2_CFG, 186 ANA_PORT_PCP_DEI_MAP, 187 ANA_PORT_CPU_FWD_CFG, 188 ANA_PORT_CPU_FWD_BPDU_CFG, 189 ANA_PORT_CPU_FWD_GARP_CFG, 190 ANA_PORT_CPU_FWD_CCM_CFG, 191 ANA_PORT_PORT_CFG, 192 ANA_PORT_POL_CFG, 193 ANA_PORT_PTP_CFG, 194 ANA_PORT_PTP_DLY1_CFG, 195 ANA_PORT_PTP_DLY2_CFG, 196 ANA_PORT_SFID_CFG, 197 ANA_PFC_PFC_CFG, 198 ANA_PFC_PFC_TIMER, 199 ANA_IPT_OAM_MEP_CFG, 200 ANA_IPT_IPT, 201 ANA_PPT_PPT, 202 ANA_FID_MAP_FID_MAP, 203 ANA_AGGR_CFG, 204 ANA_CPUQ_CFG, 205 ANA_CPUQ_CFG2, 206 ANA_CPUQ_8021_CFG, 207 ANA_DSCP_CFG, 208 ANA_DSCP_REWR_CFG, 209 ANA_VCAP_RNG_TYPE_CFG, 210 ANA_VCAP_RNG_VAL_CFG, 211 ANA_VRAP_CFG, 212 ANA_VRAP_HDR_DATA, 213 ANA_VRAP_HDR_MASK, 214 ANA_DISCARD_CFG, 215 ANA_FID_CFG, 216 ANA_POL_PIR_CFG, 217 ANA_POL_CIR_CFG, 218 ANA_POL_MODE_CFG, 219 ANA_POL_PIR_STATE, 220 ANA_POL_CIR_STATE, 221 ANA_POL_STATE, 222 ANA_POL_FLOWC, 223 ANA_POL_HYST, 224 ANA_POL_MISC_CFG, 225 QS_XTR_GRP_CFG = QS << TARGET_OFFSET, 226 QS_XTR_RD, 227 QS_XTR_FRM_PRUNING, 228 QS_XTR_FLUSH, 229 QS_XTR_DATA_PRESENT, 230 QS_XTR_CFG, 231 QS_INJ_GRP_CFG, 232 QS_INJ_WR, 233 QS_INJ_CTRL, 234 QS_INJ_STATUS, 235 QS_INJ_ERR, 236 QS_INH_DBG, 237 QSYS_PORT_MODE = QSYS << TARGET_OFFSET, 238 QSYS_SWITCH_PORT_MODE, 239 QSYS_STAT_CNT_CFG, 240 QSYS_EEE_CFG, 241 QSYS_EEE_THRES, 242 QSYS_IGR_NO_SHARING, 243 QSYS_EGR_NO_SHARING, 244 QSYS_SW_STATUS, 245 QSYS_EXT_CPU_CFG, 246 QSYS_PAD_CFG, 247 QSYS_CPU_GROUP_MAP, 248 QSYS_QMAP, 249 QSYS_ISDX_SGRP, 250 QSYS_TIMED_FRAME_ENTRY, 251 QSYS_TFRM_MISC, 252 QSYS_TFRM_PORT_DLY, 253 QSYS_TFRM_TIMER_CFG_1, 254 QSYS_TFRM_TIMER_CFG_2, 255 QSYS_TFRM_TIMER_CFG_3, 256 QSYS_TFRM_TIMER_CFG_4, 257 QSYS_TFRM_TIMER_CFG_5, 258 QSYS_TFRM_TIMER_CFG_6, 259 QSYS_TFRM_TIMER_CFG_7, 260 QSYS_TFRM_TIMER_CFG_8, 261 QSYS_RED_PROFILE, 262 QSYS_RES_QOS_MODE, 263 QSYS_RES_CFG, 264 QSYS_RES_STAT, 265 QSYS_EGR_DROP_MODE, 266 QSYS_EQ_CTRL, 267 QSYS_EVENTS_CORE, 268 QSYS_QMAXSDU_CFG_0, 269 QSYS_QMAXSDU_CFG_1, 270 QSYS_QMAXSDU_CFG_2, 271 QSYS_QMAXSDU_CFG_3, 272 QSYS_QMAXSDU_CFG_4, 273 QSYS_QMAXSDU_CFG_5, 274 QSYS_QMAXSDU_CFG_6, 275 QSYS_QMAXSDU_CFG_7, 276 QSYS_PREEMPTION_CFG, 277 QSYS_CIR_CFG, 278 QSYS_EIR_CFG, 279 QSYS_SE_CFG, 280 QSYS_SE_DWRR_CFG, 281 QSYS_SE_CONNECT, 282 QSYS_SE_DLB_SENSE, 283 QSYS_CIR_STATE, 284 QSYS_EIR_STATE, 285 QSYS_SE_STATE, 286 QSYS_HSCH_MISC_CFG, 287 QSYS_TAG_CONFIG, 288 QSYS_TAS_PARAM_CFG_CTRL, 289 QSYS_PORT_MAX_SDU, 290 QSYS_PARAM_CFG_REG_1, 291 QSYS_PARAM_CFG_REG_2, 292 QSYS_PARAM_CFG_REG_3, 293 QSYS_PARAM_CFG_REG_4, 294 QSYS_PARAM_CFG_REG_5, 295 QSYS_GCL_CFG_REG_1, 296 QSYS_GCL_CFG_REG_2, 297 QSYS_PARAM_STATUS_REG_1, 298 QSYS_PARAM_STATUS_REG_2, 299 QSYS_PARAM_STATUS_REG_3, 300 QSYS_PARAM_STATUS_REG_4, 301 QSYS_PARAM_STATUS_REG_5, 302 QSYS_PARAM_STATUS_REG_6, 303 QSYS_PARAM_STATUS_REG_7, 304 QSYS_PARAM_STATUS_REG_8, 305 QSYS_PARAM_STATUS_REG_9, 306 QSYS_GCL_STATUS_REG_1, 307 QSYS_GCL_STATUS_REG_2, 308 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET, 309 REW_TAG_CFG, 310 REW_PORT_CFG, 311 REW_DSCP_CFG, 312 REW_PCP_DEI_QOS_MAP_CFG, 313 REW_PTP_CFG, 314 REW_PTP_DLY1_CFG, 315 REW_RED_TAG_CFG, 316 REW_DSCP_REMAP_DP1_CFG, 317 REW_DSCP_REMAP_CFG, 318 REW_STAT_CFG, 319 REW_REW_STICKY, 320 REW_PPT, 321 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET, 322 SYS_COUNT_RX_UNICAST, 323 SYS_COUNT_RX_MULTICAST, 324 SYS_COUNT_RX_BROADCAST, 325 SYS_COUNT_RX_SHORTS, 326 SYS_COUNT_RX_FRAGMENTS, 327 SYS_COUNT_RX_JABBERS, 328 SYS_COUNT_RX_CRC_ALIGN_ERRS, 329 SYS_COUNT_RX_SYM_ERRS, 330 SYS_COUNT_RX_64, 331 SYS_COUNT_RX_65_127, 332 SYS_COUNT_RX_128_255, 333 SYS_COUNT_RX_256_511, 334 SYS_COUNT_RX_512_1023, 335 SYS_COUNT_RX_1024_1526, 336 SYS_COUNT_RX_1527_MAX, 337 SYS_COUNT_RX_PAUSE, 338 SYS_COUNT_RX_CONTROL, 339 SYS_COUNT_RX_LONGS, 340 SYS_COUNT_RX_CLASSIFIED_DROPS, 341 SYS_COUNT_RX_RED_PRIO_0, 342 SYS_COUNT_RX_RED_PRIO_1, 343 SYS_COUNT_RX_RED_PRIO_2, 344 SYS_COUNT_RX_RED_PRIO_3, 345 SYS_COUNT_RX_RED_PRIO_4, 346 SYS_COUNT_RX_RED_PRIO_5, 347 SYS_COUNT_RX_RED_PRIO_6, 348 SYS_COUNT_RX_RED_PRIO_7, 349 SYS_COUNT_RX_YELLOW_PRIO_0, 350 SYS_COUNT_RX_YELLOW_PRIO_1, 351 SYS_COUNT_RX_YELLOW_PRIO_2, 352 SYS_COUNT_RX_YELLOW_PRIO_3, 353 SYS_COUNT_RX_YELLOW_PRIO_4, 354 SYS_COUNT_RX_YELLOW_PRIO_5, 355 SYS_COUNT_RX_YELLOW_PRIO_6, 356 SYS_COUNT_RX_YELLOW_PRIO_7, 357 SYS_COUNT_RX_GREEN_PRIO_0, 358 SYS_COUNT_RX_GREEN_PRIO_1, 359 SYS_COUNT_RX_GREEN_PRIO_2, 360 SYS_COUNT_RX_GREEN_PRIO_3, 361 SYS_COUNT_RX_GREEN_PRIO_4, 362 SYS_COUNT_RX_GREEN_PRIO_5, 363 SYS_COUNT_RX_GREEN_PRIO_6, 364 SYS_COUNT_RX_GREEN_PRIO_7, 365 SYS_COUNT_RX_ASSEMBLY_ERRS, 366 SYS_COUNT_RX_SMD_ERRS, 367 SYS_COUNT_RX_ASSEMBLY_OK, 368 SYS_COUNT_RX_MERGE_FRAGMENTS, 369 SYS_COUNT_RX_PMAC_OCTETS, 370 SYS_COUNT_RX_PMAC_UNICAST, 371 SYS_COUNT_RX_PMAC_MULTICAST, 372 SYS_COUNT_RX_PMAC_BROADCAST, 373 SYS_COUNT_RX_PMAC_SHORTS, 374 SYS_COUNT_RX_PMAC_FRAGMENTS, 375 SYS_COUNT_RX_PMAC_JABBERS, 376 SYS_COUNT_RX_PMAC_CRC_ALIGN_ERRS, 377 SYS_COUNT_RX_PMAC_SYM_ERRS, 378 SYS_COUNT_RX_PMAC_64, 379 SYS_COUNT_RX_PMAC_65_127, 380 SYS_COUNT_RX_PMAC_128_255, 381 SYS_COUNT_RX_PMAC_256_511, 382 SYS_COUNT_RX_PMAC_512_1023, 383 SYS_COUNT_RX_PMAC_1024_1526, 384 SYS_COUNT_RX_PMAC_1527_MAX, 385 SYS_COUNT_RX_PMAC_PAUSE, 386 SYS_COUNT_RX_PMAC_CONTROL, 387 SYS_COUNT_RX_PMAC_LONGS, 388 SYS_COUNT_TX_OCTETS, 389 SYS_COUNT_TX_UNICAST, 390 SYS_COUNT_TX_MULTICAST, 391 SYS_COUNT_TX_BROADCAST, 392 SYS_COUNT_TX_COLLISION, 393 SYS_COUNT_TX_DROPS, 394 SYS_COUNT_TX_PAUSE, 395 SYS_COUNT_TX_64, 396 SYS_COUNT_TX_65_127, 397 SYS_COUNT_TX_128_255, 398 SYS_COUNT_TX_256_511, 399 SYS_COUNT_TX_512_1023, 400 SYS_COUNT_TX_1024_1526, 401 SYS_COUNT_TX_1527_MAX, 402 SYS_COUNT_TX_YELLOW_PRIO_0, 403 SYS_COUNT_TX_YELLOW_PRIO_1, 404 SYS_COUNT_TX_YELLOW_PRIO_2, 405 SYS_COUNT_TX_YELLOW_PRIO_3, 406 SYS_COUNT_TX_YELLOW_PRIO_4, 407 SYS_COUNT_TX_YELLOW_PRIO_5, 408 SYS_COUNT_TX_YELLOW_PRIO_6, 409 SYS_COUNT_TX_YELLOW_PRIO_7, 410 SYS_COUNT_TX_GREEN_PRIO_0, 411 SYS_COUNT_TX_GREEN_PRIO_1, 412 SYS_COUNT_TX_GREEN_PRIO_2, 413 SYS_COUNT_TX_GREEN_PRIO_3, 414 SYS_COUNT_TX_GREEN_PRIO_4, 415 SYS_COUNT_TX_GREEN_PRIO_5, 416 SYS_COUNT_TX_GREEN_PRIO_6, 417 SYS_COUNT_TX_GREEN_PRIO_7, 418 SYS_COUNT_TX_AGED, 419 SYS_COUNT_TX_MM_HOLD, 420 SYS_COUNT_TX_MERGE_FRAGMENTS, 421 SYS_COUNT_TX_PMAC_OCTETS, 422 SYS_COUNT_TX_PMAC_UNICAST, 423 SYS_COUNT_TX_PMAC_MULTICAST, 424 SYS_COUNT_TX_PMAC_BROADCAST, 425 SYS_COUNT_TX_PMAC_PAUSE, 426 SYS_COUNT_TX_PMAC_64, 427 SYS_COUNT_TX_PMAC_65_127, 428 SYS_COUNT_TX_PMAC_128_255, 429 SYS_COUNT_TX_PMAC_256_511, 430 SYS_COUNT_TX_PMAC_512_1023, 431 SYS_COUNT_TX_PMAC_1024_1526, 432 SYS_COUNT_TX_PMAC_1527_MAX, 433 SYS_COUNT_DROP_LOCAL, 434 SYS_COUNT_DROP_TAIL, 435 SYS_COUNT_DROP_YELLOW_PRIO_0, 436 SYS_COUNT_DROP_YELLOW_PRIO_1, 437 SYS_COUNT_DROP_YELLOW_PRIO_2, 438 SYS_COUNT_DROP_YELLOW_PRIO_3, 439 SYS_COUNT_DROP_YELLOW_PRIO_4, 440 SYS_COUNT_DROP_YELLOW_PRIO_5, 441 SYS_COUNT_DROP_YELLOW_PRIO_6, 442 SYS_COUNT_DROP_YELLOW_PRIO_7, 443 SYS_COUNT_DROP_GREEN_PRIO_0, 444 SYS_COUNT_DROP_GREEN_PRIO_1, 445 SYS_COUNT_DROP_GREEN_PRIO_2, 446 SYS_COUNT_DROP_GREEN_PRIO_3, 447 SYS_COUNT_DROP_GREEN_PRIO_4, 448 SYS_COUNT_DROP_GREEN_PRIO_5, 449 SYS_COUNT_DROP_GREEN_PRIO_6, 450 SYS_COUNT_DROP_GREEN_PRIO_7, 451 SYS_COUNT_SF_MATCHING_FRAMES, 452 SYS_COUNT_SF_NOT_PASSING_FRAMES, 453 SYS_COUNT_SF_NOT_PASSING_SDU, 454 SYS_COUNT_SF_RED_FRAMES, 455 SYS_RESET_CFG, 456 SYS_SR_ETYPE_CFG, 457 SYS_VLAN_ETYPE_CFG, 458 SYS_PORT_MODE, 459 SYS_FRONT_PORT_MODE, 460 SYS_FRM_AGING, 461 SYS_STAT_CFG, 462 SYS_SW_STATUS, 463 SYS_MISC_CFG, 464 SYS_REW_MAC_HIGH_CFG, 465 SYS_REW_MAC_LOW_CFG, 466 SYS_TIMESTAMP_OFFSET, 467 SYS_CMID, 468 SYS_PAUSE_CFG, 469 SYS_PAUSE_TOT_CFG, 470 SYS_ATOP, 471 SYS_ATOP_TOT_CFG, 472 SYS_MAC_FC_CFG, 473 SYS_MMGT, 474 SYS_MMGT_FAST, 475 SYS_EVENTS_DIF, 476 SYS_EVENTS_CORE, 477 SYS_PTP_STATUS, 478 SYS_PTP_TXSTAMP, 479 SYS_PTP_NXT, 480 SYS_PTP_CFG, 481 SYS_RAM_INIT, 482 SYS_CM_ADDR, 483 SYS_CM_DATA_WR, 484 SYS_CM_DATA_RD, 485 SYS_CM_OP, 486 SYS_CM_DATA, 487 PTP_PIN_CFG = PTP << TARGET_OFFSET, 488 PTP_PIN_TOD_SEC_MSB, 489 PTP_PIN_TOD_SEC_LSB, 490 PTP_PIN_TOD_NSEC, 491 PTP_PIN_WF_HIGH_PERIOD, 492 PTP_PIN_WF_LOW_PERIOD, 493 PTP_CFG_MISC, 494 PTP_CLK_CFG_ADJ_CFG, 495 PTP_CLK_CFG_ADJ_FREQ, 496 GCB_SOFT_RST = GCB << TARGET_OFFSET, 497 GCB_MIIM_MII_STATUS, 498 GCB_MIIM_MII_CMD, 499 GCB_MIIM_MII_DATA, 500 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, 501 DEV_PORT_MISC, 502 DEV_EVENTS, 503 DEV_EEE_CFG, 504 DEV_RX_PATH_DELAY, 505 DEV_TX_PATH_DELAY, 506 DEV_PTP_PREDICT_CFG, 507 DEV_MAC_ENA_CFG, 508 DEV_MAC_MODE_CFG, 509 DEV_MAC_MAXLEN_CFG, 510 DEV_MAC_TAGS_CFG, 511 DEV_MAC_ADV_CHK_CFG, 512 DEV_MAC_IFG_CFG, 513 DEV_MAC_HDX_CFG, 514 DEV_MAC_DBG_CFG, 515 DEV_MAC_FC_MAC_LOW_CFG, 516 DEV_MAC_FC_MAC_HIGH_CFG, 517 DEV_MAC_STICKY, 518 DEV_MM_ENABLE_CONFIG, 519 DEV_MM_VERIF_CONFIG, 520 DEV_MM_STATUS, 521 PCS1G_CFG, 522 PCS1G_MODE_CFG, 523 PCS1G_SD_CFG, 524 PCS1G_ANEG_CFG, 525 PCS1G_ANEG_NP_CFG, 526 PCS1G_LB_CFG, 527 PCS1G_DBG_CFG, 528 PCS1G_CDET_CFG, 529 PCS1G_ANEG_STATUS, 530 PCS1G_ANEG_NP_STATUS, 531 PCS1G_LINK_STATUS, 532 PCS1G_LINK_DOWN_CNT, 533 PCS1G_STICKY, 534 PCS1G_DEBUG_STATUS, 535 PCS1G_LPI_CFG, 536 PCS1G_LPI_WAKE_ERROR_CNT, 537 PCS1G_LPI_STATUS, 538 PCS1G_TSTPAT_MODE_CFG, 539 PCS1G_TSTPAT_STATUS, 540 DEV_PCS_FX100_CFG, 541 DEV_PCS_FX100_STATUS, 542 }; 543 544 enum ocelot_regfield { 545 ANA_ADVLEARN_VLAN_CHK, 546 ANA_ADVLEARN_LEARN_MIRROR, 547 ANA_ANEVENTS_FLOOD_DISCARD, 548 ANA_ANEVENTS_MSTI_DROP, 549 ANA_ANEVENTS_ACLKILL, 550 ANA_ANEVENTS_ACLUSED, 551 ANA_ANEVENTS_AUTOAGE, 552 ANA_ANEVENTS_VS2TTL1, 553 ANA_ANEVENTS_STORM_DROP, 554 ANA_ANEVENTS_LEARN_DROP, 555 ANA_ANEVENTS_AGED_ENTRY, 556 ANA_ANEVENTS_CPU_LEARN_FAILED, 557 ANA_ANEVENTS_AUTO_LEARN_FAILED, 558 ANA_ANEVENTS_LEARN_REMOVE, 559 ANA_ANEVENTS_AUTO_LEARNED, 560 ANA_ANEVENTS_AUTO_MOVED, 561 ANA_ANEVENTS_DROPPED, 562 ANA_ANEVENTS_CLASSIFIED_DROP, 563 ANA_ANEVENTS_CLASSIFIED_COPY, 564 ANA_ANEVENTS_VLAN_DISCARD, 565 ANA_ANEVENTS_FWD_DISCARD, 566 ANA_ANEVENTS_MULTICAST_FLOOD, 567 ANA_ANEVENTS_UNICAST_FLOOD, 568 ANA_ANEVENTS_DEST_KNOWN, 569 ANA_ANEVENTS_BUCKET3_MATCH, 570 ANA_ANEVENTS_BUCKET2_MATCH, 571 ANA_ANEVENTS_BUCKET1_MATCH, 572 ANA_ANEVENTS_BUCKET0_MATCH, 573 ANA_ANEVENTS_CPU_OPERATION, 574 ANA_ANEVENTS_DMAC_LOOKUP, 575 ANA_ANEVENTS_SMAC_LOOKUP, 576 ANA_ANEVENTS_SEQ_GEN_ERR_0, 577 ANA_ANEVENTS_SEQ_GEN_ERR_1, 578 ANA_TABLES_MACACCESS_B_DOM, 579 ANA_TABLES_MACTINDX_BUCKET, 580 ANA_TABLES_MACTINDX_M_INDEX, 581 QSYS_SWITCH_PORT_MODE_PORT_ENA, 582 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG, 583 QSYS_SWITCH_PORT_MODE_YEL_RSRVD, 584 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE, 585 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 586 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE, 587 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD, 588 QSYS_TIMED_FRAME_ENTRY_TFRM_FP, 589 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO, 590 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL, 591 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T, 592 SYS_PORT_MODE_DATA_WO_TS, 593 SYS_PORT_MODE_INCL_INJ_HDR, 594 SYS_PORT_MODE_INCL_XTR_HDR, 595 SYS_PORT_MODE_INCL_HDR_ERR, 596 SYS_RESET_CFG_CORE_ENA, 597 SYS_RESET_CFG_MEM_ENA, 598 SYS_RESET_CFG_MEM_INIT, 599 GCB_SOFT_RST_SWC_RST, 600 GCB_MIIM_MII_STATUS_PENDING, 601 GCB_MIIM_MII_STATUS_BUSY, 602 SYS_PAUSE_CFG_PAUSE_START, 603 SYS_PAUSE_CFG_PAUSE_STOP, 604 SYS_PAUSE_CFG_PAUSE_ENA, 605 REGFIELD_MAX 606 }; 607 608 enum { 609 /* VCAP_CORE_CFG */ 610 VCAP_CORE_UPDATE_CTRL, 611 VCAP_CORE_MV_CFG, 612 /* VCAP_CORE_CACHE */ 613 VCAP_CACHE_ENTRY_DAT, 614 VCAP_CACHE_MASK_DAT, 615 VCAP_CACHE_ACTION_DAT, 616 VCAP_CACHE_CNT_DAT, 617 VCAP_CACHE_TG_DAT, 618 /* VCAP_CONST */ 619 VCAP_CONST_VCAP_VER, 620 VCAP_CONST_ENTRY_WIDTH, 621 VCAP_CONST_ENTRY_CNT, 622 VCAP_CONST_ENTRY_SWCNT, 623 VCAP_CONST_ENTRY_TG_WIDTH, 624 VCAP_CONST_ACTION_DEF_CNT, 625 VCAP_CONST_ACTION_WIDTH, 626 VCAP_CONST_CNT_WIDTH, 627 VCAP_CONST_CORE_CNT, 628 VCAP_CONST_IF_CNT, 629 }; 630 631 enum ocelot_ptp_pins { 632 PTP_PIN_0, 633 PTP_PIN_1, 634 PTP_PIN_2, 635 PTP_PIN_3, 636 TOD_ACC_PIN 637 }; 638 639 enum ocelot_tag_prefix { 640 OCELOT_TAG_PREFIX_DISABLED = 0, 641 OCELOT_TAG_PREFIX_NONE, 642 OCELOT_TAG_PREFIX_SHORT, 643 OCELOT_TAG_PREFIX_LONG, 644 }; 645 646 struct ocelot; 647 struct device_node; 648 649 struct ocelot_ops { 650 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port); 651 int (*netdev_to_port)(struct net_device *dev); 652 int (*reset)(struct ocelot *ocelot); 653 u16 (*wm_enc)(u16 value); 654 u16 (*wm_dec)(u16 value); 655 void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse); 656 void (*psfp_init)(struct ocelot *ocelot); 657 int (*psfp_filter_add)(struct ocelot *ocelot, int port, 658 struct flow_cls_offload *f); 659 int (*psfp_filter_del)(struct ocelot *ocelot, struct flow_cls_offload *f); 660 int (*psfp_stats_get)(struct ocelot *ocelot, struct flow_cls_offload *f, 661 struct flow_stats *stats); 662 void (*cut_through_fwd)(struct ocelot *ocelot); 663 void (*tas_clock_adjust)(struct ocelot *ocelot); 664 void (*update_stats)(struct ocelot *ocelot); 665 }; 666 667 struct ocelot_vcap_policer { 668 struct list_head pol_list; 669 u16 base; 670 u16 max; 671 u16 base2; 672 u16 max2; 673 }; 674 675 struct ocelot_vcap_block { 676 struct list_head rules; 677 int count; 678 }; 679 680 struct ocelot_bridge_vlan { 681 u16 vid; 682 unsigned long portmask; 683 unsigned long untagged; 684 struct list_head list; 685 }; 686 687 enum ocelot_port_tag_config { 688 /* all VLANs are egress-untagged */ 689 OCELOT_PORT_TAG_DISABLED = 0, 690 /* all VLANs except the native VLAN and VID 0 are egress-tagged */ 691 OCELOT_PORT_TAG_NATIVE = 1, 692 /* all VLANs except VID 0 are egress-tagged */ 693 OCELOT_PORT_TAG_TRUNK_NO_VID0 = 2, 694 /* all VLANs are egress-tagged */ 695 OCELOT_PORT_TAG_TRUNK = 3, 696 }; 697 698 struct ocelot_psfp_list { 699 struct list_head stream_list; 700 struct list_head sfi_list; 701 struct list_head sgi_list; 702 /* Serialize access to the lists */ 703 struct mutex lock; 704 }; 705 706 enum ocelot_sb { 707 OCELOT_SB_BUF, 708 OCELOT_SB_REF, 709 OCELOT_SB_NUM, 710 }; 711 712 enum ocelot_sb_pool { 713 OCELOT_SB_POOL_ING, 714 OCELOT_SB_POOL_EGR, 715 OCELOT_SB_POOL_NUM, 716 }; 717 718 /* MAC table entry types. 719 * ENTRYTYPE_NORMAL is subject to aging. 720 * ENTRYTYPE_LOCKED is not subject to aging. 721 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 722 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 723 */ 724 enum macaccess_entry_type { 725 ENTRYTYPE_NORMAL = 0, 726 ENTRYTYPE_LOCKED, 727 ENTRYTYPE_MACv4, 728 ENTRYTYPE_MACv6, 729 }; 730 731 #define OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION BIT(0) 732 #define OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP BIT(1) 733 734 struct ocelot_lag_fdb { 735 unsigned char addr[ETH_ALEN]; 736 u16 vid; 737 struct net_device *bond; 738 struct list_head list; 739 }; 740 741 struct ocelot_mirror { 742 refcount_t refcount; 743 int to; 744 }; 745 746 struct ocelot_mm_state { 747 struct mutex lock; 748 enum ethtool_mm_verify_status verify_status; 749 bool tx_active; 750 }; 751 752 struct ocelot_port; 753 754 struct ocelot_port { 755 struct ocelot *ocelot; 756 757 struct regmap *target; 758 759 struct net_device *bond; 760 struct net_device *bridge; 761 762 struct ocelot_port *dsa_8021q_cpu; 763 764 /* VLAN that untagged frames are classified to, on ingress */ 765 const struct ocelot_bridge_vlan *pvid_vlan; 766 767 struct tc_taprio_qopt_offload *taprio; 768 769 phy_interface_t phy_mode; 770 771 unsigned int ptp_skbs_in_flight; 772 struct sk_buff_head tx_skbs; 773 774 u16 mrp_ring_id; 775 776 u8 ptp_cmd; 777 u8 ts_id; 778 779 u8 index; 780 781 u8 stp_state; 782 bool vlan_aware; 783 bool is_dsa_8021q_cpu; 784 bool learn_ena; 785 786 bool lag_tx_active; 787 788 int bridge_num; 789 790 int speed; 791 }; 792 793 struct ocelot { 794 struct device *dev; 795 struct devlink *devlink; 796 struct devlink_port *devlink_ports; 797 798 const struct ocelot_ops *ops; 799 struct regmap *targets[TARGET_MAX]; 800 struct regmap_field *regfields[REGFIELD_MAX]; 801 const u32 *const *map; 802 struct list_head stats_regions; 803 804 u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM]; 805 int packet_buffer_size; 806 int num_frame_refs; 807 int num_mact_rows; 808 809 struct ocelot_port **ports; 810 811 u8 base_mac[ETH_ALEN]; 812 813 struct list_head vlans; 814 struct list_head traps; 815 struct list_head lag_fdbs; 816 817 /* Switches like VSC9959 have flooding per traffic class */ 818 int num_flooding_pgids; 819 820 /* In tables like ANA:PORT and the ANA:PGID:PGID mask, 821 * the CPU is located after the physical ports (at the 822 * num_phys_ports index). 823 */ 824 u8 num_phys_ports; 825 826 int npi; 827 828 enum ocelot_tag_prefix npi_inj_prefix; 829 enum ocelot_tag_prefix npi_xtr_prefix; 830 831 unsigned long bridges; 832 833 struct list_head multicast; 834 struct list_head pgids; 835 836 struct list_head dummy_rules; 837 struct ocelot_vcap_block block[3]; 838 struct ocelot_vcap_policer vcap_pol; 839 struct vcap_props *vcap; 840 struct ocelot_mirror *mirror; 841 842 struct ocelot_psfp_list psfp; 843 844 /* Workqueue to check statistics for overflow */ 845 struct delayed_work stats_work; 846 struct workqueue_struct *stats_queue; 847 /* Lock for serializing access to the statistics array */ 848 spinlock_t stats_lock; 849 u64 *stats; 850 851 /* Lock for serializing indirect access to STAT_VIEW registers */ 852 struct mutex stat_view_lock; 853 /* Lock for serializing access to the MAC table */ 854 struct mutex mact_lock; 855 /* Lock for serializing forwarding domain changes */ 856 struct mutex fwd_domain_lock; 857 858 /* Lock for serializing Time-Aware Shaper changes */ 859 struct mutex tas_lock; 860 861 struct workqueue_struct *owq; 862 863 u8 ptp:1; 864 u8 mm_supported:1; 865 struct ptp_clock *ptp_clock; 866 struct ptp_clock_info ptp_info; 867 struct hwtstamp_config hwtstamp_config; 868 unsigned int ptp_skbs_in_flight; 869 /* Protects the 2-step TX timestamp ID logic */ 870 spinlock_t ts_id_lock; 871 /* Protects the PTP interface state */ 872 struct mutex ptp_lock; 873 /* Protects the PTP clock */ 874 spinlock_t ptp_clock_lock; 875 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM]; 876 877 struct ocelot_mm_state *mm; 878 879 struct ocelot_fdma *fdma; 880 }; 881 882 struct ocelot_policer { 883 u32 rate; /* kilobit per second */ 884 u32 burst; /* bytes */ 885 }; 886 887 #define ocelot_bulk_read(ocelot, reg, buf, count) \ 888 __ocelot_bulk_read_ix(ocelot, reg, 0, buf, count) 889 890 #define ocelot_read_ix(ocelot, reg, gi, ri) \ 891 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 892 #define ocelot_read_gix(ocelot, reg, gi) \ 893 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) 894 #define ocelot_read_rix(ocelot, reg, ri) \ 895 __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) 896 #define ocelot_read(ocelot, reg) \ 897 __ocelot_read_ix(ocelot, reg, 0) 898 899 #define ocelot_write_ix(ocelot, val, reg, gi, ri) \ 900 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 901 #define ocelot_write_gix(ocelot, val, reg, gi) \ 902 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) 903 #define ocelot_write_rix(ocelot, val, reg, ri) \ 904 __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) 905 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) 906 907 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) \ 908 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 909 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) \ 910 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) 911 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) \ 912 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) 913 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) 914 915 #define ocelot_field_write(ocelot, reg, val) \ 916 regmap_field_write((ocelot)->regfields[(reg)], (val)) 917 #define ocelot_field_read(ocelot, reg, val) \ 918 regmap_field_read((ocelot)->regfields[(reg)], (val)) 919 #define ocelot_fields_write(ocelot, id, reg, val) \ 920 regmap_fields_write((ocelot)->regfields[(reg)], (id), (val)) 921 #define ocelot_fields_read(ocelot, id, reg, val) \ 922 regmap_fields_read((ocelot)->regfields[(reg)], (id), (val)) 923 924 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \ 925 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 926 #define ocelot_target_read_gix(ocelot, target, reg, gi) \ 927 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi)) 928 #define ocelot_target_read_rix(ocelot, target, reg, ri) \ 929 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri)) 930 #define ocelot_target_read(ocelot, target, reg) \ 931 __ocelot_target_read_ix(ocelot, target, reg, 0) 932 933 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \ 934 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 935 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \ 936 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi)) 937 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \ 938 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri)) 939 #define ocelot_target_write(ocelot, target, val, reg) \ 940 __ocelot_target_write_ix(ocelot, target, val, reg, 0) 941 942 /* I/O */ 943 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); 944 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); 945 void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, u32 reg); 946 int __ocelot_bulk_read_ix(struct ocelot *ocelot, u32 reg, u32 offset, void *buf, 947 int count); 948 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); 949 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); 950 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, 951 u32 offset); 952 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target, 953 u32 reg, u32 offset); 954 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target, 955 u32 val, u32 reg, u32 offset); 956 957 /* Packet I/O */ 958 bool ocelot_can_inject(struct ocelot *ocelot, int grp); 959 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 960 u32 rew_op, struct sk_buff *skb); 961 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag); 962 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb); 963 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp); 964 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb, 965 u64 timestamp); 966 967 /* Hardware initialization */ 968 int ocelot_regfields_init(struct ocelot *ocelot, 969 const struct reg_field *const regfields); 970 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res); 971 int ocelot_reset(struct ocelot *ocelot); 972 int ocelot_init(struct ocelot *ocelot); 973 void ocelot_deinit(struct ocelot *ocelot); 974 void ocelot_init_port(struct ocelot *ocelot, int port); 975 void ocelot_deinit_port(struct ocelot *ocelot, int port); 976 977 void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu); 978 void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu); 979 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, int cpu); 980 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port); 981 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port); 982 983 /* Watermark interface */ 984 u16 ocelot_wm_enc(u16 value); 985 u16 ocelot_wm_dec(u16 wm); 986 void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse); 987 988 /* DSA callbacks */ 989 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data); 990 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data); 991 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset); 992 void ocelot_port_get_stats64(struct ocelot *ocelot, int port, 993 struct rtnl_link_stats64 *stats); 994 void ocelot_port_get_pause_stats(struct ocelot *ocelot, int port, 995 struct ethtool_pause_stats *pause_stats); 996 void ocelot_port_get_mm_stats(struct ocelot *ocelot, int port, 997 struct ethtool_mm_stats *stats); 998 void ocelot_port_get_rmon_stats(struct ocelot *ocelot, int port, 999 struct ethtool_rmon_stats *rmon_stats, 1000 const struct ethtool_rmon_hist_range **ranges); 1001 void ocelot_port_get_eth_ctrl_stats(struct ocelot *ocelot, int port, 1002 struct ethtool_eth_ctrl_stats *ctrl_stats); 1003 void ocelot_port_get_eth_mac_stats(struct ocelot *ocelot, int port, 1004 struct ethtool_eth_mac_stats *mac_stats); 1005 void ocelot_port_get_eth_phy_stats(struct ocelot *ocelot, int port, 1006 struct ethtool_eth_phy_stats *phy_stats); 1007 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1008 struct ethtool_ts_info *info); 1009 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs); 1010 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled, 1011 struct netlink_ext_ack *extack); 1012 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state); 1013 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port); 1014 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 1015 struct switchdev_brport_flags val); 1016 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 1017 struct switchdev_brport_flags val); 1018 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port); 1019 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio); 1020 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp); 1021 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio); 1022 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio); 1023 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1024 struct net_device *bridge, int bridge_num, 1025 struct netlink_ext_ack *extack); 1026 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1027 struct net_device *bridge); 1028 int ocelot_mact_flush(struct ocelot *ocelot, int port); 1029 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1030 dsa_fdb_dump_cb_t *cb, void *data); 1031 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr, 1032 u16 vid, const struct net_device *bridge); 1033 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr, 1034 u16 vid, const struct net_device *bridge); 1035 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond, 1036 const unsigned char *addr, u16 vid, 1037 const struct net_device *bridge); 1038 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond, 1039 const unsigned char *addr, u16 vid, 1040 const struct net_device *bridge); 1041 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 1042 bool untagged, struct netlink_ext_ack *extack); 1043 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 1044 bool untagged); 1045 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid); 1046 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr); 1047 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr); 1048 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 1049 struct sk_buff *skb, 1050 struct sk_buff **clone); 1051 void ocelot_get_txtstamp(struct ocelot *ocelot); 1052 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu); 1053 int ocelot_get_max_mtu(struct ocelot *ocelot, int port); 1054 int ocelot_port_policer_add(struct ocelot *ocelot, int port, 1055 struct ocelot_policer *pol); 1056 int ocelot_port_policer_del(struct ocelot *ocelot, int port); 1057 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to, 1058 bool ingress, struct netlink_ext_ack *extack); 1059 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress); 1060 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port, 1061 struct flow_cls_offload *f, bool ingress); 1062 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port, 1063 struct flow_cls_offload *f, bool ingress); 1064 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port, 1065 struct flow_cls_offload *f, bool ingress); 1066 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1067 const struct switchdev_obj_port_mdb *mdb, 1068 const struct net_device *bridge); 1069 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1070 const struct switchdev_obj_port_mdb *mdb, 1071 const struct net_device *bridge); 1072 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1073 struct net_device *bond, 1074 struct netdev_lag_upper_info *info, 1075 struct netlink_ext_ack *extack); 1076 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1077 struct net_device *bond); 1078 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active); 1079 int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond); 1080 1081 int ocelot_devlink_sb_register(struct ocelot *ocelot); 1082 void ocelot_devlink_sb_unregister(struct ocelot *ocelot); 1083 int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index, 1084 u16 pool_index, 1085 struct devlink_sb_pool_info *pool_info); 1086 int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index, 1087 u16 pool_index, u32 size, 1088 enum devlink_sb_threshold_type threshold_type, 1089 struct netlink_ext_ack *extack); 1090 int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port, 1091 unsigned int sb_index, u16 pool_index, 1092 u32 *p_threshold); 1093 int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port, 1094 unsigned int sb_index, u16 pool_index, 1095 u32 threshold, struct netlink_ext_ack *extack); 1096 int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port, 1097 unsigned int sb_index, u16 tc_index, 1098 enum devlink_sb_pool_type pool_type, 1099 u16 *p_pool_index, u32 *p_threshold); 1100 int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port, 1101 unsigned int sb_index, u16 tc_index, 1102 enum devlink_sb_pool_type pool_type, 1103 u16 pool_index, u32 threshold, 1104 struct netlink_ext_ack *extack); 1105 int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index); 1106 int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index); 1107 int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port, 1108 unsigned int sb_index, u16 pool_index, 1109 u32 *p_cur, u32 *p_max); 1110 int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port, 1111 unsigned int sb_index, u16 tc_index, 1112 enum devlink_sb_pool_type pool_type, 1113 u32 *p_cur, u32 *p_max); 1114 1115 int ocelot_port_configure_serdes(struct ocelot *ocelot, int port, 1116 struct device_node *portnp); 1117 1118 void ocelot_phylink_mac_config(struct ocelot *ocelot, int port, 1119 unsigned int link_an_mode, 1120 const struct phylink_link_state *state); 1121 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 1122 unsigned int link_an_mode, 1123 phy_interface_t interface, 1124 unsigned long quirks); 1125 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 1126 struct phy_device *phydev, 1127 unsigned int link_an_mode, 1128 phy_interface_t interface, 1129 int speed, int duplex, 1130 bool tx_pause, bool rx_pause, 1131 unsigned long quirks); 1132 1133 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx, 1134 const unsigned char mac[ETH_ALEN], 1135 unsigned int vid, enum macaccess_entry_type *type); 1136 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx, 1137 const unsigned char mac[ETH_ALEN], 1138 unsigned int vid, 1139 enum macaccess_entry_type type, 1140 int sfid, int ssid); 1141 1142 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask, 1143 unsigned long to_mask); 1144 1145 int ocelot_vcap_policer_add(struct ocelot *ocelot, u32 pol_ix, 1146 struct ocelot_policer *pol); 1147 int ocelot_vcap_policer_del(struct ocelot *ocelot, u32 pol_ix); 1148 1149 void ocelot_port_mm_irq(struct ocelot *ocelot, int port); 1150 int ocelot_port_set_mm(struct ocelot *ocelot, int port, 1151 struct ethtool_mm_cfg *cfg, 1152 struct netlink_ext_ack *extack); 1153 int ocelot_port_get_mm(struct ocelot *ocelot, int port, 1154 struct ethtool_mm_state *state); 1155 1156 #if IS_ENABLED(CONFIG_BRIDGE_MRP) 1157 int ocelot_mrp_add(struct ocelot *ocelot, int port, 1158 const struct switchdev_obj_mrp *mrp); 1159 int ocelot_mrp_del(struct ocelot *ocelot, int port, 1160 const struct switchdev_obj_mrp *mrp); 1161 int ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port, 1162 const struct switchdev_obj_ring_role_mrp *mrp); 1163 int ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, 1164 const struct switchdev_obj_ring_role_mrp *mrp); 1165 #else 1166 static inline int ocelot_mrp_add(struct ocelot *ocelot, int port, 1167 const struct switchdev_obj_mrp *mrp) 1168 { 1169 return -EOPNOTSUPP; 1170 } 1171 1172 static inline int ocelot_mrp_del(struct ocelot *ocelot, int port, 1173 const struct switchdev_obj_mrp *mrp) 1174 { 1175 return -EOPNOTSUPP; 1176 } 1177 1178 static inline int 1179 ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port, 1180 const struct switchdev_obj_ring_role_mrp *mrp) 1181 { 1182 return -EOPNOTSUPP; 1183 } 1184 1185 static inline int 1186 ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, 1187 const struct switchdev_obj_ring_role_mrp *mrp) 1188 { 1189 return -EOPNOTSUPP; 1190 } 1191 #endif 1192 1193 void ocelot_pll5_init(struct ocelot *ocelot); 1194 1195 #endif 1196