1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* Copyright (c) 2017 Microsemi Corporation 3 */ 4 5 #ifndef _SOC_MSCC_OCELOT_H 6 #define _SOC_MSCC_OCELOT_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/net_tstamp.h> 10 #include <linux/if_vlan.h> 11 #include <linux/regmap.h> 12 #include <net/dsa.h> 13 14 struct tc_mqprio_qopt_offload; 15 16 /* Port Group IDs (PGID) are masks of destination ports. 17 * 18 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each 19 * frame, and forwards the frame to the ports that are present in the logical 20 * AND of all 3 PGIDs. 21 * 22 * These PGID lookups are: 23 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by 24 * which the switch selects a destination PGID: 25 * - The {DMAC, VID} is present in the MAC table. In that case, the 26 * destination PGID is given by the DEST_IDX field of the MAC table entry 27 * that matched. 28 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The 29 * frame is disseminated as being either unicast, multicast or broadcast, 30 * and according to that, the destination PGID is chosen as being the 31 * value contained by ANA_FLOODING_FLD_UNICAST, 32 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST. 33 * The destination PGID can be an unicast set: the first PGIDs, 0 to 34 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from 35 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to 36 * a physical port and has a single bit set in the destination ports mask: 37 * that corresponding to the port number itself. In contrast, a multicast 38 * PGID will have potentially more than one single bit set in the destination 39 * ports mask. 40 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier 41 * dissects each frame and generates a 4-bit Link Aggregation Code which is 42 * used for this second PGID table lookup. The goal of link aggregation is to 43 * hash multiple flows within the same LAG on to different destination ports. 44 * The first lookup will result in a PGID with all the LAG members present in 45 * the destination ports mask, and the second lookup, by Link Aggregation 46 * Code, will ensure that each flow gets forwarded only to a single port out 47 * of that mask (there are no duplicates). 48 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table 49 * is indexed with the ingress port (plus 80). These PGIDs answer the 50 * question "is port i allowed to forward traffic to port j?" If yes, then 51 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used 52 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge. 53 */ 54 55 /* Reserve some destination PGIDs at the end of the range: 56 * PGID_BLACKHOLE: used for not forwarding the frames 57 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses 58 * of the switch port net devices, towards the CPU port module. 59 * PGID_UC: the flooding destinations for unknown unicast traffic. 60 * PGID_MC: the flooding destinations for non-IP multicast traffic. 61 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic. 62 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic. 63 * PGID_BC: the flooding destinations for broadcast traffic. 64 */ 65 #define PGID_BLACKHOLE 57 66 #define PGID_CPU 58 67 #define PGID_UC 59 68 #define PGID_MC 60 69 #define PGID_MCIPV4 61 70 #define PGID_MCIPV6 62 71 #define PGID_BC 63 72 73 #define for_each_unicast_dest_pgid(ocelot, pgid) \ 74 for ((pgid) = 0; \ 75 (pgid) < (ocelot)->num_phys_ports; \ 76 (pgid)++) 77 78 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \ 79 for ((pgid) = (ocelot)->num_phys_ports + 1; \ 80 (pgid) < PGID_BLACKHOLE; \ 81 (pgid)++) 82 83 #define for_each_aggr_pgid(ocelot, pgid) \ 84 for ((pgid) = PGID_AGGR; \ 85 (pgid) < PGID_SRC; \ 86 (pgid)++) 87 88 /* Aggregation PGIDs, one per Link Aggregation Code */ 89 #define PGID_AGGR 64 90 91 /* Source PGIDs, one per physical port */ 92 #define PGID_SRC 80 93 94 #define OCELOT_NUM_TC 8 95 96 #define OCELOT_SPEED_2500 0 97 #define OCELOT_SPEED_1000 1 98 #define OCELOT_SPEED_100 2 99 #define OCELOT_SPEED_10 3 100 101 #define OCELOT_PTP_PINS_NUM 4 102 103 #define TARGET_OFFSET 24 104 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0) 105 #define REG(reg, offset) [reg & REG_MASK] = offset 106 107 #define REG_RESERVED_ADDR 0xffffffff 108 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR) 109 110 enum ocelot_target { 111 ANA = 1, 112 QS, 113 QSYS, 114 REW, 115 SYS, 116 S0, 117 S1, 118 S2, 119 HSIO, 120 PTP, 121 FDMA, 122 GCB, 123 DEV_GMII, 124 TARGET_MAX, 125 }; 126 127 enum ocelot_reg { 128 ANA_ADVLEARN = ANA << TARGET_OFFSET, 129 ANA_VLANMASK, 130 ANA_PORT_B_DOMAIN, 131 ANA_ANAGEFIL, 132 ANA_ANEVENTS, 133 ANA_STORMLIMIT_BURST, 134 ANA_STORMLIMIT_CFG, 135 ANA_ISOLATED_PORTS, 136 ANA_COMMUNITY_PORTS, 137 ANA_AUTOAGE, 138 ANA_MACTOPTIONS, 139 ANA_LEARNDISC, 140 ANA_AGENCTRL, 141 ANA_MIRRORPORTS, 142 ANA_EMIRRORPORTS, 143 ANA_FLOODING, 144 ANA_FLOODING_IPMC, 145 ANA_SFLOW_CFG, 146 ANA_PORT_MODE, 147 ANA_CUT_THRU_CFG, 148 ANA_PGID_PGID, 149 ANA_TABLES_ANMOVED, 150 ANA_TABLES_MACHDATA, 151 ANA_TABLES_MACLDATA, 152 ANA_TABLES_STREAMDATA, 153 ANA_TABLES_MACACCESS, 154 ANA_TABLES_MACTINDX, 155 ANA_TABLES_VLANACCESS, 156 ANA_TABLES_VLANTIDX, 157 ANA_TABLES_ISDXACCESS, 158 ANA_TABLES_ISDXTIDX, 159 ANA_TABLES_ENTRYLIM, 160 ANA_TABLES_PTP_ID_HIGH, 161 ANA_TABLES_PTP_ID_LOW, 162 ANA_TABLES_STREAMACCESS, 163 ANA_TABLES_STREAMTIDX, 164 ANA_TABLES_SEQ_HISTORY, 165 ANA_TABLES_SEQ_MASK, 166 ANA_TABLES_SFID_MASK, 167 ANA_TABLES_SFIDACCESS, 168 ANA_TABLES_SFIDTIDX, 169 ANA_MSTI_STATE, 170 ANA_OAM_UPM_LM_CNT, 171 ANA_SG_ACCESS_CTRL, 172 ANA_SG_CONFIG_REG_1, 173 ANA_SG_CONFIG_REG_2, 174 ANA_SG_CONFIG_REG_3, 175 ANA_SG_CONFIG_REG_4, 176 ANA_SG_CONFIG_REG_5, 177 ANA_SG_GCL_GS_CONFIG, 178 ANA_SG_GCL_TI_CONFIG, 179 ANA_SG_STATUS_REG_1, 180 ANA_SG_STATUS_REG_2, 181 ANA_SG_STATUS_REG_3, 182 ANA_PORT_VLAN_CFG, 183 ANA_PORT_DROP_CFG, 184 ANA_PORT_QOS_CFG, 185 ANA_PORT_VCAP_CFG, 186 ANA_PORT_VCAP_S1_KEY_CFG, 187 ANA_PORT_VCAP_S2_CFG, 188 ANA_PORT_PCP_DEI_MAP, 189 ANA_PORT_CPU_FWD_CFG, 190 ANA_PORT_CPU_FWD_BPDU_CFG, 191 ANA_PORT_CPU_FWD_GARP_CFG, 192 ANA_PORT_CPU_FWD_CCM_CFG, 193 ANA_PORT_PORT_CFG, 194 ANA_PORT_POL_CFG, 195 ANA_PORT_PTP_CFG, 196 ANA_PORT_PTP_DLY1_CFG, 197 ANA_PORT_PTP_DLY2_CFG, 198 ANA_PORT_SFID_CFG, 199 ANA_PFC_PFC_CFG, 200 ANA_PFC_PFC_TIMER, 201 ANA_IPT_OAM_MEP_CFG, 202 ANA_IPT_IPT, 203 ANA_PPT_PPT, 204 ANA_FID_MAP_FID_MAP, 205 ANA_AGGR_CFG, 206 ANA_CPUQ_CFG, 207 ANA_CPUQ_CFG2, 208 ANA_CPUQ_8021_CFG, 209 ANA_DSCP_CFG, 210 ANA_DSCP_REWR_CFG, 211 ANA_VCAP_RNG_TYPE_CFG, 212 ANA_VCAP_RNG_VAL_CFG, 213 ANA_VRAP_CFG, 214 ANA_VRAP_HDR_DATA, 215 ANA_VRAP_HDR_MASK, 216 ANA_DISCARD_CFG, 217 ANA_FID_CFG, 218 ANA_POL_PIR_CFG, 219 ANA_POL_CIR_CFG, 220 ANA_POL_MODE_CFG, 221 ANA_POL_PIR_STATE, 222 ANA_POL_CIR_STATE, 223 ANA_POL_STATE, 224 ANA_POL_FLOWC, 225 ANA_POL_HYST, 226 ANA_POL_MISC_CFG, 227 QS_XTR_GRP_CFG = QS << TARGET_OFFSET, 228 QS_XTR_RD, 229 QS_XTR_FRM_PRUNING, 230 QS_XTR_FLUSH, 231 QS_XTR_DATA_PRESENT, 232 QS_XTR_CFG, 233 QS_INJ_GRP_CFG, 234 QS_INJ_WR, 235 QS_INJ_CTRL, 236 QS_INJ_STATUS, 237 QS_INJ_ERR, 238 QS_INH_DBG, 239 QSYS_PORT_MODE = QSYS << TARGET_OFFSET, 240 QSYS_SWITCH_PORT_MODE, 241 QSYS_STAT_CNT_CFG, 242 QSYS_EEE_CFG, 243 QSYS_EEE_THRES, 244 QSYS_IGR_NO_SHARING, 245 QSYS_EGR_NO_SHARING, 246 QSYS_SW_STATUS, 247 QSYS_EXT_CPU_CFG, 248 QSYS_PAD_CFG, 249 QSYS_CPU_GROUP_MAP, 250 QSYS_QMAP, 251 QSYS_ISDX_SGRP, 252 QSYS_TIMED_FRAME_ENTRY, 253 QSYS_TFRM_MISC, 254 QSYS_TFRM_PORT_DLY, 255 QSYS_TFRM_TIMER_CFG_1, 256 QSYS_TFRM_TIMER_CFG_2, 257 QSYS_TFRM_TIMER_CFG_3, 258 QSYS_TFRM_TIMER_CFG_4, 259 QSYS_TFRM_TIMER_CFG_5, 260 QSYS_TFRM_TIMER_CFG_6, 261 QSYS_TFRM_TIMER_CFG_7, 262 QSYS_TFRM_TIMER_CFG_8, 263 QSYS_RED_PROFILE, 264 QSYS_RES_QOS_MODE, 265 QSYS_RES_CFG, 266 QSYS_RES_STAT, 267 QSYS_EGR_DROP_MODE, 268 QSYS_EQ_CTRL, 269 QSYS_EVENTS_CORE, 270 QSYS_QMAXSDU_CFG_0, 271 QSYS_QMAXSDU_CFG_1, 272 QSYS_QMAXSDU_CFG_2, 273 QSYS_QMAXSDU_CFG_3, 274 QSYS_QMAXSDU_CFG_4, 275 QSYS_QMAXSDU_CFG_5, 276 QSYS_QMAXSDU_CFG_6, 277 QSYS_QMAXSDU_CFG_7, 278 QSYS_PREEMPTION_CFG, 279 QSYS_CIR_CFG, 280 QSYS_EIR_CFG, 281 QSYS_SE_CFG, 282 QSYS_SE_DWRR_CFG, 283 QSYS_SE_CONNECT, 284 QSYS_SE_DLB_SENSE, 285 QSYS_CIR_STATE, 286 QSYS_EIR_STATE, 287 QSYS_SE_STATE, 288 QSYS_HSCH_MISC_CFG, 289 QSYS_TAG_CONFIG, 290 QSYS_TAS_PARAM_CFG_CTRL, 291 QSYS_PORT_MAX_SDU, 292 QSYS_PARAM_CFG_REG_1, 293 QSYS_PARAM_CFG_REG_2, 294 QSYS_PARAM_CFG_REG_3, 295 QSYS_PARAM_CFG_REG_4, 296 QSYS_PARAM_CFG_REG_5, 297 QSYS_GCL_CFG_REG_1, 298 QSYS_GCL_CFG_REG_2, 299 QSYS_PARAM_STATUS_REG_1, 300 QSYS_PARAM_STATUS_REG_2, 301 QSYS_PARAM_STATUS_REG_3, 302 QSYS_PARAM_STATUS_REG_4, 303 QSYS_PARAM_STATUS_REG_5, 304 QSYS_PARAM_STATUS_REG_6, 305 QSYS_PARAM_STATUS_REG_7, 306 QSYS_PARAM_STATUS_REG_8, 307 QSYS_PARAM_STATUS_REG_9, 308 QSYS_GCL_STATUS_REG_1, 309 QSYS_GCL_STATUS_REG_2, 310 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET, 311 REW_TAG_CFG, 312 REW_PORT_CFG, 313 REW_DSCP_CFG, 314 REW_PCP_DEI_QOS_MAP_CFG, 315 REW_PTP_CFG, 316 REW_PTP_DLY1_CFG, 317 REW_RED_TAG_CFG, 318 REW_DSCP_REMAP_DP1_CFG, 319 REW_DSCP_REMAP_CFG, 320 REW_STAT_CFG, 321 REW_REW_STICKY, 322 REW_PPT, 323 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET, 324 SYS_COUNT_RX_UNICAST, 325 SYS_COUNT_RX_MULTICAST, 326 SYS_COUNT_RX_BROADCAST, 327 SYS_COUNT_RX_SHORTS, 328 SYS_COUNT_RX_FRAGMENTS, 329 SYS_COUNT_RX_JABBERS, 330 SYS_COUNT_RX_CRC_ALIGN_ERRS, 331 SYS_COUNT_RX_SYM_ERRS, 332 SYS_COUNT_RX_64, 333 SYS_COUNT_RX_65_127, 334 SYS_COUNT_RX_128_255, 335 SYS_COUNT_RX_256_511, 336 SYS_COUNT_RX_512_1023, 337 SYS_COUNT_RX_1024_1526, 338 SYS_COUNT_RX_1527_MAX, 339 SYS_COUNT_RX_PAUSE, 340 SYS_COUNT_RX_CONTROL, 341 SYS_COUNT_RX_LONGS, 342 SYS_COUNT_RX_CLASSIFIED_DROPS, 343 SYS_COUNT_RX_RED_PRIO_0, 344 SYS_COUNT_RX_RED_PRIO_1, 345 SYS_COUNT_RX_RED_PRIO_2, 346 SYS_COUNT_RX_RED_PRIO_3, 347 SYS_COUNT_RX_RED_PRIO_4, 348 SYS_COUNT_RX_RED_PRIO_5, 349 SYS_COUNT_RX_RED_PRIO_6, 350 SYS_COUNT_RX_RED_PRIO_7, 351 SYS_COUNT_RX_YELLOW_PRIO_0, 352 SYS_COUNT_RX_YELLOW_PRIO_1, 353 SYS_COUNT_RX_YELLOW_PRIO_2, 354 SYS_COUNT_RX_YELLOW_PRIO_3, 355 SYS_COUNT_RX_YELLOW_PRIO_4, 356 SYS_COUNT_RX_YELLOW_PRIO_5, 357 SYS_COUNT_RX_YELLOW_PRIO_6, 358 SYS_COUNT_RX_YELLOW_PRIO_7, 359 SYS_COUNT_RX_GREEN_PRIO_0, 360 SYS_COUNT_RX_GREEN_PRIO_1, 361 SYS_COUNT_RX_GREEN_PRIO_2, 362 SYS_COUNT_RX_GREEN_PRIO_3, 363 SYS_COUNT_RX_GREEN_PRIO_4, 364 SYS_COUNT_RX_GREEN_PRIO_5, 365 SYS_COUNT_RX_GREEN_PRIO_6, 366 SYS_COUNT_RX_GREEN_PRIO_7, 367 SYS_COUNT_RX_ASSEMBLY_ERRS, 368 SYS_COUNT_RX_SMD_ERRS, 369 SYS_COUNT_RX_ASSEMBLY_OK, 370 SYS_COUNT_RX_MERGE_FRAGMENTS, 371 SYS_COUNT_RX_PMAC_OCTETS, 372 SYS_COUNT_RX_PMAC_UNICAST, 373 SYS_COUNT_RX_PMAC_MULTICAST, 374 SYS_COUNT_RX_PMAC_BROADCAST, 375 SYS_COUNT_RX_PMAC_SHORTS, 376 SYS_COUNT_RX_PMAC_FRAGMENTS, 377 SYS_COUNT_RX_PMAC_JABBERS, 378 SYS_COUNT_RX_PMAC_CRC_ALIGN_ERRS, 379 SYS_COUNT_RX_PMAC_SYM_ERRS, 380 SYS_COUNT_RX_PMAC_64, 381 SYS_COUNT_RX_PMAC_65_127, 382 SYS_COUNT_RX_PMAC_128_255, 383 SYS_COUNT_RX_PMAC_256_511, 384 SYS_COUNT_RX_PMAC_512_1023, 385 SYS_COUNT_RX_PMAC_1024_1526, 386 SYS_COUNT_RX_PMAC_1527_MAX, 387 SYS_COUNT_RX_PMAC_PAUSE, 388 SYS_COUNT_RX_PMAC_CONTROL, 389 SYS_COUNT_RX_PMAC_LONGS, 390 SYS_COUNT_TX_OCTETS, 391 SYS_COUNT_TX_UNICAST, 392 SYS_COUNT_TX_MULTICAST, 393 SYS_COUNT_TX_BROADCAST, 394 SYS_COUNT_TX_COLLISION, 395 SYS_COUNT_TX_DROPS, 396 SYS_COUNT_TX_PAUSE, 397 SYS_COUNT_TX_64, 398 SYS_COUNT_TX_65_127, 399 SYS_COUNT_TX_128_255, 400 SYS_COUNT_TX_256_511, 401 SYS_COUNT_TX_512_1023, 402 SYS_COUNT_TX_1024_1526, 403 SYS_COUNT_TX_1527_MAX, 404 SYS_COUNT_TX_YELLOW_PRIO_0, 405 SYS_COUNT_TX_YELLOW_PRIO_1, 406 SYS_COUNT_TX_YELLOW_PRIO_2, 407 SYS_COUNT_TX_YELLOW_PRIO_3, 408 SYS_COUNT_TX_YELLOW_PRIO_4, 409 SYS_COUNT_TX_YELLOW_PRIO_5, 410 SYS_COUNT_TX_YELLOW_PRIO_6, 411 SYS_COUNT_TX_YELLOW_PRIO_7, 412 SYS_COUNT_TX_GREEN_PRIO_0, 413 SYS_COUNT_TX_GREEN_PRIO_1, 414 SYS_COUNT_TX_GREEN_PRIO_2, 415 SYS_COUNT_TX_GREEN_PRIO_3, 416 SYS_COUNT_TX_GREEN_PRIO_4, 417 SYS_COUNT_TX_GREEN_PRIO_5, 418 SYS_COUNT_TX_GREEN_PRIO_6, 419 SYS_COUNT_TX_GREEN_PRIO_7, 420 SYS_COUNT_TX_AGED, 421 SYS_COUNT_TX_MM_HOLD, 422 SYS_COUNT_TX_MERGE_FRAGMENTS, 423 SYS_COUNT_TX_PMAC_OCTETS, 424 SYS_COUNT_TX_PMAC_UNICAST, 425 SYS_COUNT_TX_PMAC_MULTICAST, 426 SYS_COUNT_TX_PMAC_BROADCAST, 427 SYS_COUNT_TX_PMAC_PAUSE, 428 SYS_COUNT_TX_PMAC_64, 429 SYS_COUNT_TX_PMAC_65_127, 430 SYS_COUNT_TX_PMAC_128_255, 431 SYS_COUNT_TX_PMAC_256_511, 432 SYS_COUNT_TX_PMAC_512_1023, 433 SYS_COUNT_TX_PMAC_1024_1526, 434 SYS_COUNT_TX_PMAC_1527_MAX, 435 SYS_COUNT_DROP_LOCAL, 436 SYS_COUNT_DROP_TAIL, 437 SYS_COUNT_DROP_YELLOW_PRIO_0, 438 SYS_COUNT_DROP_YELLOW_PRIO_1, 439 SYS_COUNT_DROP_YELLOW_PRIO_2, 440 SYS_COUNT_DROP_YELLOW_PRIO_3, 441 SYS_COUNT_DROP_YELLOW_PRIO_4, 442 SYS_COUNT_DROP_YELLOW_PRIO_5, 443 SYS_COUNT_DROP_YELLOW_PRIO_6, 444 SYS_COUNT_DROP_YELLOW_PRIO_7, 445 SYS_COUNT_DROP_GREEN_PRIO_0, 446 SYS_COUNT_DROP_GREEN_PRIO_1, 447 SYS_COUNT_DROP_GREEN_PRIO_2, 448 SYS_COUNT_DROP_GREEN_PRIO_3, 449 SYS_COUNT_DROP_GREEN_PRIO_4, 450 SYS_COUNT_DROP_GREEN_PRIO_5, 451 SYS_COUNT_DROP_GREEN_PRIO_6, 452 SYS_COUNT_DROP_GREEN_PRIO_7, 453 SYS_COUNT_SF_MATCHING_FRAMES, 454 SYS_COUNT_SF_NOT_PASSING_FRAMES, 455 SYS_COUNT_SF_NOT_PASSING_SDU, 456 SYS_COUNT_SF_RED_FRAMES, 457 SYS_RESET_CFG, 458 SYS_SR_ETYPE_CFG, 459 SYS_VLAN_ETYPE_CFG, 460 SYS_PORT_MODE, 461 SYS_FRONT_PORT_MODE, 462 SYS_FRM_AGING, 463 SYS_STAT_CFG, 464 SYS_SW_STATUS, 465 SYS_MISC_CFG, 466 SYS_REW_MAC_HIGH_CFG, 467 SYS_REW_MAC_LOW_CFG, 468 SYS_TIMESTAMP_OFFSET, 469 SYS_CMID, 470 SYS_PAUSE_CFG, 471 SYS_PAUSE_TOT_CFG, 472 SYS_ATOP, 473 SYS_ATOP_TOT_CFG, 474 SYS_MAC_FC_CFG, 475 SYS_MMGT, 476 SYS_MMGT_FAST, 477 SYS_EVENTS_DIF, 478 SYS_EVENTS_CORE, 479 SYS_PTP_STATUS, 480 SYS_PTP_TXSTAMP, 481 SYS_PTP_NXT, 482 SYS_PTP_CFG, 483 SYS_RAM_INIT, 484 SYS_CM_ADDR, 485 SYS_CM_DATA_WR, 486 SYS_CM_DATA_RD, 487 SYS_CM_OP, 488 SYS_CM_DATA, 489 PTP_PIN_CFG = PTP << TARGET_OFFSET, 490 PTP_PIN_TOD_SEC_MSB, 491 PTP_PIN_TOD_SEC_LSB, 492 PTP_PIN_TOD_NSEC, 493 PTP_PIN_WF_HIGH_PERIOD, 494 PTP_PIN_WF_LOW_PERIOD, 495 PTP_CFG_MISC, 496 PTP_CLK_CFG_ADJ_CFG, 497 PTP_CLK_CFG_ADJ_FREQ, 498 GCB_SOFT_RST = GCB << TARGET_OFFSET, 499 GCB_MIIM_MII_STATUS, 500 GCB_MIIM_MII_CMD, 501 GCB_MIIM_MII_DATA, 502 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, 503 DEV_PORT_MISC, 504 DEV_EVENTS, 505 DEV_EEE_CFG, 506 DEV_RX_PATH_DELAY, 507 DEV_TX_PATH_DELAY, 508 DEV_PTP_PREDICT_CFG, 509 DEV_MAC_ENA_CFG, 510 DEV_MAC_MODE_CFG, 511 DEV_MAC_MAXLEN_CFG, 512 DEV_MAC_TAGS_CFG, 513 DEV_MAC_ADV_CHK_CFG, 514 DEV_MAC_IFG_CFG, 515 DEV_MAC_HDX_CFG, 516 DEV_MAC_DBG_CFG, 517 DEV_MAC_FC_MAC_LOW_CFG, 518 DEV_MAC_FC_MAC_HIGH_CFG, 519 DEV_MAC_STICKY, 520 DEV_MM_ENABLE_CONFIG, 521 DEV_MM_VERIF_CONFIG, 522 DEV_MM_STATUS, 523 PCS1G_CFG, 524 PCS1G_MODE_CFG, 525 PCS1G_SD_CFG, 526 PCS1G_ANEG_CFG, 527 PCS1G_ANEG_NP_CFG, 528 PCS1G_LB_CFG, 529 PCS1G_DBG_CFG, 530 PCS1G_CDET_CFG, 531 PCS1G_ANEG_STATUS, 532 PCS1G_ANEG_NP_STATUS, 533 PCS1G_LINK_STATUS, 534 PCS1G_LINK_DOWN_CNT, 535 PCS1G_STICKY, 536 PCS1G_DEBUG_STATUS, 537 PCS1G_LPI_CFG, 538 PCS1G_LPI_WAKE_ERROR_CNT, 539 PCS1G_LPI_STATUS, 540 PCS1G_TSTPAT_MODE_CFG, 541 PCS1G_TSTPAT_STATUS, 542 DEV_PCS_FX100_CFG, 543 DEV_PCS_FX100_STATUS, 544 }; 545 546 enum ocelot_regfield { 547 ANA_ADVLEARN_VLAN_CHK, 548 ANA_ADVLEARN_LEARN_MIRROR, 549 ANA_ANEVENTS_FLOOD_DISCARD, 550 ANA_ANEVENTS_MSTI_DROP, 551 ANA_ANEVENTS_ACLKILL, 552 ANA_ANEVENTS_ACLUSED, 553 ANA_ANEVENTS_AUTOAGE, 554 ANA_ANEVENTS_VS2TTL1, 555 ANA_ANEVENTS_STORM_DROP, 556 ANA_ANEVENTS_LEARN_DROP, 557 ANA_ANEVENTS_AGED_ENTRY, 558 ANA_ANEVENTS_CPU_LEARN_FAILED, 559 ANA_ANEVENTS_AUTO_LEARN_FAILED, 560 ANA_ANEVENTS_LEARN_REMOVE, 561 ANA_ANEVENTS_AUTO_LEARNED, 562 ANA_ANEVENTS_AUTO_MOVED, 563 ANA_ANEVENTS_DROPPED, 564 ANA_ANEVENTS_CLASSIFIED_DROP, 565 ANA_ANEVENTS_CLASSIFIED_COPY, 566 ANA_ANEVENTS_VLAN_DISCARD, 567 ANA_ANEVENTS_FWD_DISCARD, 568 ANA_ANEVENTS_MULTICAST_FLOOD, 569 ANA_ANEVENTS_UNICAST_FLOOD, 570 ANA_ANEVENTS_DEST_KNOWN, 571 ANA_ANEVENTS_BUCKET3_MATCH, 572 ANA_ANEVENTS_BUCKET2_MATCH, 573 ANA_ANEVENTS_BUCKET1_MATCH, 574 ANA_ANEVENTS_BUCKET0_MATCH, 575 ANA_ANEVENTS_CPU_OPERATION, 576 ANA_ANEVENTS_DMAC_LOOKUP, 577 ANA_ANEVENTS_SMAC_LOOKUP, 578 ANA_ANEVENTS_SEQ_GEN_ERR_0, 579 ANA_ANEVENTS_SEQ_GEN_ERR_1, 580 ANA_TABLES_MACACCESS_B_DOM, 581 ANA_TABLES_MACTINDX_BUCKET, 582 ANA_TABLES_MACTINDX_M_INDEX, 583 QSYS_SWITCH_PORT_MODE_PORT_ENA, 584 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG, 585 QSYS_SWITCH_PORT_MODE_YEL_RSRVD, 586 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE, 587 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 588 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE, 589 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD, 590 QSYS_TIMED_FRAME_ENTRY_TFRM_FP, 591 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO, 592 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL, 593 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T, 594 SYS_PORT_MODE_DATA_WO_TS, 595 SYS_PORT_MODE_INCL_INJ_HDR, 596 SYS_PORT_MODE_INCL_XTR_HDR, 597 SYS_PORT_MODE_INCL_HDR_ERR, 598 SYS_RESET_CFG_CORE_ENA, 599 SYS_RESET_CFG_MEM_ENA, 600 SYS_RESET_CFG_MEM_INIT, 601 GCB_SOFT_RST_SWC_RST, 602 GCB_MIIM_MII_STATUS_PENDING, 603 GCB_MIIM_MII_STATUS_BUSY, 604 SYS_PAUSE_CFG_PAUSE_START, 605 SYS_PAUSE_CFG_PAUSE_STOP, 606 SYS_PAUSE_CFG_PAUSE_ENA, 607 REGFIELD_MAX 608 }; 609 610 enum { 611 /* VCAP_CORE_CFG */ 612 VCAP_CORE_UPDATE_CTRL, 613 VCAP_CORE_MV_CFG, 614 /* VCAP_CORE_CACHE */ 615 VCAP_CACHE_ENTRY_DAT, 616 VCAP_CACHE_MASK_DAT, 617 VCAP_CACHE_ACTION_DAT, 618 VCAP_CACHE_CNT_DAT, 619 VCAP_CACHE_TG_DAT, 620 /* VCAP_CONST */ 621 VCAP_CONST_VCAP_VER, 622 VCAP_CONST_ENTRY_WIDTH, 623 VCAP_CONST_ENTRY_CNT, 624 VCAP_CONST_ENTRY_SWCNT, 625 VCAP_CONST_ENTRY_TG_WIDTH, 626 VCAP_CONST_ACTION_DEF_CNT, 627 VCAP_CONST_ACTION_WIDTH, 628 VCAP_CONST_CNT_WIDTH, 629 VCAP_CONST_CORE_CNT, 630 VCAP_CONST_IF_CNT, 631 }; 632 633 enum ocelot_ptp_pins { 634 PTP_PIN_0, 635 PTP_PIN_1, 636 PTP_PIN_2, 637 PTP_PIN_3, 638 TOD_ACC_PIN 639 }; 640 641 enum ocelot_tag_prefix { 642 OCELOT_TAG_PREFIX_DISABLED = 0, 643 OCELOT_TAG_PREFIX_NONE, 644 OCELOT_TAG_PREFIX_SHORT, 645 OCELOT_TAG_PREFIX_LONG, 646 }; 647 648 struct ocelot; 649 struct device_node; 650 651 struct ocelot_ops { 652 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port); 653 int (*netdev_to_port)(struct net_device *dev); 654 int (*reset)(struct ocelot *ocelot); 655 u16 (*wm_enc)(u16 value); 656 u16 (*wm_dec)(u16 value); 657 void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse); 658 void (*psfp_init)(struct ocelot *ocelot); 659 int (*psfp_filter_add)(struct ocelot *ocelot, int port, 660 struct flow_cls_offload *f); 661 int (*psfp_filter_del)(struct ocelot *ocelot, struct flow_cls_offload *f); 662 int (*psfp_stats_get)(struct ocelot *ocelot, struct flow_cls_offload *f, 663 struct flow_stats *stats); 664 void (*cut_through_fwd)(struct ocelot *ocelot); 665 void (*tas_clock_adjust)(struct ocelot *ocelot); 666 void (*tas_guard_bands_update)(struct ocelot *ocelot, int port); 667 void (*update_stats)(struct ocelot *ocelot); 668 }; 669 670 struct ocelot_vcap_policer { 671 struct list_head pol_list; 672 u16 base; 673 u16 max; 674 u16 base2; 675 u16 max2; 676 }; 677 678 struct ocelot_vcap_block { 679 struct list_head rules; 680 int count; 681 }; 682 683 struct ocelot_bridge_vlan { 684 u16 vid; 685 unsigned long portmask; 686 unsigned long untagged; 687 struct list_head list; 688 }; 689 690 enum ocelot_port_tag_config { 691 /* all VLANs are egress-untagged */ 692 OCELOT_PORT_TAG_DISABLED = 0, 693 /* all VLANs except the native VLAN and VID 0 are egress-tagged */ 694 OCELOT_PORT_TAG_NATIVE = 1, 695 /* all VLANs except VID 0 are egress-tagged */ 696 OCELOT_PORT_TAG_TRUNK_NO_VID0 = 2, 697 /* all VLANs are egress-tagged */ 698 OCELOT_PORT_TAG_TRUNK = 3, 699 }; 700 701 struct ocelot_psfp_list { 702 struct list_head stream_list; 703 struct list_head sfi_list; 704 struct list_head sgi_list; 705 /* Serialize access to the lists */ 706 struct mutex lock; 707 }; 708 709 enum ocelot_sb { 710 OCELOT_SB_BUF, 711 OCELOT_SB_REF, 712 OCELOT_SB_NUM, 713 }; 714 715 enum ocelot_sb_pool { 716 OCELOT_SB_POOL_ING, 717 OCELOT_SB_POOL_EGR, 718 OCELOT_SB_POOL_NUM, 719 }; 720 721 /* MAC table entry types. 722 * ENTRYTYPE_NORMAL is subject to aging. 723 * ENTRYTYPE_LOCKED is not subject to aging. 724 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 725 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 726 */ 727 enum macaccess_entry_type { 728 ENTRYTYPE_NORMAL = 0, 729 ENTRYTYPE_LOCKED, 730 ENTRYTYPE_MACv4, 731 ENTRYTYPE_MACv6, 732 }; 733 734 enum ocelot_proto { 735 OCELOT_PROTO_PTP_L2 = BIT(0), 736 OCELOT_PROTO_PTP_L4 = BIT(1), 737 }; 738 739 #define OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION BIT(0) 740 #define OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP BIT(1) 741 742 struct ocelot_lag_fdb { 743 unsigned char addr[ETH_ALEN]; 744 u16 vid; 745 struct net_device *bond; 746 struct list_head list; 747 }; 748 749 struct ocelot_mirror { 750 refcount_t refcount; 751 int to; 752 }; 753 754 struct ocelot_mm_state { 755 enum ethtool_mm_verify_status verify_status; 756 bool tx_enabled; 757 bool tx_active; 758 u8 preemptible_tcs; 759 u8 active_preemptible_tcs; 760 }; 761 762 struct ocelot_port; 763 764 struct ocelot_port { 765 struct ocelot *ocelot; 766 767 struct regmap *target; 768 769 struct net_device *bond; 770 struct net_device *bridge; 771 772 struct ocelot_port *dsa_8021q_cpu; 773 774 /* VLAN that untagged frames are classified to, on ingress */ 775 const struct ocelot_bridge_vlan *pvid_vlan; 776 777 struct tc_taprio_qopt_offload *taprio; 778 779 phy_interface_t phy_mode; 780 781 unsigned int ptp_skbs_in_flight; 782 struct sk_buff_head tx_skbs; 783 784 unsigned int trap_proto; 785 786 u16 mrp_ring_id; 787 788 u8 ptp_cmd; 789 u8 ts_id; 790 791 u8 index; 792 793 u8 stp_state; 794 bool vlan_aware; 795 bool is_dsa_8021q_cpu; 796 bool learn_ena; 797 798 bool lag_tx_active; 799 800 int bridge_num; 801 802 int speed; 803 }; 804 805 struct ocelot { 806 struct device *dev; 807 struct devlink *devlink; 808 struct devlink_port *devlink_ports; 809 810 const struct ocelot_ops *ops; 811 struct regmap *targets[TARGET_MAX]; 812 struct regmap_field *regfields[REGFIELD_MAX]; 813 const u32 *const *map; 814 struct list_head stats_regions; 815 816 spinlock_t inj_lock; 817 spinlock_t xtr_lock; 818 819 u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM]; 820 int packet_buffer_size; 821 int num_frame_refs; 822 int num_mact_rows; 823 824 struct ocelot_port **ports; 825 826 u8 base_mac[ETH_ALEN]; 827 828 struct list_head vlans; 829 struct list_head traps; 830 struct list_head lag_fdbs; 831 832 /* Switches like VSC9959 have flooding per traffic class */ 833 int num_flooding_pgids; 834 835 /* In tables like ANA:PORT and the ANA:PGID:PGID mask, 836 * the CPU is located after the physical ports (at the 837 * num_phys_ports index). 838 */ 839 u8 num_phys_ports; 840 841 int npi; 842 843 enum ocelot_tag_prefix npi_inj_prefix; 844 enum ocelot_tag_prefix npi_xtr_prefix; 845 846 unsigned long bridges; 847 848 struct list_head multicast; 849 struct list_head pgids; 850 851 struct list_head dummy_rules; 852 struct ocelot_vcap_block block[3]; 853 struct ocelot_vcap_policer vcap_pol; 854 struct vcap_props *vcap; 855 struct ocelot_mirror *mirror; 856 857 struct ocelot_psfp_list psfp; 858 859 /* Workqueue to check statistics for overflow */ 860 struct delayed_work stats_work; 861 struct workqueue_struct *stats_queue; 862 /* Lock for serializing access to the statistics array */ 863 spinlock_t stats_lock; 864 u64 *stats; 865 866 /* Lock for serializing indirect access to STAT_VIEW registers */ 867 struct mutex stat_view_lock; 868 /* Lock for serializing access to the MAC table */ 869 struct mutex mact_lock; 870 /* Lock for serializing forwarding domain changes, including the 871 * configuration of the Time-Aware Shaper, MAC Merge layer and 872 * cut-through forwarding, on which it depends 873 */ 874 struct mutex fwd_domain_lock; 875 876 struct workqueue_struct *owq; 877 878 u8 ptp:1; 879 u8 mm_supported:1; 880 struct ptp_clock *ptp_clock; 881 struct ptp_clock_info ptp_info; 882 unsigned int ptp_skbs_in_flight; 883 /* Protects the 2-step TX timestamp ID logic */ 884 spinlock_t ts_id_lock; 885 /* Protects the PTP clock */ 886 spinlock_t ptp_clock_lock; 887 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM]; 888 889 struct ocelot_mm_state *mm; 890 891 struct ocelot_fdma *fdma; 892 }; 893 894 struct ocelot_policer { 895 u32 rate; /* kilobit per second */ 896 u32 burst; /* bytes */ 897 }; 898 899 #define ocelot_bulk_read(ocelot, reg, buf, count) \ 900 __ocelot_bulk_read_ix(ocelot, reg, 0, buf, count) 901 902 #define ocelot_read_ix(ocelot, reg, gi, ri) \ 903 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 904 #define ocelot_read_gix(ocelot, reg, gi) \ 905 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) 906 #define ocelot_read_rix(ocelot, reg, ri) \ 907 __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) 908 #define ocelot_read(ocelot, reg) \ 909 __ocelot_read_ix(ocelot, reg, 0) 910 911 #define ocelot_write_ix(ocelot, val, reg, gi, ri) \ 912 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 913 #define ocelot_write_gix(ocelot, val, reg, gi) \ 914 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) 915 #define ocelot_write_rix(ocelot, val, reg, ri) \ 916 __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) 917 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) 918 919 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) \ 920 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 921 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) \ 922 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) 923 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) \ 924 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) 925 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) 926 927 #define ocelot_field_write(ocelot, reg, val) \ 928 regmap_field_write((ocelot)->regfields[(reg)], (val)) 929 #define ocelot_field_read(ocelot, reg, val) \ 930 regmap_field_read((ocelot)->regfields[(reg)], (val)) 931 #define ocelot_fields_write(ocelot, id, reg, val) \ 932 regmap_fields_write((ocelot)->regfields[(reg)], (id), (val)) 933 #define ocelot_fields_read(ocelot, id, reg, val) \ 934 regmap_fields_read((ocelot)->regfields[(reg)], (id), (val)) 935 936 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \ 937 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 938 #define ocelot_target_read_gix(ocelot, target, reg, gi) \ 939 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi)) 940 #define ocelot_target_read_rix(ocelot, target, reg, ri) \ 941 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri)) 942 #define ocelot_target_read(ocelot, target, reg) \ 943 __ocelot_target_read_ix(ocelot, target, reg, 0) 944 945 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \ 946 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 947 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \ 948 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi)) 949 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \ 950 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri)) 951 #define ocelot_target_write(ocelot, target, val, reg) \ 952 __ocelot_target_write_ix(ocelot, target, val, reg, 0) 953 954 /* I/O */ 955 u32 ocelot_port_readl(struct ocelot_port *port, enum ocelot_reg reg); 956 void ocelot_port_writel(struct ocelot_port *port, u32 val, enum ocelot_reg reg); 957 void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, 958 enum ocelot_reg reg); 959 int __ocelot_bulk_read_ix(struct ocelot *ocelot, enum ocelot_reg reg, 960 u32 offset, void *buf, int count); 961 u32 __ocelot_read_ix(struct ocelot *ocelot, enum ocelot_reg reg, u32 offset); 962 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, enum ocelot_reg reg, 963 u32 offset); 964 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, 965 enum ocelot_reg reg, u32 offset); 966 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target, 967 u32 reg, u32 offset); 968 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target, 969 u32 val, u32 reg, u32 offset); 970 971 /* Packet I/O */ 972 void ocelot_lock_inj_grp(struct ocelot *ocelot, int grp); 973 void ocelot_unlock_inj_grp(struct ocelot *ocelot, int grp); 974 void ocelot_lock_xtr_grp(struct ocelot *ocelot, int grp); 975 void ocelot_unlock_xtr_grp(struct ocelot *ocelot, int grp); 976 void ocelot_lock_xtr_grp_bh(struct ocelot *ocelot, int grp); 977 void ocelot_unlock_xtr_grp_bh(struct ocelot *ocelot, int grp); 978 bool ocelot_can_inject(struct ocelot *ocelot, int grp); 979 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 980 u32 rew_op, struct sk_buff *skb); 981 void ocelot_ifh_set_basic(void *ifh, struct ocelot *ocelot, int port, 982 u32 rew_op, struct sk_buff *skb); 983 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb); 984 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp); 985 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb, 986 u64 timestamp); 987 988 /* Hardware initialization */ 989 int ocelot_regfields_init(struct ocelot *ocelot, 990 const struct reg_field *const regfields); 991 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res); 992 int ocelot_reset(struct ocelot *ocelot); 993 int ocelot_init(struct ocelot *ocelot); 994 void ocelot_deinit(struct ocelot *ocelot); 995 void ocelot_init_port(struct ocelot *ocelot, int port); 996 void ocelot_deinit_port(struct ocelot *ocelot, int port); 997 998 void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu); 999 void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu); 1000 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, int cpu); 1001 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port); 1002 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port); 1003 1004 /* Watermark interface */ 1005 u16 ocelot_wm_enc(u16 value); 1006 u16 ocelot_wm_dec(u16 wm); 1007 void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse); 1008 1009 /* DSA callbacks */ 1010 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data); 1011 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data); 1012 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset); 1013 void ocelot_port_get_stats64(struct ocelot *ocelot, int port, 1014 struct rtnl_link_stats64 *stats); 1015 void ocelot_port_get_pause_stats(struct ocelot *ocelot, int port, 1016 struct ethtool_pause_stats *pause_stats); 1017 void ocelot_port_get_mm_stats(struct ocelot *ocelot, int port, 1018 struct ethtool_mm_stats *stats); 1019 void ocelot_port_get_rmon_stats(struct ocelot *ocelot, int port, 1020 struct ethtool_rmon_stats *rmon_stats, 1021 const struct ethtool_rmon_hist_range **ranges); 1022 void ocelot_port_get_eth_ctrl_stats(struct ocelot *ocelot, int port, 1023 struct ethtool_eth_ctrl_stats *ctrl_stats); 1024 void ocelot_port_get_eth_mac_stats(struct ocelot *ocelot, int port, 1025 struct ethtool_eth_mac_stats *mac_stats); 1026 void ocelot_port_get_eth_phy_stats(struct ocelot *ocelot, int port, 1027 struct ethtool_eth_phy_stats *phy_stats); 1028 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1029 struct ethtool_ts_info *info); 1030 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs); 1031 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled, 1032 struct netlink_ext_ack *extack); 1033 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state); 1034 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port); 1035 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 1036 struct switchdev_brport_flags val); 1037 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 1038 struct switchdev_brport_flags val); 1039 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port); 1040 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio); 1041 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp); 1042 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio); 1043 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio); 1044 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1045 struct net_device *bridge, int bridge_num, 1046 struct netlink_ext_ack *extack); 1047 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1048 struct net_device *bridge); 1049 int ocelot_mact_flush(struct ocelot *ocelot, int port); 1050 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1051 dsa_fdb_dump_cb_t *cb, void *data); 1052 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr, 1053 u16 vid, const struct net_device *bridge); 1054 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr, 1055 u16 vid, const struct net_device *bridge); 1056 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond, 1057 const unsigned char *addr, u16 vid, 1058 const struct net_device *bridge); 1059 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond, 1060 const unsigned char *addr, u16 vid, 1061 const struct net_device *bridge); 1062 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 1063 bool untagged, struct netlink_ext_ack *extack); 1064 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 1065 bool untagged); 1066 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid); 1067 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr); 1068 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr); 1069 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 1070 struct sk_buff *skb, 1071 struct sk_buff **clone); 1072 void ocelot_get_txtstamp(struct ocelot *ocelot); 1073 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu); 1074 int ocelot_get_max_mtu(struct ocelot *ocelot, int port); 1075 int ocelot_port_policer_add(struct ocelot *ocelot, int port, 1076 struct ocelot_policer *pol); 1077 int ocelot_port_policer_del(struct ocelot *ocelot, int port); 1078 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to, 1079 bool ingress, struct netlink_ext_ack *extack); 1080 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress); 1081 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port, 1082 struct flow_cls_offload *f, bool ingress); 1083 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port, 1084 struct flow_cls_offload *f, bool ingress); 1085 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port, 1086 struct flow_cls_offload *f, bool ingress); 1087 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1088 const struct switchdev_obj_port_mdb *mdb, 1089 const struct net_device *bridge); 1090 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1091 const struct switchdev_obj_port_mdb *mdb, 1092 const struct net_device *bridge); 1093 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1094 struct net_device *bond, 1095 struct netdev_lag_upper_info *info, 1096 struct netlink_ext_ack *extack); 1097 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1098 struct net_device *bond); 1099 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active); 1100 int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond); 1101 1102 int ocelot_devlink_sb_register(struct ocelot *ocelot); 1103 void ocelot_devlink_sb_unregister(struct ocelot *ocelot); 1104 int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index, 1105 u16 pool_index, 1106 struct devlink_sb_pool_info *pool_info); 1107 int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index, 1108 u16 pool_index, u32 size, 1109 enum devlink_sb_threshold_type threshold_type, 1110 struct netlink_ext_ack *extack); 1111 int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port, 1112 unsigned int sb_index, u16 pool_index, 1113 u32 *p_threshold); 1114 int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port, 1115 unsigned int sb_index, u16 pool_index, 1116 u32 threshold, struct netlink_ext_ack *extack); 1117 int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port, 1118 unsigned int sb_index, u16 tc_index, 1119 enum devlink_sb_pool_type pool_type, 1120 u16 *p_pool_index, u32 *p_threshold); 1121 int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port, 1122 unsigned int sb_index, u16 tc_index, 1123 enum devlink_sb_pool_type pool_type, 1124 u16 pool_index, u32 threshold, 1125 struct netlink_ext_ack *extack); 1126 int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index); 1127 int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index); 1128 int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port, 1129 unsigned int sb_index, u16 pool_index, 1130 u32 *p_cur, u32 *p_max); 1131 int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port, 1132 unsigned int sb_index, u16 tc_index, 1133 enum devlink_sb_pool_type pool_type, 1134 u32 *p_cur, u32 *p_max); 1135 1136 int ocelot_port_configure_serdes(struct ocelot *ocelot, int port, 1137 struct device_node *portnp); 1138 1139 void ocelot_phylink_mac_config(struct ocelot *ocelot, int port, 1140 unsigned int link_an_mode, 1141 const struct phylink_link_state *state); 1142 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 1143 unsigned int link_an_mode, 1144 phy_interface_t interface, 1145 unsigned long quirks); 1146 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 1147 struct phy_device *phydev, 1148 unsigned int link_an_mode, 1149 phy_interface_t interface, 1150 int speed, int duplex, 1151 bool tx_pause, bool rx_pause, 1152 unsigned long quirks); 1153 1154 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx, 1155 const unsigned char mac[ETH_ALEN], 1156 unsigned int vid, enum macaccess_entry_type *type); 1157 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx, 1158 const unsigned char mac[ETH_ALEN], 1159 unsigned int vid, 1160 enum macaccess_entry_type type, 1161 int sfid, int ssid); 1162 1163 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask, 1164 unsigned long to_mask); 1165 1166 int ocelot_vcap_policer_add(struct ocelot *ocelot, u32 pol_ix, 1167 struct ocelot_policer *pol); 1168 int ocelot_vcap_policer_del(struct ocelot *ocelot, u32 pol_ix); 1169 1170 void ocelot_mm_irq(struct ocelot *ocelot); 1171 int ocelot_port_set_mm(struct ocelot *ocelot, int port, 1172 struct ethtool_mm_cfg *cfg, 1173 struct netlink_ext_ack *extack); 1174 int ocelot_port_get_mm(struct ocelot *ocelot, int port, 1175 struct ethtool_mm_state *state); 1176 int ocelot_port_mqprio(struct ocelot *ocelot, int port, 1177 struct tc_mqprio_qopt_offload *mqprio); 1178 1179 #if IS_ENABLED(CONFIG_BRIDGE_MRP) 1180 int ocelot_mrp_add(struct ocelot *ocelot, int port, 1181 const struct switchdev_obj_mrp *mrp); 1182 int ocelot_mrp_del(struct ocelot *ocelot, int port, 1183 const struct switchdev_obj_mrp *mrp); 1184 int ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port, 1185 const struct switchdev_obj_ring_role_mrp *mrp); 1186 int ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, 1187 const struct switchdev_obj_ring_role_mrp *mrp); 1188 #else 1189 static inline int ocelot_mrp_add(struct ocelot *ocelot, int port, 1190 const struct switchdev_obj_mrp *mrp) 1191 { 1192 return -EOPNOTSUPP; 1193 } 1194 1195 static inline int ocelot_mrp_del(struct ocelot *ocelot, int port, 1196 const struct switchdev_obj_mrp *mrp) 1197 { 1198 return -EOPNOTSUPP; 1199 } 1200 1201 static inline int 1202 ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port, 1203 const struct switchdev_obj_ring_role_mrp *mrp) 1204 { 1205 return -EOPNOTSUPP; 1206 } 1207 1208 static inline int 1209 ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, 1210 const struct switchdev_obj_ring_role_mrp *mrp) 1211 { 1212 return -EOPNOTSUPP; 1213 } 1214 #endif 1215 1216 void ocelot_pll5_init(struct ocelot *ocelot); 1217 1218 #endif 1219