15e256365SVladimir Oltean /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 25e256365SVladimir Oltean /* Copyright (c) 2017 Microsemi Corporation 35e256365SVladimir Oltean */ 45e256365SVladimir Oltean 55e256365SVladimir Oltean #ifndef _SOC_MSCC_OCELOT_H 65e256365SVladimir Oltean #define _SOC_MSCC_OCELOT_H 75e256365SVladimir Oltean 85e256365SVladimir Oltean #include <linux/ptp_clock_kernel.h> 95e256365SVladimir Oltean #include <linux/net_tstamp.h> 105e256365SVladimir Oltean #include <linux/if_vlan.h> 115e256365SVladimir Oltean #include <linux/regmap.h> 125e256365SVladimir Oltean #include <net/dsa.h> 135e256365SVladimir Oltean 141cf3299bSVladimir Oltean /* Port Group IDs (PGID) are masks of destination ports. 151cf3299bSVladimir Oltean * 161cf3299bSVladimir Oltean * For L2 forwarding, the switch performs 3 lookups in the PGID table for each 171cf3299bSVladimir Oltean * frame, and forwards the frame to the ports that are present in the logical 181cf3299bSVladimir Oltean * AND of all 3 PGIDs. 191cf3299bSVladimir Oltean * 201cf3299bSVladimir Oltean * These PGID lookups are: 211cf3299bSVladimir Oltean * - In one of PGID[0-63]: for the destination masks. There are 2 paths by 221cf3299bSVladimir Oltean * which the switch selects a destination PGID: 231cf3299bSVladimir Oltean * - The {DMAC, VID} is present in the MAC table. In that case, the 241cf3299bSVladimir Oltean * destination PGID is given by the DEST_IDX field of the MAC table entry 251cf3299bSVladimir Oltean * that matched. 261cf3299bSVladimir Oltean * - The {DMAC, VID} is not present in the MAC table (it is unknown). The 271cf3299bSVladimir Oltean * frame is disseminated as being either unicast, multicast or broadcast, 281cf3299bSVladimir Oltean * and according to that, the destination PGID is chosen as being the 291cf3299bSVladimir Oltean * value contained by ANA_FLOODING_FLD_UNICAST, 301cf3299bSVladimir Oltean * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST. 311cf3299bSVladimir Oltean * The destination PGID can be an unicast set: the first PGIDs, 0 to 321cf3299bSVladimir Oltean * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from 331cf3299bSVladimir Oltean * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to 341cf3299bSVladimir Oltean * a physical port and has a single bit set in the destination ports mask: 351cf3299bSVladimir Oltean * that corresponding to the port number itself. In contrast, a multicast 361cf3299bSVladimir Oltean * PGID will have potentially more than one single bit set in the destination 371cf3299bSVladimir Oltean * ports mask. 381cf3299bSVladimir Oltean * - In one of PGID[64-79]: for the aggregation mask. The switch classifier 391cf3299bSVladimir Oltean * dissects each frame and generates a 4-bit Link Aggregation Code which is 401cf3299bSVladimir Oltean * used for this second PGID table lookup. The goal of link aggregation is to 411cf3299bSVladimir Oltean * hash multiple flows within the same LAG on to different destination ports. 421cf3299bSVladimir Oltean * The first lookup will result in a PGID with all the LAG members present in 431cf3299bSVladimir Oltean * the destination ports mask, and the second lookup, by Link Aggregation 441cf3299bSVladimir Oltean * Code, will ensure that each flow gets forwarded only to a single port out 451cf3299bSVladimir Oltean * of that mask (there are no duplicates). 461cf3299bSVladimir Oltean * - In one of PGID[80-90]: for the source mask. The third time, the PGID table 471cf3299bSVladimir Oltean * is indexed with the ingress port (plus 80). These PGIDs answer the 481cf3299bSVladimir Oltean * question "is port i allowed to forward traffic to port j?" If yes, then 491cf3299bSVladimir Oltean * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used 501cf3299bSVladimir Oltean * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge. 511cf3299bSVladimir Oltean */ 521cf3299bSVladimir Oltean 531cf3299bSVladimir Oltean /* Reserve some destination PGIDs at the end of the range: 541cf3299bSVladimir Oltean * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses 551cf3299bSVladimir Oltean * of the switch port net devices, towards the CPU port module. 561cf3299bSVladimir Oltean * PGID_UC: the flooding destinations for unknown unicast traffic. 571cf3299bSVladimir Oltean * PGID_MC: the flooding destinations for broadcast and non-IP multicast 581cf3299bSVladimir Oltean * traffic. 591cf3299bSVladimir Oltean * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic. 601cf3299bSVladimir Oltean * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic. 611cf3299bSVladimir Oltean */ 621cf3299bSVladimir Oltean #define PGID_CPU 59 631cf3299bSVladimir Oltean #define PGID_UC 60 641cf3299bSVladimir Oltean #define PGID_MC 61 651cf3299bSVladimir Oltean #define PGID_MCIPV4 62 661cf3299bSVladimir Oltean #define PGID_MCIPV6 63 671cf3299bSVladimir Oltean 6896b029b0SVladimir Oltean #define for_each_unicast_dest_pgid(ocelot, pgid) \ 6996b029b0SVladimir Oltean for ((pgid) = 0; \ 7096b029b0SVladimir Oltean (pgid) < (ocelot)->num_phys_ports; \ 7196b029b0SVladimir Oltean (pgid)++) 7296b029b0SVladimir Oltean 7396b029b0SVladimir Oltean #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \ 7496b029b0SVladimir Oltean for ((pgid) = (ocelot)->num_phys_ports + 1; \ 7596b029b0SVladimir Oltean (pgid) < PGID_CPU; \ 7696b029b0SVladimir Oltean (pgid)++) 7796b029b0SVladimir Oltean 7896b029b0SVladimir Oltean #define for_each_aggr_pgid(ocelot, pgid) \ 7996b029b0SVladimir Oltean for ((pgid) = PGID_AGGR; \ 8096b029b0SVladimir Oltean (pgid) < PGID_SRC; \ 8196b029b0SVladimir Oltean (pgid)++) 8296b029b0SVladimir Oltean 831cf3299bSVladimir Oltean /* Aggregation PGIDs, one per Link Aggregation Code */ 841cf3299bSVladimir Oltean #define PGID_AGGR 64 851cf3299bSVladimir Oltean 861cf3299bSVladimir Oltean /* Source PGIDs, one per physical port */ 871cf3299bSVladimir Oltean #define PGID_SRC 80 881cf3299bSVladimir Oltean 895e256365SVladimir Oltean #define IFH_INJ_BYPASS BIT(31) 905e256365SVladimir Oltean #define IFH_INJ_POP_CNT_DISABLE (3 << 28) 915e256365SVladimir Oltean 925e256365SVladimir Oltean #define IFH_TAG_TYPE_C 0 935e256365SVladimir Oltean #define IFH_TAG_TYPE_S 1 945e256365SVladimir Oltean 955e256365SVladimir Oltean #define IFH_REW_OP_NOOP 0x0 965e256365SVladimir Oltean #define IFH_REW_OP_DSCP 0x1 975e256365SVladimir Oltean #define IFH_REW_OP_ONE_STEP_PTP 0x2 985e256365SVladimir Oltean #define IFH_REW_OP_TWO_STEP_PTP 0x3 995e256365SVladimir Oltean #define IFH_REW_OP_ORIGIN_PTP 0x5 1005e256365SVladimir Oltean 1015e256365SVladimir Oltean #define OCELOT_TAG_LEN 16 1025e256365SVladimir Oltean #define OCELOT_SHORT_PREFIX_LEN 4 1035e256365SVladimir Oltean #define OCELOT_LONG_PREFIX_LEN 16 1045e256365SVladimir Oltean 1055e256365SVladimir Oltean #define OCELOT_SPEED_2500 0 1065e256365SVladimir Oltean #define OCELOT_SPEED_1000 1 1075e256365SVladimir Oltean #define OCELOT_SPEED_100 2 1085e256365SVladimir Oltean #define OCELOT_SPEED_10 3 1095e256365SVladimir Oltean 110cc2d87bbSYangbo Lu #define OCELOT_PTP_PINS_NUM 4 111cc2d87bbSYangbo Lu 1125e256365SVladimir Oltean #define TARGET_OFFSET 24 1135e256365SVladimir Oltean #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0) 1145e256365SVladimir Oltean #define REG(reg, offset) [reg & REG_MASK] = offset 1155e256365SVladimir Oltean 1165e256365SVladimir Oltean #define REG_RESERVED_ADDR 0xffffffff 1175e256365SVladimir Oltean #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR) 1185e256365SVladimir Oltean 1195e256365SVladimir Oltean enum ocelot_target { 1205e256365SVladimir Oltean ANA = 1, 1215e256365SVladimir Oltean QS, 1225e256365SVladimir Oltean QSYS, 1235e256365SVladimir Oltean REW, 1245e256365SVladimir Oltean SYS, 1255e256365SVladimir Oltean S2, 1265e256365SVladimir Oltean HSIO, 1275e256365SVladimir Oltean PTP, 1285e256365SVladimir Oltean GCB, 12991c724cfSVladimir Oltean DEV_GMII, 1305e256365SVladimir Oltean TARGET_MAX, 1315e256365SVladimir Oltean }; 1325e256365SVladimir Oltean 1335e256365SVladimir Oltean enum ocelot_reg { 1345e256365SVladimir Oltean ANA_ADVLEARN = ANA << TARGET_OFFSET, 1355e256365SVladimir Oltean ANA_VLANMASK, 1365e256365SVladimir Oltean ANA_PORT_B_DOMAIN, 1375e256365SVladimir Oltean ANA_ANAGEFIL, 1385e256365SVladimir Oltean ANA_ANEVENTS, 1395e256365SVladimir Oltean ANA_STORMLIMIT_BURST, 1405e256365SVladimir Oltean ANA_STORMLIMIT_CFG, 1415e256365SVladimir Oltean ANA_ISOLATED_PORTS, 1425e256365SVladimir Oltean ANA_COMMUNITY_PORTS, 1435e256365SVladimir Oltean ANA_AUTOAGE, 1445e256365SVladimir Oltean ANA_MACTOPTIONS, 1455e256365SVladimir Oltean ANA_LEARNDISC, 1465e256365SVladimir Oltean ANA_AGENCTRL, 1475e256365SVladimir Oltean ANA_MIRRORPORTS, 1485e256365SVladimir Oltean ANA_EMIRRORPORTS, 1495e256365SVladimir Oltean ANA_FLOODING, 1505e256365SVladimir Oltean ANA_FLOODING_IPMC, 1515e256365SVladimir Oltean ANA_SFLOW_CFG, 1525e256365SVladimir Oltean ANA_PORT_MODE, 1535e256365SVladimir Oltean ANA_CUT_THRU_CFG, 1545e256365SVladimir Oltean ANA_PGID_PGID, 1555e256365SVladimir Oltean ANA_TABLES_ANMOVED, 1565e256365SVladimir Oltean ANA_TABLES_MACHDATA, 1575e256365SVladimir Oltean ANA_TABLES_MACLDATA, 1585e256365SVladimir Oltean ANA_TABLES_STREAMDATA, 1595e256365SVladimir Oltean ANA_TABLES_MACACCESS, 1605e256365SVladimir Oltean ANA_TABLES_MACTINDX, 1615e256365SVladimir Oltean ANA_TABLES_VLANACCESS, 1625e256365SVladimir Oltean ANA_TABLES_VLANTIDX, 1635e256365SVladimir Oltean ANA_TABLES_ISDXACCESS, 1645e256365SVladimir Oltean ANA_TABLES_ISDXTIDX, 1655e256365SVladimir Oltean ANA_TABLES_ENTRYLIM, 1665e256365SVladimir Oltean ANA_TABLES_PTP_ID_HIGH, 1675e256365SVladimir Oltean ANA_TABLES_PTP_ID_LOW, 1685e256365SVladimir Oltean ANA_TABLES_STREAMACCESS, 1695e256365SVladimir Oltean ANA_TABLES_STREAMTIDX, 1705e256365SVladimir Oltean ANA_TABLES_SEQ_HISTORY, 1715e256365SVladimir Oltean ANA_TABLES_SEQ_MASK, 1725e256365SVladimir Oltean ANA_TABLES_SFID_MASK, 1735e256365SVladimir Oltean ANA_TABLES_SFIDACCESS, 1745e256365SVladimir Oltean ANA_TABLES_SFIDTIDX, 1755e256365SVladimir Oltean ANA_MSTI_STATE, 1765e256365SVladimir Oltean ANA_OAM_UPM_LM_CNT, 1775e256365SVladimir Oltean ANA_SG_ACCESS_CTRL, 1785e256365SVladimir Oltean ANA_SG_CONFIG_REG_1, 1795e256365SVladimir Oltean ANA_SG_CONFIG_REG_2, 1805e256365SVladimir Oltean ANA_SG_CONFIG_REG_3, 1815e256365SVladimir Oltean ANA_SG_CONFIG_REG_4, 1825e256365SVladimir Oltean ANA_SG_CONFIG_REG_5, 1835e256365SVladimir Oltean ANA_SG_GCL_GS_CONFIG, 1845e256365SVladimir Oltean ANA_SG_GCL_TI_CONFIG, 1855e256365SVladimir Oltean ANA_SG_STATUS_REG_1, 1865e256365SVladimir Oltean ANA_SG_STATUS_REG_2, 1875e256365SVladimir Oltean ANA_SG_STATUS_REG_3, 1885e256365SVladimir Oltean ANA_PORT_VLAN_CFG, 1895e256365SVladimir Oltean ANA_PORT_DROP_CFG, 1905e256365SVladimir Oltean ANA_PORT_QOS_CFG, 1915e256365SVladimir Oltean ANA_PORT_VCAP_CFG, 1925e256365SVladimir Oltean ANA_PORT_VCAP_S1_KEY_CFG, 1935e256365SVladimir Oltean ANA_PORT_VCAP_S2_CFG, 1945e256365SVladimir Oltean ANA_PORT_PCP_DEI_MAP, 1955e256365SVladimir Oltean ANA_PORT_CPU_FWD_CFG, 1965e256365SVladimir Oltean ANA_PORT_CPU_FWD_BPDU_CFG, 1975e256365SVladimir Oltean ANA_PORT_CPU_FWD_GARP_CFG, 1985e256365SVladimir Oltean ANA_PORT_CPU_FWD_CCM_CFG, 1995e256365SVladimir Oltean ANA_PORT_PORT_CFG, 2005e256365SVladimir Oltean ANA_PORT_POL_CFG, 2015e256365SVladimir Oltean ANA_PORT_PTP_CFG, 2025e256365SVladimir Oltean ANA_PORT_PTP_DLY1_CFG, 2035e256365SVladimir Oltean ANA_PORT_PTP_DLY2_CFG, 2045e256365SVladimir Oltean ANA_PORT_SFID_CFG, 2055e256365SVladimir Oltean ANA_PFC_PFC_CFG, 2065e256365SVladimir Oltean ANA_PFC_PFC_TIMER, 2075e256365SVladimir Oltean ANA_IPT_OAM_MEP_CFG, 2085e256365SVladimir Oltean ANA_IPT_IPT, 2095e256365SVladimir Oltean ANA_PPT_PPT, 2105e256365SVladimir Oltean ANA_FID_MAP_FID_MAP, 2115e256365SVladimir Oltean ANA_AGGR_CFG, 2125e256365SVladimir Oltean ANA_CPUQ_CFG, 2135e256365SVladimir Oltean ANA_CPUQ_CFG2, 2145e256365SVladimir Oltean ANA_CPUQ_8021_CFG, 2155e256365SVladimir Oltean ANA_DSCP_CFG, 2165e256365SVladimir Oltean ANA_DSCP_REWR_CFG, 2175e256365SVladimir Oltean ANA_VCAP_RNG_TYPE_CFG, 2185e256365SVladimir Oltean ANA_VCAP_RNG_VAL_CFG, 2195e256365SVladimir Oltean ANA_VRAP_CFG, 2205e256365SVladimir Oltean ANA_VRAP_HDR_DATA, 2215e256365SVladimir Oltean ANA_VRAP_HDR_MASK, 2225e256365SVladimir Oltean ANA_DISCARD_CFG, 2235e256365SVladimir Oltean ANA_FID_CFG, 2245e256365SVladimir Oltean ANA_POL_PIR_CFG, 2255e256365SVladimir Oltean ANA_POL_CIR_CFG, 2265e256365SVladimir Oltean ANA_POL_MODE_CFG, 2275e256365SVladimir Oltean ANA_POL_PIR_STATE, 2285e256365SVladimir Oltean ANA_POL_CIR_STATE, 2295e256365SVladimir Oltean ANA_POL_STATE, 2305e256365SVladimir Oltean ANA_POL_FLOWC, 2315e256365SVladimir Oltean ANA_POL_HYST, 2325e256365SVladimir Oltean ANA_POL_MISC_CFG, 2335e256365SVladimir Oltean QS_XTR_GRP_CFG = QS << TARGET_OFFSET, 2345e256365SVladimir Oltean QS_XTR_RD, 2355e256365SVladimir Oltean QS_XTR_FRM_PRUNING, 2365e256365SVladimir Oltean QS_XTR_FLUSH, 2375e256365SVladimir Oltean QS_XTR_DATA_PRESENT, 2385e256365SVladimir Oltean QS_XTR_CFG, 2395e256365SVladimir Oltean QS_INJ_GRP_CFG, 2405e256365SVladimir Oltean QS_INJ_WR, 2415e256365SVladimir Oltean QS_INJ_CTRL, 2425e256365SVladimir Oltean QS_INJ_STATUS, 2435e256365SVladimir Oltean QS_INJ_ERR, 2445e256365SVladimir Oltean QS_INH_DBG, 2455e256365SVladimir Oltean QSYS_PORT_MODE = QSYS << TARGET_OFFSET, 2465e256365SVladimir Oltean QSYS_SWITCH_PORT_MODE, 2475e256365SVladimir Oltean QSYS_STAT_CNT_CFG, 2485e256365SVladimir Oltean QSYS_EEE_CFG, 2495e256365SVladimir Oltean QSYS_EEE_THRES, 2505e256365SVladimir Oltean QSYS_IGR_NO_SHARING, 2515e256365SVladimir Oltean QSYS_EGR_NO_SHARING, 2525e256365SVladimir Oltean QSYS_SW_STATUS, 2535e256365SVladimir Oltean QSYS_EXT_CPU_CFG, 2545e256365SVladimir Oltean QSYS_PAD_CFG, 2555e256365SVladimir Oltean QSYS_CPU_GROUP_MAP, 2565e256365SVladimir Oltean QSYS_QMAP, 2575e256365SVladimir Oltean QSYS_ISDX_SGRP, 2585e256365SVladimir Oltean QSYS_TIMED_FRAME_ENTRY, 2595e256365SVladimir Oltean QSYS_TFRM_MISC, 2605e256365SVladimir Oltean QSYS_TFRM_PORT_DLY, 2615e256365SVladimir Oltean QSYS_TFRM_TIMER_CFG_1, 2625e256365SVladimir Oltean QSYS_TFRM_TIMER_CFG_2, 2635e256365SVladimir Oltean QSYS_TFRM_TIMER_CFG_3, 2645e256365SVladimir Oltean QSYS_TFRM_TIMER_CFG_4, 2655e256365SVladimir Oltean QSYS_TFRM_TIMER_CFG_5, 2665e256365SVladimir Oltean QSYS_TFRM_TIMER_CFG_6, 2675e256365SVladimir Oltean QSYS_TFRM_TIMER_CFG_7, 2685e256365SVladimir Oltean QSYS_TFRM_TIMER_CFG_8, 2695e256365SVladimir Oltean QSYS_RED_PROFILE, 2705e256365SVladimir Oltean QSYS_RES_QOS_MODE, 2715e256365SVladimir Oltean QSYS_RES_CFG, 2725e256365SVladimir Oltean QSYS_RES_STAT, 2735e256365SVladimir Oltean QSYS_EGR_DROP_MODE, 2745e256365SVladimir Oltean QSYS_EQ_CTRL, 2755e256365SVladimir Oltean QSYS_EVENTS_CORE, 2765e256365SVladimir Oltean QSYS_QMAXSDU_CFG_0, 2775e256365SVladimir Oltean QSYS_QMAXSDU_CFG_1, 2785e256365SVladimir Oltean QSYS_QMAXSDU_CFG_2, 2795e256365SVladimir Oltean QSYS_QMAXSDU_CFG_3, 2805e256365SVladimir Oltean QSYS_QMAXSDU_CFG_4, 2815e256365SVladimir Oltean QSYS_QMAXSDU_CFG_5, 2825e256365SVladimir Oltean QSYS_QMAXSDU_CFG_6, 2835e256365SVladimir Oltean QSYS_QMAXSDU_CFG_7, 2845e256365SVladimir Oltean QSYS_PREEMPTION_CFG, 2855e256365SVladimir Oltean QSYS_CIR_CFG, 2865e256365SVladimir Oltean QSYS_EIR_CFG, 2875e256365SVladimir Oltean QSYS_SE_CFG, 2885e256365SVladimir Oltean QSYS_SE_DWRR_CFG, 2895e256365SVladimir Oltean QSYS_SE_CONNECT, 2905e256365SVladimir Oltean QSYS_SE_DLB_SENSE, 2915e256365SVladimir Oltean QSYS_CIR_STATE, 2925e256365SVladimir Oltean QSYS_EIR_STATE, 2935e256365SVladimir Oltean QSYS_SE_STATE, 2945e256365SVladimir Oltean QSYS_HSCH_MISC_CFG, 2955e256365SVladimir Oltean QSYS_TAG_CONFIG, 2965e256365SVladimir Oltean QSYS_TAS_PARAM_CFG_CTRL, 2975e256365SVladimir Oltean QSYS_PORT_MAX_SDU, 2985e256365SVladimir Oltean QSYS_PARAM_CFG_REG_1, 2995e256365SVladimir Oltean QSYS_PARAM_CFG_REG_2, 3005e256365SVladimir Oltean QSYS_PARAM_CFG_REG_3, 3015e256365SVladimir Oltean QSYS_PARAM_CFG_REG_4, 3025e256365SVladimir Oltean QSYS_PARAM_CFG_REG_5, 3035e256365SVladimir Oltean QSYS_GCL_CFG_REG_1, 3045e256365SVladimir Oltean QSYS_GCL_CFG_REG_2, 3055e256365SVladimir Oltean QSYS_PARAM_STATUS_REG_1, 3065e256365SVladimir Oltean QSYS_PARAM_STATUS_REG_2, 3075e256365SVladimir Oltean QSYS_PARAM_STATUS_REG_3, 3085e256365SVladimir Oltean QSYS_PARAM_STATUS_REG_4, 3095e256365SVladimir Oltean QSYS_PARAM_STATUS_REG_5, 3105e256365SVladimir Oltean QSYS_PARAM_STATUS_REG_6, 3115e256365SVladimir Oltean QSYS_PARAM_STATUS_REG_7, 3125e256365SVladimir Oltean QSYS_PARAM_STATUS_REG_8, 3135e256365SVladimir Oltean QSYS_PARAM_STATUS_REG_9, 3145e256365SVladimir Oltean QSYS_GCL_STATUS_REG_1, 3155e256365SVladimir Oltean QSYS_GCL_STATUS_REG_2, 3165e256365SVladimir Oltean REW_PORT_VLAN_CFG = REW << TARGET_OFFSET, 3175e256365SVladimir Oltean REW_TAG_CFG, 3185e256365SVladimir Oltean REW_PORT_CFG, 3195e256365SVladimir Oltean REW_DSCP_CFG, 3205e256365SVladimir Oltean REW_PCP_DEI_QOS_MAP_CFG, 3215e256365SVladimir Oltean REW_PTP_CFG, 3225e256365SVladimir Oltean REW_PTP_DLY1_CFG, 3235e256365SVladimir Oltean REW_RED_TAG_CFG, 3245e256365SVladimir Oltean REW_DSCP_REMAP_DP1_CFG, 3255e256365SVladimir Oltean REW_DSCP_REMAP_CFG, 3265e256365SVladimir Oltean REW_STAT_CFG, 3275e256365SVladimir Oltean REW_REW_STICKY, 3285e256365SVladimir Oltean REW_PPT, 3295e256365SVladimir Oltean SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET, 3305e256365SVladimir Oltean SYS_COUNT_RX_UNICAST, 3315e256365SVladimir Oltean SYS_COUNT_RX_MULTICAST, 3325e256365SVladimir Oltean SYS_COUNT_RX_BROADCAST, 3335e256365SVladimir Oltean SYS_COUNT_RX_SHORTS, 3345e256365SVladimir Oltean SYS_COUNT_RX_FRAGMENTS, 3355e256365SVladimir Oltean SYS_COUNT_RX_JABBERS, 3365e256365SVladimir Oltean SYS_COUNT_RX_CRC_ALIGN_ERRS, 3375e256365SVladimir Oltean SYS_COUNT_RX_SYM_ERRS, 3385e256365SVladimir Oltean SYS_COUNT_RX_64, 3395e256365SVladimir Oltean SYS_COUNT_RX_65_127, 3405e256365SVladimir Oltean SYS_COUNT_RX_128_255, 3415e256365SVladimir Oltean SYS_COUNT_RX_256_1023, 3425e256365SVladimir Oltean SYS_COUNT_RX_1024_1526, 3435e256365SVladimir Oltean SYS_COUNT_RX_1527_MAX, 3445e256365SVladimir Oltean SYS_COUNT_RX_PAUSE, 3455e256365SVladimir Oltean SYS_COUNT_RX_CONTROL, 3465e256365SVladimir Oltean SYS_COUNT_RX_LONGS, 3475e256365SVladimir Oltean SYS_COUNT_RX_CLASSIFIED_DROPS, 3485e256365SVladimir Oltean SYS_COUNT_TX_OCTETS, 3495e256365SVladimir Oltean SYS_COUNT_TX_UNICAST, 3505e256365SVladimir Oltean SYS_COUNT_TX_MULTICAST, 3515e256365SVladimir Oltean SYS_COUNT_TX_BROADCAST, 3525e256365SVladimir Oltean SYS_COUNT_TX_COLLISION, 3535e256365SVladimir Oltean SYS_COUNT_TX_DROPS, 3545e256365SVladimir Oltean SYS_COUNT_TX_PAUSE, 3555e256365SVladimir Oltean SYS_COUNT_TX_64, 3565e256365SVladimir Oltean SYS_COUNT_TX_65_127, 3575e256365SVladimir Oltean SYS_COUNT_TX_128_511, 3585e256365SVladimir Oltean SYS_COUNT_TX_512_1023, 3595e256365SVladimir Oltean SYS_COUNT_TX_1024_1526, 3605e256365SVladimir Oltean SYS_COUNT_TX_1527_MAX, 3615e256365SVladimir Oltean SYS_COUNT_TX_AGING, 3625e256365SVladimir Oltean SYS_RESET_CFG, 3635e256365SVladimir Oltean SYS_SR_ETYPE_CFG, 3645e256365SVladimir Oltean SYS_VLAN_ETYPE_CFG, 3655e256365SVladimir Oltean SYS_PORT_MODE, 3665e256365SVladimir Oltean SYS_FRONT_PORT_MODE, 3675e256365SVladimir Oltean SYS_FRM_AGING, 3685e256365SVladimir Oltean SYS_STAT_CFG, 3695e256365SVladimir Oltean SYS_SW_STATUS, 3705e256365SVladimir Oltean SYS_MISC_CFG, 3715e256365SVladimir Oltean SYS_REW_MAC_HIGH_CFG, 3725e256365SVladimir Oltean SYS_REW_MAC_LOW_CFG, 3735e256365SVladimir Oltean SYS_TIMESTAMP_OFFSET, 3745e256365SVladimir Oltean SYS_CMID, 3755e256365SVladimir Oltean SYS_PAUSE_CFG, 3765e256365SVladimir Oltean SYS_PAUSE_TOT_CFG, 3775e256365SVladimir Oltean SYS_ATOP, 3785e256365SVladimir Oltean SYS_ATOP_TOT_CFG, 3795e256365SVladimir Oltean SYS_MAC_FC_CFG, 3805e256365SVladimir Oltean SYS_MMGT, 3815e256365SVladimir Oltean SYS_MMGT_FAST, 3825e256365SVladimir Oltean SYS_EVENTS_DIF, 3835e256365SVladimir Oltean SYS_EVENTS_CORE, 3845e256365SVladimir Oltean SYS_CNT, 3855e256365SVladimir Oltean SYS_PTP_STATUS, 3865e256365SVladimir Oltean SYS_PTP_TXSTAMP, 3875e256365SVladimir Oltean SYS_PTP_NXT, 3885e256365SVladimir Oltean SYS_PTP_CFG, 3895e256365SVladimir Oltean SYS_RAM_INIT, 3905e256365SVladimir Oltean SYS_CM_ADDR, 3915e256365SVladimir Oltean SYS_CM_DATA_WR, 3925e256365SVladimir Oltean SYS_CM_DATA_RD, 3935e256365SVladimir Oltean SYS_CM_OP, 3945e256365SVladimir Oltean SYS_CM_DATA, 3955e256365SVladimir Oltean S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET, 3965e256365SVladimir Oltean S2_CORE_MV_CFG, 3975e256365SVladimir Oltean S2_CACHE_ENTRY_DAT, 3985e256365SVladimir Oltean S2_CACHE_MASK_DAT, 3995e256365SVladimir Oltean S2_CACHE_ACTION_DAT, 4005e256365SVladimir Oltean S2_CACHE_CNT_DAT, 4015e256365SVladimir Oltean S2_CACHE_TG_DAT, 4025e256365SVladimir Oltean PTP_PIN_CFG = PTP << TARGET_OFFSET, 4035e256365SVladimir Oltean PTP_PIN_TOD_SEC_MSB, 4045e256365SVladimir Oltean PTP_PIN_TOD_SEC_LSB, 4055e256365SVladimir Oltean PTP_PIN_TOD_NSEC, 40694aca082SYangbo Lu PTP_PIN_WF_HIGH_PERIOD, 40794aca082SYangbo Lu PTP_PIN_WF_LOW_PERIOD, 4085e256365SVladimir Oltean PTP_CFG_MISC, 4095e256365SVladimir Oltean PTP_CLK_CFG_ADJ_CFG, 4105e256365SVladimir Oltean PTP_CLK_CFG_ADJ_FREQ, 4115e256365SVladimir Oltean GCB_SOFT_RST = GCB << TARGET_OFFSET, 4122789658fSMaxim Kochetkov GCB_MIIM_MII_STATUS, 4132789658fSMaxim Kochetkov GCB_MIIM_MII_CMD, 4142789658fSMaxim Kochetkov GCB_MIIM_MII_DATA, 41591c724cfSVladimir Oltean DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, 41691c724cfSVladimir Oltean DEV_PORT_MISC, 41791c724cfSVladimir Oltean DEV_EVENTS, 41891c724cfSVladimir Oltean DEV_EEE_CFG, 41991c724cfSVladimir Oltean DEV_RX_PATH_DELAY, 42091c724cfSVladimir Oltean DEV_TX_PATH_DELAY, 42191c724cfSVladimir Oltean DEV_PTP_PREDICT_CFG, 42291c724cfSVladimir Oltean DEV_MAC_ENA_CFG, 42391c724cfSVladimir Oltean DEV_MAC_MODE_CFG, 42491c724cfSVladimir Oltean DEV_MAC_MAXLEN_CFG, 42591c724cfSVladimir Oltean DEV_MAC_TAGS_CFG, 42691c724cfSVladimir Oltean DEV_MAC_ADV_CHK_CFG, 42791c724cfSVladimir Oltean DEV_MAC_IFG_CFG, 42891c724cfSVladimir Oltean DEV_MAC_HDX_CFG, 42991c724cfSVladimir Oltean DEV_MAC_DBG_CFG, 43091c724cfSVladimir Oltean DEV_MAC_FC_MAC_LOW_CFG, 43191c724cfSVladimir Oltean DEV_MAC_FC_MAC_HIGH_CFG, 43291c724cfSVladimir Oltean DEV_MAC_STICKY, 43391c724cfSVladimir Oltean PCS1G_CFG, 43491c724cfSVladimir Oltean PCS1G_MODE_CFG, 43591c724cfSVladimir Oltean PCS1G_SD_CFG, 43691c724cfSVladimir Oltean PCS1G_ANEG_CFG, 43791c724cfSVladimir Oltean PCS1G_ANEG_NP_CFG, 43891c724cfSVladimir Oltean PCS1G_LB_CFG, 43991c724cfSVladimir Oltean PCS1G_DBG_CFG, 44091c724cfSVladimir Oltean PCS1G_CDET_CFG, 44191c724cfSVladimir Oltean PCS1G_ANEG_STATUS, 44291c724cfSVladimir Oltean PCS1G_ANEG_NP_STATUS, 44391c724cfSVladimir Oltean PCS1G_LINK_STATUS, 44491c724cfSVladimir Oltean PCS1G_LINK_DOWN_CNT, 44591c724cfSVladimir Oltean PCS1G_STICKY, 44691c724cfSVladimir Oltean PCS1G_DEBUG_STATUS, 44791c724cfSVladimir Oltean PCS1G_LPI_CFG, 44891c724cfSVladimir Oltean PCS1G_LPI_WAKE_ERROR_CNT, 44991c724cfSVladimir Oltean PCS1G_LPI_STATUS, 45091c724cfSVladimir Oltean PCS1G_TSTPAT_MODE_CFG, 45191c724cfSVladimir Oltean PCS1G_TSTPAT_STATUS, 45291c724cfSVladimir Oltean DEV_PCS_FX100_CFG, 45391c724cfSVladimir Oltean DEV_PCS_FX100_STATUS, 4545e256365SVladimir Oltean }; 4555e256365SVladimir Oltean 4565e256365SVladimir Oltean enum ocelot_regfield { 4575e256365SVladimir Oltean ANA_ADVLEARN_VLAN_CHK, 4585e256365SVladimir Oltean ANA_ADVLEARN_LEARN_MIRROR, 4595e256365SVladimir Oltean ANA_ANEVENTS_FLOOD_DISCARD, 4605e256365SVladimir Oltean ANA_ANEVENTS_MSTI_DROP, 4615e256365SVladimir Oltean ANA_ANEVENTS_ACLKILL, 4625e256365SVladimir Oltean ANA_ANEVENTS_ACLUSED, 4635e256365SVladimir Oltean ANA_ANEVENTS_AUTOAGE, 4645e256365SVladimir Oltean ANA_ANEVENTS_VS2TTL1, 4655e256365SVladimir Oltean ANA_ANEVENTS_STORM_DROP, 4665e256365SVladimir Oltean ANA_ANEVENTS_LEARN_DROP, 4675e256365SVladimir Oltean ANA_ANEVENTS_AGED_ENTRY, 4685e256365SVladimir Oltean ANA_ANEVENTS_CPU_LEARN_FAILED, 4695e256365SVladimir Oltean ANA_ANEVENTS_AUTO_LEARN_FAILED, 4705e256365SVladimir Oltean ANA_ANEVENTS_LEARN_REMOVE, 4715e256365SVladimir Oltean ANA_ANEVENTS_AUTO_LEARNED, 4725e256365SVladimir Oltean ANA_ANEVENTS_AUTO_MOVED, 4735e256365SVladimir Oltean ANA_ANEVENTS_DROPPED, 4745e256365SVladimir Oltean ANA_ANEVENTS_CLASSIFIED_DROP, 4755e256365SVladimir Oltean ANA_ANEVENTS_CLASSIFIED_COPY, 4765e256365SVladimir Oltean ANA_ANEVENTS_VLAN_DISCARD, 4775e256365SVladimir Oltean ANA_ANEVENTS_FWD_DISCARD, 4785e256365SVladimir Oltean ANA_ANEVENTS_MULTICAST_FLOOD, 4795e256365SVladimir Oltean ANA_ANEVENTS_UNICAST_FLOOD, 4805e256365SVladimir Oltean ANA_ANEVENTS_DEST_KNOWN, 4815e256365SVladimir Oltean ANA_ANEVENTS_BUCKET3_MATCH, 4825e256365SVladimir Oltean ANA_ANEVENTS_BUCKET2_MATCH, 4835e256365SVladimir Oltean ANA_ANEVENTS_BUCKET1_MATCH, 4845e256365SVladimir Oltean ANA_ANEVENTS_BUCKET0_MATCH, 4855e256365SVladimir Oltean ANA_ANEVENTS_CPU_OPERATION, 4865e256365SVladimir Oltean ANA_ANEVENTS_DMAC_LOOKUP, 4875e256365SVladimir Oltean ANA_ANEVENTS_SMAC_LOOKUP, 4885e256365SVladimir Oltean ANA_ANEVENTS_SEQ_GEN_ERR_0, 4895e256365SVladimir Oltean ANA_ANEVENTS_SEQ_GEN_ERR_1, 4905e256365SVladimir Oltean ANA_TABLES_MACACCESS_B_DOM, 4915e256365SVladimir Oltean ANA_TABLES_MACTINDX_BUCKET, 4925e256365SVladimir Oltean ANA_TABLES_MACTINDX_M_INDEX, 493886e1387SVladimir Oltean QSYS_SWITCH_PORT_MODE_PORT_ENA, 494886e1387SVladimir Oltean QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG, 495886e1387SVladimir Oltean QSYS_SWITCH_PORT_MODE_YEL_RSRVD, 496886e1387SVladimir Oltean QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE, 497886e1387SVladimir Oltean QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 498886e1387SVladimir Oltean QSYS_SWITCH_PORT_MODE_TX_PFC_MODE, 4995e256365SVladimir Oltean QSYS_TIMED_FRAME_ENTRY_TFRM_VLD, 5005e256365SVladimir Oltean QSYS_TIMED_FRAME_ENTRY_TFRM_FP, 5015e256365SVladimir Oltean QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO, 5025e256365SVladimir Oltean QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL, 5035e256365SVladimir Oltean QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T, 504886e1387SVladimir Oltean SYS_PORT_MODE_DATA_WO_TS, 505886e1387SVladimir Oltean SYS_PORT_MODE_INCL_INJ_HDR, 506886e1387SVladimir Oltean SYS_PORT_MODE_INCL_XTR_HDR, 507886e1387SVladimir Oltean SYS_PORT_MODE_INCL_HDR_ERR, 5085e256365SVladimir Oltean SYS_RESET_CFG_CORE_ENA, 5095e256365SVladimir Oltean SYS_RESET_CFG_MEM_ENA, 5105e256365SVladimir Oltean SYS_RESET_CFG_MEM_INIT, 5115e256365SVladimir Oltean GCB_SOFT_RST_SWC_RST, 5122789658fSMaxim Kochetkov GCB_MIIM_MII_STATUS_PENDING, 5132789658fSMaxim Kochetkov GCB_MIIM_MII_STATUS_BUSY, 514541132f0SMaxim Kochetkov SYS_PAUSE_CFG_PAUSE_START, 515541132f0SMaxim Kochetkov SYS_PAUSE_CFG_PAUSE_STOP, 516541132f0SMaxim Kochetkov SYS_PAUSE_CFG_PAUSE_ENA, 5175e256365SVladimir Oltean REGFIELD_MAX 5185e256365SVladimir Oltean }; 5195e256365SVladimir Oltean 5203007bc73SYangbo Lu enum ocelot_ptp_pins { 5213007bc73SYangbo Lu PTP_PIN_0, 5223007bc73SYangbo Lu PTP_PIN_1, 5233007bc73SYangbo Lu PTP_PIN_2, 5243007bc73SYangbo Lu PTP_PIN_3, 5255e256365SVladimir Oltean TOD_ACC_PIN 5265e256365SVladimir Oltean }; 5275e256365SVladimir Oltean 5285e256365SVladimir Oltean struct ocelot_stat_layout { 5295e256365SVladimir Oltean u32 offset; 5305e256365SVladimir Oltean char name[ETH_GSTRING_LEN]; 5315e256365SVladimir Oltean }; 5325e256365SVladimir Oltean 5335e256365SVladimir Oltean enum ocelot_tag_prefix { 5345e256365SVladimir Oltean OCELOT_TAG_PREFIX_DISABLED = 0, 5355e256365SVladimir Oltean OCELOT_TAG_PREFIX_NONE, 5365e256365SVladimir Oltean OCELOT_TAG_PREFIX_SHORT, 5375e256365SVladimir Oltean OCELOT_TAG_PREFIX_LONG, 5385e256365SVladimir Oltean }; 5395e256365SVladimir Oltean 5405e256365SVladimir Oltean struct ocelot; 5415e256365SVladimir Oltean 5425e256365SVladimir Oltean struct ocelot_ops { 5435e256365SVladimir Oltean int (*reset)(struct ocelot *ocelot); 544aa92d836SMaxim Kochetkov u16 (*wm_enc)(u16 value); 5455e256365SVladimir Oltean }; 5465e256365SVladimir Oltean 547aae4e500SVladimir Oltean struct ocelot_vcap_block { 548a56d7a34SVladimir Oltean struct list_head rules; 549a56d7a34SVladimir Oltean int count; 550c9a7fe12SXiaoliang Yang int pol_lpr; 551a56d7a34SVladimir Oltean }; 552a56d7a34SVladimir Oltean 5535e256365SVladimir Oltean struct ocelot_port { 5545e256365SVladimir Oltean struct ocelot *ocelot; 5555e256365SVladimir Oltean 55691c724cfSVladimir Oltean struct regmap *target; 5575e256365SVladimir Oltean 55887b0f983SVladimir Oltean bool vlan_aware; 55987b0f983SVladimir Oltean 5605e256365SVladimir Oltean /* Ingress default VLAN (pvid) */ 5615e256365SVladimir Oltean u16 pvid; 5625e256365SVladimir Oltean 5635e256365SVladimir Oltean /* Egress default VLAN (vid) */ 5645e256365SVladimir Oltean u16 vid; 5655e256365SVladimir Oltean 5665e256365SVladimir Oltean u8 ptp_cmd; 567b049da13SYangbo Lu struct sk_buff_head tx_skbs; 5685e256365SVladimir Oltean u8 ts_id; 569*6565243cSVladimir Oltean spinlock_t ts_id_lock; 570ee50d07cSVladimir Oltean 571ee50d07cSVladimir Oltean phy_interface_t phy_mode; 57267c24049SVladimir Oltean 57367c24049SVladimir Oltean u8 *xmit_template; 5745e256365SVladimir Oltean }; 5755e256365SVladimir Oltean 5765e256365SVladimir Oltean struct ocelot { 5775e256365SVladimir Oltean struct device *dev; 5785e256365SVladimir Oltean 5795e256365SVladimir Oltean const struct ocelot_ops *ops; 5805e256365SVladimir Oltean struct regmap *targets[TARGET_MAX]; 5815e256365SVladimir Oltean struct regmap_field *regfields[REGFIELD_MAX]; 5825e256365SVladimir Oltean const u32 *const *map; 5835e256365SVladimir Oltean const struct ocelot_stat_layout *stats_layout; 5845e256365SVladimir Oltean unsigned int num_stats; 5855e256365SVladimir Oltean 5865e256365SVladimir Oltean int shared_queue_sz; 58721ce7f3eSVladimir Oltean int num_mact_rows; 5885e256365SVladimir Oltean 5895e256365SVladimir Oltean struct net_device *hw_bridge_dev; 5905e256365SVladimir Oltean u16 bridge_mask; 5915e256365SVladimir Oltean u16 bridge_fwd_mask; 5925e256365SVladimir Oltean 5935e256365SVladimir Oltean struct ocelot_port **ports; 5945e256365SVladimir Oltean 5955e256365SVladimir Oltean u8 base_mac[ETH_ALEN]; 5965e256365SVladimir Oltean 5975e256365SVladimir Oltean /* Keep track of the vlan port masks */ 5985e256365SVladimir Oltean u32 vlan_mask[VLAN_N_VID]; 5995e256365SVladimir Oltean 60069df578cSVladimir Oltean /* In tables like ANA:PORT and the ANA:PGID:PGID mask, 60169df578cSVladimir Oltean * the CPU is located after the physical ports (at the 60269df578cSVladimir Oltean * num_phys_ports index). 60369df578cSVladimir Oltean */ 6045e256365SVladimir Oltean u8 num_phys_ports; 6055e256365SVladimir Oltean 6060b912fc9SVladimir Oltean int npi; 6070b912fc9SVladimir Oltean 6080b912fc9SVladimir Oltean enum ocelot_tag_prefix inj_prefix; 6090b912fc9SVladimir Oltean enum ocelot_tag_prefix xtr_prefix; 6100b912fc9SVladimir Oltean 6115e256365SVladimir Oltean u32 *lags; 6125e256365SVladimir Oltean 6135e256365SVladimir Oltean struct list_head multicast; 6145e256365SVladimir Oltean 615aae4e500SVladimir Oltean struct ocelot_vcap_block block; 616a56d7a34SVladimir Oltean 617e0632940SVladimir Oltean const struct vcap_field *vcap_is2_keys; 618e0632940SVladimir Oltean const struct vcap_field *vcap_is2_actions; 6198551cdebSVladimir Oltean const struct vcap_props *vcap; 620e0632940SVladimir Oltean 6215e256365SVladimir Oltean /* Workqueue to check statistics for overflow with its lock */ 6225e256365SVladimir Oltean struct mutex stats_lock; 6235e256365SVladimir Oltean u64 *stats; 6245e256365SVladimir Oltean struct delayed_work stats_work; 6255e256365SVladimir Oltean struct workqueue_struct *stats_queue; 6265e256365SVladimir Oltean 6275e256365SVladimir Oltean u8 ptp:1; 6285e256365SVladimir Oltean struct ptp_clock *ptp_clock; 6295e256365SVladimir Oltean struct ptp_clock_info ptp_info; 6305e256365SVladimir Oltean struct hwtstamp_config hwtstamp_config; 6315e256365SVladimir Oltean /* Protects the PTP interface state */ 6325e256365SVladimir Oltean struct mutex ptp_lock; 6335e256365SVladimir Oltean /* Protects the PTP clock */ 6345e256365SVladimir Oltean spinlock_t ptp_clock_lock; 635cc2d87bbSYangbo Lu struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM]; 6365e256365SVladimir Oltean }; 6375e256365SVladimir Oltean 638fc411eaaSVladimir Oltean struct ocelot_policer { 639fc411eaaSVladimir Oltean u32 rate; /* kilobit per second */ 640fc411eaaSVladimir Oltean u32 burst; /* bytes */ 641fc411eaaSVladimir Oltean }; 642fc411eaaSVladimir Oltean 6435e256365SVladimir Oltean #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 6445e256365SVladimir Oltean #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) 6455e256365SVladimir Oltean #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) 6465e256365SVladimir Oltean #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0) 6475e256365SVladimir Oltean 6485e256365SVladimir Oltean #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 6495e256365SVladimir Oltean #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) 6505e256365SVladimir Oltean #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) 6515e256365SVladimir Oltean #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) 6525e256365SVladimir Oltean 6535e256365SVladimir Oltean #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 6545e256365SVladimir Oltean #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) 6555e256365SVladimir Oltean #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) 6565e256365SVladimir Oltean #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) 6575e256365SVladimir Oltean 658886e1387SVladimir Oltean #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val)) 659886e1387SVladimir Oltean #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val)) 660886e1387SVladimir Oltean #define ocelot_fields_write(ocelot, id, reg, val) regmap_fields_write((ocelot)->regfields[(reg)], (id), (val)) 661886e1387SVladimir Oltean #define ocelot_fields_read(ocelot, id, reg, val) regmap_fields_read((ocelot)->regfields[(reg)], (id), (val)) 662886e1387SVladimir Oltean 6635e256365SVladimir Oltean /* I/O */ 6645e256365SVladimir Oltean u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); 6655e256365SVladimir Oltean void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); 6665e256365SVladimir Oltean u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); 6675e256365SVladimir Oltean void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); 6685e256365SVladimir Oltean void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, 6695e256365SVladimir Oltean u32 offset); 6705e256365SVladimir Oltean 6715e256365SVladimir Oltean /* Hardware initialization */ 6725e256365SVladimir Oltean int ocelot_regfields_init(struct ocelot *ocelot, 6735e256365SVladimir Oltean const struct reg_field *const regfields); 6745e256365SVladimir Oltean struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res); 67569df578cSVladimir Oltean void ocelot_configure_cpu(struct ocelot *ocelot, int npi, 6765e256365SVladimir Oltean enum ocelot_tag_prefix injection, 6775e256365SVladimir Oltean enum ocelot_tag_prefix extraction); 6785e256365SVladimir Oltean int ocelot_init(struct ocelot *ocelot); 6795e256365SVladimir Oltean void ocelot_deinit(struct ocelot *ocelot); 6805e256365SVladimir Oltean void ocelot_init_port(struct ocelot *ocelot, int port); 6815e256365SVladimir Oltean 6825e256365SVladimir Oltean /* DSA callbacks */ 6835e256365SVladimir Oltean void ocelot_port_enable(struct ocelot *ocelot, int port, 6845e256365SVladimir Oltean struct phy_device *phy); 6855e256365SVladimir Oltean void ocelot_port_disable(struct ocelot *ocelot, int port); 6865e256365SVladimir Oltean void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data); 6875e256365SVladimir Oltean void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data); 6885e256365SVladimir Oltean int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset); 6895e256365SVladimir Oltean int ocelot_get_ts_info(struct ocelot *ocelot, int port, 6905e256365SVladimir Oltean struct ethtool_ts_info *info); 6915e256365SVladimir Oltean void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs); 6925e256365SVladimir Oltean void ocelot_adjust_link(struct ocelot *ocelot, int port, 6935e256365SVladimir Oltean struct phy_device *phydev); 6945e256365SVladimir Oltean void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 6955e256365SVladimir Oltean bool vlan_aware); 6965e256365SVladimir Oltean void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state); 6975e256365SVladimir Oltean int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 6985e256365SVladimir Oltean struct net_device *bridge); 6995e256365SVladimir Oltean int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 7005e256365SVladimir Oltean struct net_device *bridge); 7015e256365SVladimir Oltean int ocelot_fdb_dump(struct ocelot *ocelot, int port, 7025e256365SVladimir Oltean dsa_fdb_dump_cb_t *cb, void *data); 7035e256365SVladimir Oltean int ocelot_fdb_add(struct ocelot *ocelot, int port, 70487b0f983SVladimir Oltean const unsigned char *addr, u16 vid); 7055e256365SVladimir Oltean int ocelot_fdb_del(struct ocelot *ocelot, int port, 7065e256365SVladimir Oltean const unsigned char *addr, u16 vid); 7075e256365SVladimir Oltean int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 7085e256365SVladimir Oltean bool untagged); 7095e256365SVladimir Oltean int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid); 710f145922dSYangbo Lu int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr); 711f145922dSYangbo Lu int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr); 712400928bfSYangbo Lu int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port, 713400928bfSYangbo Lu struct sk_buff *skb); 714e23a7b3eSYangbo Lu void ocelot_get_txtstamp(struct ocelot *ocelot); 7150b912fc9SVladimir Oltean void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu); 7160b912fc9SVladimir Oltean int ocelot_get_max_mtu(struct ocelot *ocelot, int port); 717fc411eaaSVladimir Oltean int ocelot_port_policer_add(struct ocelot *ocelot, int port, 718fc411eaaSVladimir Oltean struct ocelot_policer *pol); 719fc411eaaSVladimir Oltean int ocelot_port_policer_del(struct ocelot *ocelot, int port); 72007d985eeSVladimir Oltean int ocelot_cls_flower_replace(struct ocelot *ocelot, int port, 72107d985eeSVladimir Oltean struct flow_cls_offload *f, bool ingress); 72207d985eeSVladimir Oltean int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port, 72307d985eeSVladimir Oltean struct flow_cls_offload *f, bool ingress); 72407d985eeSVladimir Oltean int ocelot_cls_flower_stats(struct ocelot *ocelot, int port, 72507d985eeSVladimir Oltean struct flow_cls_offload *f, bool ingress); 726209edf95SVladimir Oltean int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 727209edf95SVladimir Oltean const struct switchdev_obj_port_mdb *mdb); 728209edf95SVladimir Oltean int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 729209edf95SVladimir Oltean const struct switchdev_obj_port_mdb *mdb); 7305e256365SVladimir Oltean 7315e256365SVladimir Oltean #endif 732