17aa1aa6eSZhao Qiang /* 27aa1aa6eSZhao Qiang * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. 37aa1aa6eSZhao Qiang * 47aa1aa6eSZhao Qiang * Authors: Shlomi Gridish <gridish@freescale.com> 57aa1aa6eSZhao Qiang * Li Yang <leoli@freescale.com> 67aa1aa6eSZhao Qiang * 77aa1aa6eSZhao Qiang * Description: 87aa1aa6eSZhao Qiang * Internal header file for UCC unit routines. 97aa1aa6eSZhao Qiang * 107aa1aa6eSZhao Qiang * This program is free software; you can redistribute it and/or modify it 117aa1aa6eSZhao Qiang * under the terms of the GNU General Public License as published by the 127aa1aa6eSZhao Qiang * Free Software Foundation; either version 2 of the License, or (at your 137aa1aa6eSZhao Qiang * option) any later version. 147aa1aa6eSZhao Qiang */ 157aa1aa6eSZhao Qiang #ifndef __UCC_H__ 167aa1aa6eSZhao Qiang #define __UCC_H__ 177aa1aa6eSZhao Qiang 187aa1aa6eSZhao Qiang #include <soc/fsl/qe/immap_qe.h> 197aa1aa6eSZhao Qiang #include <soc/fsl/qe/qe.h> 207aa1aa6eSZhao Qiang 217aa1aa6eSZhao Qiang #define STATISTICS 227aa1aa6eSZhao Qiang 237aa1aa6eSZhao Qiang #define UCC_MAX_NUM 8 247aa1aa6eSZhao Qiang 257aa1aa6eSZhao Qiang /* Slow or fast type for UCCs. 267aa1aa6eSZhao Qiang */ 277aa1aa6eSZhao Qiang enum ucc_speed_type { 287aa1aa6eSZhao Qiang UCC_SPEED_TYPE_FAST = UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX, 297aa1aa6eSZhao Qiang UCC_SPEED_TYPE_SLOW = UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX 307aa1aa6eSZhao Qiang }; 317aa1aa6eSZhao Qiang 327aa1aa6eSZhao Qiang /* ucc_set_type 337aa1aa6eSZhao Qiang * Sets UCC to slow or fast mode. 347aa1aa6eSZhao Qiang * 357aa1aa6eSZhao Qiang * ucc_num - (In) number of UCC (0-7). 367aa1aa6eSZhao Qiang * speed - (In) slow or fast mode for UCC. 377aa1aa6eSZhao Qiang */ 387aa1aa6eSZhao Qiang int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed); 397aa1aa6eSZhao Qiang 407aa1aa6eSZhao Qiang int ucc_set_qe_mux_mii_mng(unsigned int ucc_num); 417aa1aa6eSZhao Qiang 427aa1aa6eSZhao Qiang int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock, 437aa1aa6eSZhao Qiang enum comm_dir mode); 44bb8b2062SZhao Qiang int ucc_set_tdm_rxtx_clk(unsigned int tdm_num, enum qe_clock clock, 45bb8b2062SZhao Qiang enum comm_dir mode); 46bb8b2062SZhao Qiang int ucc_set_tdm_rxtx_sync(unsigned int tdm_num, enum qe_clock clock, 47bb8b2062SZhao Qiang enum comm_dir mode); 487aa1aa6eSZhao Qiang 497aa1aa6eSZhao Qiang int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask); 507aa1aa6eSZhao Qiang 517aa1aa6eSZhao Qiang /* QE MUX clock routing for UCC 527aa1aa6eSZhao Qiang */ 537aa1aa6eSZhao Qiang static inline int ucc_set_qe_mux_grant(unsigned int ucc_num, int set) 547aa1aa6eSZhao Qiang { 557aa1aa6eSZhao Qiang return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT); 567aa1aa6eSZhao Qiang } 577aa1aa6eSZhao Qiang 587aa1aa6eSZhao Qiang static inline int ucc_set_qe_mux_tsa(unsigned int ucc_num, int set) 597aa1aa6eSZhao Qiang { 607aa1aa6eSZhao Qiang return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA); 617aa1aa6eSZhao Qiang } 627aa1aa6eSZhao Qiang 637aa1aa6eSZhao Qiang static inline int ucc_set_qe_mux_bkpt(unsigned int ucc_num, int set) 647aa1aa6eSZhao Qiang { 657aa1aa6eSZhao Qiang return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT); 667aa1aa6eSZhao Qiang } 677aa1aa6eSZhao Qiang 687aa1aa6eSZhao Qiang #endif /* __UCC_H__ */ 69