1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. 4 * 5 * Authors: Shlomi Gridish <gridish@freescale.com> 6 * Li Yang <leoli@freescale.com> 7 * 8 * Description: 9 * QUICC Engine (QE) external definitions and structure. 10 */ 11 #ifndef _ASM_POWERPC_QE_H 12 #define _ASM_POWERPC_QE_H 13 #ifdef __KERNEL__ 14 15 #include <linux/compiler.h> 16 #include <linux/genalloc.h> 17 #include <linux/spinlock.h> 18 #include <linux/errno.h> 19 #include <linux/err.h> 20 #include <soc/fsl/cpm.h> 21 #include <soc/fsl/qe/immap_qe.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/types.h> 25 26 #define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */ 27 #define QE_NUM_OF_BRGS 16 28 #define QE_NUM_OF_PORTS 1024 29 30 /* Clocks and BRGs */ 31 enum qe_clock { 32 QE_CLK_NONE = 0, 33 QE_BRG1, /* Baud Rate Generator 1 */ 34 QE_BRG2, /* Baud Rate Generator 2 */ 35 QE_BRG3, /* Baud Rate Generator 3 */ 36 QE_BRG4, /* Baud Rate Generator 4 */ 37 QE_BRG5, /* Baud Rate Generator 5 */ 38 QE_BRG6, /* Baud Rate Generator 6 */ 39 QE_BRG7, /* Baud Rate Generator 7 */ 40 QE_BRG8, /* Baud Rate Generator 8 */ 41 QE_BRG9, /* Baud Rate Generator 9 */ 42 QE_BRG10, /* Baud Rate Generator 10 */ 43 QE_BRG11, /* Baud Rate Generator 11 */ 44 QE_BRG12, /* Baud Rate Generator 12 */ 45 QE_BRG13, /* Baud Rate Generator 13 */ 46 QE_BRG14, /* Baud Rate Generator 14 */ 47 QE_BRG15, /* Baud Rate Generator 15 */ 48 QE_BRG16, /* Baud Rate Generator 16 */ 49 QE_CLK1, /* Clock 1 */ 50 QE_CLK2, /* Clock 2 */ 51 QE_CLK3, /* Clock 3 */ 52 QE_CLK4, /* Clock 4 */ 53 QE_CLK5, /* Clock 5 */ 54 QE_CLK6, /* Clock 6 */ 55 QE_CLK7, /* Clock 7 */ 56 QE_CLK8, /* Clock 8 */ 57 QE_CLK9, /* Clock 9 */ 58 QE_CLK10, /* Clock 10 */ 59 QE_CLK11, /* Clock 11 */ 60 QE_CLK12, /* Clock 12 */ 61 QE_CLK13, /* Clock 13 */ 62 QE_CLK14, /* Clock 14 */ 63 QE_CLK15, /* Clock 15 */ 64 QE_CLK16, /* Clock 16 */ 65 QE_CLK17, /* Clock 17 */ 66 QE_CLK18, /* Clock 18 */ 67 QE_CLK19, /* Clock 19 */ 68 QE_CLK20, /* Clock 20 */ 69 QE_CLK21, /* Clock 21 */ 70 QE_CLK22, /* Clock 22 */ 71 QE_CLK23, /* Clock 23 */ 72 QE_CLK24, /* Clock 24 */ 73 QE_RSYNC_PIN, /* RSYNC from pin */ 74 QE_TSYNC_PIN, /* TSYNC from pin */ 75 QE_CLK_DUMMY 76 }; 77 78 static inline bool qe_clock_is_brg(enum qe_clock clk) 79 { 80 return clk >= QE_BRG1 && clk <= QE_BRG16; 81 } 82 83 extern spinlock_t cmxgcr_lock; 84 85 /* Export QE common operations */ 86 #ifdef CONFIG_QUICC_ENGINE 87 extern void qe_reset(void); 88 #else 89 static inline void qe_reset(void) {} 90 #endif 91 92 int cpm_muram_init(void); 93 94 #if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) 95 s32 cpm_muram_alloc(unsigned long size, unsigned long align); 96 void cpm_muram_free(s32 offset); 97 s32 cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); 98 void __iomem *cpm_muram_addr(unsigned long offset); 99 unsigned long cpm_muram_offset(const void __iomem *addr); 100 dma_addr_t cpm_muram_dma(void __iomem *addr); 101 void cpm_muram_free_addr(const void __iomem *addr); 102 #else 103 static inline s32 cpm_muram_alloc(unsigned long size, 104 unsigned long align) 105 { 106 return -ENOSYS; 107 } 108 109 static inline void cpm_muram_free(s32 offset) 110 { 111 } 112 113 static inline s32 cpm_muram_alloc_fixed(unsigned long offset, 114 unsigned long size) 115 { 116 return -ENOSYS; 117 } 118 119 static inline void __iomem *cpm_muram_addr(unsigned long offset) 120 { 121 return NULL; 122 } 123 124 static inline unsigned long cpm_muram_offset(const void __iomem *addr) 125 { 126 return -ENOSYS; 127 } 128 129 static inline dma_addr_t cpm_muram_dma(void __iomem *addr) 130 { 131 return 0; 132 } 133 static inline void cpm_muram_free_addr(const void __iomem *addr) 134 { 135 } 136 #endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */ 137 138 /* QE PIO */ 139 #define QE_PIO_PINS 32 140 141 struct qe_pio_regs { 142 __be32 cpodr; /* Open drain register */ 143 __be32 cpdata; /* Data register */ 144 __be32 cpdir1; /* Direction register */ 145 __be32 cpdir2; /* Direction register */ 146 __be32 cppar1; /* Pin assignment register */ 147 __be32 cppar2; /* Pin assignment register */ 148 #ifdef CONFIG_PPC_85xx 149 u8 pad[8]; 150 #endif 151 }; 152 153 #define QE_PIO_DIR_IN 2 154 #define QE_PIO_DIR_OUT 1 155 extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, 156 int dir, int open_drain, int assignment, 157 int has_irq); 158 #ifdef CONFIG_QUICC_ENGINE 159 extern int par_io_init(struct device_node *np); 160 extern int par_io_of_config(struct device_node *np); 161 extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, 162 int assignment, int has_irq); 163 extern int par_io_data_set(u8 port, u8 pin, u8 val); 164 #else 165 static inline int par_io_init(struct device_node *np) { return -ENOSYS; } 166 static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; } 167 static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, 168 int assignment, int has_irq) { return -ENOSYS; } 169 static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } 170 #endif /* CONFIG_QUICC_ENGINE */ 171 172 /* 173 * Pin multiplexing functions. 174 */ 175 struct qe_pin; 176 #ifdef CONFIG_QE_GPIO 177 extern struct qe_pin *qe_pin_request(struct device_node *np, int index); 178 extern void qe_pin_free(struct qe_pin *qe_pin); 179 extern void qe_pin_set_gpio(struct qe_pin *qe_pin); 180 extern void qe_pin_set_dedicated(struct qe_pin *pin); 181 #else 182 static inline struct qe_pin *qe_pin_request(struct device_node *np, int index) 183 { 184 return ERR_PTR(-ENOSYS); 185 } 186 static inline void qe_pin_free(struct qe_pin *qe_pin) {} 187 static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {} 188 static inline void qe_pin_set_dedicated(struct qe_pin *pin) {} 189 #endif /* CONFIG_QE_GPIO */ 190 191 #ifdef CONFIG_QUICC_ENGINE 192 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); 193 #else 194 static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, 195 u32 cmd_input) 196 { 197 return -ENOSYS; 198 } 199 #endif /* CONFIG_QUICC_ENGINE */ 200 201 /* QE internal API */ 202 enum qe_clock qe_clock_source(const char *source); 203 unsigned int qe_get_brg_clk(void); 204 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); 205 int qe_get_snum(void); 206 void qe_put_snum(u8 snum); 207 unsigned int qe_get_num_of_risc(void); 208 unsigned int qe_get_num_of_snums(void); 209 210 static inline int qe_alive_during_sleep(void) 211 { 212 /* 213 * MPC8568E reference manual says: 214 * 215 * "...power down sequence waits for all I/O interfaces to become idle. 216 * In some applications this may happen eventually without actively 217 * shutting down interfaces, but most likely, software will have to 218 * take steps to shut down the eTSEC, QUICC Engine Block, and PCI 219 * interfaces before issuing the command (either the write to the core 220 * MSR[WE] as described above or writing to POWMGTCSR) to put the 221 * device into sleep state." 222 * 223 * MPC8569E reference manual has a similar paragraph. 224 */ 225 #ifdef CONFIG_PPC_85xx 226 return 0; 227 #else 228 return 1; 229 #endif 230 } 231 232 /* we actually use cpm_muram implementation, define this for convenience */ 233 #define qe_muram_init cpm_muram_init 234 #define qe_muram_alloc cpm_muram_alloc 235 #define qe_muram_alloc_fixed cpm_muram_alloc_fixed 236 #define qe_muram_free cpm_muram_free 237 #define qe_muram_addr cpm_muram_addr 238 #define qe_muram_offset cpm_muram_offset 239 #define qe_muram_dma cpm_muram_dma 240 #define qe_muram_free_addr cpm_muram_free_addr 241 242 #ifdef CONFIG_PPC32 243 #define qe_iowrite8(val, addr) out_8(addr, val) 244 #define qe_iowrite16be(val, addr) out_be16(addr, val) 245 #define qe_iowrite32be(val, addr) out_be32(addr, val) 246 #define qe_ioread8(addr) in_8(addr) 247 #define qe_ioread16be(addr) in_be16(addr) 248 #define qe_ioread32be(addr) in_be32(addr) 249 #else 250 #define qe_iowrite8(val, addr) iowrite8(val, addr) 251 #define qe_iowrite16be(val, addr) iowrite16be(val, addr) 252 #define qe_iowrite32be(val, addr) iowrite32be(val, addr) 253 #define qe_ioread8(addr) ioread8(addr) 254 #define qe_ioread16be(addr) ioread16be(addr) 255 #define qe_ioread32be(addr) ioread32be(addr) 256 #endif 257 258 #define qe_setbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) | (_v), (_addr)) 259 #define qe_clrbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) & ~(_v), (_addr)) 260 261 #define qe_setbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) | (_v), (_addr)) 262 #define qe_clrbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) & ~(_v), (_addr)) 263 264 #define qe_setbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) | (_v), (_addr)) 265 #define qe_clrbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) & ~(_v), (_addr)) 266 267 #define qe_clrsetbits_be32(addr, clear, set) \ 268 qe_iowrite32be((qe_ioread32be(addr) & ~(clear)) | (set), (addr)) 269 #define qe_clrsetbits_be16(addr, clear, set) \ 270 qe_iowrite16be((qe_ioread16be(addr) & ~(clear)) | (set), (addr)) 271 #define qe_clrsetbits_8(addr, clear, set) \ 272 qe_iowrite8((qe_ioread8(addr) & ~(clear)) | (set), (addr)) 273 274 /* Structure that defines QE firmware binary files. 275 * 276 * See Documentation/powerpc/qe_firmware.rst for a description of these 277 * fields. 278 */ 279 struct qe_firmware { 280 struct qe_header { 281 __be32 length; /* Length of the entire structure, in bytes */ 282 u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ 283 u8 version; /* Version of this layout. First ver is '1' */ 284 } header; 285 u8 id[62]; /* Null-terminated identifier string */ 286 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ 287 u8 count; /* Number of microcode[] structures */ 288 struct { 289 __be16 model; /* The SOC model */ 290 u8 major; /* The SOC revision major */ 291 u8 minor; /* The SOC revision minor */ 292 } __attribute__ ((packed)) soc; 293 u8 padding[4]; /* Reserved, for alignment */ 294 __be64 extended_modes; /* Extended modes */ 295 __be32 vtraps[8]; /* Virtual trap addresses */ 296 u8 reserved[4]; /* Reserved, for future expansion */ 297 struct qe_microcode { 298 u8 id[32]; /* Null-terminated identifier */ 299 __be32 traps[16]; /* Trap addresses, 0 == ignore */ 300 __be32 eccr; /* The value for the ECCR register */ 301 __be32 iram_offset; /* Offset into I-RAM for the code */ 302 __be32 count; /* Number of 32-bit words of the code */ 303 __be32 code_offset; /* Offset of the actual microcode */ 304 u8 major; /* The microcode version major */ 305 u8 minor; /* The microcode version minor */ 306 u8 revision; /* The microcode version revision */ 307 u8 padding; /* Reserved, for alignment */ 308 u8 reserved[4]; /* Reserved, for future expansion */ 309 } __packed microcode[]; 310 /* All microcode binaries should be located here */ 311 /* CRC32 should be located here, after the microcode binaries */ 312 } __attribute__ ((packed)); 313 314 struct qe_firmware_info { 315 char id[64]; /* Firmware name */ 316 u32 vtraps[8]; /* Virtual trap addresses */ 317 u64 extended_modes; /* Extended modes */ 318 }; 319 320 #ifdef CONFIG_QUICC_ENGINE 321 /* Upload a firmware to the QE */ 322 int qe_upload_firmware(const struct qe_firmware *firmware); 323 #else 324 static inline int qe_upload_firmware(const struct qe_firmware *firmware) 325 { 326 return -ENOSYS; 327 } 328 #endif /* CONFIG_QUICC_ENGINE */ 329 330 /* Obtain information on the uploaded firmware */ 331 struct qe_firmware_info *qe_get_firmware_info(void); 332 333 /* QE USB */ 334 int qe_usb_clock_set(enum qe_clock clk, int rate); 335 336 /* Buffer descriptors */ 337 struct qe_bd { 338 __be16 status; 339 __be16 length; 340 __be32 buf; 341 } __attribute__ ((packed)); 342 343 #define BD_STATUS_MASK 0xffff0000 344 #define BD_LENGTH_MASK 0x0000ffff 345 346 /* Alignment */ 347 #define QE_INTR_TABLE_ALIGN 16 /* ??? */ 348 #define QE_ALIGNMENT_OF_BD 8 349 #define QE_ALIGNMENT_OF_PRAM 64 350 351 /* RISC allocation */ 352 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ 353 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ 354 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ 355 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ 356 #define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ 357 QE_RISC_ALLOCATION_RISC2) 358 #define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ 359 QE_RISC_ALLOCATION_RISC2 | \ 360 QE_RISC_ALLOCATION_RISC3 | \ 361 QE_RISC_ALLOCATION_RISC4) 362 363 /* QE extended filtering Table Lookup Key Size */ 364 enum qe_fltr_tbl_lookup_key_size { 365 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES 366 = 0x3f, /* LookupKey parsed by the Generate LookupKey 367 CMD is truncated to 8 bytes */ 368 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES 369 = 0x5f, /* LookupKey parsed by the Generate LookupKey 370 CMD is truncated to 16 bytes */ 371 }; 372 373 /* QE FLTR extended filtering Largest External Table Lookup Key Size */ 374 enum qe_fltr_largest_external_tbl_lookup_key_size { 375 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE 376 = 0x0,/* not used */ 377 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES 378 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */ 379 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES 380 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */ 381 }; 382 383 /* structure representing QE parameter RAM */ 384 struct qe_timer_tables { 385 u16 tm_base; /* QE timer table base adr */ 386 u16 tm_ptr; /* QE timer table pointer */ 387 u16 r_tmr; /* QE timer mode register */ 388 u16 r_tmv; /* QE timer valid register */ 389 u32 tm_cmd; /* QE timer cmd register */ 390 u32 tm_cnt; /* QE timer internal cnt */ 391 } __attribute__ ((packed)); 392 393 #define QE_FLTR_TAD_SIZE 8 394 395 /* QE extended filtering Termination Action Descriptor (TAD) */ 396 struct qe_fltr_tad { 397 u8 serialized[QE_FLTR_TAD_SIZE]; 398 } __attribute__ ((packed)); 399 400 /* Communication Direction */ 401 enum comm_dir { 402 COMM_DIR_NONE = 0, 403 COMM_DIR_RX = 1, 404 COMM_DIR_TX = 2, 405 COMM_DIR_RX_AND_TX = 3 406 }; 407 408 /* QE CMXUCR Registers. 409 * There are two UCCs represented in each of the four CMXUCR registers. 410 * These values are for the UCC in the LSBs 411 */ 412 #define QE_CMXUCR_MII_ENET_MNG 0x00007000 413 #define QE_CMXUCR_MII_ENET_MNG_SHIFT 12 414 #define QE_CMXUCR_GRANT 0x00008000 415 #define QE_CMXUCR_TSA 0x00004000 416 #define QE_CMXUCR_BKPT 0x00000100 417 #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F 418 419 /* QE CMXGCR Registers. 420 */ 421 #define QE_CMXGCR_MII_ENET_MNG 0x00007000 422 #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 423 #define QE_CMXGCR_USBCS 0x0000000f 424 #define QE_CMXGCR_USBCS_CLK3 0x1 425 #define QE_CMXGCR_USBCS_CLK5 0x2 426 #define QE_CMXGCR_USBCS_CLK7 0x3 427 #define QE_CMXGCR_USBCS_CLK9 0x4 428 #define QE_CMXGCR_USBCS_CLK13 0x5 429 #define QE_CMXGCR_USBCS_CLK17 0x6 430 #define QE_CMXGCR_USBCS_CLK19 0x7 431 #define QE_CMXGCR_USBCS_CLK21 0x8 432 #define QE_CMXGCR_USBCS_BRG9 0x9 433 #define QE_CMXGCR_USBCS_BRG10 0xa 434 435 /* QE CECR Commands. 436 */ 437 #define QE_CR_FLG 0x00010000 438 #define QE_RESET 0x80000000 439 #define QE_INIT_TX_RX 0x00000000 440 #define QE_INIT_RX 0x00000001 441 #define QE_INIT_TX 0x00000002 442 #define QE_ENTER_HUNT_MODE 0x00000003 443 #define QE_STOP_TX 0x00000004 444 #define QE_GRACEFUL_STOP_TX 0x00000005 445 #define QE_RESTART_TX 0x00000006 446 #define QE_CLOSE_RX_BD 0x00000007 447 #define QE_SWITCH_COMMAND 0x00000007 448 #define QE_SET_GROUP_ADDRESS 0x00000008 449 #define QE_START_IDMA 0x00000009 450 #define QE_MCC_STOP_RX 0x00000009 451 #define QE_ATM_TRANSMIT 0x0000000a 452 #define QE_HPAC_CLEAR_ALL 0x0000000b 453 #define QE_GRACEFUL_STOP_RX 0x0000001a 454 #define QE_RESTART_RX 0x0000001b 455 #define QE_HPAC_SET_PRIORITY 0x0000010b 456 #define QE_HPAC_STOP_TX 0x0000020b 457 #define QE_HPAC_STOP_RX 0x0000030b 458 #define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b 459 #define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b 460 #define QE_HPAC_START_TX 0x0000060b 461 #define QE_HPAC_START_RX 0x0000070b 462 #define QE_USB_STOP_TX 0x0000000a 463 #define QE_USB_RESTART_TX 0x0000000c 464 #define QE_QMC_STOP_TX 0x0000000c 465 #define QE_QMC_STOP_RX 0x0000000d 466 #define QE_SS7_SU_FIL_RESET 0x0000000e 467 /* jonathbr added from here down for 83xx */ 468 #define QE_RESET_BCS 0x0000000a 469 #define QE_MCC_INIT_TX_RX_16 0x00000003 470 #define QE_MCC_STOP_TX 0x00000004 471 #define QE_MCC_INIT_TX_1 0x00000005 472 #define QE_MCC_INIT_RX_1 0x00000006 473 #define QE_MCC_RESET 0x00000007 474 #define QE_SET_TIMER 0x00000008 475 #define QE_RANDOM_NUMBER 0x0000000c 476 #define QE_ATM_MULTI_THREAD_INIT 0x00000011 477 #define QE_ASSIGN_PAGE 0x00000012 478 #define QE_ADD_REMOVE_HASH_ENTRY 0x00000013 479 #define QE_START_FLOW_CONTROL 0x00000014 480 #define QE_STOP_FLOW_CONTROL 0x00000015 481 #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 482 483 #define QE_ASSIGN_RISC 0x00000010 484 #define QE_CR_MCN_NORMAL_SHIFT 6 485 #define QE_CR_MCN_USB_SHIFT 4 486 #define QE_CR_MCN_RISC_ASSIGN_SHIFT 8 487 #define QE_CR_SNUM_SHIFT 17 488 489 /* QE CECR Sub Block - sub block of QE command. 490 */ 491 #define QE_CR_SUBBLOCK_INVALID 0x00000000 492 #define QE_CR_SUBBLOCK_USB 0x03200000 493 #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 494 #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 495 #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 496 #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 497 #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 498 #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 499 #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 500 #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 501 #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 502 #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 503 #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 504 #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 505 #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 506 #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 507 #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 508 #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 509 #define QE_CR_SUBBLOCK_MCC1 0x03800000 510 #define QE_CR_SUBBLOCK_MCC2 0x03a00000 511 #define QE_CR_SUBBLOCK_MCC3 0x03000000 512 #define QE_CR_SUBBLOCK_IDMA1 0x02800000 513 #define QE_CR_SUBBLOCK_IDMA2 0x02a00000 514 #define QE_CR_SUBBLOCK_IDMA3 0x02c00000 515 #define QE_CR_SUBBLOCK_IDMA4 0x02e00000 516 #define QE_CR_SUBBLOCK_HPAC 0x01e00000 517 #define QE_CR_SUBBLOCK_SPI1 0x01400000 518 #define QE_CR_SUBBLOCK_SPI2 0x01600000 519 #define QE_CR_SUBBLOCK_RAND 0x01c00000 520 #define QE_CR_SUBBLOCK_TIMER 0x01e00000 521 #define QE_CR_SUBBLOCK_GENERAL 0x03c00000 522 523 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */ 524 #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ 525 #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 526 #define QE_CR_PROTOCOL_QMC 0x02 527 #define QE_CR_PROTOCOL_UART 0x04 528 #define QE_CR_PROTOCOL_ATM_POS 0x0A 529 #define QE_CR_PROTOCOL_ETHERNET 0x0C 530 #define QE_CR_PROTOCOL_L2_SWITCH 0x0D 531 532 /* BRG configuration register */ 533 #define QE_BRGC_ENABLE 0x00010000 534 #define QE_BRGC_DIVISOR_SHIFT 1 535 #define QE_BRGC_DIVISOR_MAX 0xFFF 536 #define QE_BRGC_DIV16 1 537 538 /* QE Timers registers */ 539 #define QE_GTCFR1_PCAS 0x80 540 #define QE_GTCFR1_STP2 0x20 541 #define QE_GTCFR1_RST2 0x10 542 #define QE_GTCFR1_GM2 0x08 543 #define QE_GTCFR1_GM1 0x04 544 #define QE_GTCFR1_STP1 0x02 545 #define QE_GTCFR1_RST1 0x01 546 547 /* SDMA registers */ 548 #define QE_SDSR_BER1 0x02000000 549 #define QE_SDSR_BER2 0x01000000 550 551 #define QE_SDMR_GLB_1_MSK 0x80000000 552 #define QE_SDMR_ADR_SEL 0x20000000 553 #define QE_SDMR_BER1_MSK 0x02000000 554 #define QE_SDMR_BER2_MSK 0x01000000 555 #define QE_SDMR_EB1_MSK 0x00800000 556 #define QE_SDMR_ER1_MSK 0x00080000 557 #define QE_SDMR_ER2_MSK 0x00040000 558 #define QE_SDMR_CEN_MASK 0x0000E000 559 #define QE_SDMR_SBER_1 0x00000200 560 #define QE_SDMR_SBER_2 0x00000200 561 #define QE_SDMR_EB1_PR_MASK 0x000000C0 562 #define QE_SDMR_ER1_PR 0x00000008 563 564 #define QE_SDMR_CEN_SHIFT 13 565 #define QE_SDMR_EB1_PR_SHIFT 6 566 567 #define QE_SDTM_MSNUM_SHIFT 24 568 569 #define QE_SDEBCR_BA_MASK 0x01FFFFFF 570 571 /* Communication Processor */ 572 #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ 573 #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ 574 #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ 575 576 /* I-RAM */ 577 #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ 578 #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ 579 #define QE_IRAM_READY 0x80000000 /* Ready */ 580 581 /* UPC */ 582 #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ 583 #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ 584 #define UPGCR_RMS 0x20000000 /* Receive master/slave mode */ 585 #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */ 586 #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ 587 588 /* UCC GUEMR register */ 589 #define UCC_GUEMR_MODE_MASK_RX 0x02 590 #define UCC_GUEMR_MODE_FAST_RX 0x02 591 #define UCC_GUEMR_MODE_SLOW_RX 0x00 592 #define UCC_GUEMR_MODE_MASK_TX 0x01 593 #define UCC_GUEMR_MODE_FAST_TX 0x01 594 #define UCC_GUEMR_MODE_SLOW_TX 0x00 595 #define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX) 596 #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but 597 must be set 1 */ 598 599 /* structure representing UCC SLOW parameter RAM */ 600 struct ucc_slow_pram { 601 __be16 rbase; /* RX BD base address */ 602 __be16 tbase; /* TX BD base address */ 603 u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */ 604 u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */ 605 __be16 mrblr; /* Rx buffer length */ 606 __be32 rstate; /* Rx internal state */ 607 __be32 rptr; /* Rx internal data pointer */ 608 __be16 rbptr; /* rb BD Pointer */ 609 __be16 rcount; /* Rx internal byte count */ 610 __be32 rtemp; /* Rx temp */ 611 __be32 tstate; /* Tx internal state */ 612 __be32 tptr; /* Tx internal data pointer */ 613 __be16 tbptr; /* Tx BD pointer */ 614 __be16 tcount; /* Tx byte count */ 615 __be32 ttemp; /* Tx temp */ 616 __be32 rcrc; /* temp receive CRC */ 617 __be32 tcrc; /* temp transmit CRC */ 618 } __attribute__ ((packed)); 619 620 /* General UCC SLOW Mode Register (GUMRH & GUMRL) */ 621 #define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000 622 #define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000 623 #define UCC_SLOW_GUMR_H_REVD 0x00002000 624 #define UCC_SLOW_GUMR_H_TRX 0x00001000 625 #define UCC_SLOW_GUMR_H_TTX 0x00000800 626 #define UCC_SLOW_GUMR_H_CDP 0x00000400 627 #define UCC_SLOW_GUMR_H_CTSP 0x00000200 628 #define UCC_SLOW_GUMR_H_CDS 0x00000100 629 #define UCC_SLOW_GUMR_H_CTSS 0x00000080 630 #define UCC_SLOW_GUMR_H_TFL 0x00000040 631 #define UCC_SLOW_GUMR_H_RFW 0x00000020 632 #define UCC_SLOW_GUMR_H_TXSY 0x00000010 633 #define UCC_SLOW_GUMR_H_4SYNC 0x00000004 634 #define UCC_SLOW_GUMR_H_8SYNC 0x00000008 635 #define UCC_SLOW_GUMR_H_16SYNC 0x0000000c 636 #define UCC_SLOW_GUMR_H_RTSM 0x00000002 637 #define UCC_SLOW_GUMR_H_RSYN 0x00000001 638 639 #define UCC_SLOW_GUMR_L_TCI 0x10000000 640 #define UCC_SLOW_GUMR_L_RINV 0x02000000 641 #define UCC_SLOW_GUMR_L_TINV 0x01000000 642 #define UCC_SLOW_GUMR_L_TEND 0x00040000 643 #define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000 644 #define UCC_SLOW_GUMR_L_TDCR_32 0x00030000 645 #define UCC_SLOW_GUMR_L_TDCR_16 0x00020000 646 #define UCC_SLOW_GUMR_L_TDCR_8 0x00010000 647 #define UCC_SLOW_GUMR_L_TDCR_1 0x00000000 648 #define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000 649 #define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000 650 #define UCC_SLOW_GUMR_L_RDCR_16 0x00008000 651 #define UCC_SLOW_GUMR_L_RDCR_8 0x00004000 652 #define UCC_SLOW_GUMR_L_RDCR_1 0x00000000 653 #define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800 654 #define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000 655 #define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100 656 #define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000 657 #define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0 658 #define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0 659 #define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080 660 #define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040 661 #define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000 662 #define UCC_SLOW_GUMR_L_ENR 0x00000020 663 #define UCC_SLOW_GUMR_L_ENT 0x00000010 664 #define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F 665 #define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008 666 #define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006 667 #define UCC_SLOW_GUMR_L_MODE_UART 0x00000004 668 #define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002 669 670 /* General UCC FAST Mode Register */ 671 #define UCC_FAST_GUMR_LOOPBACK 0x40000000 672 #define UCC_FAST_GUMR_TCI 0x20000000 673 #define UCC_FAST_GUMR_TRX 0x10000000 674 #define UCC_FAST_GUMR_TTX 0x08000000 675 #define UCC_FAST_GUMR_CDP 0x04000000 676 #define UCC_FAST_GUMR_CTSP 0x02000000 677 #define UCC_FAST_GUMR_CDS 0x01000000 678 #define UCC_FAST_GUMR_CTSS 0x00800000 679 #define UCC_FAST_GUMR_TXSY 0x00020000 680 #define UCC_FAST_GUMR_RSYN 0x00010000 681 #define UCC_FAST_GUMR_SYNL_MASK 0x0000C000 682 #define UCC_FAST_GUMR_SYNL_16 0x0000C000 683 #define UCC_FAST_GUMR_SYNL_8 0x00008000 684 #define UCC_FAST_GUMR_SYNL_AUTO 0x00004000 685 #define UCC_FAST_GUMR_RTSM 0x00002000 686 #define UCC_FAST_GUMR_REVD 0x00000400 687 #define UCC_FAST_GUMR_ENR 0x00000020 688 #define UCC_FAST_GUMR_ENT 0x00000010 689 690 /* UART Slow UCC Event Register (UCCE) */ 691 #define UCC_UART_UCCE_AB 0x0200 692 #define UCC_UART_UCCE_IDLE 0x0100 693 #define UCC_UART_UCCE_GRA 0x0080 694 #define UCC_UART_UCCE_BRKE 0x0040 695 #define UCC_UART_UCCE_BRKS 0x0020 696 #define UCC_UART_UCCE_CCR 0x0008 697 #define UCC_UART_UCCE_BSY 0x0004 698 #define UCC_UART_UCCE_TX 0x0002 699 #define UCC_UART_UCCE_RX 0x0001 700 701 /* HDLC Slow UCC Event Register (UCCE) */ 702 #define UCC_HDLC_UCCE_GLR 0x1000 703 #define UCC_HDLC_UCCE_GLT 0x0800 704 #define UCC_HDLC_UCCE_IDLE 0x0100 705 #define UCC_HDLC_UCCE_BRKE 0x0040 706 #define UCC_HDLC_UCCE_BRKS 0x0020 707 #define UCC_HDLC_UCCE_TXE 0x0010 708 #define UCC_HDLC_UCCE_RXF 0x0008 709 #define UCC_HDLC_UCCE_BSY 0x0004 710 #define UCC_HDLC_UCCE_TXB 0x0002 711 #define UCC_HDLC_UCCE_RXB 0x0001 712 713 /* BISYNC Slow UCC Event Register (UCCE) */ 714 #define UCC_BISYNC_UCCE_GRA 0x0080 715 #define UCC_BISYNC_UCCE_TXE 0x0010 716 #define UCC_BISYNC_UCCE_RCH 0x0008 717 #define UCC_BISYNC_UCCE_BSY 0x0004 718 #define UCC_BISYNC_UCCE_TXB 0x0002 719 #define UCC_BISYNC_UCCE_RXB 0x0001 720 721 /* Gigabit Ethernet Fast UCC Event Register (UCCE) */ 722 #define UCC_GETH_UCCE_MPD 0x80000000 723 #define UCC_GETH_UCCE_SCAR 0x40000000 724 #define UCC_GETH_UCCE_GRA 0x20000000 725 #define UCC_GETH_UCCE_CBPR 0x10000000 726 #define UCC_GETH_UCCE_BSY 0x08000000 727 #define UCC_GETH_UCCE_RXC 0x04000000 728 #define UCC_GETH_UCCE_TXC 0x02000000 729 #define UCC_GETH_UCCE_TXE 0x01000000 730 #define UCC_GETH_UCCE_TXB7 0x00800000 731 #define UCC_GETH_UCCE_TXB6 0x00400000 732 #define UCC_GETH_UCCE_TXB5 0x00200000 733 #define UCC_GETH_UCCE_TXB4 0x00100000 734 #define UCC_GETH_UCCE_TXB3 0x00080000 735 #define UCC_GETH_UCCE_TXB2 0x00040000 736 #define UCC_GETH_UCCE_TXB1 0x00020000 737 #define UCC_GETH_UCCE_TXB0 0x00010000 738 #define UCC_GETH_UCCE_RXB7 0x00008000 739 #define UCC_GETH_UCCE_RXB6 0x00004000 740 #define UCC_GETH_UCCE_RXB5 0x00002000 741 #define UCC_GETH_UCCE_RXB4 0x00001000 742 #define UCC_GETH_UCCE_RXB3 0x00000800 743 #define UCC_GETH_UCCE_RXB2 0x00000400 744 #define UCC_GETH_UCCE_RXB1 0x00000200 745 #define UCC_GETH_UCCE_RXB0 0x00000100 746 #define UCC_GETH_UCCE_RXF7 0x00000080 747 #define UCC_GETH_UCCE_RXF6 0x00000040 748 #define UCC_GETH_UCCE_RXF5 0x00000020 749 #define UCC_GETH_UCCE_RXF4 0x00000010 750 #define UCC_GETH_UCCE_RXF3 0x00000008 751 #define UCC_GETH_UCCE_RXF2 0x00000004 752 #define UCC_GETH_UCCE_RXF1 0x00000002 753 #define UCC_GETH_UCCE_RXF0 0x00000001 754 755 /* UCC Protocol Specific Mode Register (UPSMR), when used for UART */ 756 #define UCC_UART_UPSMR_FLC 0x8000 757 #define UCC_UART_UPSMR_SL 0x4000 758 #define UCC_UART_UPSMR_CL_MASK 0x3000 759 #define UCC_UART_UPSMR_CL_8 0x3000 760 #define UCC_UART_UPSMR_CL_7 0x2000 761 #define UCC_UART_UPSMR_CL_6 0x1000 762 #define UCC_UART_UPSMR_CL_5 0x0000 763 #define UCC_UART_UPSMR_UM_MASK 0x0c00 764 #define UCC_UART_UPSMR_UM_NORMAL 0x0000 765 #define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400 766 #define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00 767 #define UCC_UART_UPSMR_FRZ 0x0200 768 #define UCC_UART_UPSMR_RZS 0x0100 769 #define UCC_UART_UPSMR_SYN 0x0080 770 #define UCC_UART_UPSMR_DRT 0x0040 771 #define UCC_UART_UPSMR_PEN 0x0010 772 #define UCC_UART_UPSMR_RPM_MASK 0x000c 773 #define UCC_UART_UPSMR_RPM_ODD 0x0000 774 #define UCC_UART_UPSMR_RPM_LOW 0x0004 775 #define UCC_UART_UPSMR_RPM_EVEN 0x0008 776 #define UCC_UART_UPSMR_RPM_HIGH 0x000C 777 #define UCC_UART_UPSMR_TPM_MASK 0x0003 778 #define UCC_UART_UPSMR_TPM_ODD 0x0000 779 #define UCC_UART_UPSMR_TPM_LOW 0x0001 780 #define UCC_UART_UPSMR_TPM_EVEN 0x0002 781 #define UCC_UART_UPSMR_TPM_HIGH 0x0003 782 783 /* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */ 784 #define UCC_GETH_UPSMR_FTFE 0x80000000 785 #define UCC_GETH_UPSMR_PTPE 0x40000000 786 #define UCC_GETH_UPSMR_ECM 0x04000000 787 #define UCC_GETH_UPSMR_HSE 0x02000000 788 #define UCC_GETH_UPSMR_PRO 0x00400000 789 #define UCC_GETH_UPSMR_CAP 0x00200000 790 #define UCC_GETH_UPSMR_RSH 0x00100000 791 #define UCC_GETH_UPSMR_RPM 0x00080000 792 #define UCC_GETH_UPSMR_R10M 0x00040000 793 #define UCC_GETH_UPSMR_RLPB 0x00020000 794 #define UCC_GETH_UPSMR_TBIM 0x00010000 795 #define UCC_GETH_UPSMR_RES1 0x00002000 796 #define UCC_GETH_UPSMR_RMM 0x00001000 797 #define UCC_GETH_UPSMR_CAM 0x00000400 798 #define UCC_GETH_UPSMR_BRO 0x00000200 799 #define UCC_GETH_UPSMR_SMM 0x00000080 800 #define UCC_GETH_UPSMR_SGMM 0x00000020 801 802 /* UCC Protocol Specific Mode Register (UPSMR), when used for HDLC */ 803 #define UCC_HDLC_UPSMR_RTE 0x02000000 804 #define UCC_HDLC_UPSMR_BUS 0x00200000 805 #define UCC_HDLC_UPSMR_CW8 0x00007000 806 807 /* UCC Transmit On Demand Register (UTODR) */ 808 #define UCC_SLOW_TOD 0x8000 809 #define UCC_FAST_TOD 0x8000 810 811 /* UCC Bus Mode Register masks */ 812 /* Not to be confused with the Bundle Mode Register */ 813 #define UCC_BMR_GBL 0x20 814 #define UCC_BMR_BO_BE 0x10 815 #define UCC_BMR_CETM 0x04 816 #define UCC_BMR_DTB 0x02 817 #define UCC_BMR_BDB 0x01 818 819 /* Function code masks */ 820 #define FC_GBL 0x20 821 #define FC_DTB_LCL 0x02 822 #define UCC_FAST_FUNCTION_CODE_GBL 0x20 823 #define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02 824 #define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01 825 826 #endif /* __KERNEL__ */ 827 #endif /* _ASM_POWERPC_QE_H */ 828