1 /* 2 * QUICC Engine (QE) Internal Memory Map. 3 * The Internal Memory Map for devices with QE on them. This 4 * is the superset of all QE devices (8360, etc.). 5 6 * Copyright (C) 2006. Freescale Semiconductor, Inc. All rights reserved. 7 * 8 * Authors: Shlomi Gridish <gridish@freescale.com> 9 * Li Yang <leoli@freescale.com> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 */ 16 #ifndef _ASM_POWERPC_IMMAP_QE_H 17 #define _ASM_POWERPC_IMMAP_QE_H 18 #ifdef __KERNEL__ 19 20 #include <linux/kernel.h> 21 #include <asm/io.h> 22 23 #define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */ 24 25 /* QE I-RAM */ 26 struct qe_iram { 27 __be32 iadd; /* I-RAM Address Register */ 28 __be32 idata; /* I-RAM Data Register */ 29 u8 res0[0x04]; 30 __be32 iready; /* I-RAM Ready Register */ 31 u8 res1[0x70]; 32 } __attribute__ ((packed)); 33 34 /* QE Interrupt Controller */ 35 struct qe_ic_regs { 36 __be32 qicr; 37 __be32 qivec; 38 __be32 qripnr; 39 __be32 qipnr; 40 __be32 qipxcc; 41 __be32 qipycc; 42 __be32 qipwcc; 43 __be32 qipzcc; 44 __be32 qimr; 45 __be32 qrimr; 46 __be32 qicnr; 47 u8 res0[0x4]; 48 __be32 qiprta; 49 __be32 qiprtb; 50 u8 res1[0x4]; 51 __be32 qricr; 52 u8 res2[0x20]; 53 __be32 qhivec; 54 u8 res3[0x1C]; 55 } __attribute__ ((packed)); 56 57 /* Communications Processor */ 58 struct cp_qe { 59 __be32 cecr; /* QE command register */ 60 __be32 ceccr; /* QE controller configuration register */ 61 __be32 cecdr; /* QE command data register */ 62 u8 res0[0xA]; 63 __be16 ceter; /* QE timer event register */ 64 u8 res1[0x2]; 65 __be16 cetmr; /* QE timers mask register */ 66 __be32 cetscr; /* QE time-stamp timer control register */ 67 __be32 cetsr1; /* QE time-stamp register 1 */ 68 __be32 cetsr2; /* QE time-stamp register 2 */ 69 u8 res2[0x8]; 70 __be32 cevter; /* QE virtual tasks event register */ 71 __be32 cevtmr; /* QE virtual tasks mask register */ 72 __be16 cercr; /* QE RAM control register */ 73 u8 res3[0x2]; 74 u8 res4[0x24]; 75 __be16 ceexe1; /* QE external request 1 event register */ 76 u8 res5[0x2]; 77 __be16 ceexm1; /* QE external request 1 mask register */ 78 u8 res6[0x2]; 79 __be16 ceexe2; /* QE external request 2 event register */ 80 u8 res7[0x2]; 81 __be16 ceexm2; /* QE external request 2 mask register */ 82 u8 res8[0x2]; 83 __be16 ceexe3; /* QE external request 3 event register */ 84 u8 res9[0x2]; 85 __be16 ceexm3; /* QE external request 3 mask register */ 86 u8 res10[0x2]; 87 __be16 ceexe4; /* QE external request 4 event register */ 88 u8 res11[0x2]; 89 __be16 ceexm4; /* QE external request 4 mask register */ 90 u8 res12[0x3A]; 91 __be32 ceurnr; /* QE microcode revision number register */ 92 u8 res13[0x244]; 93 } __attribute__ ((packed)); 94 95 /* QE Multiplexer */ 96 struct qe_mux { 97 __be32 cmxgcr; /* CMX general clock route register */ 98 __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */ 99 __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */ 100 __be32 cmxsi1syr; /* CMX SI1 SYNC route register */ 101 __be32 cmxucr[4]; /* CMX UCCx clock route registers */ 102 __be32 cmxupcr; /* CMX UPC clock route register */ 103 u8 res0[0x1C]; 104 } __attribute__ ((packed)); 105 106 /* QE Timers */ 107 struct qe_timers { 108 u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/ 109 u8 res0[0x3]; 110 u8 gtcfr2; /* Timer 3 and timer 4 global config register*/ 111 u8 res1[0xB]; 112 __be16 gtmdr1; /* Timer 1 mode register */ 113 __be16 gtmdr2; /* Timer 2 mode register */ 114 __be16 gtrfr1; /* Timer 1 reference register */ 115 __be16 gtrfr2; /* Timer 2 reference register */ 116 __be16 gtcpr1; /* Timer 1 capture register */ 117 __be16 gtcpr2; /* Timer 2 capture register */ 118 __be16 gtcnr1; /* Timer 1 counter */ 119 __be16 gtcnr2; /* Timer 2 counter */ 120 __be16 gtmdr3; /* Timer 3 mode register */ 121 __be16 gtmdr4; /* Timer 4 mode register */ 122 __be16 gtrfr3; /* Timer 3 reference register */ 123 __be16 gtrfr4; /* Timer 4 reference register */ 124 __be16 gtcpr3; /* Timer 3 capture register */ 125 __be16 gtcpr4; /* Timer 4 capture register */ 126 __be16 gtcnr3; /* Timer 3 counter */ 127 __be16 gtcnr4; /* Timer 4 counter */ 128 __be16 gtevr1; /* Timer 1 event register */ 129 __be16 gtevr2; /* Timer 2 event register */ 130 __be16 gtevr3; /* Timer 3 event register */ 131 __be16 gtevr4; /* Timer 4 event register */ 132 __be16 gtps; /* Timer 1 prescale register */ 133 u8 res2[0x46]; 134 } __attribute__ ((packed)); 135 136 /* BRG */ 137 struct qe_brg { 138 __be32 brgc[16]; /* BRG configuration registers */ 139 u8 res0[0x40]; 140 } __attribute__ ((packed)); 141 142 /* SPI */ 143 struct spi { 144 u8 res0[0x20]; 145 __be32 spmode; /* SPI mode register */ 146 u8 res1[0x2]; 147 u8 spie; /* SPI event register */ 148 u8 res2[0x1]; 149 u8 res3[0x2]; 150 u8 spim; /* SPI mask register */ 151 u8 res4[0x1]; 152 u8 res5[0x1]; 153 u8 spcom; /* SPI command register */ 154 u8 res6[0x2]; 155 __be32 spitd; /* SPI transmit data register (cpu mode) */ 156 __be32 spird; /* SPI receive data register (cpu mode) */ 157 u8 res7[0x8]; 158 } __attribute__ ((packed)); 159 160 /* SI */ 161 struct si1 { 162 __be16 sixmr1[4]; /* SI1 TDMx (x = A B C D) mode register */ 163 u8 siglmr1_h; /* SI1 global mode register high */ 164 u8 res0[0x1]; 165 u8 sicmdr1_h; /* SI1 command register high */ 166 u8 res2[0x1]; 167 u8 sistr1_h; /* SI1 status register high */ 168 u8 res3[0x1]; 169 __be16 sirsr1_h; /* SI1 RAM shadow address register high */ 170 u8 sitarc1; /* SI1 RAM counter Tx TDMA */ 171 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ 172 u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ 173 u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ 174 u8 sirarc1; /* SI1 RAM counter Rx TDMA */ 175 u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ 176 u8 sircrc1; /* SI1 RAM counter Rx TDMC */ 177 u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ 178 u8 res4[0x8]; 179 __be16 siemr1; /* SI1 TDME mode register 16 bits */ 180 __be16 sifmr1; /* SI1 TDMF mode register 16 bits */ 181 __be16 sigmr1; /* SI1 TDMG mode register 16 bits */ 182 __be16 sihmr1; /* SI1 TDMH mode register 16 bits */ 183 u8 siglmg1_l; /* SI1 global mode register low 8 bits */ 184 u8 res5[0x1]; 185 u8 sicmdr1_l; /* SI1 command register low 8 bits */ 186 u8 res6[0x1]; 187 u8 sistr1_l; /* SI1 status register low 8 bits */ 188 u8 res7[0x1]; 189 __be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/ 190 u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ 191 u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ 192 u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ 193 u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ 194 u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ 195 u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ 196 u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ 197 u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ 198 u8 res8[0x8]; 199 __be32 siml1; /* SI1 multiframe limit register */ 200 u8 siedm1; /* SI1 extended diagnostic mode register */ 201 u8 res9[0xBB]; 202 } __attribute__ ((packed)); 203 204 /* SI Routing Tables */ 205 struct sir { 206 u8 tx[0x400]; 207 u8 rx[0x400]; 208 u8 res0[0x800]; 209 } __attribute__ ((packed)); 210 211 /* USB Controller */ 212 struct qe_usb_ctlr { 213 u8 usb_usmod; 214 u8 usb_usadr; 215 u8 usb_uscom; 216 u8 res1[1]; 217 __be16 usb_usep[4]; 218 u8 res2[4]; 219 __be16 usb_usber; 220 u8 res3[2]; 221 __be16 usb_usbmr; 222 u8 res4[1]; 223 u8 usb_usbs; 224 __be16 usb_ussft; 225 u8 res5[2]; 226 __be16 usb_usfrn; 227 u8 res6[0x22]; 228 } __attribute__ ((packed)); 229 230 /* MCC */ 231 struct qe_mcc { 232 __be32 mcce; /* MCC event register */ 233 __be32 mccm; /* MCC mask register */ 234 __be32 mccf; /* MCC configuration register */ 235 __be32 merl; /* MCC emergency request level register */ 236 u8 res0[0xF0]; 237 } __attribute__ ((packed)); 238 239 /* QE UCC Slow */ 240 struct ucc_slow { 241 __be32 gumr_l; /* UCCx general mode register (low) */ 242 __be32 gumr_h; /* UCCx general mode register (high) */ 243 __be16 upsmr; /* UCCx protocol-specific mode register */ 244 u8 res0[0x2]; 245 __be16 utodr; /* UCCx transmit on demand register */ 246 __be16 udsr; /* UCCx data synchronization register */ 247 __be16 ucce; /* UCCx event register */ 248 u8 res1[0x2]; 249 __be16 uccm; /* UCCx mask register */ 250 u8 res2[0x1]; 251 u8 uccs; /* UCCx status register */ 252 u8 res3[0x24]; 253 __be16 utpt; 254 u8 res4[0x52]; 255 u8 guemr; /* UCC general extended mode register */ 256 } __attribute__ ((packed)); 257 258 /* QE UCC Fast */ 259 struct ucc_fast { 260 __be32 gumr; /* UCCx general mode register */ 261 __be32 upsmr; /* UCCx protocol-specific mode register */ 262 __be16 utodr; /* UCCx transmit on demand register */ 263 u8 res0[0x2]; 264 __be16 udsr; /* UCCx data synchronization register */ 265 u8 res1[0x2]; 266 __be32 ucce; /* UCCx event register */ 267 __be32 uccm; /* UCCx mask register */ 268 u8 uccs; /* UCCx status register */ 269 u8 res2[0x7]; 270 __be32 urfb; /* UCC receive FIFO base */ 271 __be16 urfs; /* UCC receive FIFO size */ 272 u8 res3[0x2]; 273 __be16 urfet; /* UCC receive FIFO emergency threshold */ 274 __be16 urfset; /* UCC receive FIFO special emergency 275 threshold */ 276 __be32 utfb; /* UCC transmit FIFO base */ 277 __be16 utfs; /* UCC transmit FIFO size */ 278 u8 res4[0x2]; 279 __be16 utfet; /* UCC transmit FIFO emergency threshold */ 280 u8 res5[0x2]; 281 __be16 utftt; /* UCC transmit FIFO transmit threshold */ 282 u8 res6[0x2]; 283 __be16 utpt; /* UCC transmit polling timer */ 284 u8 res7[0x2]; 285 __be32 urtry; /* UCC retry counter register */ 286 u8 res8[0x4C]; 287 u8 guemr; /* UCC general extended mode register */ 288 } __attribute__ ((packed)); 289 290 struct ucc { 291 union { 292 struct ucc_slow slow; 293 struct ucc_fast fast; 294 u8 res[0x200]; /* UCC blocks are 512 bytes each */ 295 }; 296 } __attribute__ ((packed)); 297 298 /* MultiPHY UTOPIA POS Controllers (UPC) */ 299 struct upc { 300 __be32 upgcr; /* UTOPIA/POS general configuration register */ 301 __be32 uplpa; /* UTOPIA/POS last PHY address */ 302 __be32 uphec; /* ATM HEC register */ 303 __be32 upuc; /* UTOPIA/POS UCC configuration */ 304 __be32 updc1; /* UTOPIA/POS device 1 configuration */ 305 __be32 updc2; /* UTOPIA/POS device 2 configuration */ 306 __be32 updc3; /* UTOPIA/POS device 3 configuration */ 307 __be32 updc4; /* UTOPIA/POS device 4 configuration */ 308 __be32 upstpa; /* UTOPIA/POS STPA threshold */ 309 u8 res0[0xC]; 310 __be32 updrs1_h; /* UTOPIA/POS device 1 rate select */ 311 __be32 updrs1_l; /* UTOPIA/POS device 1 rate select */ 312 __be32 updrs2_h; /* UTOPIA/POS device 2 rate select */ 313 __be32 updrs2_l; /* UTOPIA/POS device 2 rate select */ 314 __be32 updrs3_h; /* UTOPIA/POS device 3 rate select */ 315 __be32 updrs3_l; /* UTOPIA/POS device 3 rate select */ 316 __be32 updrs4_h; /* UTOPIA/POS device 4 rate select */ 317 __be32 updrs4_l; /* UTOPIA/POS device 4 rate select */ 318 __be32 updrp1; /* UTOPIA/POS device 1 receive priority low */ 319 __be32 updrp2; /* UTOPIA/POS device 2 receive priority low */ 320 __be32 updrp3; /* UTOPIA/POS device 3 receive priority low */ 321 __be32 updrp4; /* UTOPIA/POS device 4 receive priority low */ 322 __be32 upde1; /* UTOPIA/POS device 1 event */ 323 __be32 upde2; /* UTOPIA/POS device 2 event */ 324 __be32 upde3; /* UTOPIA/POS device 3 event */ 325 __be32 upde4; /* UTOPIA/POS device 4 event */ 326 __be16 uprp1; 327 __be16 uprp2; 328 __be16 uprp3; 329 __be16 uprp4; 330 u8 res1[0x8]; 331 __be16 uptirr1_0; /* Device 1 transmit internal rate 0 */ 332 __be16 uptirr1_1; /* Device 1 transmit internal rate 1 */ 333 __be16 uptirr1_2; /* Device 1 transmit internal rate 2 */ 334 __be16 uptirr1_3; /* Device 1 transmit internal rate 3 */ 335 __be16 uptirr2_0; /* Device 2 transmit internal rate 0 */ 336 __be16 uptirr2_1; /* Device 2 transmit internal rate 1 */ 337 __be16 uptirr2_2; /* Device 2 transmit internal rate 2 */ 338 __be16 uptirr2_3; /* Device 2 transmit internal rate 3 */ 339 __be16 uptirr3_0; /* Device 3 transmit internal rate 0 */ 340 __be16 uptirr3_1; /* Device 3 transmit internal rate 1 */ 341 __be16 uptirr3_2; /* Device 3 transmit internal rate 2 */ 342 __be16 uptirr3_3; /* Device 3 transmit internal rate 3 */ 343 __be16 uptirr4_0; /* Device 4 transmit internal rate 0 */ 344 __be16 uptirr4_1; /* Device 4 transmit internal rate 1 */ 345 __be16 uptirr4_2; /* Device 4 transmit internal rate 2 */ 346 __be16 uptirr4_3; /* Device 4 transmit internal rate 3 */ 347 __be32 uper1; /* Device 1 port enable register */ 348 __be32 uper2; /* Device 2 port enable register */ 349 __be32 uper3; /* Device 3 port enable register */ 350 __be32 uper4; /* Device 4 port enable register */ 351 u8 res2[0x150]; 352 } __attribute__ ((packed)); 353 354 /* SDMA */ 355 struct sdma { 356 __be32 sdsr; /* Serial DMA status register */ 357 __be32 sdmr; /* Serial DMA mode register */ 358 __be32 sdtr1; /* SDMA system bus threshold register */ 359 __be32 sdtr2; /* SDMA secondary bus threshold register */ 360 __be32 sdhy1; /* SDMA system bus hysteresis register */ 361 __be32 sdhy2; /* SDMA secondary bus hysteresis register */ 362 __be32 sdta1; /* SDMA system bus address register */ 363 __be32 sdta2; /* SDMA secondary bus address register */ 364 __be32 sdtm1; /* SDMA system bus MSNUM register */ 365 __be32 sdtm2; /* SDMA secondary bus MSNUM register */ 366 u8 res0[0x10]; 367 __be32 sdaqr; /* SDMA address bus qualify register */ 368 __be32 sdaqmr; /* SDMA address bus qualify mask register */ 369 u8 res1[0x4]; 370 __be32 sdebcr; /* SDMA CAM entries base register */ 371 u8 res2[0x38]; 372 } __attribute__ ((packed)); 373 374 /* Debug Space */ 375 struct dbg { 376 __be32 bpdcr; /* Breakpoint debug command register */ 377 __be32 bpdsr; /* Breakpoint debug status register */ 378 __be32 bpdmr; /* Breakpoint debug mask register */ 379 __be32 bprmrr0; /* Breakpoint request mode risc register 0 */ 380 __be32 bprmrr1; /* Breakpoint request mode risc register 1 */ 381 u8 res0[0x8]; 382 __be32 bprmtr0; /* Breakpoint request mode trb register 0 */ 383 __be32 bprmtr1; /* Breakpoint request mode trb register 1 */ 384 u8 res1[0x8]; 385 __be32 bprmir; /* Breakpoint request mode immediate register */ 386 __be32 bprmsr; /* Breakpoint request mode serial register */ 387 __be32 bpemr; /* Breakpoint exit mode register */ 388 u8 res2[0x48]; 389 } __attribute__ ((packed)); 390 391 /* 392 * RISC Special Registers (Trap and Breakpoint). These are described in 393 * the QE Developer's Handbook. 394 */ 395 struct rsp { 396 __be32 tibcr[16]; /* Trap/instruction breakpoint control regs */ 397 u8 res0[64]; 398 __be32 ibcr0; 399 __be32 ibs0; 400 __be32 ibcnr0; 401 u8 res1[4]; 402 __be32 ibcr1; 403 __be32 ibs1; 404 __be32 ibcnr1; 405 __be32 npcr; 406 __be32 dbcr; 407 __be32 dbar; 408 __be32 dbamr; 409 __be32 dbsr; 410 __be32 dbcnr; 411 u8 res2[12]; 412 __be32 dbdr_h; 413 __be32 dbdr_l; 414 __be32 dbdmr_h; 415 __be32 dbdmr_l; 416 __be32 bsr; 417 __be32 bor; 418 __be32 bior; 419 u8 res3[4]; 420 __be32 iatr[4]; 421 __be32 eccr; /* Exception control configuration register */ 422 __be32 eicr; 423 u8 res4[0x100-0xf8]; 424 } __attribute__ ((packed)); 425 426 struct qe_immap { 427 struct qe_iram iram; /* I-RAM */ 428 struct qe_ic_regs ic; /* Interrupt Controller */ 429 struct cp_qe cp; /* Communications Processor */ 430 struct qe_mux qmx; /* QE Multiplexer */ 431 struct qe_timers qet; /* QE Timers */ 432 struct spi spi[0x2]; /* spi */ 433 struct qe_mcc mcc; /* mcc */ 434 struct qe_brg brg; /* brg */ 435 struct qe_usb_ctlr usb; /* USB */ 436 struct si1 si1; /* SI */ 437 u8 res11[0x800]; 438 struct sir sir; /* SI Routing Tables */ 439 struct ucc ucc1; /* ucc1 */ 440 struct ucc ucc3; /* ucc3 */ 441 struct ucc ucc5; /* ucc5 */ 442 struct ucc ucc7; /* ucc7 */ 443 u8 res12[0x600]; 444 struct upc upc1; /* MultiPHY UTOPIA POS Ctrlr 1*/ 445 struct ucc ucc2; /* ucc2 */ 446 struct ucc ucc4; /* ucc4 */ 447 struct ucc ucc6; /* ucc6 */ 448 struct ucc ucc8; /* ucc8 */ 449 u8 res13[0x600]; 450 struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/ 451 struct sdma sdma; /* SDMA */ 452 struct dbg dbg; /* 0x104080 - 0x1040FF 453 Debug Space */ 454 struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF 455 RISC Special Registers 456 (Trap and Breakpoint) */ 457 u8 res14[0x300]; /* 0x104300 - 0x1045FF */ 458 u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */ 459 u8 res16[0x8000]; /* 0x108000 - 0x110000 */ 460 u8 muram[0xC000]; /* 0x110000 - 0x11C000 461 Multi-user RAM */ 462 u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ 463 u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ 464 } __attribute__ ((packed)); 465 466 extern struct qe_immap __iomem *qe_immr; 467 468 #endif /* __KERNEL__ */ 469 #endif /* _ASM_POWERPC_IMMAP_QE_H */ 470