1d5b4a762SRasmus Villemoes /* SPDX-License-Identifier: GPL-2.0 */ 2d5b4a762SRasmus Villemoes #ifndef __CPM_H 3d5b4a762SRasmus Villemoes #define __CPM_H 4d5b4a762SRasmus Villemoes 5d5b4a762SRasmus Villemoes #include <linux/compiler.h> 6d5b4a762SRasmus Villemoes #include <linux/types.h> 7d5b4a762SRasmus Villemoes #include <linux/errno.h> 8d5b4a762SRasmus Villemoes #include <linux/of.h> 9d5b4a762SRasmus Villemoes #include <soc/fsl/qe/qe.h> 10d5b4a762SRasmus Villemoes 11d5b4a762SRasmus Villemoes /* 12d5b4a762SRasmus Villemoes * SPI Parameter RAM common to QE and CPM. 13d5b4a762SRasmus Villemoes */ 14d5b4a762SRasmus Villemoes struct spi_pram { 15d5b4a762SRasmus Villemoes __be16 rbase; /* Rx Buffer descriptor base address */ 16d5b4a762SRasmus Villemoes __be16 tbase; /* Tx Buffer descriptor base address */ 17d5b4a762SRasmus Villemoes u8 rfcr; /* Rx function code */ 18d5b4a762SRasmus Villemoes u8 tfcr; /* Tx function code */ 19d5b4a762SRasmus Villemoes __be16 mrblr; /* Max receive buffer length */ 20d5b4a762SRasmus Villemoes __be32 rstate; /* Internal */ 21d5b4a762SRasmus Villemoes __be32 rdp; /* Internal */ 22d5b4a762SRasmus Villemoes __be16 rbptr; /* Internal */ 23d5b4a762SRasmus Villemoes __be16 rbc; /* Internal */ 24d5b4a762SRasmus Villemoes __be32 rxtmp; /* Internal */ 25d5b4a762SRasmus Villemoes __be32 tstate; /* Internal */ 26d5b4a762SRasmus Villemoes __be32 tdp; /* Internal */ 27d5b4a762SRasmus Villemoes __be16 tbptr; /* Internal */ 28d5b4a762SRasmus Villemoes __be16 tbc; /* Internal */ 29d5b4a762SRasmus Villemoes __be32 txtmp; /* Internal */ 30d5b4a762SRasmus Villemoes __be32 res; /* Tx temp. */ 31d5b4a762SRasmus Villemoes __be16 rpbase; /* Relocation pointer (CPM1 only) */ 32d5b4a762SRasmus Villemoes __be16 res1; /* Reserved */ 33d5b4a762SRasmus Villemoes }; 34d5b4a762SRasmus Villemoes 35d5b4a762SRasmus Villemoes /* 36d5b4a762SRasmus Villemoes * USB Controller pram common to QE and CPM. 37d5b4a762SRasmus Villemoes */ 38d5b4a762SRasmus Villemoes struct usb_ctlr { 39d5b4a762SRasmus Villemoes u8 usb_usmod; 40d5b4a762SRasmus Villemoes u8 usb_usadr; 41d5b4a762SRasmus Villemoes u8 usb_uscom; 42d5b4a762SRasmus Villemoes u8 res1[1]; 43d5b4a762SRasmus Villemoes __be16 usb_usep[4]; 44d5b4a762SRasmus Villemoes u8 res2[4]; 45d5b4a762SRasmus Villemoes __be16 usb_usber; 46d5b4a762SRasmus Villemoes u8 res3[2]; 47d5b4a762SRasmus Villemoes __be16 usb_usbmr; 48d5b4a762SRasmus Villemoes u8 res4[1]; 49d5b4a762SRasmus Villemoes u8 usb_usbs; 50d5b4a762SRasmus Villemoes /* Fields down below are QE-only */ 51d5b4a762SRasmus Villemoes __be16 usb_ussft; 52d5b4a762SRasmus Villemoes u8 res5[2]; 53d5b4a762SRasmus Villemoes __be16 usb_usfrn; 54d5b4a762SRasmus Villemoes u8 res6[0x22]; 55d5b4a762SRasmus Villemoes } __attribute__ ((packed)); 56d5b4a762SRasmus Villemoes 57d5b4a762SRasmus Villemoes /* 58d5b4a762SRasmus Villemoes * Function code bits, usually generic to devices. 59d5b4a762SRasmus Villemoes */ 60d5b4a762SRasmus Villemoes #ifdef CONFIG_CPM1 61d5b4a762SRasmus Villemoes #define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */ 62d5b4a762SRasmus Villemoes #define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */ 63d5b4a762SRasmus Villemoes #define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */ 64d5b4a762SRasmus Villemoes #define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */ 65d5b4a762SRasmus Villemoes #else 66d5b4a762SRasmus Villemoes #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ 67d5b4a762SRasmus Villemoes #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ 68d5b4a762SRasmus Villemoes #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ 69d5b4a762SRasmus Villemoes #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ 70d5b4a762SRasmus Villemoes #endif 71d5b4a762SRasmus Villemoes #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ 72d5b4a762SRasmus Villemoes 73d5b4a762SRasmus Villemoes /* Opcodes common to CPM1 and CPM2 74d5b4a762SRasmus Villemoes */ 75d5b4a762SRasmus Villemoes #define CPM_CR_INIT_TRX ((ushort)0x0000) 76d5b4a762SRasmus Villemoes #define CPM_CR_INIT_RX ((ushort)0x0001) 77d5b4a762SRasmus Villemoes #define CPM_CR_INIT_TX ((ushort)0x0002) 78d5b4a762SRasmus Villemoes #define CPM_CR_HUNT_MODE ((ushort)0x0003) 79d5b4a762SRasmus Villemoes #define CPM_CR_STOP_TX ((ushort)0x0004) 80d5b4a762SRasmus Villemoes #define CPM_CR_GRA_STOP_TX ((ushort)0x0005) 81d5b4a762SRasmus Villemoes #define CPM_CR_RESTART_TX ((ushort)0x0006) 82d5b4a762SRasmus Villemoes #define CPM_CR_CLOSE_RX_BD ((ushort)0x0007) 83d5b4a762SRasmus Villemoes #define CPM_CR_SET_GADDR ((ushort)0x0008) 84d5b4a762SRasmus Villemoes #define CPM_CR_SET_TIMER ((ushort)0x0008) 85d5b4a762SRasmus Villemoes #define CPM_CR_STOP_IDMA ((ushort)0x000b) 86d5b4a762SRasmus Villemoes 87d5b4a762SRasmus Villemoes /* Buffer descriptors used by many of the CPM protocols. */ 88d5b4a762SRasmus Villemoes typedef struct cpm_buf_desc { 89d5b4a762SRasmus Villemoes ushort cbd_sc; /* Status and Control */ 90d5b4a762SRasmus Villemoes ushort cbd_datlen; /* Data length in buffer */ 91d5b4a762SRasmus Villemoes uint cbd_bufaddr; /* Buffer address in host memory */ 92d5b4a762SRasmus Villemoes } cbd_t; 93d5b4a762SRasmus Villemoes 94d5b4a762SRasmus Villemoes /* Buffer descriptor control/status used by serial 95d5b4a762SRasmus Villemoes */ 96d5b4a762SRasmus Villemoes 97d5b4a762SRasmus Villemoes #define BD_SC_EMPTY (0x8000) /* Receive is empty */ 98d5b4a762SRasmus Villemoes #define BD_SC_READY (0x8000) /* Transmit is ready */ 99d5b4a762SRasmus Villemoes #define BD_SC_WRAP (0x2000) /* Last buffer descriptor */ 100d5b4a762SRasmus Villemoes #define BD_SC_INTRPT (0x1000) /* Interrupt on change */ 101d5b4a762SRasmus Villemoes #define BD_SC_LAST (0x0800) /* Last buffer in frame */ 102d5b4a762SRasmus Villemoes #define BD_SC_TC (0x0400) /* Transmit CRC */ 103d5b4a762SRasmus Villemoes #define BD_SC_CM (0x0200) /* Continuous mode */ 104d5b4a762SRasmus Villemoes #define BD_SC_ID (0x0100) /* Rec'd too many idles */ 105d5b4a762SRasmus Villemoes #define BD_SC_P (0x0100) /* xmt preamble */ 106d5b4a762SRasmus Villemoes #define BD_SC_BR (0x0020) /* Break received */ 107d5b4a762SRasmus Villemoes #define BD_SC_FR (0x0010) /* Framing error */ 108d5b4a762SRasmus Villemoes #define BD_SC_PR (0x0008) /* Parity error */ 109d5b4a762SRasmus Villemoes #define BD_SC_NAK (0x0004) /* NAK - did not respond */ 110d5b4a762SRasmus Villemoes #define BD_SC_OV (0x0002) /* Overrun */ 111d5b4a762SRasmus Villemoes #define BD_SC_UN (0x0002) /* Underrun */ 112d5b4a762SRasmus Villemoes #define BD_SC_CD (0x0001) /* */ 113d5b4a762SRasmus Villemoes #define BD_SC_CL (0x0001) /* Collision */ 114d5b4a762SRasmus Villemoes 115d5b4a762SRasmus Villemoes /* Buffer descriptor control/status used by Ethernet receive. 116d5b4a762SRasmus Villemoes * Common to SCC and FCC. 117d5b4a762SRasmus Villemoes */ 118d5b4a762SRasmus Villemoes #define BD_ENET_RX_EMPTY (0x8000) 119d5b4a762SRasmus Villemoes #define BD_ENET_RX_WRAP (0x2000) 120d5b4a762SRasmus Villemoes #define BD_ENET_RX_INTR (0x1000) 121d5b4a762SRasmus Villemoes #define BD_ENET_RX_LAST (0x0800) 122d5b4a762SRasmus Villemoes #define BD_ENET_RX_FIRST (0x0400) 123d5b4a762SRasmus Villemoes #define BD_ENET_RX_MISS (0x0100) 124d5b4a762SRasmus Villemoes #define BD_ENET_RX_BC (0x0080) /* FCC Only */ 125d5b4a762SRasmus Villemoes #define BD_ENET_RX_MC (0x0040) /* FCC Only */ 126d5b4a762SRasmus Villemoes #define BD_ENET_RX_LG (0x0020) 127d5b4a762SRasmus Villemoes #define BD_ENET_RX_NO (0x0010) 128d5b4a762SRasmus Villemoes #define BD_ENET_RX_SH (0x0008) 129d5b4a762SRasmus Villemoes #define BD_ENET_RX_CR (0x0004) 130d5b4a762SRasmus Villemoes #define BD_ENET_RX_OV (0x0002) 131d5b4a762SRasmus Villemoes #define BD_ENET_RX_CL (0x0001) 132d5b4a762SRasmus Villemoes #define BD_ENET_RX_STATS (0x01ff) /* All status bits */ 133d5b4a762SRasmus Villemoes 134d5b4a762SRasmus Villemoes /* Buffer descriptor control/status used by Ethernet transmit. 135d5b4a762SRasmus Villemoes * Common to SCC and FCC. 136d5b4a762SRasmus Villemoes */ 137d5b4a762SRasmus Villemoes #define BD_ENET_TX_READY (0x8000) 138d5b4a762SRasmus Villemoes #define BD_ENET_TX_PAD (0x4000) 139d5b4a762SRasmus Villemoes #define BD_ENET_TX_WRAP (0x2000) 140d5b4a762SRasmus Villemoes #define BD_ENET_TX_INTR (0x1000) 141d5b4a762SRasmus Villemoes #define BD_ENET_TX_LAST (0x0800) 142d5b4a762SRasmus Villemoes #define BD_ENET_TX_TC (0x0400) 143d5b4a762SRasmus Villemoes #define BD_ENET_TX_DEF (0x0200) 144d5b4a762SRasmus Villemoes #define BD_ENET_TX_HB (0x0100) 145d5b4a762SRasmus Villemoes #define BD_ENET_TX_LC (0x0080) 146d5b4a762SRasmus Villemoes #define BD_ENET_TX_RL (0x0040) 147d5b4a762SRasmus Villemoes #define BD_ENET_TX_RCMASK (0x003c) 148d5b4a762SRasmus Villemoes #define BD_ENET_TX_UN (0x0002) 149d5b4a762SRasmus Villemoes #define BD_ENET_TX_CSL (0x0001) 150d5b4a762SRasmus Villemoes #define BD_ENET_TX_STATS (0x03ff) /* All status bits */ 151d5b4a762SRasmus Villemoes 152d5b4a762SRasmus Villemoes /* Buffer descriptor control/status used by Transparent mode SCC. 153d5b4a762SRasmus Villemoes */ 154d5b4a762SRasmus Villemoes #define BD_SCC_TX_LAST (0x0800) 155d5b4a762SRasmus Villemoes 156d5b4a762SRasmus Villemoes /* Buffer descriptor control/status used by I2C. 157d5b4a762SRasmus Villemoes */ 158d5b4a762SRasmus Villemoes #define BD_I2C_START (0x0400) 159d5b4a762SRasmus Villemoes 160d5b4a762SRasmus Villemoes #ifdef CONFIG_CPM 161d5b4a762SRasmus Villemoes int cpm_command(u32 command, u8 opcode); 162d5b4a762SRasmus Villemoes #else cpm_command(u32 command,u8 opcode)163d5b4a762SRasmus Villemoesstatic inline int cpm_command(u32 command, u8 opcode) 164d5b4a762SRasmus Villemoes { 165d5b4a762SRasmus Villemoes return -ENOSYS; 166d5b4a762SRasmus Villemoes } 167d5b4a762SRasmus Villemoes #endif /* CONFIG_CPM */ 168d5b4a762SRasmus Villemoes 169d5b4a762SRasmus Villemoes int cpm2_gpiochip_add32(struct device *dev); 170d5b4a762SRasmus Villemoes 171d5b4a762SRasmus Villemoes #endif 172