1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Microchip SAMA7 UDDR Controller and DDR3 PHY Controller registers offsets 4 * and bit definitions. 5 * 6 * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries 7 * 8 * Author: Claudu Beznea <claudiu.beznea@microchip.com> 9 */ 10 11 #ifndef __SAMA7_DDR_H__ 12 #define __SAMA7_DDR_H__ 13 14 #ifdef CONFIG_SOC_SAMA7 15 16 /* DDR3PHY */ 17 #define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */ 18 #define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */ 19 #define DDR3PHY_PIR_ITMSRST (1 << 4) /* Interface Timing Module Soft Reset */ 20 #define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */ 21 #define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */ 22 #define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */ 23 24 #define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */ 25 #define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */ 26 #define DDR3PHY_PGCR_CKDV0 (1 << 12) /* CK Disable Value */ 27 28 #define DDR3PHY_PGSR (0x0C) /* DDR3PHY PHY General Status Register */ 29 #define DDR3PHY_PGSR_IDONE (1 << 0) /* Initialization Done */ 30 31 #define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */ 32 #define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */ 33 #define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */ 34 #define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */ 35 36 #define DDR3PHY_DXCCR (0x28) /* DDR3PHY DATX8 Common Configuration Register */ 37 #define DDR3PHY_DXCCR_DXPDR (1 << 3) /* Data Power Down Receiver */ 38 39 #define DDR3PHY_DSGCR (0x2C) /* DDR3PHY DDR System General Configuration Register */ 40 #define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */ 41 42 #define DDR3PHY_ZQ0SR0 (0x188) /* ZQ status register 0 */ 43 44 /* UDDRC */ 45 #define UDDRC_STAT (0x04) /* UDDRC Operating Mode Status Register */ 46 #define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */ 47 #define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PHY Master Request */ 48 #define UDDRC_STAT_SELFREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused solely under Automatic Self-refresh control */ 49 #define UDDRC_STAT_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by Automatic Self-refresh only */ 50 #define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */ 51 #define UDDRC_STAT_OPMODE_INIT (0x0 << 0) /* Init */ 52 #define UDDRC_STAT_OPMODE_NORMAL (0x1 << 0) /* Normal */ 53 #define UDDRC_STAT_OPMODE_PWRDOWN (0x2 << 0) /* Power-down */ 54 #define UDDRC_STAT_OPMODE_SELF_REFRESH (0x3 << 0) /* Self-refresh */ 55 #define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */ 56 57 #define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */ 58 #define UDDRC_PWRCTRL_SELFREF_SW (1 << 5) /* Software self-refresh */ 59 60 #define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */ 61 #define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) /* PHY initialization complete enable signal */ 62 63 #define UDDRC_SWCTRL (0x320) /* UDDRC Software Register Programming Control Enable */ 64 #define UDDRC_SWCTRL_SW_DONE (1 << 0) /* Enable quasi-dynamic register programming outside reset */ 65 66 #define UDDRC_SWSTAT (0x324) /* UDDRC Software Register Programming Control Status */ 67 #define UDDRC_SWSTAT_SW_DONE_ACK (1 << 0) /* Register programming done */ 68 69 #define UDDRC_PSTAT (0x3FC) /* UDDRC Port Status Register */ 70 #define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */ 71 72 #define UDDRC_PCTRL_0 (0x490) /* UDDRC Port 0 Control Register */ 73 #define UDDRC_PCTRL_1 (0x540) /* UDDRC Port 1 Control Register */ 74 #define UDDRC_PCTRL_2 (0x5F0) /* UDDRC Port 2 Control Register */ 75 #define UDDRC_PCTRL_3 (0x6A0) /* UDDRC Port 3 Control Register */ 76 #define UDDRC_PCTRL_4 (0x750) /* UDDRC Port 4 Control Register */ 77 78 #endif /* CONFIG_SOC_SAMA7 */ 79 80 #endif /* __SAMA7_DDR_H__ */ 81