1 /* 2 * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef __SOC_ARC_TIMERS_H 10 #define __SOC_ARC_TIMERS_H 11 12 #include <soc/arc/aux.h> 13 14 /* Timer related Aux registers */ 15 #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ 16 #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ 17 #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ 18 #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */ 19 #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ 20 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ 21 22 /* CTRL reg bits */ 23 #define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */ 24 #define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ 25 26 #define ARC_TIMERN_MAX 0xFFFFFFFF 27 28 #define ARC_REG_TIMERS_BCR 0x75 29 30 struct bcr_timer { 31 #ifdef CONFIG_CPU_BIG_ENDIAN 32 unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8; 33 #else 34 unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15; 35 #endif 36 }; 37 38 #endif 39