1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #ifndef _MANA_H 5 #define _MANA_H 6 7 #include <net/xdp.h> 8 9 #include "gdma.h" 10 #include "hw_channel.h" 11 12 /* Microsoft Azure Network Adapter (MANA)'s definitions 13 * 14 * Structures labeled with "HW DATA" are exchanged with the hardware. All of 15 * them are naturally aligned and hence don't need __packed. 16 */ 17 18 /* MANA protocol version */ 19 #define MANA_MAJOR_VERSION 0 20 #define MANA_MINOR_VERSION 1 21 #define MANA_MICRO_VERSION 1 22 23 typedef u64 mana_handle_t; 24 #define INVALID_MANA_HANDLE ((mana_handle_t)-1) 25 26 enum TRI_STATE { 27 TRI_STATE_UNKNOWN = -1, 28 TRI_STATE_FALSE = 0, 29 TRI_STATE_TRUE = 1 30 }; 31 32 /* Number of entries for hardware indirection table must be in power of 2 */ 33 #define MANA_INDIRECT_TABLE_SIZE 64 34 #define MANA_INDIRECT_TABLE_MASK (MANA_INDIRECT_TABLE_SIZE - 1) 35 36 /* The Toeplitz hash key's length in bytes: should be multiple of 8 */ 37 #define MANA_HASH_KEY_SIZE 40 38 39 #define COMP_ENTRY_SIZE 64 40 41 #define RX_BUFFERS_PER_QUEUE 512 42 43 #define MAX_SEND_BUFFERS_PER_QUEUE 256 44 45 #define EQ_SIZE (8 * PAGE_SIZE) 46 #define LOG2_EQ_THROTTLE 3 47 48 #define MAX_PORTS_IN_MANA_DEV 256 49 50 /* Update this count whenever the respective structures are changed */ 51 #define MANA_STATS_RX_COUNT 5 52 #define MANA_STATS_TX_COUNT 11 53 54 struct mana_stats_rx { 55 u64 packets; 56 u64 bytes; 57 u64 xdp_drop; 58 u64 xdp_tx; 59 u64 xdp_redirect; 60 struct u64_stats_sync syncp; 61 }; 62 63 struct mana_stats_tx { 64 u64 packets; 65 u64 bytes; 66 u64 xdp_xmit; 67 u64 tso_packets; 68 u64 tso_bytes; 69 u64 tso_inner_packets; 70 u64 tso_inner_bytes; 71 u64 short_pkt_fmt; 72 u64 long_pkt_fmt; 73 u64 csum_partial; 74 u64 mana_map_err; 75 struct u64_stats_sync syncp; 76 }; 77 78 struct mana_txq { 79 struct gdma_queue *gdma_sq; 80 81 union { 82 u32 gdma_txq_id; 83 struct { 84 u32 reserved1 : 10; 85 u32 vsq_frame : 14; 86 u32 reserved2 : 8; 87 }; 88 }; 89 90 u16 vp_offset; 91 92 struct net_device *ndev; 93 94 /* The SKBs are sent to the HW and we are waiting for the CQEs. */ 95 struct sk_buff_head pending_skbs; 96 struct netdev_queue *net_txq; 97 98 atomic_t pending_sends; 99 100 struct mana_stats_tx stats; 101 }; 102 103 /* skb data and frags dma mappings */ 104 struct mana_skb_head { 105 /* GSO pkts may have 2 SGEs for the linear part*/ 106 dma_addr_t dma_handle[MAX_SKB_FRAGS + 2]; 107 108 u32 size[MAX_SKB_FRAGS + 2]; 109 }; 110 111 #define MANA_HEADROOM sizeof(struct mana_skb_head) 112 113 enum mana_tx_pkt_format { 114 MANA_SHORT_PKT_FMT = 0, 115 MANA_LONG_PKT_FMT = 1, 116 }; 117 118 struct mana_tx_short_oob { 119 u32 pkt_fmt : 2; 120 u32 is_outer_ipv4 : 1; 121 u32 is_outer_ipv6 : 1; 122 u32 comp_iphdr_csum : 1; 123 u32 comp_tcp_csum : 1; 124 u32 comp_udp_csum : 1; 125 u32 supress_txcqe_gen : 1; 126 u32 vcq_num : 24; 127 128 u32 trans_off : 10; /* Transport header offset */ 129 u32 vsq_frame : 14; 130 u32 short_vp_offset : 8; 131 }; /* HW DATA */ 132 133 struct mana_tx_long_oob { 134 u32 is_encap : 1; 135 u32 inner_is_ipv6 : 1; 136 u32 inner_tcp_opt : 1; 137 u32 inject_vlan_pri_tag : 1; 138 u32 reserved1 : 12; 139 u32 pcp : 3; /* 802.1Q */ 140 u32 dei : 1; /* 802.1Q */ 141 u32 vlan_id : 12; /* 802.1Q */ 142 143 u32 inner_frame_offset : 10; 144 u32 inner_ip_rel_offset : 6; 145 u32 long_vp_offset : 12; 146 u32 reserved2 : 4; 147 148 u32 reserved3; 149 u32 reserved4; 150 }; /* HW DATA */ 151 152 struct mana_tx_oob { 153 struct mana_tx_short_oob s_oob; 154 struct mana_tx_long_oob l_oob; 155 }; /* HW DATA */ 156 157 enum mana_cq_type { 158 MANA_CQ_TYPE_RX, 159 MANA_CQ_TYPE_TX, 160 }; 161 162 enum mana_cqe_type { 163 CQE_INVALID = 0, 164 CQE_RX_OKAY = 1, 165 CQE_RX_COALESCED_4 = 2, 166 CQE_RX_OBJECT_FENCE = 3, 167 CQE_RX_TRUNCATED = 4, 168 169 CQE_TX_OKAY = 32, 170 CQE_TX_SA_DROP = 33, 171 CQE_TX_MTU_DROP = 34, 172 CQE_TX_INVALID_OOB = 35, 173 CQE_TX_INVALID_ETH_TYPE = 36, 174 CQE_TX_HDR_PROCESSING_ERROR = 37, 175 CQE_TX_VF_DISABLED = 38, 176 CQE_TX_VPORT_IDX_OUT_OF_RANGE = 39, 177 CQE_TX_VPORT_DISABLED = 40, 178 CQE_TX_VLAN_TAGGING_VIOLATION = 41, 179 }; 180 181 #define MANA_CQE_COMPLETION 1 182 183 struct mana_cqe_header { 184 u32 cqe_type : 6; 185 u32 client_type : 2; 186 u32 vendor_err : 24; 187 }; /* HW DATA */ 188 189 /* NDIS HASH Types */ 190 #define NDIS_HASH_IPV4 BIT(0) 191 #define NDIS_HASH_TCP_IPV4 BIT(1) 192 #define NDIS_HASH_UDP_IPV4 BIT(2) 193 #define NDIS_HASH_IPV6 BIT(3) 194 #define NDIS_HASH_TCP_IPV6 BIT(4) 195 #define NDIS_HASH_UDP_IPV6 BIT(5) 196 #define NDIS_HASH_IPV6_EX BIT(6) 197 #define NDIS_HASH_TCP_IPV6_EX BIT(7) 198 #define NDIS_HASH_UDP_IPV6_EX BIT(8) 199 200 #define MANA_HASH_L3 (NDIS_HASH_IPV4 | NDIS_HASH_IPV6 | NDIS_HASH_IPV6_EX) 201 #define MANA_HASH_L4 \ 202 (NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4 | NDIS_HASH_TCP_IPV6 | \ 203 NDIS_HASH_UDP_IPV6 | NDIS_HASH_TCP_IPV6_EX | NDIS_HASH_UDP_IPV6_EX) 204 205 struct mana_rxcomp_perpkt_info { 206 u32 pkt_len : 16; 207 u32 reserved1 : 16; 208 u32 reserved2; 209 u32 pkt_hash; 210 }; /* HW DATA */ 211 212 #define MANA_RXCOMP_OOB_NUM_PPI 4 213 214 /* Receive completion OOB */ 215 struct mana_rxcomp_oob { 216 struct mana_cqe_header cqe_hdr; 217 218 u32 rx_vlan_id : 12; 219 u32 rx_vlantag_present : 1; 220 u32 rx_outer_iphdr_csum_succeed : 1; 221 u32 rx_outer_iphdr_csum_fail : 1; 222 u32 reserved1 : 1; 223 u32 rx_hashtype : 9; 224 u32 rx_iphdr_csum_succeed : 1; 225 u32 rx_iphdr_csum_fail : 1; 226 u32 rx_tcp_csum_succeed : 1; 227 u32 rx_tcp_csum_fail : 1; 228 u32 rx_udp_csum_succeed : 1; 229 u32 rx_udp_csum_fail : 1; 230 u32 reserved2 : 1; 231 232 struct mana_rxcomp_perpkt_info ppi[MANA_RXCOMP_OOB_NUM_PPI]; 233 234 u32 rx_wqe_offset; 235 }; /* HW DATA */ 236 237 struct mana_tx_comp_oob { 238 struct mana_cqe_header cqe_hdr; 239 240 u32 tx_data_offset; 241 242 u32 tx_sgl_offset : 5; 243 u32 tx_wqe_offset : 27; 244 245 u32 reserved[12]; 246 }; /* HW DATA */ 247 248 struct mana_rxq; 249 250 #define CQE_POLLING_BUFFER 512 251 252 struct mana_cq { 253 struct gdma_queue *gdma_cq; 254 255 /* Cache the CQ id (used to verify if each CQE comes to the right CQ. */ 256 u32 gdma_id; 257 258 /* Type of the CQ: TX or RX */ 259 enum mana_cq_type type; 260 261 /* Pointer to the mana_rxq that is pushing RX CQEs to the queue. 262 * Only and must be non-NULL if type is MANA_CQ_TYPE_RX. 263 */ 264 struct mana_rxq *rxq; 265 266 /* Pointer to the mana_txq that is pushing TX CQEs to the queue. 267 * Only and must be non-NULL if type is MANA_CQ_TYPE_TX. 268 */ 269 struct mana_txq *txq; 270 271 /* Buffer which the CQ handler can copy the CQE's into. */ 272 struct gdma_comp gdma_comp_buf[CQE_POLLING_BUFFER]; 273 274 /* NAPI data */ 275 struct napi_struct napi; 276 int work_done; 277 int budget; 278 }; 279 280 struct mana_recv_buf_oob { 281 /* A valid GDMA work request representing the data buffer. */ 282 struct gdma_wqe_request wqe_req; 283 284 void *buf_va; 285 bool from_pool; /* allocated from a page pool */ 286 287 /* SGL of the buffer going to be sent has part of the work request. */ 288 u32 num_sge; 289 struct gdma_sge sgl[MAX_RX_WQE_SGL_ENTRIES]; 290 291 /* Required to store the result of mana_gd_post_work_request. 292 * gdma_posted_wqe_info.wqe_size_in_bu is required for progressing the 293 * work queue when the WQE is consumed. 294 */ 295 struct gdma_posted_wqe_info wqe_inf; 296 }; 297 298 #define MANA_RXBUF_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) \ 299 + ETH_HLEN) 300 301 #define MANA_XDP_MTU_MAX (PAGE_SIZE - MANA_RXBUF_PAD - XDP_PACKET_HEADROOM) 302 303 struct mana_rxq { 304 struct gdma_queue *gdma_rq; 305 /* Cache the gdma receive queue id */ 306 u32 gdma_id; 307 308 /* Index of RQ in the vPort, not gdma receive queue id */ 309 u32 rxq_idx; 310 311 u32 datasize; 312 u32 alloc_size; 313 u32 headroom; 314 315 mana_handle_t rxobj; 316 317 struct mana_cq rx_cq; 318 319 struct completion fence_event; 320 321 struct net_device *ndev; 322 323 /* Total number of receive buffers to be allocated */ 324 u32 num_rx_buf; 325 326 u32 buf_index; 327 328 struct mana_stats_rx stats; 329 330 struct bpf_prog __rcu *bpf_prog; 331 struct xdp_rxq_info xdp_rxq; 332 void *xdp_save_va; /* for reusing */ 333 bool xdp_flush; 334 int xdp_rc; /* XDP redirect return code */ 335 336 struct page_pool *page_pool; 337 338 /* MUST BE THE LAST MEMBER: 339 * Each receive buffer has an associated mana_recv_buf_oob. 340 */ 341 struct mana_recv_buf_oob rx_oobs[]; 342 }; 343 344 struct mana_tx_qp { 345 struct mana_txq txq; 346 347 struct mana_cq tx_cq; 348 349 mana_handle_t tx_object; 350 }; 351 352 struct mana_ethtool_stats { 353 u64 stop_queue; 354 u64 wake_queue; 355 u64 hc_tx_bytes; 356 u64 hc_tx_ucast_pkts; 357 u64 hc_tx_ucast_bytes; 358 u64 hc_tx_bcast_pkts; 359 u64 hc_tx_bcast_bytes; 360 u64 hc_tx_mcast_pkts; 361 u64 hc_tx_mcast_bytes; 362 u64 tx_cqe_err; 363 u64 tx_cqe_unknown_type; 364 u64 rx_coalesced_err; 365 u64 rx_cqe_unknown_type; 366 }; 367 368 struct mana_context { 369 struct gdma_dev *gdma_dev; 370 371 u16 num_ports; 372 373 struct mana_eq *eqs; 374 375 struct net_device *ports[MAX_PORTS_IN_MANA_DEV]; 376 }; 377 378 struct mana_port_context { 379 struct mana_context *ac; 380 struct net_device *ndev; 381 382 u8 mac_addr[ETH_ALEN]; 383 384 enum TRI_STATE rss_state; 385 386 mana_handle_t default_rxobj; 387 bool tx_shortform_allowed; 388 u16 tx_vp_offset; 389 390 struct mana_tx_qp *tx_qp; 391 392 /* Indirection Table for RX & TX. The values are queue indexes */ 393 u32 indir_table[MANA_INDIRECT_TABLE_SIZE]; 394 395 /* Indirection table containing RxObject Handles */ 396 mana_handle_t rxobj_table[MANA_INDIRECT_TABLE_SIZE]; 397 398 /* Hash key used by the NIC */ 399 u8 hashkey[MANA_HASH_KEY_SIZE]; 400 401 /* This points to an array of num_queues of RQ pointers. */ 402 struct mana_rxq **rxqs; 403 404 /* pre-allocated rx buffer array */ 405 void **rxbufs_pre; 406 dma_addr_t *das_pre; 407 int rxbpre_total; 408 u32 rxbpre_datasize; 409 u32 rxbpre_alloc_size; 410 u32 rxbpre_headroom; 411 412 struct bpf_prog *bpf_prog; 413 414 /* Create num_queues EQs, SQs, SQ-CQs, RQs and RQ-CQs, respectively. */ 415 unsigned int max_queues; 416 unsigned int num_queues; 417 418 mana_handle_t port_handle; 419 mana_handle_t pf_filter_handle; 420 421 /* Mutex for sharing access to vport_use_count */ 422 struct mutex vport_mutex; 423 int vport_use_count; 424 425 u16 port_idx; 426 427 bool port_is_up; 428 bool port_st_save; /* Saved port state */ 429 430 struct mana_ethtool_stats eth_stats; 431 }; 432 433 netdev_tx_t mana_start_xmit(struct sk_buff *skb, struct net_device *ndev); 434 int mana_config_rss(struct mana_port_context *ac, enum TRI_STATE rx, 435 bool update_hash, bool update_tab); 436 437 int mana_alloc_queues(struct net_device *ndev); 438 int mana_attach(struct net_device *ndev); 439 int mana_detach(struct net_device *ndev, bool from_close); 440 441 int mana_probe(struct gdma_dev *gd, bool resuming); 442 void mana_remove(struct gdma_dev *gd, bool suspending); 443 444 void mana_xdp_tx(struct sk_buff *skb, struct net_device *ndev); 445 int mana_xdp_xmit(struct net_device *ndev, int n, struct xdp_frame **frames, 446 u32 flags); 447 u32 mana_run_xdp(struct net_device *ndev, struct mana_rxq *rxq, 448 struct xdp_buff *xdp, void *buf_va, uint pkt_len); 449 struct bpf_prog *mana_xdp_get(struct mana_port_context *apc); 450 void mana_chn_setxdp(struct mana_port_context *apc, struct bpf_prog *prog); 451 int mana_bpf(struct net_device *ndev, struct netdev_bpf *bpf); 452 void mana_query_gf_stats(struct mana_port_context *apc); 453 454 extern const struct ethtool_ops mana_ethtool_ops; 455 456 /* A CQ can be created not associated with any EQ */ 457 #define GDMA_CQ_NO_EQ 0xffff 458 459 struct mana_obj_spec { 460 u32 queue_index; 461 u64 gdma_region; 462 u32 queue_size; 463 u32 attached_eq; 464 u32 modr_ctx_id; 465 }; 466 467 enum mana_command_code { 468 MANA_QUERY_DEV_CONFIG = 0x20001, 469 MANA_QUERY_GF_STAT = 0x20002, 470 MANA_CONFIG_VPORT_TX = 0x20003, 471 MANA_CREATE_WQ_OBJ = 0x20004, 472 MANA_DESTROY_WQ_OBJ = 0x20005, 473 MANA_FENCE_RQ = 0x20006, 474 MANA_CONFIG_VPORT_RX = 0x20007, 475 MANA_QUERY_VPORT_CONFIG = 0x20008, 476 477 /* Privileged commands for the PF mode */ 478 MANA_REGISTER_FILTER = 0x28000, 479 MANA_DEREGISTER_FILTER = 0x28001, 480 MANA_REGISTER_HW_PORT = 0x28003, 481 MANA_DEREGISTER_HW_PORT = 0x28004, 482 }; 483 484 /* Query Device Configuration */ 485 struct mana_query_device_cfg_req { 486 struct gdma_req_hdr hdr; 487 488 /* MANA Nic Driver Capability flags */ 489 u64 mn_drv_cap_flags1; 490 u64 mn_drv_cap_flags2; 491 u64 mn_drv_cap_flags3; 492 u64 mn_drv_cap_flags4; 493 494 u32 proto_major_ver; 495 u32 proto_minor_ver; 496 u32 proto_micro_ver; 497 498 u32 reserved; 499 }; /* HW DATA */ 500 501 struct mana_query_device_cfg_resp { 502 struct gdma_resp_hdr hdr; 503 504 u64 pf_cap_flags1; 505 u64 pf_cap_flags2; 506 u64 pf_cap_flags3; 507 u64 pf_cap_flags4; 508 509 u16 max_num_vports; 510 u16 reserved; 511 u32 max_num_eqs; 512 513 /* response v2: */ 514 u16 adapter_mtu; 515 u16 reserved2; 516 u32 reserved3; 517 }; /* HW DATA */ 518 519 /* Query vPort Configuration */ 520 struct mana_query_vport_cfg_req { 521 struct gdma_req_hdr hdr; 522 u32 vport_index; 523 }; /* HW DATA */ 524 525 struct mana_query_vport_cfg_resp { 526 struct gdma_resp_hdr hdr; 527 u32 max_num_sq; 528 u32 max_num_rq; 529 u32 num_indirection_ent; 530 u32 reserved1; 531 u8 mac_addr[6]; 532 u8 reserved2[2]; 533 mana_handle_t vport; 534 }; /* HW DATA */ 535 536 /* Configure vPort */ 537 struct mana_config_vport_req { 538 struct gdma_req_hdr hdr; 539 mana_handle_t vport; 540 u32 pdid; 541 u32 doorbell_pageid; 542 }; /* HW DATA */ 543 544 struct mana_config_vport_resp { 545 struct gdma_resp_hdr hdr; 546 u16 tx_vport_offset; 547 u8 short_form_allowed; 548 u8 reserved; 549 }; /* HW DATA */ 550 551 /* Create WQ Object */ 552 struct mana_create_wqobj_req { 553 struct gdma_req_hdr hdr; 554 mana_handle_t vport; 555 u32 wq_type; 556 u32 reserved; 557 u64 wq_gdma_region; 558 u64 cq_gdma_region; 559 u32 wq_size; 560 u32 cq_size; 561 u32 cq_moderation_ctx_id; 562 u32 cq_parent_qid; 563 }; /* HW DATA */ 564 565 struct mana_create_wqobj_resp { 566 struct gdma_resp_hdr hdr; 567 u32 wq_id; 568 u32 cq_id; 569 mana_handle_t wq_obj; 570 }; /* HW DATA */ 571 572 /* Destroy WQ Object */ 573 struct mana_destroy_wqobj_req { 574 struct gdma_req_hdr hdr; 575 u32 wq_type; 576 u32 reserved; 577 mana_handle_t wq_obj_handle; 578 }; /* HW DATA */ 579 580 struct mana_destroy_wqobj_resp { 581 struct gdma_resp_hdr hdr; 582 }; /* HW DATA */ 583 584 /* Fence RQ */ 585 struct mana_fence_rq_req { 586 struct gdma_req_hdr hdr; 587 mana_handle_t wq_obj_handle; 588 }; /* HW DATA */ 589 590 struct mana_fence_rq_resp { 591 struct gdma_resp_hdr hdr; 592 }; /* HW DATA */ 593 594 /* Query stats RQ */ 595 struct mana_query_gf_stat_req { 596 struct gdma_req_hdr hdr; 597 u64 req_stats; 598 }; /* HW DATA */ 599 600 struct mana_query_gf_stat_resp { 601 struct gdma_resp_hdr hdr; 602 u64 reported_stats; 603 /* rx errors/discards */ 604 u64 discard_rx_nowqe; 605 u64 err_rx_vport_disabled; 606 /* rx bytes/packets */ 607 u64 hc_rx_bytes; 608 u64 hc_rx_ucast_pkts; 609 u64 hc_rx_ucast_bytes; 610 u64 hc_rx_bcast_pkts; 611 u64 hc_rx_bcast_bytes; 612 u64 hc_rx_mcast_pkts; 613 u64 hc_rx_mcast_bytes; 614 /* tx errors */ 615 u64 err_tx_gf_disabled; 616 u64 err_tx_vport_disabled; 617 u64 err_tx_inval_vport_offset_pkt; 618 u64 err_tx_vlan_enforcement; 619 u64 err_tx_ethtype_enforcement; 620 u64 err_tx_SA_enforecement; 621 u64 err_tx_SQPDID_enforcement; 622 u64 err_tx_CQPDID_enforcement; 623 u64 err_tx_mtu_violation; 624 u64 err_tx_inval_oob; 625 /* tx bytes/packets */ 626 u64 hc_tx_bytes; 627 u64 hc_tx_ucast_pkts; 628 u64 hc_tx_ucast_bytes; 629 u64 hc_tx_bcast_pkts; 630 u64 hc_tx_bcast_bytes; 631 u64 hc_tx_mcast_pkts; 632 u64 hc_tx_mcast_bytes; 633 /* tx error */ 634 u64 err_tx_gdma; 635 }; /* HW DATA */ 636 637 /* Configure vPort Rx Steering */ 638 struct mana_cfg_rx_steer_req_v2 { 639 struct gdma_req_hdr hdr; 640 mana_handle_t vport; 641 u16 num_indir_entries; 642 u16 indir_tab_offset; 643 u32 rx_enable; 644 u32 rss_enable; 645 u8 update_default_rxobj; 646 u8 update_hashkey; 647 u8 update_indir_tab; 648 u8 reserved; 649 mana_handle_t default_rxobj; 650 u8 hashkey[MANA_HASH_KEY_SIZE]; 651 u8 cqe_coalescing_enable; 652 u8 reserved2[7]; 653 }; /* HW DATA */ 654 655 struct mana_cfg_rx_steer_resp { 656 struct gdma_resp_hdr hdr; 657 }; /* HW DATA */ 658 659 /* Register HW vPort */ 660 struct mana_register_hw_vport_req { 661 struct gdma_req_hdr hdr; 662 u16 attached_gfid; 663 u8 is_pf_default_vport; 664 u8 reserved1; 665 u8 allow_all_ether_types; 666 u8 reserved2; 667 u8 reserved3; 668 u8 reserved4; 669 }; /* HW DATA */ 670 671 struct mana_register_hw_vport_resp { 672 struct gdma_resp_hdr hdr; 673 mana_handle_t hw_vport_handle; 674 }; /* HW DATA */ 675 676 /* Deregister HW vPort */ 677 struct mana_deregister_hw_vport_req { 678 struct gdma_req_hdr hdr; 679 mana_handle_t hw_vport_handle; 680 }; /* HW DATA */ 681 682 struct mana_deregister_hw_vport_resp { 683 struct gdma_resp_hdr hdr; 684 }; /* HW DATA */ 685 686 /* Register filter */ 687 struct mana_register_filter_req { 688 struct gdma_req_hdr hdr; 689 mana_handle_t vport; 690 u8 mac_addr[6]; 691 u8 reserved1; 692 u8 reserved2; 693 u8 reserved3; 694 u8 reserved4; 695 u16 reserved5; 696 u32 reserved6; 697 u32 reserved7; 698 u32 reserved8; 699 }; /* HW DATA */ 700 701 struct mana_register_filter_resp { 702 struct gdma_resp_hdr hdr; 703 mana_handle_t filter_handle; 704 }; /* HW DATA */ 705 706 /* Deregister filter */ 707 struct mana_deregister_filter_req { 708 struct gdma_req_hdr hdr; 709 mana_handle_t filter_handle; 710 }; /* HW DATA */ 711 712 struct mana_deregister_filter_resp { 713 struct gdma_resp_hdr hdr; 714 }; /* HW DATA */ 715 716 /* Requested GF stats Flags */ 717 /* Rx discards/Errors */ 718 #define STATISTICS_FLAGS_RX_DISCARDS_NO_WQE 0x0000000000000001 719 #define STATISTICS_FLAGS_RX_ERRORS_VPORT_DISABLED 0x0000000000000002 720 /* Rx bytes/pkts */ 721 #define STATISTICS_FLAGS_HC_RX_BYTES 0x0000000000000004 722 #define STATISTICS_FLAGS_HC_RX_UCAST_PACKETS 0x0000000000000008 723 #define STATISTICS_FLAGS_HC_RX_UCAST_BYTES 0x0000000000000010 724 #define STATISTICS_FLAGS_HC_RX_MCAST_PACKETS 0x0000000000000020 725 #define STATISTICS_FLAGS_HC_RX_MCAST_BYTES 0x0000000000000040 726 #define STATISTICS_FLAGS_HC_RX_BCAST_PACKETS 0x0000000000000080 727 #define STATISTICS_FLAGS_HC_RX_BCAST_BYTES 0x0000000000000100 728 /* Tx errors */ 729 #define STATISTICS_FLAGS_TX_ERRORS_GF_DISABLED 0x0000000000000200 730 #define STATISTICS_FLAGS_TX_ERRORS_VPORT_DISABLED 0x0000000000000400 731 #define STATISTICS_FLAGS_TX_ERRORS_INVAL_VPORT_OFFSET_PACKETS \ 732 0x0000000000000800 733 #define STATISTICS_FLAGS_TX_ERRORS_VLAN_ENFORCEMENT 0x0000000000001000 734 #define STATISTICS_FLAGS_TX_ERRORS_ETH_TYPE_ENFORCEMENT \ 735 0x0000000000002000 736 #define STATISTICS_FLAGS_TX_ERRORS_SA_ENFORCEMENT 0x0000000000004000 737 #define STATISTICS_FLAGS_TX_ERRORS_SQPDID_ENFORCEMENT 0x0000000000008000 738 #define STATISTICS_FLAGS_TX_ERRORS_CQPDID_ENFORCEMENT 0x0000000000010000 739 #define STATISTICS_FLAGS_TX_ERRORS_MTU_VIOLATION 0x0000000000020000 740 #define STATISTICS_FLAGS_TX_ERRORS_INVALID_OOB 0x0000000000040000 741 /* Tx bytes/pkts */ 742 #define STATISTICS_FLAGS_HC_TX_BYTES 0x0000000000080000 743 #define STATISTICS_FLAGS_HC_TX_UCAST_PACKETS 0x0000000000100000 744 #define STATISTICS_FLAGS_HC_TX_UCAST_BYTES 0x0000000000200000 745 #define STATISTICS_FLAGS_HC_TX_MCAST_PACKETS 0x0000000000400000 746 #define STATISTICS_FLAGS_HC_TX_MCAST_BYTES 0x0000000000800000 747 #define STATISTICS_FLAGS_HC_TX_BCAST_PACKETS 0x0000000001000000 748 #define STATISTICS_FLAGS_HC_TX_BCAST_BYTES 0x0000000002000000 749 /* Tx error */ 750 #define STATISTICS_FLAGS_TX_ERRORS_GDMA_ERROR 0x0000000004000000 751 752 #define MANA_MAX_NUM_QUEUES 64 753 754 #define MANA_SHORT_VPORT_OFFSET_MAX ((1U << 8) - 1) 755 756 struct mana_tx_package { 757 struct gdma_wqe_request wqe_req; 758 struct gdma_sge sgl_array[5]; 759 struct gdma_sge *sgl_ptr; 760 761 struct mana_tx_oob tx_oob; 762 763 struct gdma_posted_wqe_info wqe_info; 764 }; 765 766 int mana_create_wq_obj(struct mana_port_context *apc, 767 mana_handle_t vport, 768 u32 wq_type, struct mana_obj_spec *wq_spec, 769 struct mana_obj_spec *cq_spec, 770 mana_handle_t *wq_obj); 771 772 void mana_destroy_wq_obj(struct mana_port_context *apc, u32 wq_type, 773 mana_handle_t wq_obj); 774 775 int mana_cfg_vport(struct mana_port_context *apc, u32 protection_dom_id, 776 u32 doorbell_pg_id); 777 void mana_uncfg_vport(struct mana_port_context *apc); 778 #endif /* _MANA_H */ 779