1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #ifndef _GDMA_H 5 #define _GDMA_H 6 7 #include <linux/dma-mapping.h> 8 #include <linux/netdevice.h> 9 10 #include "shm_channel.h" 11 12 #define GDMA_STATUS_MORE_ENTRIES 0x00000105 13 14 /* Structures labeled with "HW DATA" are exchanged with the hardware. All of 15 * them are naturally aligned and hence don't need __packed. 16 */ 17 18 enum gdma_request_type { 19 GDMA_VERIFY_VF_DRIVER_VERSION = 1, 20 GDMA_QUERY_MAX_RESOURCES = 2, 21 GDMA_LIST_DEVICES = 3, 22 GDMA_REGISTER_DEVICE = 4, 23 GDMA_DEREGISTER_DEVICE = 5, 24 GDMA_GENERATE_TEST_EQE = 10, 25 GDMA_CREATE_QUEUE = 12, 26 GDMA_DISABLE_QUEUE = 13, 27 GDMA_ALLOCATE_RESOURCE_RANGE = 22, 28 GDMA_DESTROY_RESOURCE_RANGE = 24, 29 GDMA_CREATE_DMA_REGION = 25, 30 GDMA_DMA_REGION_ADD_PAGES = 26, 31 GDMA_DESTROY_DMA_REGION = 27, 32 GDMA_CREATE_PD = 29, 33 GDMA_DESTROY_PD = 30, 34 GDMA_CREATE_MR = 31, 35 GDMA_DESTROY_MR = 32, 36 }; 37 38 #define GDMA_RESOURCE_DOORBELL_PAGE 27 39 40 enum gdma_queue_type { 41 GDMA_INVALID_QUEUE, 42 GDMA_SQ, 43 GDMA_RQ, 44 GDMA_CQ, 45 GDMA_EQ, 46 }; 47 48 enum gdma_work_request_flags { 49 GDMA_WR_NONE = 0, 50 GDMA_WR_OOB_IN_SGL = BIT(0), 51 GDMA_WR_PAD_BY_SGE0 = BIT(1), 52 }; 53 54 enum gdma_eqe_type { 55 GDMA_EQE_COMPLETION = 3, 56 GDMA_EQE_TEST_EVENT = 64, 57 GDMA_EQE_HWC_INIT_EQ_ID_DB = 129, 58 GDMA_EQE_HWC_INIT_DATA = 130, 59 GDMA_EQE_HWC_INIT_DONE = 131, 60 }; 61 62 enum { 63 GDMA_DEVICE_NONE = 0, 64 GDMA_DEVICE_HWC = 1, 65 GDMA_DEVICE_MANA = 2, 66 }; 67 68 struct gdma_resource { 69 /* Protect the bitmap */ 70 spinlock_t lock; 71 72 /* The bitmap size in bits. */ 73 u32 size; 74 75 /* The bitmap tracks the resources. */ 76 unsigned long *map; 77 }; 78 79 union gdma_doorbell_entry { 80 u64 as_uint64; 81 82 struct { 83 u64 id : 24; 84 u64 reserved : 8; 85 u64 tail_ptr : 31; 86 u64 arm : 1; 87 } cq; 88 89 struct { 90 u64 id : 24; 91 u64 wqe_cnt : 8; 92 u64 tail_ptr : 32; 93 } rq; 94 95 struct { 96 u64 id : 24; 97 u64 reserved : 8; 98 u64 tail_ptr : 32; 99 } sq; 100 101 struct { 102 u64 id : 16; 103 u64 reserved : 16; 104 u64 tail_ptr : 31; 105 u64 arm : 1; 106 } eq; 107 }; /* HW DATA */ 108 109 struct gdma_msg_hdr { 110 u32 hdr_type; 111 u32 msg_type; 112 u16 msg_version; 113 u16 hwc_msg_id; 114 u32 msg_size; 115 }; /* HW DATA */ 116 117 struct gdma_dev_id { 118 union { 119 struct { 120 u16 type; 121 u16 instance; 122 }; 123 124 u32 as_uint32; 125 }; 126 }; /* HW DATA */ 127 128 struct gdma_req_hdr { 129 struct gdma_msg_hdr req; 130 struct gdma_msg_hdr resp; /* The expected response */ 131 struct gdma_dev_id dev_id; 132 u32 activity_id; 133 }; /* HW DATA */ 134 135 struct gdma_resp_hdr { 136 struct gdma_msg_hdr response; 137 struct gdma_dev_id dev_id; 138 u32 activity_id; 139 u32 status; 140 u32 reserved; 141 }; /* HW DATA */ 142 143 struct gdma_general_req { 144 struct gdma_req_hdr hdr; 145 }; /* HW DATA */ 146 147 #define GDMA_MESSAGE_V1 1 148 149 struct gdma_general_resp { 150 struct gdma_resp_hdr hdr; 151 }; /* HW DATA */ 152 153 #define GDMA_STANDARD_HEADER_TYPE 0 154 155 static inline void mana_gd_init_req_hdr(struct gdma_req_hdr *hdr, u32 code, 156 u32 req_size, u32 resp_size) 157 { 158 hdr->req.hdr_type = GDMA_STANDARD_HEADER_TYPE; 159 hdr->req.msg_type = code; 160 hdr->req.msg_version = GDMA_MESSAGE_V1; 161 hdr->req.msg_size = req_size; 162 163 hdr->resp.hdr_type = GDMA_STANDARD_HEADER_TYPE; 164 hdr->resp.msg_type = code; 165 hdr->resp.msg_version = GDMA_MESSAGE_V1; 166 hdr->resp.msg_size = resp_size; 167 } 168 169 /* The 16-byte struct is part of the GDMA work queue entry (WQE). */ 170 struct gdma_sge { 171 u64 address; 172 u32 mem_key; 173 u32 size; 174 }; /* HW DATA */ 175 176 struct gdma_wqe_request { 177 struct gdma_sge *sgl; 178 u32 num_sge; 179 180 u32 inline_oob_size; 181 const void *inline_oob_data; 182 183 u32 flags; 184 u32 client_data_unit; 185 }; 186 187 enum gdma_page_type { 188 GDMA_PAGE_TYPE_4K, 189 }; 190 191 #define GDMA_INVALID_DMA_REGION 0 192 193 struct gdma_mem_info { 194 struct device *dev; 195 196 dma_addr_t dma_handle; 197 void *virt_addr; 198 u64 length; 199 200 /* Allocated by the PF driver */ 201 u64 dma_region_handle; 202 }; 203 204 #define REGISTER_ATB_MST_MKEY_LOWER_SIZE 8 205 206 struct gdma_dev { 207 struct gdma_context *gdma_context; 208 209 struct gdma_dev_id dev_id; 210 211 u32 pdid; 212 u32 doorbell; 213 u32 gpa_mkey; 214 215 /* GDMA driver specific pointer */ 216 void *driver_data; 217 218 struct auxiliary_device *adev; 219 }; 220 221 #define MINIMUM_SUPPORTED_PAGE_SIZE PAGE_SIZE 222 223 #define GDMA_CQE_SIZE 64 224 #define GDMA_EQE_SIZE 16 225 #define GDMA_MAX_SQE_SIZE 512 226 #define GDMA_MAX_RQE_SIZE 256 227 228 #define GDMA_COMP_DATA_SIZE 0x3C 229 230 #define GDMA_EVENT_DATA_SIZE 0xC 231 232 /* The WQE size must be a multiple of the Basic Unit, which is 32 bytes. */ 233 #define GDMA_WQE_BU_SIZE 32 234 235 #define INVALID_PDID UINT_MAX 236 #define INVALID_DOORBELL UINT_MAX 237 #define INVALID_MEM_KEY UINT_MAX 238 #define INVALID_QUEUE_ID UINT_MAX 239 #define INVALID_PCI_MSIX_INDEX UINT_MAX 240 241 struct gdma_comp { 242 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 243 u32 wq_num; 244 bool is_sq; 245 }; 246 247 struct gdma_event { 248 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 249 u8 type; 250 }; 251 252 struct gdma_queue; 253 254 struct mana_eq { 255 struct gdma_queue *eq; 256 }; 257 258 typedef void gdma_eq_callback(void *context, struct gdma_queue *q, 259 struct gdma_event *e); 260 261 typedef void gdma_cq_callback(void *context, struct gdma_queue *q); 262 263 /* The 'head' is the producer index. For SQ/RQ, when the driver posts a WQE 264 * (Note: the WQE size must be a multiple of the 32-byte Basic Unit), the 265 * driver increases the 'head' in BUs rather than in bytes, and notifies 266 * the HW of the updated head. For EQ/CQ, the driver uses the 'head' to track 267 * the HW head, and increases the 'head' by 1 for every processed EQE/CQE. 268 * 269 * The 'tail' is the consumer index for SQ/RQ. After the CQE of the SQ/RQ is 270 * processed, the driver increases the 'tail' to indicate that WQEs have 271 * been consumed by the HW, so the driver can post new WQEs into the SQ/RQ. 272 * 273 * The driver doesn't use the 'tail' for EQ/CQ, because the driver ensures 274 * that the EQ/CQ is big enough so they can't overflow, and the driver uses 275 * the owner bits mechanism to detect if the queue has become empty. 276 */ 277 struct gdma_queue { 278 struct gdma_dev *gdma_dev; 279 280 enum gdma_queue_type type; 281 u32 id; 282 283 struct gdma_mem_info mem_info; 284 285 void *queue_mem_ptr; 286 u32 queue_size; 287 288 bool monitor_avl_buf; 289 290 u32 head; 291 u32 tail; 292 293 /* Extra fields specific to EQ/CQ. */ 294 union { 295 struct { 296 bool disable_needed; 297 298 gdma_eq_callback *callback; 299 void *context; 300 301 unsigned int msix_index; 302 303 u32 log2_throttle_limit; 304 } eq; 305 306 struct { 307 gdma_cq_callback *callback; 308 void *context; 309 310 struct gdma_queue *parent; /* For CQ/EQ relationship */ 311 } cq; 312 }; 313 }; 314 315 struct gdma_queue_spec { 316 enum gdma_queue_type type; 317 bool monitor_avl_buf; 318 unsigned int queue_size; 319 320 /* Extra fields specific to EQ/CQ. */ 321 union { 322 struct { 323 gdma_eq_callback *callback; 324 void *context; 325 326 unsigned long log2_throttle_limit; 327 } eq; 328 329 struct { 330 gdma_cq_callback *callback; 331 void *context; 332 333 struct gdma_queue *parent_eq; 334 335 } cq; 336 }; 337 }; 338 339 struct gdma_irq_context { 340 void (*handler)(void *arg); 341 void *arg; 342 }; 343 344 struct gdma_context { 345 struct device *dev; 346 347 /* Per-vPort max number of queues */ 348 unsigned int max_num_queues; 349 unsigned int max_num_msix; 350 unsigned int num_msix_usable; 351 struct gdma_resource msix_resource; 352 struct gdma_irq_context *irq_contexts; 353 354 /* This maps a CQ index to the queue structure. */ 355 unsigned int max_num_cqs; 356 struct gdma_queue **cq_table; 357 358 /* Protect eq_test_event and test_event_eq_id */ 359 struct mutex eq_test_event_mutex; 360 struct completion eq_test_event; 361 u32 test_event_eq_id; 362 363 bool is_pf; 364 phys_addr_t bar0_pa; 365 void __iomem *bar0_va; 366 void __iomem *shm_base; 367 void __iomem *db_page_base; 368 phys_addr_t phys_db_page_base; 369 u32 db_page_size; 370 int numa_node; 371 372 /* Shared memory chanenl (used to bootstrap HWC) */ 373 struct shm_channel shm_channel; 374 375 /* Hardware communication channel (HWC) */ 376 struct gdma_dev hwc; 377 378 /* Azure network adapter */ 379 struct gdma_dev mana; 380 }; 381 382 #define MAX_NUM_GDMA_DEVICES 4 383 384 static inline bool mana_gd_is_mana(struct gdma_dev *gd) 385 { 386 return gd->dev_id.type == GDMA_DEVICE_MANA; 387 } 388 389 static inline bool mana_gd_is_hwc(struct gdma_dev *gd) 390 { 391 return gd->dev_id.type == GDMA_DEVICE_HWC; 392 } 393 394 u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset); 395 u32 mana_gd_wq_avail_space(struct gdma_queue *wq); 396 397 int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq); 398 399 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 400 const struct gdma_queue_spec *spec, 401 struct gdma_queue **queue_ptr); 402 403 int mana_gd_create_mana_eq(struct gdma_dev *gd, 404 const struct gdma_queue_spec *spec, 405 struct gdma_queue **queue_ptr); 406 407 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 408 const struct gdma_queue_spec *spec, 409 struct gdma_queue **queue_ptr); 410 411 void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue); 412 413 int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe); 414 415 void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit); 416 417 struct gdma_wqe { 418 u32 reserved :24; 419 u32 last_vbytes :8; 420 421 union { 422 u32 flags; 423 424 struct { 425 u32 num_sge :8; 426 u32 inline_oob_size_div4:3; 427 u32 client_oob_in_sgl :1; 428 u32 reserved1 :4; 429 u32 client_data_unit :14; 430 u32 reserved2 :2; 431 }; 432 }; 433 }; /* HW DATA */ 434 435 #define INLINE_OOB_SMALL_SIZE 8 436 #define INLINE_OOB_LARGE_SIZE 24 437 438 #define MAX_TX_WQE_SIZE 512 439 #define MAX_RX_WQE_SIZE 256 440 441 #define MAX_TX_WQE_SGL_ENTRIES ((GDMA_MAX_SQE_SIZE - \ 442 sizeof(struct gdma_sge) - INLINE_OOB_SMALL_SIZE) / \ 443 sizeof(struct gdma_sge)) 444 445 #define MAX_RX_WQE_SGL_ENTRIES ((GDMA_MAX_RQE_SIZE - \ 446 sizeof(struct gdma_sge)) / sizeof(struct gdma_sge)) 447 448 struct gdma_cqe { 449 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 450 451 union { 452 u32 as_uint32; 453 454 struct { 455 u32 wq_num : 24; 456 u32 is_sq : 1; 457 u32 reserved : 4; 458 u32 owner_bits : 3; 459 }; 460 } cqe_info; 461 }; /* HW DATA */ 462 463 #define GDMA_CQE_OWNER_BITS 3 464 465 #define GDMA_CQE_OWNER_MASK ((1 << GDMA_CQE_OWNER_BITS) - 1) 466 467 #define SET_ARM_BIT 1 468 469 #define GDMA_EQE_OWNER_BITS 3 470 471 union gdma_eqe_info { 472 u32 as_uint32; 473 474 struct { 475 u32 type : 8; 476 u32 reserved1 : 8; 477 u32 client_id : 2; 478 u32 reserved2 : 11; 479 u32 owner_bits : 3; 480 }; 481 }; /* HW DATA */ 482 483 #define GDMA_EQE_OWNER_MASK ((1 << GDMA_EQE_OWNER_BITS) - 1) 484 #define INITIALIZED_OWNER_BIT(log2_num_entries) (1UL << (log2_num_entries)) 485 486 struct gdma_eqe { 487 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 488 u32 eqe_info; 489 }; /* HW DATA */ 490 491 #define GDMA_REG_DB_PAGE_OFFSET 8 492 #define GDMA_REG_DB_PAGE_SIZE 0x10 493 #define GDMA_REG_SHM_OFFSET 0x18 494 495 #define GDMA_PF_REG_DB_PAGE_SIZE 0xD0 496 #define GDMA_PF_REG_DB_PAGE_OFF 0xC8 497 #define GDMA_PF_REG_SHM_OFF 0x70 498 499 #define GDMA_SRIOV_REG_CFG_BASE_OFF 0x108 500 501 #define MANA_PF_DEVICE_ID 0x00B9 502 #define MANA_VF_DEVICE_ID 0x00BA 503 504 struct gdma_posted_wqe_info { 505 u32 wqe_size_in_bu; 506 }; 507 508 /* GDMA_GENERATE_TEST_EQE */ 509 struct gdma_generate_test_event_req { 510 struct gdma_req_hdr hdr; 511 u32 queue_index; 512 }; /* HW DATA */ 513 514 /* GDMA_VERIFY_VF_DRIVER_VERSION */ 515 enum { 516 GDMA_PROTOCOL_V1 = 1, 517 GDMA_PROTOCOL_FIRST = GDMA_PROTOCOL_V1, 518 GDMA_PROTOCOL_LAST = GDMA_PROTOCOL_V1, 519 }; 520 521 #define GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT BIT(0) 522 523 /* Advertise to the NIC firmware: the NAPI work_done variable race is fixed, 524 * so the driver is able to reliably support features like busy_poll. 525 */ 526 #define GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX BIT(2) 527 528 #define GDMA_DRV_CAP_FLAGS1 \ 529 (GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT | \ 530 GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX) 531 532 #define GDMA_DRV_CAP_FLAGS2 0 533 534 #define GDMA_DRV_CAP_FLAGS3 0 535 536 #define GDMA_DRV_CAP_FLAGS4 0 537 538 struct gdma_verify_ver_req { 539 struct gdma_req_hdr hdr; 540 541 /* Mandatory fields required for protocol establishment */ 542 u64 protocol_ver_min; 543 u64 protocol_ver_max; 544 545 /* Gdma Driver Capability Flags */ 546 u64 gd_drv_cap_flags1; 547 u64 gd_drv_cap_flags2; 548 u64 gd_drv_cap_flags3; 549 u64 gd_drv_cap_flags4; 550 551 /* Advisory fields */ 552 u64 drv_ver; 553 u32 os_type; /* Linux = 0x10; Windows = 0x20; Other = 0x30 */ 554 u32 reserved; 555 u32 os_ver_major; 556 u32 os_ver_minor; 557 u32 os_ver_build; 558 u32 os_ver_platform; 559 u64 reserved_2; 560 u8 os_ver_str1[128]; 561 u8 os_ver_str2[128]; 562 u8 os_ver_str3[128]; 563 u8 os_ver_str4[128]; 564 }; /* HW DATA */ 565 566 struct gdma_verify_ver_resp { 567 struct gdma_resp_hdr hdr; 568 u64 gdma_protocol_ver; 569 u64 pf_cap_flags1; 570 u64 pf_cap_flags2; 571 u64 pf_cap_flags3; 572 u64 pf_cap_flags4; 573 }; /* HW DATA */ 574 575 /* GDMA_QUERY_MAX_RESOURCES */ 576 struct gdma_query_max_resources_resp { 577 struct gdma_resp_hdr hdr; 578 u32 status; 579 u32 max_sq; 580 u32 max_rq; 581 u32 max_cq; 582 u32 max_eq; 583 u32 max_db; 584 u32 max_mst; 585 u32 max_cq_mod_ctx; 586 u32 max_mod_cq; 587 u32 max_msix; 588 }; /* HW DATA */ 589 590 /* GDMA_LIST_DEVICES */ 591 struct gdma_list_devices_resp { 592 struct gdma_resp_hdr hdr; 593 u32 num_of_devs; 594 u32 reserved; 595 struct gdma_dev_id devs[64]; 596 }; /* HW DATA */ 597 598 /* GDMA_REGISTER_DEVICE */ 599 struct gdma_register_device_resp { 600 struct gdma_resp_hdr hdr; 601 u32 pdid; 602 u32 gpa_mkey; 603 u32 db_id; 604 }; /* HW DATA */ 605 606 struct gdma_allocate_resource_range_req { 607 struct gdma_req_hdr hdr; 608 u32 resource_type; 609 u32 num_resources; 610 u32 alignment; 611 u32 allocated_resources; 612 }; 613 614 struct gdma_allocate_resource_range_resp { 615 struct gdma_resp_hdr hdr; 616 u32 allocated_resources; 617 }; 618 619 struct gdma_destroy_resource_range_req { 620 struct gdma_req_hdr hdr; 621 u32 resource_type; 622 u32 num_resources; 623 u32 allocated_resources; 624 }; 625 626 /* GDMA_CREATE_QUEUE */ 627 struct gdma_create_queue_req { 628 struct gdma_req_hdr hdr; 629 u32 type; 630 u32 reserved1; 631 u32 pdid; 632 u32 doolbell_id; 633 u64 gdma_region; 634 u32 reserved2; 635 u32 queue_size; 636 u32 log2_throttle_limit; 637 u32 eq_pci_msix_index; 638 u32 cq_mod_ctx_id; 639 u32 cq_parent_eq_id; 640 u8 rq_drop_on_overrun; 641 u8 rq_err_on_wqe_overflow; 642 u8 rq_chain_rec_wqes; 643 u8 sq_hw_db; 644 u32 reserved3; 645 }; /* HW DATA */ 646 647 struct gdma_create_queue_resp { 648 struct gdma_resp_hdr hdr; 649 u32 queue_index; 650 }; /* HW DATA */ 651 652 /* GDMA_DISABLE_QUEUE */ 653 struct gdma_disable_queue_req { 654 struct gdma_req_hdr hdr; 655 u32 type; 656 u32 queue_index; 657 u32 alloc_res_id_on_creation; 658 }; /* HW DATA */ 659 660 enum atb_page_size { 661 ATB_PAGE_SIZE_4K, 662 ATB_PAGE_SIZE_8K, 663 ATB_PAGE_SIZE_16K, 664 ATB_PAGE_SIZE_32K, 665 ATB_PAGE_SIZE_64K, 666 ATB_PAGE_SIZE_128K, 667 ATB_PAGE_SIZE_256K, 668 ATB_PAGE_SIZE_512K, 669 ATB_PAGE_SIZE_1M, 670 ATB_PAGE_SIZE_2M, 671 ATB_PAGE_SIZE_MAX, 672 }; 673 674 enum gdma_mr_access_flags { 675 GDMA_ACCESS_FLAG_LOCAL_READ = BIT_ULL(0), 676 GDMA_ACCESS_FLAG_LOCAL_WRITE = BIT_ULL(1), 677 GDMA_ACCESS_FLAG_REMOTE_READ = BIT_ULL(2), 678 GDMA_ACCESS_FLAG_REMOTE_WRITE = BIT_ULL(3), 679 GDMA_ACCESS_FLAG_REMOTE_ATOMIC = BIT_ULL(4), 680 }; 681 682 /* GDMA_CREATE_DMA_REGION */ 683 struct gdma_create_dma_region_req { 684 struct gdma_req_hdr hdr; 685 686 /* The total size of the DMA region */ 687 u64 length; 688 689 /* The offset in the first page */ 690 u32 offset_in_page; 691 692 /* enum gdma_page_type */ 693 u32 gdma_page_type; 694 695 /* The total number of pages */ 696 u32 page_count; 697 698 /* If page_addr_list_len is smaller than page_count, 699 * the remaining page addresses will be added via the 700 * message GDMA_DMA_REGION_ADD_PAGES. 701 */ 702 u32 page_addr_list_len; 703 u64 page_addr_list[]; 704 }; /* HW DATA */ 705 706 struct gdma_create_dma_region_resp { 707 struct gdma_resp_hdr hdr; 708 u64 dma_region_handle; 709 }; /* HW DATA */ 710 711 /* GDMA_DMA_REGION_ADD_PAGES */ 712 struct gdma_dma_region_add_pages_req { 713 struct gdma_req_hdr hdr; 714 715 u64 dma_region_handle; 716 717 u32 page_addr_list_len; 718 u32 reserved3; 719 720 u64 page_addr_list[]; 721 }; /* HW DATA */ 722 723 /* GDMA_DESTROY_DMA_REGION */ 724 struct gdma_destroy_dma_region_req { 725 struct gdma_req_hdr hdr; 726 727 u64 dma_region_handle; 728 }; /* HW DATA */ 729 730 enum gdma_pd_flags { 731 GDMA_PD_FLAG_INVALID = 0, 732 }; 733 734 struct gdma_create_pd_req { 735 struct gdma_req_hdr hdr; 736 enum gdma_pd_flags flags; 737 u32 reserved; 738 };/* HW DATA */ 739 740 struct gdma_create_pd_resp { 741 struct gdma_resp_hdr hdr; 742 u64 pd_handle; 743 u32 pd_id; 744 u32 reserved; 745 };/* HW DATA */ 746 747 struct gdma_destroy_pd_req { 748 struct gdma_req_hdr hdr; 749 u64 pd_handle; 750 };/* HW DATA */ 751 752 struct gdma_destory_pd_resp { 753 struct gdma_resp_hdr hdr; 754 };/* HW DATA */ 755 756 enum gdma_mr_type { 757 /* Guest Virtual Address - MRs of this type allow access 758 * to memory mapped by PTEs associated with this MR using a virtual 759 * address that is set up in the MST 760 */ 761 GDMA_MR_TYPE_GVA = 2, 762 }; 763 764 struct gdma_create_mr_params { 765 u64 pd_handle; 766 enum gdma_mr_type mr_type; 767 union { 768 struct { 769 u64 dma_region_handle; 770 u64 virtual_address; 771 enum gdma_mr_access_flags access_flags; 772 } gva; 773 }; 774 }; 775 776 struct gdma_create_mr_request { 777 struct gdma_req_hdr hdr; 778 u64 pd_handle; 779 enum gdma_mr_type mr_type; 780 u32 reserved_1; 781 782 union { 783 struct { 784 u64 dma_region_handle; 785 u64 virtual_address; 786 enum gdma_mr_access_flags access_flags; 787 } gva; 788 789 }; 790 u32 reserved_2; 791 };/* HW DATA */ 792 793 struct gdma_create_mr_response { 794 struct gdma_resp_hdr hdr; 795 u64 mr_handle; 796 u32 lkey; 797 u32 rkey; 798 };/* HW DATA */ 799 800 struct gdma_destroy_mr_request { 801 struct gdma_req_hdr hdr; 802 u64 mr_handle; 803 };/* HW DATA */ 804 805 struct gdma_destroy_mr_response { 806 struct gdma_resp_hdr hdr; 807 };/* HW DATA */ 808 809 int mana_gd_verify_vf_version(struct pci_dev *pdev); 810 811 int mana_gd_register_device(struct gdma_dev *gd); 812 int mana_gd_deregister_device(struct gdma_dev *gd); 813 814 int mana_gd_post_work_request(struct gdma_queue *wq, 815 const struct gdma_wqe_request *wqe_req, 816 struct gdma_posted_wqe_info *wqe_info); 817 818 int mana_gd_post_and_ring(struct gdma_queue *queue, 819 const struct gdma_wqe_request *wqe, 820 struct gdma_posted_wqe_info *wqe_info); 821 822 int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r); 823 void mana_gd_free_res_map(struct gdma_resource *r); 824 825 void mana_gd_wq_ring_doorbell(struct gdma_context *gc, 826 struct gdma_queue *queue); 827 828 int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 829 struct gdma_mem_info *gmi); 830 831 void mana_gd_free_memory(struct gdma_mem_info *gmi); 832 833 int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req, 834 u32 resp_len, void *resp); 835 836 int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle); 837 838 #endif /* _GDMA_H */ 839