1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Renesas RPC-IF core driver 4 * 5 * Copyright (C) 2018~2019 Renesas Solutions Corp. 6 * Copyright (C) 2019 Macronix International Co., Ltd. 7 * Copyright (C) 2019-2020 Cogent Embedded, Inc. 8 */ 9 10 #ifndef __RENESAS_RPC_IF_H 11 #define __RENESAS_RPC_IF_H 12 13 #include <linux/pm_runtime.h> 14 #include <linux/types.h> 15 16 enum rpcif_data_dir { 17 RPCIF_NO_DATA, 18 RPCIF_DATA_IN, 19 RPCIF_DATA_OUT, 20 }; 21 22 struct rpcif_op { 23 struct { 24 u8 buswidth; 25 u8 opcode; 26 bool ddr; 27 } cmd, ocmd; 28 29 struct { 30 u8 nbytes; 31 u8 buswidth; 32 bool ddr; 33 u64 val; 34 } addr; 35 36 struct { 37 u8 ncycles; 38 u8 buswidth; 39 } dummy; 40 41 struct { 42 u8 nbytes; 43 u8 buswidth; 44 bool ddr; 45 u32 val; 46 } option; 47 48 struct { 49 u8 buswidth; 50 unsigned int nbytes; 51 enum rpcif_data_dir dir; 52 bool ddr; 53 union { 54 void *in; 55 const void *out; 56 } buf; 57 } data; 58 }; 59 60 struct rpcif { 61 struct device *dev; 62 void __iomem *base; 63 void __iomem *dirmap; 64 struct regmap *regmap; 65 struct reset_control *rstc; 66 size_t size; 67 enum rpcif_data_dir dir; 68 u8 bus_size; 69 void *buffer; 70 u32 xferlen; 71 u32 smcr; 72 u32 smadr; 73 u32 command; /* DRCMR or SMCMR */ 74 u32 option; /* DROPR or SMOPR */ 75 u32 enable; /* DRENR or SMENR */ 76 u32 dummy; /* DRDMCR or SMDMCR */ 77 u32 ddr; /* DRDRENR or SMDRENR */ 78 }; 79 80 int rpcif_sw_init(struct rpcif *rpc, struct device *dev); 81 void rpcif_hw_init(struct rpcif *rpc, bool hyperflash); 82 void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs, 83 size_t *len); 84 int rpcif_manual_xfer(struct rpcif *rpc); 85 ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf); 86 87 static inline void rpcif_enable_rpm(struct rpcif *rpc) 88 { 89 pm_runtime_enable(rpc->dev); 90 } 91 92 static inline void rpcif_disable_rpm(struct rpcif *rpc) 93 { 94 pm_runtime_disable(rpc->dev); 95 } 96 97 #endif // __RENESAS_RPC_IF_H 98