1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * adv7842 - Analog Devices ADV7842 video decoder driver 4 * 5 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 6 */ 7 8 #ifndef _ADV7842_ 9 #define _ADV7842_ 10 11 /* Analog input muxing modes (AFE register 0x02, [2:0]) */ 12 enum adv7842_ain_sel { 13 ADV7842_AIN1_2_3_NC_SYNC_1_2 = 0, 14 ADV7842_AIN4_5_6_NC_SYNC_2_1 = 1, 15 ADV7842_AIN7_8_9_NC_SYNC_3_1 = 2, 16 ADV7842_AIN10_11_12_NC_SYNC_4_1 = 3, 17 ADV7842_AIN9_4_5_6_SYNC_2_1 = 4, 18 }; 19 20 /* 21 * Bus rotation and reordering. This is used to specify component reordering on 22 * the board and describes the components order on the bus when the ADV7842 23 * outputs RGB. 24 */ 25 enum adv7842_bus_order { 26 ADV7842_BUS_ORDER_RGB, /* No operation */ 27 ADV7842_BUS_ORDER_GRB, /* Swap 1-2 */ 28 ADV7842_BUS_ORDER_RBG, /* Swap 2-3 */ 29 ADV7842_BUS_ORDER_BGR, /* Swap 1-3 */ 30 ADV7842_BUS_ORDER_BRG, /* Rotate right */ 31 ADV7842_BUS_ORDER_GBR, /* Rotate left */ 32 }; 33 34 /* Input Color Space (IO register 0x02, [7:4]) */ 35 enum adv7842_inp_color_space { 36 ADV7842_INP_COLOR_SPACE_LIM_RGB = 0, 37 ADV7842_INP_COLOR_SPACE_FULL_RGB = 1, 38 ADV7842_INP_COLOR_SPACE_LIM_YCbCr_601 = 2, 39 ADV7842_INP_COLOR_SPACE_LIM_YCbCr_709 = 3, 40 ADV7842_INP_COLOR_SPACE_XVYCC_601 = 4, 41 ADV7842_INP_COLOR_SPACE_XVYCC_709 = 5, 42 ADV7842_INP_COLOR_SPACE_FULL_YCbCr_601 = 6, 43 ADV7842_INP_COLOR_SPACE_FULL_YCbCr_709 = 7, 44 ADV7842_INP_COLOR_SPACE_AUTO = 0xf, 45 }; 46 47 /* Select output format (IO register 0x03, [4:2]) */ 48 enum adv7842_op_format_mode_sel { 49 ADV7842_OP_FORMAT_MODE0 = 0x00, 50 ADV7842_OP_FORMAT_MODE1 = 0x04, 51 ADV7842_OP_FORMAT_MODE2 = 0x08, 52 }; 53 54 /* Mode of operation */ 55 enum adv7842_mode { 56 ADV7842_MODE_SDP, 57 ADV7842_MODE_COMP, 58 ADV7842_MODE_RGB, 59 ADV7842_MODE_HDMI 60 }; 61 62 /* Video standard select (IO register 0x00, [5:0]) */ 63 enum adv7842_vid_std_select { 64 /* SDP */ 65 ADV7842_SDP_VID_STD_CVBS_SD_4x1 = 0x01, 66 ADV7842_SDP_VID_STD_YC_SD4_x1 = 0x09, 67 /* RGB */ 68 ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE = 0x07, 69 /* HDMI GR */ 70 ADV7842_HDMI_GR_VID_STD_AUTO_GRAPH_MODE = 0x02, 71 /* HDMI COMP */ 72 ADV7842_HDMI_COMP_VID_STD_HD_1250P = 0x1e, 73 }; 74 75 enum adv7842_select_input { 76 ADV7842_SELECT_HDMI_PORT_A, 77 ADV7842_SELECT_HDMI_PORT_B, 78 ADV7842_SELECT_VGA_RGB, 79 ADV7842_SELECT_VGA_COMP, 80 ADV7842_SELECT_SDP_CVBS, 81 ADV7842_SELECT_SDP_YC, 82 }; 83 84 enum adv7842_drive_strength { 85 ADV7842_DR_STR_LOW = 0, 86 ADV7842_DR_STR_MEDIUM_LOW = 1, 87 ADV7842_DR_STR_MEDIUM_HIGH = 2, 88 ADV7842_DR_STR_HIGH = 3, 89 }; 90 91 struct adv7842_sdp_csc_coeff { 92 bool manual; 93 u16 scaling; 94 u16 A1; 95 u16 A2; 96 u16 A3; 97 u16 A4; 98 u16 B1; 99 u16 B2; 100 u16 B3; 101 u16 B4; 102 u16 C1; 103 u16 C2; 104 u16 C3; 105 u16 C4; 106 }; 107 108 struct adv7842_sdp_io_sync_adjustment { 109 bool adjust; 110 u16 hs_beg; 111 u16 hs_width; 112 u16 de_beg; 113 u16 de_end; 114 u8 vs_beg_o; 115 u8 vs_beg_e; 116 u8 vs_end_o; 117 u8 vs_end_e; 118 u8 de_v_beg_o; 119 u8 de_v_beg_e; 120 u8 de_v_end_o; 121 u8 de_v_end_e; 122 }; 123 124 /* Platform dependent definition */ 125 struct adv7842_platform_data { 126 /* chip reset during probe */ 127 unsigned chip_reset:1; 128 129 /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */ 130 unsigned disable_pwrdnb:1; 131 132 /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */ 133 unsigned disable_cable_det_rst:1; 134 135 /* Analog input muxing mode */ 136 enum adv7842_ain_sel ain_sel; 137 138 /* Bus rotation and reordering */ 139 enum adv7842_bus_order bus_order; 140 141 /* Select output format mode */ 142 enum adv7842_op_format_mode_sel op_format_mode_sel; 143 144 /* Default mode */ 145 enum adv7842_mode mode; 146 147 /* Default input */ 148 unsigned input; 149 150 /* Video standard */ 151 enum adv7842_vid_std_select vid_std_select; 152 153 /* IO register 0x02 */ 154 unsigned alt_gamma:1; 155 156 /* IO register 0x05 */ 157 unsigned blank_data:1; 158 unsigned insert_av_codes:1; 159 unsigned replicate_av_codes:1; 160 161 /* IO register 0x30 */ 162 unsigned output_bus_lsb_to_msb:1; 163 164 /* IO register 0x14 */ 165 enum adv7842_drive_strength dr_str_data; 166 enum adv7842_drive_strength dr_str_clk; 167 enum adv7842_drive_strength dr_str_sync; 168 169 /* 170 * IO register 0x19: Adjustment to the LLC DLL phase in 171 * increments of 1/32 of a clock period. 172 */ 173 unsigned llc_dll_phase:5; 174 175 /* External RAM for 3-D comb or frame synchronizer */ 176 unsigned sd_ram_size; /* ram size in MB */ 177 unsigned sd_ram_ddr:1; /* ddr or sdr sdram */ 178 179 /* HDMI free run, CP-reg 0xBA */ 180 unsigned hdmi_free_run_enable:1; 181 /* 0 = Mode 0: run when there is no TMDS clock 182 1 = Mode 1: run when there is no TMDS clock or the 183 video resolution does not match programmed one. */ 184 unsigned hdmi_free_run_mode:1; 185 186 /* SDP free run, CP-reg 0xDD */ 187 unsigned sdp_free_run_auto:1; 188 unsigned sdp_free_run_man_col_en:1; 189 unsigned sdp_free_run_cbar_en:1; 190 unsigned sdp_free_run_force:1; 191 192 /* HPA manual (0) or auto (1), affects HDMI register 0x69 */ 193 unsigned hpa_auto:1; 194 195 struct adv7842_sdp_csc_coeff sdp_csc_coeff; 196 197 struct adv7842_sdp_io_sync_adjustment sdp_io_sync_625; 198 struct adv7842_sdp_io_sync_adjustment sdp_io_sync_525; 199 200 /* i2c addresses */ 201 u8 i2c_sdp_io; 202 u8 i2c_sdp; 203 u8 i2c_cp; 204 u8 i2c_vdp; 205 u8 i2c_afe; 206 u8 i2c_hdmi; 207 u8 i2c_repeater; 208 u8 i2c_edid; 209 u8 i2c_infoframe; 210 u8 i2c_cec; 211 u8 i2c_avlink; 212 }; 213 214 #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000) 215 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001) 216 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002) 217 218 /* custom ioctl, used to test the external RAM that's used by the 219 * deinterlacer. */ 220 #define ADV7842_CMD_RAM_TEST _IO('V', BASE_VIDIOC_PRIVATE) 221 222 #define ADV7842_EDID_PORT_A 0 223 #define ADV7842_EDID_PORT_B 1 224 #define ADV7842_EDID_PORT_VGA 2 225 #define ADV7842_PAD_SOURCE 3 226 227 #endif 228