1 /* 2 * NetChip 2280 high/full speed USB device controller. 3 * Unlike many such controllers, this one talks PCI. 4 * 5 * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com) 6 * Copyright (C) 2003 David Brownell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #ifndef __LINUX_USB_NET2280_H 24 #define __LINUX_USB_NET2280_H 25 26 /*-------------------------------------------------------------------------*/ 27 28 /* NET2280 MEMORY MAPPED REGISTERS 29 * 30 * The register layout came from the chip documentation, and the bit 31 * number definitions were extracted from chip specification. 32 * 33 * Use the shift operator ('<<') to build bit masks, with readl/writel 34 * to access the registers through PCI. 35 */ 36 37 /* main registers, BAR0 + 0x0000 */ 38 struct net2280_regs { 39 /* offset 0x0000 */ 40 u32 devinit; 41 #define LOCAL_CLOCK_FREQUENCY 8 42 #define FORCE_PCI_RESET 7 43 #define PCI_ID 6 44 #define PCI_ENABLE 5 45 #define FIFO_SOFT_RESET 4 46 #define CFG_SOFT_RESET 3 47 #define PCI_SOFT_RESET 2 48 #define USB_SOFT_RESET 1 49 #define M8051_RESET 0 50 u32 eectl; 51 #define EEPROM_ADDRESS_WIDTH 23 52 #define EEPROM_CHIP_SELECT_ACTIVE 22 53 #define EEPROM_PRESENT 21 54 #define EEPROM_VALID 20 55 #define EEPROM_BUSY 19 56 #define EEPROM_CHIP_SELECT_ENABLE 18 57 #define EEPROM_BYTE_READ_START 17 58 #define EEPROM_BYTE_WRITE_START 16 59 #define EEPROM_READ_DATA 8 60 #define EEPROM_WRITE_DATA 0 61 u32 eeclkfreq; 62 u32 _unused0; 63 /* offset 0x0010 */ 64 65 u32 pciirqenb0; /* interrupt PCI master ... */ 66 #define SETUP_PACKET_INTERRUPT_ENABLE 7 67 #define ENDPOINT_F_INTERRUPT_ENABLE 6 68 #define ENDPOINT_E_INTERRUPT_ENABLE 5 69 #define ENDPOINT_D_INTERRUPT_ENABLE 4 70 #define ENDPOINT_C_INTERRUPT_ENABLE 3 71 #define ENDPOINT_B_INTERRUPT_ENABLE 2 72 #define ENDPOINT_A_INTERRUPT_ENABLE 1 73 #define ENDPOINT_0_INTERRUPT_ENABLE 0 74 u32 pciirqenb1; 75 #define PCI_INTERRUPT_ENABLE 31 76 #define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 77 #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 78 #define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 79 #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 80 #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 81 #define PCI_TARGET_ABORT_ASSERTED_INTERRUPT_ENABLE 18 82 #define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 83 #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 84 #define GPIO_INTERRUPT_ENABLE 13 85 #define DMA_D_INTERRUPT_ENABLE 12 86 #define DMA_C_INTERRUPT_ENABLE 11 87 #define DMA_B_INTERRUPT_ENABLE 10 88 #define DMA_A_INTERRUPT_ENABLE 9 89 #define EEPROM_DONE_INTERRUPT_ENABLE 8 90 #define VBUS_INTERRUPT_ENABLE 7 91 #define CONTROL_STATUS_INTERRUPT_ENABLE 6 92 #define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 93 #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 94 #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 95 #define RESUME_INTERRUPT_ENABLE 1 96 #define SOF_INTERRUPT_ENABLE 0 97 u32 cpu_irqenb0; /* ... or onboard 8051 */ 98 #define SETUP_PACKET_INTERRUPT_ENABLE 7 99 #define ENDPOINT_F_INTERRUPT_ENABLE 6 100 #define ENDPOINT_E_INTERRUPT_ENABLE 5 101 #define ENDPOINT_D_INTERRUPT_ENABLE 4 102 #define ENDPOINT_C_INTERRUPT_ENABLE 3 103 #define ENDPOINT_B_INTERRUPT_ENABLE 2 104 #define ENDPOINT_A_INTERRUPT_ENABLE 1 105 #define ENDPOINT_0_INTERRUPT_ENABLE 0 106 u32 cpu_irqenb1; 107 #define CPU_INTERRUPT_ENABLE 31 108 #define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 109 #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 110 #define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 111 #define PCI_INTA_INTERRUPT_ENABLE 24 112 #define PCI_PME_INTERRUPT_ENABLE 23 113 #define PCI_SERR_INTERRUPT_ENABLE 22 114 #define PCI_PERR_INTERRUPT_ENABLE 21 115 #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 116 #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 117 #define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 118 #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 119 #define GPIO_INTERRUPT_ENABLE 13 120 #define DMA_D_INTERRUPT_ENABLE 12 121 #define DMA_C_INTERRUPT_ENABLE 11 122 #define DMA_B_INTERRUPT_ENABLE 10 123 #define DMA_A_INTERRUPT_ENABLE 9 124 #define EEPROM_DONE_INTERRUPT_ENABLE 8 125 #define VBUS_INTERRUPT_ENABLE 7 126 #define CONTROL_STATUS_INTERRUPT_ENABLE 6 127 #define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 128 #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 129 #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 130 #define RESUME_INTERRUPT_ENABLE 1 131 #define SOF_INTERRUPT_ENABLE 0 132 133 /* offset 0x0020 */ 134 u32 _unused1; 135 u32 usbirqenb1; 136 #define USB_INTERRUPT_ENABLE 31 137 #define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 138 #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 139 #define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 140 #define PCI_INTA_INTERRUPT_ENABLE 24 141 #define PCI_PME_INTERRUPT_ENABLE 23 142 #define PCI_SERR_INTERRUPT_ENABLE 22 143 #define PCI_PERR_INTERRUPT_ENABLE 21 144 #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 145 #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 146 #define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 147 #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 148 #define GPIO_INTERRUPT_ENABLE 13 149 #define DMA_D_INTERRUPT_ENABLE 12 150 #define DMA_C_INTERRUPT_ENABLE 11 151 #define DMA_B_INTERRUPT_ENABLE 10 152 #define DMA_A_INTERRUPT_ENABLE 9 153 #define EEPROM_DONE_INTERRUPT_ENABLE 8 154 #define VBUS_INTERRUPT_ENABLE 7 155 #define CONTROL_STATUS_INTERRUPT_ENABLE 6 156 #define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 157 #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 158 #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 159 #define RESUME_INTERRUPT_ENABLE 1 160 #define SOF_INTERRUPT_ENABLE 0 161 u32 irqstat0; 162 #define INTA_ASSERTED 12 163 #define SETUP_PACKET_INTERRUPT 7 164 #define ENDPOINT_F_INTERRUPT 6 165 #define ENDPOINT_E_INTERRUPT 5 166 #define ENDPOINT_D_INTERRUPT 4 167 #define ENDPOINT_C_INTERRUPT 3 168 #define ENDPOINT_B_INTERRUPT 2 169 #define ENDPOINT_A_INTERRUPT 1 170 #define ENDPOINT_0_INTERRUPT 0 171 u32 irqstat1; 172 #define POWER_STATE_CHANGE_INTERRUPT 27 173 #define PCI_ARBITER_TIMEOUT_INTERRUPT 26 174 #define PCI_PARITY_ERROR_INTERRUPT 25 175 #define PCI_INTA_INTERRUPT 24 176 #define PCI_PME_INTERRUPT 23 177 #define PCI_SERR_INTERRUPT 22 178 #define PCI_PERR_INTERRUPT 21 179 #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT 20 180 #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT 19 181 #define PCI_RETRY_ABORT_INTERRUPT 17 182 #define PCI_MASTER_CYCLE_DONE_INTERRUPT 16 183 #define SOF_DOWN_INTERRUPT 14 184 #define GPIO_INTERRUPT 13 185 #define DMA_D_INTERRUPT 12 186 #define DMA_C_INTERRUPT 11 187 #define DMA_B_INTERRUPT 10 188 #define DMA_A_INTERRUPT 9 189 #define EEPROM_DONE_INTERRUPT 8 190 #define VBUS_INTERRUPT 7 191 #define CONTROL_STATUS_INTERRUPT 6 192 #define ROOT_PORT_RESET_INTERRUPT 4 193 #define SUSPEND_REQUEST_INTERRUPT 3 194 #define SUSPEND_REQUEST_CHANGE_INTERRUPT 2 195 #define RESUME_INTERRUPT 1 196 #define SOF_INTERRUPT 0 197 /* offset 0x0030 */ 198 u32 idxaddr; 199 u32 idxdata; 200 u32 fifoctl; 201 #define PCI_BASE2_RANGE 16 202 #define IGNORE_FIFO_AVAILABILITY 3 203 #define PCI_BASE2_SELECT 2 204 #define FIFO_CONFIGURATION_SELECT 0 205 u32 _unused2; 206 /* offset 0x0040 */ 207 u32 memaddr; 208 #define START 28 209 #define DIRECTION 27 210 #define FIFO_DIAGNOSTIC_SELECT 24 211 #define MEMORY_ADDRESS 0 212 u32 memdata0; 213 u32 memdata1; 214 u32 _unused3; 215 /* offset 0x0050 */ 216 u32 gpioctl; 217 #define GPIO3_LED_SELECT 12 218 #define GPIO3_INTERRUPT_ENABLE 11 219 #define GPIO2_INTERRUPT_ENABLE 10 220 #define GPIO1_INTERRUPT_ENABLE 9 221 #define GPIO0_INTERRUPT_ENABLE 8 222 #define GPIO3_OUTPUT_ENABLE 7 223 #define GPIO2_OUTPUT_ENABLE 6 224 #define GPIO1_OUTPUT_ENABLE 5 225 #define GPIO0_OUTPUT_ENABLE 4 226 #define GPIO3_DATA 3 227 #define GPIO2_DATA 2 228 #define GPIO1_DATA 1 229 #define GPIO0_DATA 0 230 u32 gpiostat; 231 #define GPIO3_INTERRUPT 3 232 #define GPIO2_INTERRUPT 2 233 #define GPIO1_INTERRUPT 1 234 #define GPIO0_INTERRUPT 0 235 } __attribute__ ((packed)); 236 237 /* usb control, BAR0 + 0x0080 */ 238 struct net2280_usb_regs { 239 /* offset 0x0080 */ 240 u32 stdrsp; 241 #define STALL_UNSUPPORTED_REQUESTS 31 242 #define SET_TEST_MODE 16 243 #define GET_OTHER_SPEED_CONFIGURATION 15 244 #define GET_DEVICE_QUALIFIER 14 245 #define SET_ADDRESS 13 246 #define ENDPOINT_SET_CLEAR_HALT 12 247 #define DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP 11 248 #define GET_STRING_DESCRIPTOR_2 10 249 #define GET_STRING_DESCRIPTOR_1 9 250 #define GET_STRING_DESCRIPTOR_0 8 251 #define GET_SET_INTERFACE 6 252 #define GET_SET_CONFIGURATION 5 253 #define GET_CONFIGURATION_DESCRIPTOR 4 254 #define GET_DEVICE_DESCRIPTOR 3 255 #define GET_ENDPOINT_STATUS 2 256 #define GET_INTERFACE_STATUS 1 257 #define GET_DEVICE_STATUS 0 258 u32 prodvendid; 259 #define PRODUCT_ID 16 260 #define VENDOR_ID 0 261 u32 relnum; 262 u32 usbctl; 263 #define SERIAL_NUMBER_INDEX 16 264 #define PRODUCT_ID_STRING_ENABLE 13 265 #define VENDOR_ID_STRING_ENABLE 12 266 #define USB_ROOT_PORT_WAKEUP_ENABLE 11 267 #define VBUS_PIN 10 268 #define TIMED_DISCONNECT 9 269 #define SUSPEND_IMMEDIATELY 7 270 #define SELF_POWERED_USB_DEVICE 6 271 #define REMOTE_WAKEUP_SUPPORT 5 272 #define PME_POLARITY 4 273 #define USB_DETECT_ENABLE 3 274 #define PME_WAKEUP_ENABLE 2 275 #define DEVICE_REMOTE_WAKEUP_ENABLE 1 276 #define SELF_POWERED_STATUS 0 277 /* offset 0x0090 */ 278 u32 usbstat; 279 #define HIGH_SPEED 7 280 #define FULL_SPEED 6 281 #define GENERATE_RESUME 5 282 #define GENERATE_DEVICE_REMOTE_WAKEUP 4 283 u32 xcvrdiag; 284 #define FORCE_HIGH_SPEED_MODE 31 285 #define FORCE_FULL_SPEED_MODE 30 286 #define USB_TEST_MODE 24 287 #define LINE_STATE 16 288 #define TRANSCEIVER_OPERATION_MODE 2 289 #define TRANSCEIVER_SELECT 1 290 #define TERMINATION_SELECT 0 291 u32 setup0123; 292 u32 setup4567; 293 /* offset 0x0090 */ 294 u32 _unused0; 295 u32 ouraddr; 296 #define FORCE_IMMEDIATE 7 297 #define OUR_USB_ADDRESS 0 298 u32 ourconfig; 299 } __attribute__ ((packed)); 300 301 /* pci control, BAR0 + 0x0100 */ 302 struct net2280_pci_regs { 303 /* offset 0x0100 */ 304 u32 pcimstctl; 305 #define PCI_ARBITER_PARK_SELECT 13 306 #define PCI_MULTI LEVEL_ARBITER 12 307 #define PCI_RETRY_ABORT_ENABLE 11 308 #define DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE 10 309 #define DMA_READ_MULTIPLE_ENABLE 9 310 #define DMA_READ_LINE_ENABLE 8 311 #define PCI_MASTER_COMMAND_SELECT 6 312 #define MEM_READ_OR_WRITE 0 313 #define IO_READ_OR_WRITE 1 314 #define CFG_READ_OR_WRITE 2 315 #define PCI_MASTER_START 5 316 #define PCI_MASTER_READ_WRITE 4 317 #define PCI_MASTER_WRITE 0 318 #define PCI_MASTER_READ 1 319 #define PCI_MASTER_BYTE_WRITE_ENABLES 0 320 u32 pcimstaddr; 321 u32 pcimstdata; 322 u32 pcimststat; 323 #define PCI_ARBITER_CLEAR 2 324 #define PCI_EXTERNAL_ARBITER 1 325 #define PCI_HOST_MODE 0 326 } __attribute__ ((packed)); 327 328 /* dma control, BAR0 + 0x0180 ... array of four structs like this, 329 * for channels 0..3. see also struct net2280_dma: descriptor 330 * that can be loaded into some of these registers. 331 */ 332 struct net2280_dma_regs { /* [11.7] */ 333 /* offset 0x0180, 0x01a0, 0x01c0, 0x01e0, */ 334 u32 dmactl; 335 #define DMA_SCATTER_GATHER_DONE_INTERRUPT_ENABLE 25 336 #define DMA_CLEAR_COUNT_ENABLE 21 337 #define DESCRIPTOR_POLLING_RATE 19 338 #define POLL_CONTINUOUS 0 339 #define POLL_1_USEC 1 340 #define POLL_100_USEC 2 341 #define POLL_1_MSEC 3 342 #define DMA_VALID_BIT_POLLING_ENABLE 18 343 #define DMA_VALID_BIT_ENABLE 17 344 #define DMA_SCATTER_GATHER_ENABLE 16 345 #define DMA_OUT_AUTO_START_ENABLE 4 346 #define DMA_PREEMPT_ENABLE 3 347 #define DMA_FIFO_VALIDATE 2 348 #define DMA_ENABLE 1 349 #define DMA_ADDRESS_HOLD 0 350 u32 dmastat; 351 #define DMA_ABORT_DONE_INTERRUPT 27 352 #define DMA_SCATTER_GATHER_DONE_INTERRUPT 25 353 #define DMA_TRANSACTION_DONE_INTERRUPT 24 354 #define DMA_ABORT 1 355 #define DMA_START 0 356 u32 _unused0[2]; 357 /* offset 0x0190, 0x01b0, 0x01d0, 0x01f0, */ 358 u32 dmacount; 359 #define VALID_BIT 31 360 #define DMA_DIRECTION 30 361 #define DMA_DONE_INTERRUPT_ENABLE 29 362 #define END_OF_CHAIN 28 363 #define DMA_BYTE_COUNT_MASK ((1<<24)-1) 364 #define DMA_BYTE_COUNT 0 365 u32 dmaaddr; 366 u32 dmadesc; 367 u32 _unused1; 368 } __attribute__ ((packed)); 369 370 /* dedicated endpoint registers, BAR0 + 0x0200 */ 371 372 struct net2280_dep_regs { /* [11.8] */ 373 /* offset 0x0200, 0x0210, 0x220, 0x230, 0x240 */ 374 u32 dep_cfg; 375 /* offset 0x0204, 0x0214, 0x224, 0x234, 0x244 */ 376 u32 dep_rsp; 377 u32 _unused[2]; 378 } __attribute__ ((packed)); 379 380 /* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs 381 * like this, for ep0 then the configurable endpoints A..F 382 * ep0 reserved for control; E and F have only 64 bytes of fifo 383 */ 384 struct net2280_ep_regs { /* [11.9] */ 385 /* offset 0x0300, 0x0320, 0x0340, 0x0360, 0x0380, 0x03a0, 0x03c0 */ 386 u32 ep_cfg; 387 #define ENDPOINT_BYTE_COUNT 16 388 #define ENDPOINT_ENABLE 10 389 #define ENDPOINT_TYPE 8 390 #define ENDPOINT_DIRECTION 7 391 #define ENDPOINT_NUMBER 0 392 u32 ep_rsp; 393 #define SET_NAK_OUT_PACKETS 15 394 #define SET_EP_HIDE_STATUS_PHASE 14 395 #define SET_EP_FORCE_CRC_ERROR 13 396 #define SET_INTERRUPT_MODE 12 397 #define SET_CONTROL_STATUS_PHASE_HANDSHAKE 11 398 #define SET_NAK_OUT_PACKETS_MODE 10 399 #define SET_ENDPOINT_TOGGLE 9 400 #define SET_ENDPOINT_HALT 8 401 #define CLEAR_NAK_OUT_PACKETS 7 402 #define CLEAR_EP_HIDE_STATUS_PHASE 6 403 #define CLEAR_EP_FORCE_CRC_ERROR 5 404 #define CLEAR_INTERRUPT_MODE 4 405 #define CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE 3 406 #define CLEAR_NAK_OUT_PACKETS_MODE 2 407 #define CLEAR_ENDPOINT_TOGGLE 1 408 #define CLEAR_ENDPOINT_HALT 0 409 u32 ep_irqenb; 410 #define SHORT_PACKET_OUT_DONE_INTERRUPT_ENABLE 6 411 #define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE 5 412 #define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE 3 413 #define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE 2 414 #define DATA_OUT_PING_TOKEN_INTERRUPT_ENABLE 1 415 #define DATA_IN_TOKEN_INTERRUPT_ENABLE 0 416 u32 ep_stat; 417 #define FIFO_VALID_COUNT 24 418 #define HIGH_BANDWIDTH_OUT_TRANSACTION_PID 22 419 #define TIMEOUT 21 420 #define USB_STALL_SENT 20 421 #define USB_IN_NAK_SENT 19 422 #define USB_IN_ACK_RCVD 18 423 #define USB_OUT_PING_NAK_SENT 17 424 #define USB_OUT_ACK_SENT 16 425 #define FIFO_OVERFLOW 13 426 #define FIFO_UNDERFLOW 12 427 #define FIFO_FULL 11 428 #define FIFO_EMPTY 10 429 #define FIFO_FLUSH 9 430 #define SHORT_PACKET_OUT_DONE_INTERRUPT 6 431 #define SHORT_PACKET_TRANSFERRED_INTERRUPT 5 432 #define NAK_OUT_PACKETS 4 433 #define DATA_PACKET_RECEIVED_INTERRUPT 3 434 #define DATA_PACKET_TRANSMITTED_INTERRUPT 2 435 #define DATA_OUT_PING_TOKEN_INTERRUPT 1 436 #define DATA_IN_TOKEN_INTERRUPT 0 437 /* offset 0x0310, 0x0330, 0x0350, 0x0370, 0x0390, 0x03b0, 0x03d0 */ 438 u32 ep_avail; 439 u32 ep_data; 440 u32 _unused0[2]; 441 } __attribute__ ((packed)); 442 443 #endif /* __LINUX_USB_NET2280_H */ 444