xref: /openbmc/linux/include/linux/tegra-icc.h (revision 9a38cb27)
1*9a38cb27SSumit Gupta /* SPDX-License-Identifier: GPL-2.0-only */
2*9a38cb27SSumit Gupta /*
3*9a38cb27SSumit Gupta  * Copyright (C) 2022-2023 NVIDIA CORPORATION.  All rights reserved.
4*9a38cb27SSumit Gupta  */
5*9a38cb27SSumit Gupta 
6*9a38cb27SSumit Gupta #ifndef LINUX_TEGRA_ICC_H
7*9a38cb27SSumit Gupta #define LINUX_TEGRA_ICC_H
8*9a38cb27SSumit Gupta 
9*9a38cb27SSumit Gupta enum tegra_icc_client_type {
10*9a38cb27SSumit Gupta 	TEGRA_ICC_NONE,
11*9a38cb27SSumit Gupta 	TEGRA_ICC_NISO,
12*9a38cb27SSumit Gupta 	TEGRA_ICC_ISO_DISPLAY,
13*9a38cb27SSumit Gupta 	TEGRA_ICC_ISO_VI,
14*9a38cb27SSumit Gupta 	TEGRA_ICC_ISO_AUDIO,
15*9a38cb27SSumit Gupta 	TEGRA_ICC_ISO_VIFAL,
16*9a38cb27SSumit Gupta };
17*9a38cb27SSumit Gupta 
18*9a38cb27SSumit Gupta /* ICC ID's for MC client's used in BPMP */
19*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_DEBUG		1
20*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_CPU_CLUSTER0	2
21*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_CPU_CLUSTER1	3
22*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_CPU_CLUSTER2	4
23*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_GPU		5
24*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_CACTMON		6
25*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_DISPLAY		7
26*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_VI		8
27*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_EQOS		9
28*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_PCIE_0		10
29*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_PCIE_1		11
30*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_PCIE_2		12
31*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_PCIE_3		13
32*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_PCIE_4		14
33*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_PCIE_5		15
34*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_PCIE_6		16
35*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_PCIE_7		17
36*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_PCIE_8		18
37*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_PCIE_9		19
38*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_PCIE_10		20
39*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_DLA_0		21
40*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_DLA_1		22
41*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_SDMMC_1		23
42*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_SDMMC_2		24
43*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_SDMMC_3		25
44*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_SDMMC_4		26
45*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_NVDEC		27
46*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_NVENC		28
47*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_NVJPG_0		29
48*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_NVJPG_1		30
49*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_OFAA		31
50*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_XUSB_HOST	32
51*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_XUSB_DEV		33
52*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_TSEC		34
53*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_VIC		35
54*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_APE		36
55*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_APEDMA		37
56*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_SE		38
57*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_ISP		39
58*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_HDA		40
59*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_VIFAL		41
60*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_VI2FAL		42
61*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_VI2		43
62*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_RCE		44
63*9a38cb27SSumit Gupta #define TEGRA_ICC_BPMP_PVA		45
64*9a38cb27SSumit Gupta 
65*9a38cb27SSumit Gupta #endif /* LINUX_TEGRA_ICC_H */
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