1 #ifndef __SUNGEM_PHY_H__ 2 #define __SUNGEM_PHY_H__ 3 4 struct mii_phy; 5 6 /* Operations supported by any kind of PHY */ 7 struct mii_phy_ops 8 { 9 int (*init)(struct mii_phy *phy); 10 int (*suspend)(struct mii_phy *phy); 11 int (*setup_aneg)(struct mii_phy *phy, u32 advertise); 12 int (*setup_forced)(struct mii_phy *phy, int speed, int fd); 13 int (*poll_link)(struct mii_phy *phy); 14 int (*read_link)(struct mii_phy *phy); 15 int (*enable_fiber)(struct mii_phy *phy, int autoneg); 16 }; 17 18 /* Structure used to statically define an mii/gii based PHY */ 19 struct mii_phy_def 20 { 21 u32 phy_id; /* Concatenated ID1 << 16 | ID2 */ 22 u32 phy_id_mask; /* Significant bits */ 23 u32 features; /* Ethtool SUPPORTED_* defines */ 24 int magic_aneg; /* Autoneg does all speed test for us */ 25 const char* name; 26 const struct mii_phy_ops* ops; 27 }; 28 29 enum { 30 BCM54XX_COPPER, 31 BCM54XX_FIBER, 32 BCM54XX_GBIC, 33 BCM54XX_SGMII, 34 BCM54XX_UNKNOWN, 35 }; 36 37 /* An instance of a PHY, partially borrowed from mii_if_info */ 38 struct mii_phy 39 { 40 struct mii_phy_def* def; 41 u32 advertising; 42 int mii_id; 43 44 /* 1: autoneg enabled, 0: disabled */ 45 int autoneg; 46 47 /* forced speed & duplex (no autoneg) 48 * partner speed & duplex & pause (autoneg) 49 */ 50 int speed; 51 int duplex; 52 int pause; 53 54 /* Provided by host chip */ 55 struct net_device *dev; 56 int (*mdio_read) (struct net_device *dev, int mii_id, int reg); 57 void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val); 58 void *platform_data; 59 }; 60 61 /* Pass in a struct mii_phy with dev, mdio_read and mdio_write 62 * filled, the remaining fields will be filled on return 63 */ 64 extern int sungem_phy_probe(struct mii_phy *phy, int mii_id); 65 66 67 /* MII definitions missing from mii.h */ 68 69 #define BMCR_SPD2 0x0040 /* Gigabit enable (bcm54xx) */ 70 #define LPA_PAUSE 0x0400 71 72 /* More PHY registers (model specific) */ 73 74 /* MII BCM5201 MULTIPHY interrupt register */ 75 #define MII_BCM5201_INTERRUPT 0x1A 76 #define MII_BCM5201_INTERRUPT_INTENABLE 0x4000 77 78 #define MII_BCM5201_AUXMODE2 0x1B 79 #define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008 80 81 #define MII_BCM5201_MULTIPHY 0x1E 82 83 /* MII BCM5201 MULTIPHY register bits */ 84 #define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002 85 #define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008 86 87 /* MII BCM5221 Additional registers */ 88 #define MII_BCM5221_TEST 0x1f 89 #define MII_BCM5221_TEST_ENABLE_SHADOWS 0x0080 90 #define MII_BCM5221_SHDOW_AUX_STAT2 0x1b 91 #define MII_BCM5221_SHDOW_AUX_STAT2_APD 0x0020 92 #define MII_BCM5221_SHDOW_AUX_MODE4 0x1a 93 #define MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE 0x0001 94 #define MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR 0x0004 95 96 /* MII BCM5241 Additional registers */ 97 #define MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR 0x0008 98 99 /* MII BCM5400 1000-BASET Control register */ 100 #define MII_BCM5400_GB_CONTROL 0x09 101 #define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200 102 103 /* MII BCM5400 AUXCONTROL register */ 104 #define MII_BCM5400_AUXCONTROL 0x18 105 #define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004 106 107 /* MII BCM5400 AUXSTATUS register */ 108 #define MII_BCM5400_AUXSTATUS 0x19 109 #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700 110 #define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8 111 112 /* 1000BT control (Marvell & BCM54xx at least) */ 113 #define MII_1000BASETCONTROL 0x09 114 #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 115 #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100 116 117 /* Marvell 88E1011 PHY control */ 118 #define MII_M1011_PHY_SPEC_CONTROL 0x10 119 #define MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX 0x20 120 #define MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX 0x40 121 122 /* Marvell 88E1011 PHY status */ 123 #define MII_M1011_PHY_SPEC_STATUS 0x11 124 #define MII_M1011_PHY_SPEC_STATUS_1000 0x8000 125 #define MII_M1011_PHY_SPEC_STATUS_100 0x4000 126 #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000 127 #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000 128 #define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800 129 #define MII_M1011_PHY_SPEC_STATUS_TX_PAUSE 0x0008 130 #define MII_M1011_PHY_SPEC_STATUS_RX_PAUSE 0x0004 131 132 #endif /* __SUNGEM_PHY_H__ */ 133