1 /* SPDX-License-Identifier: GPL-2.0-or-later 2 * 3 * Copyright (C) 2005 David Brownell 4 */ 5 6 #ifndef __LINUX_SPI_H 7 #define __LINUX_SPI_H 8 9 #include <linux/bits.h> 10 #include <linux/device.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/slab.h> 13 #include <linux/kthread.h> 14 #include <linux/completion.h> 15 #include <linux/scatterlist.h> 16 #include <linux/gpio/consumer.h> 17 18 #include <uapi/linux/spi/spi.h> 19 #include <linux/acpi.h> 20 21 struct dma_chan; 22 struct software_node; 23 struct ptp_system_timestamp; 24 struct spi_controller; 25 struct spi_transfer; 26 struct spi_controller_mem_ops; 27 struct spi_controller_mem_caps; 28 29 /* 30 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, 31 * and SPI infrastructure. 32 */ 33 extern struct bus_type spi_bus_type; 34 35 /** 36 * struct spi_statistics - statistics for spi transfers 37 * @lock: lock protecting this structure 38 * 39 * @messages: number of spi-messages handled 40 * @transfers: number of spi_transfers handled 41 * @errors: number of errors during spi_transfer 42 * @timedout: number of timeouts during spi_transfer 43 * 44 * @spi_sync: number of times spi_sync is used 45 * @spi_sync_immediate: 46 * number of times spi_sync is executed immediately 47 * in calling context without queuing and scheduling 48 * @spi_async: number of times spi_async is used 49 * 50 * @bytes: number of bytes transferred to/from device 51 * @bytes_tx: number of bytes sent to device 52 * @bytes_rx: number of bytes received from device 53 * 54 * @transfer_bytes_histo: 55 * transfer bytes histogramm 56 * 57 * @transfers_split_maxsize: 58 * number of transfers that have been split because of 59 * maxsize limit 60 */ 61 struct spi_statistics { 62 spinlock_t lock; /* lock for the whole structure */ 63 64 unsigned long messages; 65 unsigned long transfers; 66 unsigned long errors; 67 unsigned long timedout; 68 69 unsigned long spi_sync; 70 unsigned long spi_sync_immediate; 71 unsigned long spi_async; 72 73 unsigned long long bytes; 74 unsigned long long bytes_rx; 75 unsigned long long bytes_tx; 76 77 #define SPI_STATISTICS_HISTO_SIZE 17 78 unsigned long transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE]; 79 80 unsigned long transfers_split_maxsize; 81 }; 82 83 #define SPI_STATISTICS_ADD_TO_FIELD(stats, field, count) \ 84 do { \ 85 unsigned long flags; \ 86 spin_lock_irqsave(&(stats)->lock, flags); \ 87 (stats)->field += count; \ 88 spin_unlock_irqrestore(&(stats)->lock, flags); \ 89 } while (0) 90 91 #define SPI_STATISTICS_INCREMENT_FIELD(stats, field) \ 92 SPI_STATISTICS_ADD_TO_FIELD(stats, field, 1) 93 94 /** 95 * struct spi_delay - SPI delay information 96 * @value: Value for the delay 97 * @unit: Unit for the delay 98 */ 99 struct spi_delay { 100 #define SPI_DELAY_UNIT_USECS 0 101 #define SPI_DELAY_UNIT_NSECS 1 102 #define SPI_DELAY_UNIT_SCK 2 103 u16 value; 104 u8 unit; 105 }; 106 107 extern int spi_delay_to_ns(struct spi_delay *_delay, struct spi_transfer *xfer); 108 extern int spi_delay_exec(struct spi_delay *_delay, struct spi_transfer *xfer); 109 110 /** 111 * struct spi_device - Controller side proxy for an SPI slave device 112 * @dev: Driver model representation of the device. 113 * @controller: SPI controller used with the device. 114 * @master: Copy of controller, for backwards compatibility. 115 * @max_speed_hz: Maximum clock rate to be used with this chip 116 * (on this board); may be changed by the device's driver. 117 * The spi_transfer.speed_hz can override this for each transfer. 118 * @chip_select: Chipselect, distinguishing chips handled by @controller. 119 * @mode: The spi mode defines how data is clocked out and in. 120 * This may be changed by the device's driver. 121 * The "active low" default for chipselect mode can be overridden 122 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for 123 * each word in a transfer (by specifying SPI_LSB_FIRST). 124 * @bits_per_word: Data transfers involve one or more words; word sizes 125 * like eight or 12 bits are common. In-memory wordsizes are 126 * powers of two bytes (e.g. 20 bit samples use 32 bits). 127 * This may be changed by the device's driver, or left at the 128 * default (0) indicating protocol words are eight bit bytes. 129 * The spi_transfer.bits_per_word can override this for each transfer. 130 * @rt: Make the pump thread real time priority. 131 * @irq: Negative, or the number passed to request_irq() to receive 132 * interrupts from this device. 133 * @controller_state: Controller's runtime state 134 * @controller_data: Board-specific definitions for controller, such as 135 * FIFO initialization parameters; from board_info.controller_data 136 * @modalias: Name of the driver to use with this device, or an alias 137 * for that name. This appears in the sysfs "modalias" attribute 138 * for driver coldplugging, and in uevents used for hotplugging 139 * @driver_override: If the name of a driver is written to this attribute, then 140 * the device will bind to the named driver and only the named driver. 141 * @cs_gpiod: gpio descriptor of the chipselect line (optional, NULL when 142 * not using a GPIO line) 143 * @word_delay: delay to be inserted between consecutive 144 * words of a transfer 145 * @cs_setup: delay to be introduced by the controller after CS is asserted 146 * @cs_hold: delay to be introduced by the controller before CS is deasserted 147 * @cs_inactive: delay to be introduced by the controller after CS is 148 * deasserted. If @cs_change_delay is used from @spi_transfer, then the 149 * two delays will be added up. 150 * @statistics: statistics for the spi_device 151 * 152 * A @spi_device is used to interchange data between an SPI slave 153 * (usually a discrete chip) and CPU memory. 154 * 155 * In @dev, the platform_data is used to hold information about this 156 * device that's meaningful to the device's protocol driver, but not 157 * to its controller. One example might be an identifier for a chip 158 * variant with slightly different functionality; another might be 159 * information about how this particular board wires the chip's pins. 160 */ 161 struct spi_device { 162 struct device dev; 163 struct spi_controller *controller; 164 struct spi_controller *master; /* compatibility layer */ 165 u32 max_speed_hz; 166 u8 chip_select; 167 u8 bits_per_word; 168 bool rt; 169 #define SPI_NO_TX BIT(31) /* no transmit wire */ 170 #define SPI_NO_RX BIT(30) /* no receive wire */ 171 /* 172 * All bits defined above should be covered by SPI_MODE_KERNEL_MASK. 173 * The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart, 174 * which is defined in 'include/uapi/linux/spi/spi.h'. 175 * The bits defined here are from bit 31 downwards, while in 176 * SPI_MODE_USER_MASK are from 0 upwards. 177 * These bits must not overlap. A static assert check should make sure of that. 178 * If adding extra bits, make sure to decrease the bit index below as well. 179 */ 180 #define SPI_MODE_KERNEL_MASK (~(BIT(30) - 1)) 181 u32 mode; 182 int irq; 183 void *controller_state; 184 void *controller_data; 185 char modalias[SPI_NAME_SIZE]; 186 const char *driver_override; 187 struct gpio_desc *cs_gpiod; /* chip select gpio desc */ 188 struct spi_delay word_delay; /* inter-word delay */ 189 /* CS delays */ 190 struct spi_delay cs_setup; 191 struct spi_delay cs_hold; 192 struct spi_delay cs_inactive; 193 194 /* the statistics */ 195 struct spi_statistics statistics; 196 197 /* 198 * likely need more hooks for more protocol options affecting how 199 * the controller talks to each chip, like: 200 * - memory packing (12 bit samples into low bits, others zeroed) 201 * - priority 202 * - chipselect delays 203 * - ... 204 */ 205 }; 206 207 /* Make sure that SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK don't overlap */ 208 static_assert((SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK) == 0, 209 "SPI_MODE_USER_MASK & SPI_MODE_KERNEL_MASK must not overlap"); 210 211 static inline struct spi_device *to_spi_device(struct device *dev) 212 { 213 return dev ? container_of(dev, struct spi_device, dev) : NULL; 214 } 215 216 /* most drivers won't need to care about device refcounting */ 217 static inline struct spi_device *spi_dev_get(struct spi_device *spi) 218 { 219 return (spi && get_device(&spi->dev)) ? spi : NULL; 220 } 221 222 static inline void spi_dev_put(struct spi_device *spi) 223 { 224 if (spi) 225 put_device(&spi->dev); 226 } 227 228 /* ctldata is for the bus_controller driver's runtime state */ 229 static inline void *spi_get_ctldata(struct spi_device *spi) 230 { 231 return spi->controller_state; 232 } 233 234 static inline void spi_set_ctldata(struct spi_device *spi, void *state) 235 { 236 spi->controller_state = state; 237 } 238 239 /* device driver data */ 240 241 static inline void spi_set_drvdata(struct spi_device *spi, void *data) 242 { 243 dev_set_drvdata(&spi->dev, data); 244 } 245 246 static inline void *spi_get_drvdata(struct spi_device *spi) 247 { 248 return dev_get_drvdata(&spi->dev); 249 } 250 251 struct spi_message; 252 253 /** 254 * struct spi_driver - Host side "protocol" driver 255 * @id_table: List of SPI devices supported by this driver 256 * @probe: Binds this driver to the spi device. Drivers can verify 257 * that the device is actually present, and may need to configure 258 * characteristics (such as bits_per_word) which weren't needed for 259 * the initial configuration done during system setup. 260 * @remove: Unbinds this driver from the spi device 261 * @shutdown: Standard shutdown callback used during system state 262 * transitions such as powerdown/halt and kexec 263 * @driver: SPI device drivers should initialize the name and owner 264 * field of this structure. 265 * 266 * This represents the kind of device driver that uses SPI messages to 267 * interact with the hardware at the other end of a SPI link. It's called 268 * a "protocol" driver because it works through messages rather than talking 269 * directly to SPI hardware (which is what the underlying SPI controller 270 * driver does to pass those messages). These protocols are defined in the 271 * specification for the device(s) supported by the driver. 272 * 273 * As a rule, those device protocols represent the lowest level interface 274 * supported by a driver, and it will support upper level interfaces too. 275 * Examples of such upper levels include frameworks like MTD, networking, 276 * MMC, RTC, filesystem character device nodes, and hardware monitoring. 277 */ 278 struct spi_driver { 279 const struct spi_device_id *id_table; 280 int (*probe)(struct spi_device *spi); 281 void (*remove)(struct spi_device *spi); 282 void (*shutdown)(struct spi_device *spi); 283 struct device_driver driver; 284 }; 285 286 static inline struct spi_driver *to_spi_driver(struct device_driver *drv) 287 { 288 return drv ? container_of(drv, struct spi_driver, driver) : NULL; 289 } 290 291 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv); 292 293 /** 294 * spi_unregister_driver - reverse effect of spi_register_driver 295 * @sdrv: the driver to unregister 296 * Context: can sleep 297 */ 298 static inline void spi_unregister_driver(struct spi_driver *sdrv) 299 { 300 if (sdrv) 301 driver_unregister(&sdrv->driver); 302 } 303 304 extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 chip_select); 305 306 /* use a define to avoid include chaining to get THIS_MODULE */ 307 #define spi_register_driver(driver) \ 308 __spi_register_driver(THIS_MODULE, driver) 309 310 /** 311 * module_spi_driver() - Helper macro for registering a SPI driver 312 * @__spi_driver: spi_driver struct 313 * 314 * Helper macro for SPI drivers which do not do anything special in module 315 * init/exit. This eliminates a lot of boilerplate. Each module may only 316 * use this macro once, and calling it replaces module_init() and module_exit() 317 */ 318 #define module_spi_driver(__spi_driver) \ 319 module_driver(__spi_driver, spi_register_driver, \ 320 spi_unregister_driver) 321 322 /** 323 * struct spi_controller - interface to SPI master or slave controller 324 * @dev: device interface to this driver 325 * @list: link with the global spi_controller list 326 * @bus_num: board-specific (and often SOC-specific) identifier for a 327 * given SPI controller. 328 * @num_chipselect: chipselects are used to distinguish individual 329 * SPI slaves, and are numbered from zero to num_chipselects. 330 * each slave has a chipselect signal, but it's common that not 331 * every chipselect is connected to a slave. 332 * @dma_alignment: SPI controller constraint on DMA buffers alignment. 333 * @mode_bits: flags understood by this controller driver 334 * @buswidth_override_bits: flags to override for this controller driver 335 * @bits_per_word_mask: A mask indicating which values of bits_per_word are 336 * supported by the driver. Bit n indicates that a bits_per_word n+1 is 337 * supported. If set, the SPI core will reject any transfer with an 338 * unsupported bits_per_word. If not set, this value is simply ignored, 339 * and it's up to the individual driver to perform any validation. 340 * @min_speed_hz: Lowest supported transfer speed 341 * @max_speed_hz: Highest supported transfer speed 342 * @flags: other constraints relevant to this driver 343 * @slave: indicates that this is an SPI slave controller 344 * @devm_allocated: whether the allocation of this struct is devres-managed 345 * @max_transfer_size: function that returns the max transfer size for 346 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 347 * @max_message_size: function that returns the max message size for 348 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 349 * @io_mutex: mutex for physical bus access 350 * @bus_lock_spinlock: spinlock for SPI bus locking 351 * @bus_lock_mutex: mutex for exclusion of multiple callers 352 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use 353 * @setup: updates the device mode and clocking records used by a 354 * device's SPI controller; protocol code may call this. This 355 * must fail if an unrecognized or unsupported mode is requested. 356 * It's always safe to call this unless transfers are pending on 357 * the device whose settings are being modified. 358 * @set_cs_timing: optional hook for SPI devices to request SPI master 359 * controller for configuring specific CS setup time, hold time and inactive 360 * delay interms of clock counts 361 * @transfer: adds a message to the controller's transfer queue. 362 * @cleanup: frees controller-specific state 363 * @can_dma: determine whether this controller supports DMA 364 * @queued: whether this controller is providing an internal message queue 365 * @kworker: pointer to thread struct for message pump 366 * @pump_messages: work struct for scheduling work to the message pump 367 * @queue_lock: spinlock to syncronise access to message queue 368 * @queue: message queue 369 * @idling: the device is entering idle state 370 * @cur_msg: the currently in-flight message 371 * @cur_msg_prepared: spi_prepare_message was called for the currently 372 * in-flight message 373 * @cur_msg_mapped: message has been mapped for DMA 374 * @last_cs: the last chip_select that is recorded by set_cs, -1 on non chip 375 * selected 376 * @last_cs_mode_high: was (mode & SPI_CS_HIGH) true on the last call to set_cs. 377 * @xfer_completion: used by core transfer_one_message() 378 * @busy: message pump is busy 379 * @running: message pump is running 380 * @rt: whether this queue is set to run as a realtime task 381 * @auto_runtime_pm: the core should ensure a runtime PM reference is held 382 * while the hardware is prepared, using the parent 383 * device for the spidev 384 * @max_dma_len: Maximum length of a DMA transfer for the device. 385 * @prepare_transfer_hardware: a message will soon arrive from the queue 386 * so the subsystem requests the driver to prepare the transfer hardware 387 * by issuing this call 388 * @transfer_one_message: the subsystem calls the driver to transfer a single 389 * message while queuing transfers that arrive in the meantime. When the 390 * driver is finished with this message, it must call 391 * spi_finalize_current_message() so the subsystem can issue the next 392 * message 393 * @unprepare_transfer_hardware: there are currently no more messages on the 394 * queue so the subsystem notifies the driver that it may relax the 395 * hardware by issuing this call 396 * 397 * @set_cs: set the logic level of the chip select line. May be called 398 * from interrupt context. 399 * @prepare_message: set up the controller to transfer a single message, 400 * for example doing DMA mapping. Called from threaded 401 * context. 402 * @transfer_one: transfer a single spi_transfer. 403 * 404 * - return 0 if the transfer is finished, 405 * - return 1 if the transfer is still in progress. When 406 * the driver is finished with this transfer it must 407 * call spi_finalize_current_transfer() so the subsystem 408 * can issue the next transfer. Note: transfer_one and 409 * transfer_one_message are mutually exclusive; when both 410 * are set, the generic subsystem does not call your 411 * transfer_one callback. 412 * @handle_err: the subsystem calls the driver to handle an error that occurs 413 * in the generic implementation of transfer_one_message(). 414 * @mem_ops: optimized/dedicated operations for interactions with SPI memory. 415 * This field is optional and should only be implemented if the 416 * controller has native support for memory like operations. 417 * @mem_caps: controller capabilities for the handling of memory operations. 418 * @unprepare_message: undo any work done by prepare_message(). 419 * @slave_abort: abort the ongoing transfer request on an SPI slave controller 420 * @cs_gpiods: Array of GPIO descs to use as chip select lines; one per CS 421 * number. Any individual value may be NULL for CS lines that 422 * are not GPIOs (driven by the SPI controller itself). 423 * @use_gpio_descriptors: Turns on the code in the SPI core to parse and grab 424 * GPIO descriptors. This will fill in @cs_gpiods and SPI devices will have 425 * the cs_gpiod assigned if a GPIO line is found for the chipselect. 426 * @unused_native_cs: When cs_gpiods is used, spi_register_controller() will 427 * fill in this field with the first unused native CS, to be used by SPI 428 * controller drivers that need to drive a native CS when using GPIO CS. 429 * @max_native_cs: When cs_gpiods is used, and this field is filled in, 430 * spi_register_controller() will validate all native CS (including the 431 * unused native CS) against this value. 432 * @statistics: statistics for the spi_controller 433 * @dma_tx: DMA transmit channel 434 * @dma_rx: DMA receive channel 435 * @dummy_rx: dummy receive buffer for full-duplex devices 436 * @dummy_tx: dummy transmit buffer for full-duplex devices 437 * @fw_translate_cs: If the boot firmware uses different numbering scheme 438 * what Linux expects, this optional hook can be used to translate 439 * between the two. 440 * @ptp_sts_supported: If the driver sets this to true, it must provide a 441 * time snapshot in @spi_transfer->ptp_sts as close as possible to the 442 * moment in time when @spi_transfer->ptp_sts_word_pre and 443 * @spi_transfer->ptp_sts_word_post were transmitted. 444 * If the driver does not set this, the SPI core takes the snapshot as 445 * close to the driver hand-over as possible. 446 * @irq_flags: Interrupt enable state during PTP system timestamping 447 * @fallback: fallback to pio if dma transfer return failure with 448 * SPI_TRANS_FAIL_NO_START. 449 * 450 * Each SPI controller can communicate with one or more @spi_device 451 * children. These make a small bus, sharing MOSI, MISO and SCK signals 452 * but not chip select signals. Each device may be configured to use a 453 * different clock rate, since those shared signals are ignored unless 454 * the chip is selected. 455 * 456 * The driver for an SPI controller manages access to those devices through 457 * a queue of spi_message transactions, copying data between CPU memory and 458 * an SPI slave device. For each such message it queues, it calls the 459 * message's completion function when the transaction completes. 460 */ 461 struct spi_controller { 462 struct device dev; 463 464 struct list_head list; 465 466 /* other than negative (== assign one dynamically), bus_num is fully 467 * board-specific. usually that simplifies to being SOC-specific. 468 * example: one SOC has three SPI controllers, numbered 0..2, 469 * and one board's schematics might show it using SPI-2. software 470 * would normally use bus_num=2 for that controller. 471 */ 472 s16 bus_num; 473 474 /* chipselects will be integral to many controllers; some others 475 * might use board-specific GPIOs. 476 */ 477 u16 num_chipselect; 478 479 /* some SPI controllers pose alignment requirements on DMAable 480 * buffers; let protocol drivers know about these requirements. 481 */ 482 u16 dma_alignment; 483 484 /* spi_device.mode flags understood by this controller driver */ 485 u32 mode_bits; 486 487 /* spi_device.mode flags override flags for this controller */ 488 u32 buswidth_override_bits; 489 490 /* bitmask of supported bits_per_word for transfers */ 491 u32 bits_per_word_mask; 492 #define SPI_BPW_MASK(bits) BIT((bits) - 1) 493 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1) 494 495 /* limits on transfer speed */ 496 u32 min_speed_hz; 497 u32 max_speed_hz; 498 499 /* other constraints relevant to this driver */ 500 u16 flags; 501 #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* can't do full duplex */ 502 #define SPI_CONTROLLER_NO_RX BIT(1) /* can't do buffer read */ 503 #define SPI_CONTROLLER_NO_TX BIT(2) /* can't do buffer write */ 504 #define SPI_CONTROLLER_MUST_RX BIT(3) /* requires rx */ 505 #define SPI_CONTROLLER_MUST_TX BIT(4) /* requires tx */ 506 507 #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */ 508 509 /* flag indicating if the allocation of this struct is devres-managed */ 510 bool devm_allocated; 511 512 /* flag indicating this is an SPI slave controller */ 513 bool slave; 514 515 /* 516 * on some hardware transfer / message size may be constrained 517 * the limit may depend on device transfer settings 518 */ 519 size_t (*max_transfer_size)(struct spi_device *spi); 520 size_t (*max_message_size)(struct spi_device *spi); 521 522 /* I/O mutex */ 523 struct mutex io_mutex; 524 525 /* Used to avoid adding the same CS twice */ 526 struct mutex add_lock; 527 528 /* lock and mutex for SPI bus locking */ 529 spinlock_t bus_lock_spinlock; 530 struct mutex bus_lock_mutex; 531 532 /* flag indicating that the SPI bus is locked for exclusive use */ 533 bool bus_lock_flag; 534 535 /* Setup mode and clock, etc (spi driver may call many times). 536 * 537 * IMPORTANT: this may be called when transfers to another 538 * device are active. DO NOT UPDATE SHARED REGISTERS in ways 539 * which could break those transfers. 540 */ 541 int (*setup)(struct spi_device *spi); 542 543 /* 544 * set_cs_timing() method is for SPI controllers that supports 545 * configuring CS timing. 546 * 547 * This hook allows SPI client drivers to request SPI controllers 548 * to configure specific CS timing through spi_set_cs_timing() after 549 * spi_setup(). 550 */ 551 int (*set_cs_timing)(struct spi_device *spi); 552 553 /* bidirectional bulk transfers 554 * 555 * + The transfer() method may not sleep; its main role is 556 * just to add the message to the queue. 557 * + For now there's no remove-from-queue operation, or 558 * any other request management 559 * + To a given spi_device, message queueing is pure fifo 560 * 561 * + The controller's main job is to process its message queue, 562 * selecting a chip (for masters), then transferring data 563 * + If there are multiple spi_device children, the i/o queue 564 * arbitration algorithm is unspecified (round robin, fifo, 565 * priority, reservations, preemption, etc) 566 * 567 * + Chipselect stays active during the entire message 568 * (unless modified by spi_transfer.cs_change != 0). 569 * + The message transfers use clock and SPI mode parameters 570 * previously established by setup() for this device 571 */ 572 int (*transfer)(struct spi_device *spi, 573 struct spi_message *mesg); 574 575 /* called on release() to free memory provided by spi_controller */ 576 void (*cleanup)(struct spi_device *spi); 577 578 /* 579 * Used to enable core support for DMA handling, if can_dma() 580 * exists and returns true then the transfer will be mapped 581 * prior to transfer_one() being called. The driver should 582 * not modify or store xfer and dma_tx and dma_rx must be set 583 * while the device is prepared. 584 */ 585 bool (*can_dma)(struct spi_controller *ctlr, 586 struct spi_device *spi, 587 struct spi_transfer *xfer); 588 struct device *dma_map_dev; 589 590 /* 591 * These hooks are for drivers that want to use the generic 592 * controller transfer queueing mechanism. If these are used, the 593 * transfer() function above must NOT be specified by the driver. 594 * Over time we expect SPI drivers to be phased over to this API. 595 */ 596 bool queued; 597 struct kthread_worker *kworker; 598 struct kthread_work pump_messages; 599 spinlock_t queue_lock; 600 struct list_head queue; 601 struct spi_message *cur_msg; 602 bool idling; 603 bool busy; 604 bool running; 605 bool rt; 606 bool auto_runtime_pm; 607 bool cur_msg_prepared; 608 bool cur_msg_mapped; 609 char last_cs; 610 bool last_cs_mode_high; 611 bool fallback; 612 struct completion xfer_completion; 613 size_t max_dma_len; 614 615 int (*prepare_transfer_hardware)(struct spi_controller *ctlr); 616 int (*transfer_one_message)(struct spi_controller *ctlr, 617 struct spi_message *mesg); 618 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr); 619 int (*prepare_message)(struct spi_controller *ctlr, 620 struct spi_message *message); 621 int (*unprepare_message)(struct spi_controller *ctlr, 622 struct spi_message *message); 623 int (*slave_abort)(struct spi_controller *ctlr); 624 625 /* 626 * These hooks are for drivers that use a generic implementation 627 * of transfer_one_message() provided by the core. 628 */ 629 void (*set_cs)(struct spi_device *spi, bool enable); 630 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi, 631 struct spi_transfer *transfer); 632 void (*handle_err)(struct spi_controller *ctlr, 633 struct spi_message *message); 634 635 /* Optimized handlers for SPI memory-like operations. */ 636 const struct spi_controller_mem_ops *mem_ops; 637 const struct spi_controller_mem_caps *mem_caps; 638 639 /* gpio chip select */ 640 struct gpio_desc **cs_gpiods; 641 bool use_gpio_descriptors; 642 s8 unused_native_cs; 643 s8 max_native_cs; 644 645 /* statistics */ 646 struct spi_statistics statistics; 647 648 /* DMA channels for use with core dmaengine helpers */ 649 struct dma_chan *dma_tx; 650 struct dma_chan *dma_rx; 651 652 /* dummy data for full duplex devices */ 653 void *dummy_rx; 654 void *dummy_tx; 655 656 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); 657 658 /* 659 * Driver sets this field to indicate it is able to snapshot SPI 660 * transfers (needed e.g. for reading the time of POSIX clocks) 661 */ 662 bool ptp_sts_supported; 663 664 /* Interrupt enable state during PTP system timestamping */ 665 unsigned long irq_flags; 666 }; 667 668 static inline void *spi_controller_get_devdata(struct spi_controller *ctlr) 669 { 670 return dev_get_drvdata(&ctlr->dev); 671 } 672 673 static inline void spi_controller_set_devdata(struct spi_controller *ctlr, 674 void *data) 675 { 676 dev_set_drvdata(&ctlr->dev, data); 677 } 678 679 static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr) 680 { 681 if (!ctlr || !get_device(&ctlr->dev)) 682 return NULL; 683 return ctlr; 684 } 685 686 static inline void spi_controller_put(struct spi_controller *ctlr) 687 { 688 if (ctlr) 689 put_device(&ctlr->dev); 690 } 691 692 static inline bool spi_controller_is_slave(struct spi_controller *ctlr) 693 { 694 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave; 695 } 696 697 /* PM calls that need to be issued by the driver */ 698 extern int spi_controller_suspend(struct spi_controller *ctlr); 699 extern int spi_controller_resume(struct spi_controller *ctlr); 700 701 /* Calls the driver make to interact with the message queue */ 702 extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr); 703 extern void spi_finalize_current_message(struct spi_controller *ctlr); 704 extern void spi_finalize_current_transfer(struct spi_controller *ctlr); 705 706 /* Helper calls for driver to timestamp transfer */ 707 void spi_take_timestamp_pre(struct spi_controller *ctlr, 708 struct spi_transfer *xfer, 709 size_t progress, bool irqs_off); 710 void spi_take_timestamp_post(struct spi_controller *ctlr, 711 struct spi_transfer *xfer, 712 size_t progress, bool irqs_off); 713 714 /* the spi driver core manages memory for the spi_controller classdev */ 715 extern struct spi_controller *__spi_alloc_controller(struct device *host, 716 unsigned int size, bool slave); 717 718 static inline struct spi_controller *spi_alloc_master(struct device *host, 719 unsigned int size) 720 { 721 return __spi_alloc_controller(host, size, false); 722 } 723 724 static inline struct spi_controller *spi_alloc_slave(struct device *host, 725 unsigned int size) 726 { 727 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 728 return NULL; 729 730 return __spi_alloc_controller(host, size, true); 731 } 732 733 struct spi_controller *__devm_spi_alloc_controller(struct device *dev, 734 unsigned int size, 735 bool slave); 736 737 static inline struct spi_controller *devm_spi_alloc_master(struct device *dev, 738 unsigned int size) 739 { 740 return __devm_spi_alloc_controller(dev, size, false); 741 } 742 743 static inline struct spi_controller *devm_spi_alloc_slave(struct device *dev, 744 unsigned int size) 745 { 746 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 747 return NULL; 748 749 return __devm_spi_alloc_controller(dev, size, true); 750 } 751 752 extern int spi_register_controller(struct spi_controller *ctlr); 753 extern int devm_spi_register_controller(struct device *dev, 754 struct spi_controller *ctlr); 755 extern void spi_unregister_controller(struct spi_controller *ctlr); 756 757 #if IS_ENABLED(CONFIG_ACPI) 758 extern struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr, 759 struct acpi_device *adev, 760 int index); 761 int acpi_spi_count_resources(struct acpi_device *adev); 762 #endif 763 764 /* 765 * SPI resource management while processing a SPI message 766 */ 767 768 typedef void (*spi_res_release_t)(struct spi_controller *ctlr, 769 struct spi_message *msg, 770 void *res); 771 772 /** 773 * struct spi_res - spi resource management structure 774 * @entry: list entry 775 * @release: release code called prior to freeing this resource 776 * @data: extra data allocated for the specific use-case 777 * 778 * this is based on ideas from devres, but focused on life-cycle 779 * management during spi_message processing 780 */ 781 struct spi_res { 782 struct list_head entry; 783 spi_res_release_t release; 784 unsigned long long data[]; /* guarantee ull alignment */ 785 }; 786 787 /*---------------------------------------------------------------------------*/ 788 789 /* 790 * I/O INTERFACE between SPI controller and protocol drivers 791 * 792 * Protocol drivers use a queue of spi_messages, each transferring data 793 * between the controller and memory buffers. 794 * 795 * The spi_messages themselves consist of a series of read+write transfer 796 * segments. Those segments always read the same number of bits as they 797 * write; but one or the other is easily ignored by passing a null buffer 798 * pointer. (This is unlike most types of I/O API, because SPI hardware 799 * is full duplex.) 800 * 801 * NOTE: Allocation of spi_transfer and spi_message memory is entirely 802 * up to the protocol driver, which guarantees the integrity of both (as 803 * well as the data buffers) for as long as the message is queued. 804 */ 805 806 /** 807 * struct spi_transfer - a read/write buffer pair 808 * @tx_buf: data to be written (dma-safe memory), or NULL 809 * @rx_buf: data to be read (dma-safe memory), or NULL 810 * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped 811 * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped 812 * @tx_nbits: number of bits used for writing. If 0 the default 813 * (SPI_NBITS_SINGLE) is used. 814 * @rx_nbits: number of bits used for reading. If 0 the default 815 * (SPI_NBITS_SINGLE) is used. 816 * @len: size of rx and tx buffers (in bytes) 817 * @speed_hz: Select a speed other than the device default for this 818 * transfer. If 0 the default (from @spi_device) is used. 819 * @bits_per_word: select a bits_per_word other than the device default 820 * for this transfer. If 0 the default (from @spi_device) is used. 821 * @dummy_data: indicates transfer is dummy bytes transfer. 822 * @cs_change: affects chipselect after this transfer completes 823 * @cs_change_delay: delay between cs deassert and assert when 824 * @cs_change is set and @spi_transfer is not the last in @spi_message 825 * @delay: delay to be introduced after this transfer before 826 * (optionally) changing the chipselect status, then starting 827 * the next transfer or completing this @spi_message. 828 * @word_delay: inter word delay to be introduced after each word size 829 * (set by bits_per_word) transmission. 830 * @effective_speed_hz: the effective SCK-speed that was used to 831 * transfer this transfer. Set to 0 if the spi bus driver does 832 * not support it. 833 * @transfer_list: transfers are sequenced through @spi_message.transfers 834 * @tx_sg: Scatterlist for transmit, currently not for client use 835 * @rx_sg: Scatterlist for receive, currently not for client use 836 * @ptp_sts_word_pre: The word (subject to bits_per_word semantics) offset 837 * within @tx_buf for which the SPI device is requesting that the time 838 * snapshot for this transfer begins. Upon completing the SPI transfer, 839 * this value may have changed compared to what was requested, depending 840 * on the available snapshotting resolution (DMA transfer, 841 * @ptp_sts_supported is false, etc). 842 * @ptp_sts_word_post: See @ptp_sts_word_post. The two can be equal (meaning 843 * that a single byte should be snapshotted). 844 * If the core takes care of the timestamp (if @ptp_sts_supported is false 845 * for this controller), it will set @ptp_sts_word_pre to 0, and 846 * @ptp_sts_word_post to the length of the transfer. This is done 847 * purposefully (instead of setting to spi_transfer->len - 1) to denote 848 * that a transfer-level snapshot taken from within the driver may still 849 * be of higher quality. 850 * @ptp_sts: Pointer to a memory location held by the SPI slave device where a 851 * PTP system timestamp structure may lie. If drivers use PIO or their 852 * hardware has some sort of assist for retrieving exact transfer timing, 853 * they can (and should) assert @ptp_sts_supported and populate this 854 * structure using the ptp_read_system_*ts helper functions. 855 * The timestamp must represent the time at which the SPI slave device has 856 * processed the word, i.e. the "pre" timestamp should be taken before 857 * transmitting the "pre" word, and the "post" timestamp after receiving 858 * transmit confirmation from the controller for the "post" word. 859 * @timestamped: true if the transfer has been timestamped 860 * @error: Error status logged by spi controller driver. 861 * 862 * SPI transfers always write the same number of bytes as they read. 863 * Protocol drivers should always provide @rx_buf and/or @tx_buf. 864 * In some cases, they may also want to provide DMA addresses for 865 * the data being transferred; that may reduce overhead, when the 866 * underlying driver uses dma. 867 * 868 * If the transmit buffer is null, zeroes will be shifted out 869 * while filling @rx_buf. If the receive buffer is null, the data 870 * shifted in will be discarded. Only "len" bytes shift out (or in). 871 * It's an error to try to shift out a partial word. (For example, by 872 * shifting out three bytes with word size of sixteen or twenty bits; 873 * the former uses two bytes per word, the latter uses four bytes.) 874 * 875 * In-memory data values are always in native CPU byte order, translated 876 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So 877 * for example when bits_per_word is sixteen, buffers are 2N bytes long 878 * (@len = 2N) and hold N sixteen bit words in CPU byte order. 879 * 880 * When the word size of the SPI transfer is not a power-of-two multiple 881 * of eight bits, those in-memory words include extra bits. In-memory 882 * words are always seen by protocol drivers as right-justified, so the 883 * undefined (rx) or unused (tx) bits are always the most significant bits. 884 * 885 * All SPI transfers start with the relevant chipselect active. Normally 886 * it stays selected until after the last transfer in a message. Drivers 887 * can affect the chipselect signal using cs_change. 888 * 889 * (i) If the transfer isn't the last one in the message, this flag is 890 * used to make the chipselect briefly go inactive in the middle of the 891 * message. Toggling chipselect in this way may be needed to terminate 892 * a chip command, letting a single spi_message perform all of group of 893 * chip transactions together. 894 * 895 * (ii) When the transfer is the last one in the message, the chip may 896 * stay selected until the next transfer. On multi-device SPI busses 897 * with nothing blocking messages going to other devices, this is just 898 * a performance hint; starting a message to another device deselects 899 * this one. But in other cases, this can be used to ensure correctness. 900 * Some devices need protocol transactions to be built from a series of 901 * spi_message submissions, where the content of one message is determined 902 * by the results of previous messages and where the whole transaction 903 * ends when the chipselect goes intactive. 904 * 905 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information 906 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these 907 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x) 908 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer. 909 * 910 * The code that submits an spi_message (and its spi_transfers) 911 * to the lower layers is responsible for managing its memory. 912 * Zero-initialize every field you don't set up explicitly, to 913 * insulate against future API updates. After you submit a message 914 * and its transfers, ignore them until its completion callback. 915 */ 916 struct spi_transfer { 917 /* it's ok if tx_buf == rx_buf (right?) 918 * for MicroWire, one buffer must be null 919 * buffers must work with dma_*map_single() calls, unless 920 * spi_message.is_dma_mapped reports a pre-existing mapping 921 */ 922 const void *tx_buf; 923 void *rx_buf; 924 unsigned len; 925 926 dma_addr_t tx_dma; 927 dma_addr_t rx_dma; 928 struct sg_table tx_sg; 929 struct sg_table rx_sg; 930 931 unsigned dummy_data:1; 932 unsigned cs_change:1; 933 unsigned tx_nbits:3; 934 unsigned rx_nbits:3; 935 #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */ 936 #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */ 937 #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */ 938 u8 bits_per_word; 939 struct spi_delay delay; 940 struct spi_delay cs_change_delay; 941 struct spi_delay word_delay; 942 u32 speed_hz; 943 944 u32 effective_speed_hz; 945 946 unsigned int ptp_sts_word_pre; 947 unsigned int ptp_sts_word_post; 948 949 struct ptp_system_timestamp *ptp_sts; 950 951 bool timestamped; 952 953 struct list_head transfer_list; 954 955 #define SPI_TRANS_FAIL_NO_START BIT(0) 956 u16 error; 957 }; 958 959 /** 960 * struct spi_message - one multi-segment SPI transaction 961 * @transfers: list of transfer segments in this transaction 962 * @spi: SPI device to which the transaction is queued 963 * @is_dma_mapped: if true, the caller provided both dma and cpu virtual 964 * addresses for each transfer buffer 965 * @complete: called to report transaction completions 966 * @context: the argument to complete() when it's called 967 * @frame_length: the total number of bytes in the message 968 * @actual_length: the total number of bytes that were transferred in all 969 * successful segments 970 * @status: zero for success, else negative errno 971 * @queue: for use by whichever driver currently owns the message 972 * @state: for use by whichever driver currently owns the message 973 * @resources: for resource management when the spi message is processed 974 * 975 * A @spi_message is used to execute an atomic sequence of data transfers, 976 * each represented by a struct spi_transfer. The sequence is "atomic" 977 * in the sense that no other spi_message may use that SPI bus until that 978 * sequence completes. On some systems, many such sequences can execute as 979 * a single programmed DMA transfer. On all systems, these messages are 980 * queued, and might complete after transactions to other devices. Messages 981 * sent to a given spi_device are always executed in FIFO order. 982 * 983 * The code that submits an spi_message (and its spi_transfers) 984 * to the lower layers is responsible for managing its memory. 985 * Zero-initialize every field you don't set up explicitly, to 986 * insulate against future API updates. After you submit a message 987 * and its transfers, ignore them until its completion callback. 988 */ 989 struct spi_message { 990 struct list_head transfers; 991 992 struct spi_device *spi; 993 994 unsigned is_dma_mapped:1; 995 996 /* REVISIT: we might want a flag affecting the behavior of the 997 * last transfer ... allowing things like "read 16 bit length L" 998 * immediately followed by "read L bytes". Basically imposing 999 * a specific message scheduling algorithm. 1000 * 1001 * Some controller drivers (message-at-a-time queue processing) 1002 * could provide that as their default scheduling algorithm. But 1003 * others (with multi-message pipelines) could need a flag to 1004 * tell them about such special cases. 1005 */ 1006 1007 /* completion is reported through a callback */ 1008 void (*complete)(void *context); 1009 void *context; 1010 unsigned frame_length; 1011 unsigned actual_length; 1012 int status; 1013 1014 /* for optional use by whatever driver currently owns the 1015 * spi_message ... between calls to spi_async and then later 1016 * complete(), that's the spi_controller controller driver. 1017 */ 1018 struct list_head queue; 1019 void *state; 1020 1021 /* list of spi_res reources when the spi message is processed */ 1022 struct list_head resources; 1023 }; 1024 1025 static inline void spi_message_init_no_memset(struct spi_message *m) 1026 { 1027 INIT_LIST_HEAD(&m->transfers); 1028 INIT_LIST_HEAD(&m->resources); 1029 } 1030 1031 static inline void spi_message_init(struct spi_message *m) 1032 { 1033 memset(m, 0, sizeof *m); 1034 spi_message_init_no_memset(m); 1035 } 1036 1037 static inline void 1038 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) 1039 { 1040 list_add_tail(&t->transfer_list, &m->transfers); 1041 } 1042 1043 static inline void 1044 spi_transfer_del(struct spi_transfer *t) 1045 { 1046 list_del(&t->transfer_list); 1047 } 1048 1049 static inline int 1050 spi_transfer_delay_exec(struct spi_transfer *t) 1051 { 1052 return spi_delay_exec(&t->delay, t); 1053 } 1054 1055 /** 1056 * spi_message_init_with_transfers - Initialize spi_message and append transfers 1057 * @m: spi_message to be initialized 1058 * @xfers: An array of spi transfers 1059 * @num_xfers: Number of items in the xfer array 1060 * 1061 * This function initializes the given spi_message and adds each spi_transfer in 1062 * the given array to the message. 1063 */ 1064 static inline void 1065 spi_message_init_with_transfers(struct spi_message *m, 1066 struct spi_transfer *xfers, unsigned int num_xfers) 1067 { 1068 unsigned int i; 1069 1070 spi_message_init(m); 1071 for (i = 0; i < num_xfers; ++i) 1072 spi_message_add_tail(&xfers[i], m); 1073 } 1074 1075 /* It's fine to embed message and transaction structures in other data 1076 * structures so long as you don't free them while they're in use. 1077 */ 1078 1079 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) 1080 { 1081 struct spi_message *m; 1082 1083 m = kzalloc(sizeof(struct spi_message) 1084 + ntrans * sizeof(struct spi_transfer), 1085 flags); 1086 if (m) { 1087 unsigned i; 1088 struct spi_transfer *t = (struct spi_transfer *)(m + 1); 1089 1090 spi_message_init_no_memset(m); 1091 for (i = 0; i < ntrans; i++, t++) 1092 spi_message_add_tail(t, m); 1093 } 1094 return m; 1095 } 1096 1097 static inline void spi_message_free(struct spi_message *m) 1098 { 1099 kfree(m); 1100 } 1101 1102 extern int spi_setup(struct spi_device *spi); 1103 extern int spi_async(struct spi_device *spi, struct spi_message *message); 1104 extern int spi_slave_abort(struct spi_device *spi); 1105 1106 static inline size_t 1107 spi_max_message_size(struct spi_device *spi) 1108 { 1109 struct spi_controller *ctlr = spi->controller; 1110 1111 if (!ctlr->max_message_size) 1112 return SIZE_MAX; 1113 return ctlr->max_message_size(spi); 1114 } 1115 1116 static inline size_t 1117 spi_max_transfer_size(struct spi_device *spi) 1118 { 1119 struct spi_controller *ctlr = spi->controller; 1120 size_t tr_max = SIZE_MAX; 1121 size_t msg_max = spi_max_message_size(spi); 1122 1123 if (ctlr->max_transfer_size) 1124 tr_max = ctlr->max_transfer_size(spi); 1125 1126 /* transfer size limit must not be greater than messsage size limit */ 1127 return min(tr_max, msg_max); 1128 } 1129 1130 /** 1131 * spi_is_bpw_supported - Check if bits per word is supported 1132 * @spi: SPI device 1133 * @bpw: Bits per word 1134 * 1135 * This function checks to see if the SPI controller supports @bpw. 1136 * 1137 * Returns: 1138 * True if @bpw is supported, false otherwise. 1139 */ 1140 static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw) 1141 { 1142 u32 bpw_mask = spi->master->bits_per_word_mask; 1143 1144 if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw))) 1145 return true; 1146 1147 return false; 1148 } 1149 1150 /*---------------------------------------------------------------------------*/ 1151 1152 /* SPI transfer replacement methods which make use of spi_res */ 1153 1154 struct spi_replaced_transfers; 1155 typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr, 1156 struct spi_message *msg, 1157 struct spi_replaced_transfers *res); 1158 /** 1159 * struct spi_replaced_transfers - structure describing the spi_transfer 1160 * replacements that have occurred 1161 * so that they can get reverted 1162 * @release: some extra release code to get executed prior to 1163 * relasing this structure 1164 * @extradata: pointer to some extra data if requested or NULL 1165 * @replaced_transfers: transfers that have been replaced and which need 1166 * to get restored 1167 * @replaced_after: the transfer after which the @replaced_transfers 1168 * are to get re-inserted 1169 * @inserted: number of transfers inserted 1170 * @inserted_transfers: array of spi_transfers of array-size @inserted, 1171 * that have been replacing replaced_transfers 1172 * 1173 * note: that @extradata will point to @inserted_transfers[@inserted] 1174 * if some extra allocation is requested, so alignment will be the same 1175 * as for spi_transfers 1176 */ 1177 struct spi_replaced_transfers { 1178 spi_replaced_release_t release; 1179 void *extradata; 1180 struct list_head replaced_transfers; 1181 struct list_head *replaced_after; 1182 size_t inserted; 1183 struct spi_transfer inserted_transfers[]; 1184 }; 1185 1186 /*---------------------------------------------------------------------------*/ 1187 1188 /* SPI transfer transformation methods */ 1189 1190 extern int spi_split_transfers_maxsize(struct spi_controller *ctlr, 1191 struct spi_message *msg, 1192 size_t maxsize, 1193 gfp_t gfp); 1194 1195 /*---------------------------------------------------------------------------*/ 1196 1197 /* All these synchronous SPI transfer routines are utilities layered 1198 * over the core async transfer primitive. Here, "synchronous" means 1199 * they will sleep uninterruptibly until the async transfer completes. 1200 */ 1201 1202 extern int spi_sync(struct spi_device *spi, struct spi_message *message); 1203 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message); 1204 extern int spi_bus_lock(struct spi_controller *ctlr); 1205 extern int spi_bus_unlock(struct spi_controller *ctlr); 1206 1207 /** 1208 * spi_sync_transfer - synchronous SPI data transfer 1209 * @spi: device with which data will be exchanged 1210 * @xfers: An array of spi_transfers 1211 * @num_xfers: Number of items in the xfer array 1212 * Context: can sleep 1213 * 1214 * Does a synchronous SPI data transfer of the given spi_transfer array. 1215 * 1216 * For more specific semantics see spi_sync(). 1217 * 1218 * Return: zero on success, else a negative error code. 1219 */ 1220 static inline int 1221 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers, 1222 unsigned int num_xfers) 1223 { 1224 struct spi_message msg; 1225 1226 spi_message_init_with_transfers(&msg, xfers, num_xfers); 1227 1228 return spi_sync(spi, &msg); 1229 } 1230 1231 /** 1232 * spi_write - SPI synchronous write 1233 * @spi: device to which data will be written 1234 * @buf: data buffer 1235 * @len: data buffer size 1236 * Context: can sleep 1237 * 1238 * This function writes the buffer @buf. 1239 * Callable only from contexts that can sleep. 1240 * 1241 * Return: zero on success, else a negative error code. 1242 */ 1243 static inline int 1244 spi_write(struct spi_device *spi, const void *buf, size_t len) 1245 { 1246 struct spi_transfer t = { 1247 .tx_buf = buf, 1248 .len = len, 1249 }; 1250 1251 return spi_sync_transfer(spi, &t, 1); 1252 } 1253 1254 /** 1255 * spi_read - SPI synchronous read 1256 * @spi: device from which data will be read 1257 * @buf: data buffer 1258 * @len: data buffer size 1259 * Context: can sleep 1260 * 1261 * This function reads the buffer @buf. 1262 * Callable only from contexts that can sleep. 1263 * 1264 * Return: zero on success, else a negative error code. 1265 */ 1266 static inline int 1267 spi_read(struct spi_device *spi, void *buf, size_t len) 1268 { 1269 struct spi_transfer t = { 1270 .rx_buf = buf, 1271 .len = len, 1272 }; 1273 1274 return spi_sync_transfer(spi, &t, 1); 1275 } 1276 1277 /* this copies txbuf and rxbuf data; for small transfers only! */ 1278 extern int spi_write_then_read(struct spi_device *spi, 1279 const void *txbuf, unsigned n_tx, 1280 void *rxbuf, unsigned n_rx); 1281 1282 /** 1283 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read 1284 * @spi: device with which data will be exchanged 1285 * @cmd: command to be written before data is read back 1286 * Context: can sleep 1287 * 1288 * Callable only from contexts that can sleep. 1289 * 1290 * Return: the (unsigned) eight bit number returned by the 1291 * device, or else a negative error code. 1292 */ 1293 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) 1294 { 1295 ssize_t status; 1296 u8 result; 1297 1298 status = spi_write_then_read(spi, &cmd, 1, &result, 1); 1299 1300 /* return negative errno or unsigned value */ 1301 return (status < 0) ? status : result; 1302 } 1303 1304 /** 1305 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read 1306 * @spi: device with which data will be exchanged 1307 * @cmd: command to be written before data is read back 1308 * Context: can sleep 1309 * 1310 * The number is returned in wire-order, which is at least sometimes 1311 * big-endian. 1312 * 1313 * Callable only from contexts that can sleep. 1314 * 1315 * Return: the (unsigned) sixteen bit number returned by the 1316 * device, or else a negative error code. 1317 */ 1318 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) 1319 { 1320 ssize_t status; 1321 u16 result; 1322 1323 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1324 1325 /* return negative errno or unsigned value */ 1326 return (status < 0) ? status : result; 1327 } 1328 1329 /** 1330 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read 1331 * @spi: device with which data will be exchanged 1332 * @cmd: command to be written before data is read back 1333 * Context: can sleep 1334 * 1335 * This function is similar to spi_w8r16, with the exception that it will 1336 * convert the read 16 bit data word from big-endian to native endianness. 1337 * 1338 * Callable only from contexts that can sleep. 1339 * 1340 * Return: the (unsigned) sixteen bit number returned by the device in cpu 1341 * endianness, or else a negative error code. 1342 */ 1343 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd) 1344 1345 { 1346 ssize_t status; 1347 __be16 result; 1348 1349 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1350 if (status < 0) 1351 return status; 1352 1353 return be16_to_cpu(result); 1354 } 1355 1356 /*---------------------------------------------------------------------------*/ 1357 1358 /* 1359 * INTERFACE between board init code and SPI infrastructure. 1360 * 1361 * No SPI driver ever sees these SPI device table segments, but 1362 * it's how the SPI core (or adapters that get hotplugged) grows 1363 * the driver model tree. 1364 * 1365 * As a rule, SPI devices can't be probed. Instead, board init code 1366 * provides a table listing the devices which are present, with enough 1367 * information to bind and set up the device's driver. There's basic 1368 * support for nonstatic configurations too; enough to handle adding 1369 * parport adapters, or microcontrollers acting as USB-to-SPI bridges. 1370 */ 1371 1372 /** 1373 * struct spi_board_info - board-specific template for a SPI device 1374 * @modalias: Initializes spi_device.modalias; identifies the driver. 1375 * @platform_data: Initializes spi_device.platform_data; the particular 1376 * data stored there is driver-specific. 1377 * @swnode: Software node for the device. 1378 * @controller_data: Initializes spi_device.controller_data; some 1379 * controllers need hints about hardware setup, e.g. for DMA. 1380 * @irq: Initializes spi_device.irq; depends on how the board is wired. 1381 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits 1382 * from the chip datasheet and board-specific signal quality issues. 1383 * @bus_num: Identifies which spi_controller parents the spi_device; unused 1384 * by spi_new_device(), and otherwise depends on board wiring. 1385 * @chip_select: Initializes spi_device.chip_select; depends on how 1386 * the board is wired. 1387 * @mode: Initializes spi_device.mode; based on the chip datasheet, board 1388 * wiring (some devices support both 3WIRE and standard modes), and 1389 * possibly presence of an inverter in the chipselect path. 1390 * 1391 * When adding new SPI devices to the device tree, these structures serve 1392 * as a partial device template. They hold information which can't always 1393 * be determined by drivers. Information that probe() can establish (such 1394 * as the default transfer wordsize) is not included here. 1395 * 1396 * These structures are used in two places. Their primary role is to 1397 * be stored in tables of board-specific device descriptors, which are 1398 * declared early in board initialization and then used (much later) to 1399 * populate a controller's device tree after the that controller's driver 1400 * initializes. A secondary (and atypical) role is as a parameter to 1401 * spi_new_device() call, which happens after those controller drivers 1402 * are active in some dynamic board configuration models. 1403 */ 1404 struct spi_board_info { 1405 /* the device name and module name are coupled, like platform_bus; 1406 * "modalias" is normally the driver name. 1407 * 1408 * platform_data goes to spi_device.dev.platform_data, 1409 * controller_data goes to spi_device.controller_data, 1410 * irq is copied too 1411 */ 1412 char modalias[SPI_NAME_SIZE]; 1413 const void *platform_data; 1414 const struct software_node *swnode; 1415 void *controller_data; 1416 int irq; 1417 1418 /* slower signaling on noisy or low voltage boards */ 1419 u32 max_speed_hz; 1420 1421 1422 /* bus_num is board specific and matches the bus_num of some 1423 * spi_controller that will probably be registered later. 1424 * 1425 * chip_select reflects how this chip is wired to that master; 1426 * it's less than num_chipselect. 1427 */ 1428 u16 bus_num; 1429 u16 chip_select; 1430 1431 /* mode becomes spi_device.mode, and is essential for chips 1432 * where the default of SPI_CS_HIGH = 0 is wrong. 1433 */ 1434 u32 mode; 1435 1436 /* ... may need additional spi_device chip config data here. 1437 * avoid stuff protocol drivers can set; but include stuff 1438 * needed to behave without being bound to a driver: 1439 * - quirks like clock rate mattering when not selected 1440 */ 1441 }; 1442 1443 #ifdef CONFIG_SPI 1444 extern int 1445 spi_register_board_info(struct spi_board_info const *info, unsigned n); 1446 #else 1447 /* board init code may ignore whether SPI is configured or not */ 1448 static inline int 1449 spi_register_board_info(struct spi_board_info const *info, unsigned n) 1450 { return 0; } 1451 #endif 1452 1453 /* If you're hotplugging an adapter with devices (parport, usb, etc) 1454 * use spi_new_device() to describe each device. You can also call 1455 * spi_unregister_device() to start making that device vanish, but 1456 * normally that would be handled by spi_unregister_controller(). 1457 * 1458 * You can also use spi_alloc_device() and spi_add_device() to use a two 1459 * stage registration sequence for each spi_device. This gives the caller 1460 * some more control over the spi_device structure before it is registered, 1461 * but requires that caller to initialize fields that would otherwise 1462 * be defined using the board info. 1463 */ 1464 extern struct spi_device * 1465 spi_alloc_device(struct spi_controller *ctlr); 1466 1467 extern int 1468 spi_add_device(struct spi_device *spi); 1469 1470 extern struct spi_device * 1471 spi_new_device(struct spi_controller *, struct spi_board_info *); 1472 1473 extern void spi_unregister_device(struct spi_device *spi); 1474 1475 extern const struct spi_device_id * 1476 spi_get_device_id(const struct spi_device *sdev); 1477 1478 static inline bool 1479 spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer) 1480 { 1481 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers); 1482 } 1483 1484 /* Compatibility layer */ 1485 #define spi_master spi_controller 1486 1487 #define SPI_MASTER_HALF_DUPLEX SPI_CONTROLLER_HALF_DUPLEX 1488 #define SPI_MASTER_NO_RX SPI_CONTROLLER_NO_RX 1489 #define SPI_MASTER_NO_TX SPI_CONTROLLER_NO_TX 1490 #define SPI_MASTER_MUST_RX SPI_CONTROLLER_MUST_RX 1491 #define SPI_MASTER_MUST_TX SPI_CONTROLLER_MUST_TX 1492 1493 #define spi_master_get_devdata(_ctlr) spi_controller_get_devdata(_ctlr) 1494 #define spi_master_set_devdata(_ctlr, _data) \ 1495 spi_controller_set_devdata(_ctlr, _data) 1496 #define spi_master_get(_ctlr) spi_controller_get(_ctlr) 1497 #define spi_master_put(_ctlr) spi_controller_put(_ctlr) 1498 #define spi_master_suspend(_ctlr) spi_controller_suspend(_ctlr) 1499 #define spi_master_resume(_ctlr) spi_controller_resume(_ctlr) 1500 1501 #define spi_register_master(_ctlr) spi_register_controller(_ctlr) 1502 #define devm_spi_register_master(_dev, _ctlr) \ 1503 devm_spi_register_controller(_dev, _ctlr) 1504 #define spi_unregister_master(_ctlr) spi_unregister_controller(_ctlr) 1505 1506 #endif /* __LINUX_SPI_H */ 1507