1 /* 2 * Copyright (C) 2005 David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #ifndef __LINUX_SPI_H 16 #define __LINUX_SPI_H 17 18 #include <linux/device.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/slab.h> 21 #include <linux/kthread.h> 22 #include <linux/completion.h> 23 #include <linux/scatterlist.h> 24 25 struct dma_chan; 26 struct property_entry; 27 struct spi_controller; 28 struct spi_transfer; 29 struct spi_controller_mem_ops; 30 31 /* 32 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, 33 * and SPI infrastructure. 34 */ 35 extern struct bus_type spi_bus_type; 36 37 /** 38 * struct spi_statistics - statistics for spi transfers 39 * @lock: lock protecting this structure 40 * 41 * @messages: number of spi-messages handled 42 * @transfers: number of spi_transfers handled 43 * @errors: number of errors during spi_transfer 44 * @timedout: number of timeouts during spi_transfer 45 * 46 * @spi_sync: number of times spi_sync is used 47 * @spi_sync_immediate: 48 * number of times spi_sync is executed immediately 49 * in calling context without queuing and scheduling 50 * @spi_async: number of times spi_async is used 51 * 52 * @bytes: number of bytes transferred to/from device 53 * @bytes_tx: number of bytes sent to device 54 * @bytes_rx: number of bytes received from device 55 * 56 * @transfer_bytes_histo: 57 * transfer bytes histogramm 58 * 59 * @transfers_split_maxsize: 60 * number of transfers that have been split because of 61 * maxsize limit 62 */ 63 struct spi_statistics { 64 spinlock_t lock; /* lock for the whole structure */ 65 66 unsigned long messages; 67 unsigned long transfers; 68 unsigned long errors; 69 unsigned long timedout; 70 71 unsigned long spi_sync; 72 unsigned long spi_sync_immediate; 73 unsigned long spi_async; 74 75 unsigned long long bytes; 76 unsigned long long bytes_rx; 77 unsigned long long bytes_tx; 78 79 #define SPI_STATISTICS_HISTO_SIZE 17 80 unsigned long transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE]; 81 82 unsigned long transfers_split_maxsize; 83 }; 84 85 void spi_statistics_add_transfer_stats(struct spi_statistics *stats, 86 struct spi_transfer *xfer, 87 struct spi_controller *ctlr); 88 89 #define SPI_STATISTICS_ADD_TO_FIELD(stats, field, count) \ 90 do { \ 91 unsigned long flags; \ 92 spin_lock_irqsave(&(stats)->lock, flags); \ 93 (stats)->field += count; \ 94 spin_unlock_irqrestore(&(stats)->lock, flags); \ 95 } while (0) 96 97 #define SPI_STATISTICS_INCREMENT_FIELD(stats, field) \ 98 SPI_STATISTICS_ADD_TO_FIELD(stats, field, 1) 99 100 /** 101 * struct spi_device - Controller side proxy for an SPI slave device 102 * @dev: Driver model representation of the device. 103 * @controller: SPI controller used with the device. 104 * @master: Copy of controller, for backwards compatibility. 105 * @max_speed_hz: Maximum clock rate to be used with this chip 106 * (on this board); may be changed by the device's driver. 107 * The spi_transfer.speed_hz can override this for each transfer. 108 * @chip_select: Chipselect, distinguishing chips handled by @controller. 109 * @mode: The spi mode defines how data is clocked out and in. 110 * This may be changed by the device's driver. 111 * The "active low" default for chipselect mode can be overridden 112 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for 113 * each word in a transfer (by specifying SPI_LSB_FIRST). 114 * @bits_per_word: Data transfers involve one or more words; word sizes 115 * like eight or 12 bits are common. In-memory wordsizes are 116 * powers of two bytes (e.g. 20 bit samples use 32 bits). 117 * This may be changed by the device's driver, or left at the 118 * default (0) indicating protocol words are eight bit bytes. 119 * The spi_transfer.bits_per_word can override this for each transfer. 120 * @irq: Negative, or the number passed to request_irq() to receive 121 * interrupts from this device. 122 * @controller_state: Controller's runtime state 123 * @controller_data: Board-specific definitions for controller, such as 124 * FIFO initialization parameters; from board_info.controller_data 125 * @modalias: Name of the driver to use with this device, or an alias 126 * for that name. This appears in the sysfs "modalias" attribute 127 * for driver coldplugging, and in uevents used for hotplugging 128 * @cs_gpio: gpio number of the chipselect line (optional, -ENOENT when 129 * not using a GPIO line) 130 * 131 * @statistics: statistics for the spi_device 132 * 133 * A @spi_device is used to interchange data between an SPI slave 134 * (usually a discrete chip) and CPU memory. 135 * 136 * In @dev, the platform_data is used to hold information about this 137 * device that's meaningful to the device's protocol driver, but not 138 * to its controller. One example might be an identifier for a chip 139 * variant with slightly different functionality; another might be 140 * information about how this particular board wires the chip's pins. 141 */ 142 struct spi_device { 143 struct device dev; 144 struct spi_controller *controller; 145 struct spi_controller *master; /* compatibility layer */ 146 u32 max_speed_hz; 147 u8 chip_select; 148 u8 bits_per_word; 149 u16 mode; 150 #define SPI_CPHA 0x01 /* clock phase */ 151 #define SPI_CPOL 0x02 /* clock polarity */ 152 #define SPI_MODE_0 (0|0) /* (original MicroWire) */ 153 #define SPI_MODE_1 (0|SPI_CPHA) 154 #define SPI_MODE_2 (SPI_CPOL|0) 155 #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) 156 #define SPI_CS_HIGH 0x04 /* chipselect active high? */ 157 #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ 158 #define SPI_3WIRE 0x10 /* SI/SO signals shared */ 159 #define SPI_LOOP 0x20 /* loopback mode */ 160 #define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */ 161 #define SPI_READY 0x80 /* slave pulls low to pause */ 162 #define SPI_TX_DUAL 0x100 /* transmit with 2 wires */ 163 #define SPI_TX_QUAD 0x200 /* transmit with 4 wires */ 164 #define SPI_RX_DUAL 0x400 /* receive with 2 wires */ 165 #define SPI_RX_QUAD 0x800 /* receive with 4 wires */ 166 int irq; 167 void *controller_state; 168 void *controller_data; 169 char modalias[SPI_NAME_SIZE]; 170 int cs_gpio; /* chip select gpio */ 171 172 /* the statistics */ 173 struct spi_statistics statistics; 174 175 /* 176 * likely need more hooks for more protocol options affecting how 177 * the controller talks to each chip, like: 178 * - memory packing (12 bit samples into low bits, others zeroed) 179 * - priority 180 * - drop chipselect after each word 181 * - chipselect delays 182 * - ... 183 */ 184 }; 185 186 static inline struct spi_device *to_spi_device(struct device *dev) 187 { 188 return dev ? container_of(dev, struct spi_device, dev) : NULL; 189 } 190 191 /* most drivers won't need to care about device refcounting */ 192 static inline struct spi_device *spi_dev_get(struct spi_device *spi) 193 { 194 return (spi && get_device(&spi->dev)) ? spi : NULL; 195 } 196 197 static inline void spi_dev_put(struct spi_device *spi) 198 { 199 if (spi) 200 put_device(&spi->dev); 201 } 202 203 /* ctldata is for the bus_controller driver's runtime state */ 204 static inline void *spi_get_ctldata(struct spi_device *spi) 205 { 206 return spi->controller_state; 207 } 208 209 static inline void spi_set_ctldata(struct spi_device *spi, void *state) 210 { 211 spi->controller_state = state; 212 } 213 214 /* device driver data */ 215 216 static inline void spi_set_drvdata(struct spi_device *spi, void *data) 217 { 218 dev_set_drvdata(&spi->dev, data); 219 } 220 221 static inline void *spi_get_drvdata(struct spi_device *spi) 222 { 223 return dev_get_drvdata(&spi->dev); 224 } 225 226 struct spi_message; 227 struct spi_transfer; 228 229 /** 230 * struct spi_driver - Host side "protocol" driver 231 * @id_table: List of SPI devices supported by this driver 232 * @probe: Binds this driver to the spi device. Drivers can verify 233 * that the device is actually present, and may need to configure 234 * characteristics (such as bits_per_word) which weren't needed for 235 * the initial configuration done during system setup. 236 * @remove: Unbinds this driver from the spi device 237 * @shutdown: Standard shutdown callback used during system state 238 * transitions such as powerdown/halt and kexec 239 * @driver: SPI device drivers should initialize the name and owner 240 * field of this structure. 241 * 242 * This represents the kind of device driver that uses SPI messages to 243 * interact with the hardware at the other end of a SPI link. It's called 244 * a "protocol" driver because it works through messages rather than talking 245 * directly to SPI hardware (which is what the underlying SPI controller 246 * driver does to pass those messages). These protocols are defined in the 247 * specification for the device(s) supported by the driver. 248 * 249 * As a rule, those device protocols represent the lowest level interface 250 * supported by a driver, and it will support upper level interfaces too. 251 * Examples of such upper levels include frameworks like MTD, networking, 252 * MMC, RTC, filesystem character device nodes, and hardware monitoring. 253 */ 254 struct spi_driver { 255 const struct spi_device_id *id_table; 256 int (*probe)(struct spi_device *spi); 257 int (*remove)(struct spi_device *spi); 258 void (*shutdown)(struct spi_device *spi); 259 struct device_driver driver; 260 }; 261 262 static inline struct spi_driver *to_spi_driver(struct device_driver *drv) 263 { 264 return drv ? container_of(drv, struct spi_driver, driver) : NULL; 265 } 266 267 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv); 268 269 /** 270 * spi_unregister_driver - reverse effect of spi_register_driver 271 * @sdrv: the driver to unregister 272 * Context: can sleep 273 */ 274 static inline void spi_unregister_driver(struct spi_driver *sdrv) 275 { 276 if (sdrv) 277 driver_unregister(&sdrv->driver); 278 } 279 280 /* use a define to avoid include chaining to get THIS_MODULE */ 281 #define spi_register_driver(driver) \ 282 __spi_register_driver(THIS_MODULE, driver) 283 284 /** 285 * module_spi_driver() - Helper macro for registering a SPI driver 286 * @__spi_driver: spi_driver struct 287 * 288 * Helper macro for SPI drivers which do not do anything special in module 289 * init/exit. This eliminates a lot of boilerplate. Each module may only 290 * use this macro once, and calling it replaces module_init() and module_exit() 291 */ 292 #define module_spi_driver(__spi_driver) \ 293 module_driver(__spi_driver, spi_register_driver, \ 294 spi_unregister_driver) 295 296 /** 297 * struct spi_controller - interface to SPI master or slave controller 298 * @dev: device interface to this driver 299 * @list: link with the global spi_controller list 300 * @bus_num: board-specific (and often SOC-specific) identifier for a 301 * given SPI controller. 302 * @num_chipselect: chipselects are used to distinguish individual 303 * SPI slaves, and are numbered from zero to num_chipselects. 304 * each slave has a chipselect signal, but it's common that not 305 * every chipselect is connected to a slave. 306 * @dma_alignment: SPI controller constraint on DMA buffers alignment. 307 * @mode_bits: flags understood by this controller driver 308 * @bits_per_word_mask: A mask indicating which values of bits_per_word are 309 * supported by the driver. Bit n indicates that a bits_per_word n+1 is 310 * supported. If set, the SPI core will reject any transfer with an 311 * unsupported bits_per_word. If not set, this value is simply ignored, 312 * and it's up to the individual driver to perform any validation. 313 * @min_speed_hz: Lowest supported transfer speed 314 * @max_speed_hz: Highest supported transfer speed 315 * @flags: other constraints relevant to this driver 316 * @slave: indicates that this is an SPI slave controller 317 * @max_transfer_size: function that returns the max transfer size for 318 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 319 * @max_message_size: function that returns the max message size for 320 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 321 * @io_mutex: mutex for physical bus access 322 * @bus_lock_spinlock: spinlock for SPI bus locking 323 * @bus_lock_mutex: mutex for exclusion of multiple callers 324 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use 325 * @setup: updates the device mode and clocking records used by a 326 * device's SPI controller; protocol code may call this. This 327 * must fail if an unrecognized or unsupported mode is requested. 328 * It's always safe to call this unless transfers are pending on 329 * the device whose settings are being modified. 330 * @transfer: adds a message to the controller's transfer queue. 331 * @cleanup: frees controller-specific state 332 * @can_dma: determine whether this controller supports DMA 333 * @queued: whether this controller is providing an internal message queue 334 * @kworker: thread struct for message pump 335 * @kworker_task: pointer to task for message pump kworker thread 336 * @pump_messages: work struct for scheduling work to the message pump 337 * @queue_lock: spinlock to syncronise access to message queue 338 * @queue: message queue 339 * @idling: the device is entering idle state 340 * @cur_msg: the currently in-flight message 341 * @cur_msg_prepared: spi_prepare_message was called for the currently 342 * in-flight message 343 * @cur_msg_mapped: message has been mapped for DMA 344 * @xfer_completion: used by core transfer_one_message() 345 * @busy: message pump is busy 346 * @running: message pump is running 347 * @rt: whether this queue is set to run as a realtime task 348 * @auto_runtime_pm: the core should ensure a runtime PM reference is held 349 * while the hardware is prepared, using the parent 350 * device for the spidev 351 * @max_dma_len: Maximum length of a DMA transfer for the device. 352 * @prepare_transfer_hardware: a message will soon arrive from the queue 353 * so the subsystem requests the driver to prepare the transfer hardware 354 * by issuing this call 355 * @transfer_one_message: the subsystem calls the driver to transfer a single 356 * message while queuing transfers that arrive in the meantime. When the 357 * driver is finished with this message, it must call 358 * spi_finalize_current_message() so the subsystem can issue the next 359 * message 360 * @unprepare_transfer_hardware: there are currently no more messages on the 361 * queue so the subsystem notifies the driver that it may relax the 362 * hardware by issuing this call 363 * @set_cs: set the logic level of the chip select line. May be called 364 * from interrupt context. 365 * @prepare_message: set up the controller to transfer a single message, 366 * for example doing DMA mapping. Called from threaded 367 * context. 368 * @transfer_one: transfer a single spi_transfer. 369 * - return 0 if the transfer is finished, 370 * - return 1 if the transfer is still in progress. When 371 * the driver is finished with this transfer it must 372 * call spi_finalize_current_transfer() so the subsystem 373 * can issue the next transfer. Note: transfer_one and 374 * transfer_one_message are mutually exclusive; when both 375 * are set, the generic subsystem does not call your 376 * transfer_one callback. 377 * @handle_err: the subsystem calls the driver to handle an error that occurs 378 * in the generic implementation of transfer_one_message(). 379 * @mem_ops: optimized/dedicated operations for interactions with SPI memory. 380 * This field is optional and should only be implemented if the 381 * controller has native support for memory like operations. 382 * @unprepare_message: undo any work done by prepare_message(). 383 * @slave_abort: abort the ongoing transfer request on an SPI slave controller 384 * @cs_gpios: Array of GPIOs to use as chip select lines; one per CS 385 * number. Any individual value may be -ENOENT for CS lines that 386 * are not GPIOs (driven by the SPI controller itself). 387 * @statistics: statistics for the spi_controller 388 * @dma_tx: DMA transmit channel 389 * @dma_rx: DMA receive channel 390 * @dummy_rx: dummy receive buffer for full-duplex devices 391 * @dummy_tx: dummy transmit buffer for full-duplex devices 392 * @fw_translate_cs: If the boot firmware uses different numbering scheme 393 * what Linux expects, this optional hook can be used to translate 394 * between the two. 395 * 396 * Each SPI controller can communicate with one or more @spi_device 397 * children. These make a small bus, sharing MOSI, MISO and SCK signals 398 * but not chip select signals. Each device may be configured to use a 399 * different clock rate, since those shared signals are ignored unless 400 * the chip is selected. 401 * 402 * The driver for an SPI controller manages access to those devices through 403 * a queue of spi_message transactions, copying data between CPU memory and 404 * an SPI slave device. For each such message it queues, it calls the 405 * message's completion function when the transaction completes. 406 */ 407 struct spi_controller { 408 struct device dev; 409 410 struct list_head list; 411 412 /* other than negative (== assign one dynamically), bus_num is fully 413 * board-specific. usually that simplifies to being SOC-specific. 414 * example: one SOC has three SPI controllers, numbered 0..2, 415 * and one board's schematics might show it using SPI-2. software 416 * would normally use bus_num=2 for that controller. 417 */ 418 s16 bus_num; 419 420 /* chipselects will be integral to many controllers; some others 421 * might use board-specific GPIOs. 422 */ 423 u16 num_chipselect; 424 425 /* some SPI controllers pose alignment requirements on DMAable 426 * buffers; let protocol drivers know about these requirements. 427 */ 428 u16 dma_alignment; 429 430 /* spi_device.mode flags understood by this controller driver */ 431 u16 mode_bits; 432 433 /* bitmask of supported bits_per_word for transfers */ 434 u32 bits_per_word_mask; 435 #define SPI_BPW_MASK(bits) BIT((bits) - 1) 436 #define SPI_BIT_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) 437 #define SPI_BPW_RANGE_MASK(min, max) (SPI_BIT_MASK(max) - SPI_BIT_MASK(min - 1)) 438 439 /* limits on transfer speed */ 440 u32 min_speed_hz; 441 u32 max_speed_hz; 442 443 /* other constraints relevant to this driver */ 444 u16 flags; 445 #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* can't do full duplex */ 446 #define SPI_CONTROLLER_NO_RX BIT(1) /* can't do buffer read */ 447 #define SPI_CONTROLLER_NO_TX BIT(2) /* can't do buffer write */ 448 #define SPI_CONTROLLER_MUST_RX BIT(3) /* requires rx */ 449 #define SPI_CONTROLLER_MUST_TX BIT(4) /* requires tx */ 450 451 #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */ 452 453 /* flag indicating this is an SPI slave controller */ 454 bool slave; 455 456 /* 457 * on some hardware transfer / message size may be constrained 458 * the limit may depend on device transfer settings 459 */ 460 size_t (*max_transfer_size)(struct spi_device *spi); 461 size_t (*max_message_size)(struct spi_device *spi); 462 463 /* I/O mutex */ 464 struct mutex io_mutex; 465 466 /* lock and mutex for SPI bus locking */ 467 spinlock_t bus_lock_spinlock; 468 struct mutex bus_lock_mutex; 469 470 /* flag indicating that the SPI bus is locked for exclusive use */ 471 bool bus_lock_flag; 472 473 /* Setup mode and clock, etc (spi driver may call many times). 474 * 475 * IMPORTANT: this may be called when transfers to another 476 * device are active. DO NOT UPDATE SHARED REGISTERS in ways 477 * which could break those transfers. 478 */ 479 int (*setup)(struct spi_device *spi); 480 481 /* bidirectional bulk transfers 482 * 483 * + The transfer() method may not sleep; its main role is 484 * just to add the message to the queue. 485 * + For now there's no remove-from-queue operation, or 486 * any other request management 487 * + To a given spi_device, message queueing is pure fifo 488 * 489 * + The controller's main job is to process its message queue, 490 * selecting a chip (for masters), then transferring data 491 * + If there are multiple spi_device children, the i/o queue 492 * arbitration algorithm is unspecified (round robin, fifo, 493 * priority, reservations, preemption, etc) 494 * 495 * + Chipselect stays active during the entire message 496 * (unless modified by spi_transfer.cs_change != 0). 497 * + The message transfers use clock and SPI mode parameters 498 * previously established by setup() for this device 499 */ 500 int (*transfer)(struct spi_device *spi, 501 struct spi_message *mesg); 502 503 /* called on release() to free memory provided by spi_controller */ 504 void (*cleanup)(struct spi_device *spi); 505 506 /* 507 * Used to enable core support for DMA handling, if can_dma() 508 * exists and returns true then the transfer will be mapped 509 * prior to transfer_one() being called. The driver should 510 * not modify or store xfer and dma_tx and dma_rx must be set 511 * while the device is prepared. 512 */ 513 bool (*can_dma)(struct spi_controller *ctlr, 514 struct spi_device *spi, 515 struct spi_transfer *xfer); 516 517 /* 518 * These hooks are for drivers that want to use the generic 519 * controller transfer queueing mechanism. If these are used, the 520 * transfer() function above must NOT be specified by the driver. 521 * Over time we expect SPI drivers to be phased over to this API. 522 */ 523 bool queued; 524 struct kthread_worker kworker; 525 struct task_struct *kworker_task; 526 struct kthread_work pump_messages; 527 spinlock_t queue_lock; 528 struct list_head queue; 529 struct spi_message *cur_msg; 530 bool idling; 531 bool busy; 532 bool running; 533 bool rt; 534 bool auto_runtime_pm; 535 bool cur_msg_prepared; 536 bool cur_msg_mapped; 537 struct completion xfer_completion; 538 size_t max_dma_len; 539 540 int (*prepare_transfer_hardware)(struct spi_controller *ctlr); 541 int (*transfer_one_message)(struct spi_controller *ctlr, 542 struct spi_message *mesg); 543 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr); 544 int (*prepare_message)(struct spi_controller *ctlr, 545 struct spi_message *message); 546 int (*unprepare_message)(struct spi_controller *ctlr, 547 struct spi_message *message); 548 int (*slave_abort)(struct spi_controller *ctlr); 549 550 /* 551 * These hooks are for drivers that use a generic implementation 552 * of transfer_one_message() provied by the core. 553 */ 554 void (*set_cs)(struct spi_device *spi, bool enable); 555 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi, 556 struct spi_transfer *transfer); 557 void (*handle_err)(struct spi_controller *ctlr, 558 struct spi_message *message); 559 560 /* Optimized handlers for SPI memory-like operations. */ 561 const struct spi_controller_mem_ops *mem_ops; 562 563 /* gpio chip select */ 564 int *cs_gpios; 565 566 /* statistics */ 567 struct spi_statistics statistics; 568 569 /* DMA channels for use with core dmaengine helpers */ 570 struct dma_chan *dma_tx; 571 struct dma_chan *dma_rx; 572 573 /* dummy data for full duplex devices */ 574 void *dummy_rx; 575 void *dummy_tx; 576 577 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); 578 }; 579 580 static inline void *spi_controller_get_devdata(struct spi_controller *ctlr) 581 { 582 return dev_get_drvdata(&ctlr->dev); 583 } 584 585 static inline void spi_controller_set_devdata(struct spi_controller *ctlr, 586 void *data) 587 { 588 dev_set_drvdata(&ctlr->dev, data); 589 } 590 591 static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr) 592 { 593 if (!ctlr || !get_device(&ctlr->dev)) 594 return NULL; 595 return ctlr; 596 } 597 598 static inline void spi_controller_put(struct spi_controller *ctlr) 599 { 600 if (ctlr) 601 put_device(&ctlr->dev); 602 } 603 604 static inline bool spi_controller_is_slave(struct spi_controller *ctlr) 605 { 606 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave; 607 } 608 609 /* PM calls that need to be issued by the driver */ 610 extern int spi_controller_suspend(struct spi_controller *ctlr); 611 extern int spi_controller_resume(struct spi_controller *ctlr); 612 613 /* Calls the driver make to interact with the message queue */ 614 extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr); 615 extern void spi_finalize_current_message(struct spi_controller *ctlr); 616 extern void spi_finalize_current_transfer(struct spi_controller *ctlr); 617 618 /* the spi driver core manages memory for the spi_controller classdev */ 619 extern struct spi_controller *__spi_alloc_controller(struct device *host, 620 unsigned int size, bool slave); 621 622 static inline struct spi_controller *spi_alloc_master(struct device *host, 623 unsigned int size) 624 { 625 return __spi_alloc_controller(host, size, false); 626 } 627 628 static inline struct spi_controller *spi_alloc_slave(struct device *host, 629 unsigned int size) 630 { 631 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 632 return NULL; 633 634 return __spi_alloc_controller(host, size, true); 635 } 636 637 extern int spi_register_controller(struct spi_controller *ctlr); 638 extern int devm_spi_register_controller(struct device *dev, 639 struct spi_controller *ctlr); 640 extern void spi_unregister_controller(struct spi_controller *ctlr); 641 642 extern struct spi_controller *spi_busnum_to_master(u16 busnum); 643 644 /* 645 * SPI resource management while processing a SPI message 646 */ 647 648 typedef void (*spi_res_release_t)(struct spi_controller *ctlr, 649 struct spi_message *msg, 650 void *res); 651 652 /** 653 * struct spi_res - spi resource management structure 654 * @entry: list entry 655 * @release: release code called prior to freeing this resource 656 * @data: extra data allocated for the specific use-case 657 * 658 * this is based on ideas from devres, but focused on life-cycle 659 * management during spi_message processing 660 */ 661 struct spi_res { 662 struct list_head entry; 663 spi_res_release_t release; 664 unsigned long long data[]; /* guarantee ull alignment */ 665 }; 666 667 extern void *spi_res_alloc(struct spi_device *spi, 668 spi_res_release_t release, 669 size_t size, gfp_t gfp); 670 extern void spi_res_add(struct spi_message *message, void *res); 671 extern void spi_res_free(void *res); 672 673 extern void spi_res_release(struct spi_controller *ctlr, 674 struct spi_message *message); 675 676 /*---------------------------------------------------------------------------*/ 677 678 /* 679 * I/O INTERFACE between SPI controller and protocol drivers 680 * 681 * Protocol drivers use a queue of spi_messages, each transferring data 682 * between the controller and memory buffers. 683 * 684 * The spi_messages themselves consist of a series of read+write transfer 685 * segments. Those segments always read the same number of bits as they 686 * write; but one or the other is easily ignored by passing a null buffer 687 * pointer. (This is unlike most types of I/O API, because SPI hardware 688 * is full duplex.) 689 * 690 * NOTE: Allocation of spi_transfer and spi_message memory is entirely 691 * up to the protocol driver, which guarantees the integrity of both (as 692 * well as the data buffers) for as long as the message is queued. 693 */ 694 695 /** 696 * struct spi_transfer - a read/write buffer pair 697 * @tx_buf: data to be written (dma-safe memory), or NULL 698 * @rx_buf: data to be read (dma-safe memory), or NULL 699 * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped 700 * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped 701 * @tx_nbits: number of bits used for writing. If 0 the default 702 * (SPI_NBITS_SINGLE) is used. 703 * @rx_nbits: number of bits used for reading. If 0 the default 704 * (SPI_NBITS_SINGLE) is used. 705 * @len: size of rx and tx buffers (in bytes) 706 * @speed_hz: Select a speed other than the device default for this 707 * transfer. If 0 the default (from @spi_device) is used. 708 * @bits_per_word: select a bits_per_word other than the device default 709 * for this transfer. If 0 the default (from @spi_device) is used. 710 * @cs_change: affects chipselect after this transfer completes 711 * @delay_usecs: microseconds to delay after this transfer before 712 * (optionally) changing the chipselect status, then starting 713 * the next transfer or completing this @spi_message. 714 * @transfer_list: transfers are sequenced through @spi_message.transfers 715 * @tx_sg: Scatterlist for transmit, currently not for client use 716 * @rx_sg: Scatterlist for receive, currently not for client use 717 * 718 * SPI transfers always write the same number of bytes as they read. 719 * Protocol drivers should always provide @rx_buf and/or @tx_buf. 720 * In some cases, they may also want to provide DMA addresses for 721 * the data being transferred; that may reduce overhead, when the 722 * underlying driver uses dma. 723 * 724 * If the transmit buffer is null, zeroes will be shifted out 725 * while filling @rx_buf. If the receive buffer is null, the data 726 * shifted in will be discarded. Only "len" bytes shift out (or in). 727 * It's an error to try to shift out a partial word. (For example, by 728 * shifting out three bytes with word size of sixteen or twenty bits; 729 * the former uses two bytes per word, the latter uses four bytes.) 730 * 731 * In-memory data values are always in native CPU byte order, translated 732 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So 733 * for example when bits_per_word is sixteen, buffers are 2N bytes long 734 * (@len = 2N) and hold N sixteen bit words in CPU byte order. 735 * 736 * When the word size of the SPI transfer is not a power-of-two multiple 737 * of eight bits, those in-memory words include extra bits. In-memory 738 * words are always seen by protocol drivers as right-justified, so the 739 * undefined (rx) or unused (tx) bits are always the most significant bits. 740 * 741 * All SPI transfers start with the relevant chipselect active. Normally 742 * it stays selected until after the last transfer in a message. Drivers 743 * can affect the chipselect signal using cs_change. 744 * 745 * (i) If the transfer isn't the last one in the message, this flag is 746 * used to make the chipselect briefly go inactive in the middle of the 747 * message. Toggling chipselect in this way may be needed to terminate 748 * a chip command, letting a single spi_message perform all of group of 749 * chip transactions together. 750 * 751 * (ii) When the transfer is the last one in the message, the chip may 752 * stay selected until the next transfer. On multi-device SPI busses 753 * with nothing blocking messages going to other devices, this is just 754 * a performance hint; starting a message to another device deselects 755 * this one. But in other cases, this can be used to ensure correctness. 756 * Some devices need protocol transactions to be built from a series of 757 * spi_message submissions, where the content of one message is determined 758 * by the results of previous messages and where the whole transaction 759 * ends when the chipselect goes intactive. 760 * 761 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information 762 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these 763 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x) 764 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer. 765 * 766 * The code that submits an spi_message (and its spi_transfers) 767 * to the lower layers is responsible for managing its memory. 768 * Zero-initialize every field you don't set up explicitly, to 769 * insulate against future API updates. After you submit a message 770 * and its transfers, ignore them until its completion callback. 771 */ 772 struct spi_transfer { 773 /* it's ok if tx_buf == rx_buf (right?) 774 * for MicroWire, one buffer must be null 775 * buffers must work with dma_*map_single() calls, unless 776 * spi_message.is_dma_mapped reports a pre-existing mapping 777 */ 778 const void *tx_buf; 779 void *rx_buf; 780 unsigned len; 781 782 dma_addr_t tx_dma; 783 dma_addr_t rx_dma; 784 struct sg_table tx_sg; 785 struct sg_table rx_sg; 786 787 unsigned cs_change:1; 788 unsigned tx_nbits:3; 789 unsigned rx_nbits:3; 790 #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */ 791 #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */ 792 #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */ 793 u8 bits_per_word; 794 u16 delay_usecs; 795 u32 speed_hz; 796 797 struct list_head transfer_list; 798 }; 799 800 /** 801 * struct spi_message - one multi-segment SPI transaction 802 * @transfers: list of transfer segments in this transaction 803 * @spi: SPI device to which the transaction is queued 804 * @is_dma_mapped: if true, the caller provided both dma and cpu virtual 805 * addresses for each transfer buffer 806 * @complete: called to report transaction completions 807 * @context: the argument to complete() when it's called 808 * @frame_length: the total number of bytes in the message 809 * @actual_length: the total number of bytes that were transferred in all 810 * successful segments 811 * @status: zero for success, else negative errno 812 * @queue: for use by whichever driver currently owns the message 813 * @state: for use by whichever driver currently owns the message 814 * @resources: for resource management when the spi message is processed 815 * 816 * A @spi_message is used to execute an atomic sequence of data transfers, 817 * each represented by a struct spi_transfer. The sequence is "atomic" 818 * in the sense that no other spi_message may use that SPI bus until that 819 * sequence completes. On some systems, many such sequences can execute as 820 * as single programmed DMA transfer. On all systems, these messages are 821 * queued, and might complete after transactions to other devices. Messages 822 * sent to a given spi_device are always executed in FIFO order. 823 * 824 * The code that submits an spi_message (and its spi_transfers) 825 * to the lower layers is responsible for managing its memory. 826 * Zero-initialize every field you don't set up explicitly, to 827 * insulate against future API updates. After you submit a message 828 * and its transfers, ignore them until its completion callback. 829 */ 830 struct spi_message { 831 struct list_head transfers; 832 833 struct spi_device *spi; 834 835 unsigned is_dma_mapped:1; 836 837 /* REVISIT: we might want a flag affecting the behavior of the 838 * last transfer ... allowing things like "read 16 bit length L" 839 * immediately followed by "read L bytes". Basically imposing 840 * a specific message scheduling algorithm. 841 * 842 * Some controller drivers (message-at-a-time queue processing) 843 * could provide that as their default scheduling algorithm. But 844 * others (with multi-message pipelines) could need a flag to 845 * tell them about such special cases. 846 */ 847 848 /* completion is reported through a callback */ 849 void (*complete)(void *context); 850 void *context; 851 unsigned frame_length; 852 unsigned actual_length; 853 int status; 854 855 /* for optional use by whatever driver currently owns the 856 * spi_message ... between calls to spi_async and then later 857 * complete(), that's the spi_controller controller driver. 858 */ 859 struct list_head queue; 860 void *state; 861 862 /* list of spi_res reources when the spi message is processed */ 863 struct list_head resources; 864 }; 865 866 static inline void spi_message_init_no_memset(struct spi_message *m) 867 { 868 INIT_LIST_HEAD(&m->transfers); 869 INIT_LIST_HEAD(&m->resources); 870 } 871 872 static inline void spi_message_init(struct spi_message *m) 873 { 874 memset(m, 0, sizeof *m); 875 spi_message_init_no_memset(m); 876 } 877 878 static inline void 879 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) 880 { 881 list_add_tail(&t->transfer_list, &m->transfers); 882 } 883 884 static inline void 885 spi_transfer_del(struct spi_transfer *t) 886 { 887 list_del(&t->transfer_list); 888 } 889 890 /** 891 * spi_message_init_with_transfers - Initialize spi_message and append transfers 892 * @m: spi_message to be initialized 893 * @xfers: An array of spi transfers 894 * @num_xfers: Number of items in the xfer array 895 * 896 * This function initializes the given spi_message and adds each spi_transfer in 897 * the given array to the message. 898 */ 899 static inline void 900 spi_message_init_with_transfers(struct spi_message *m, 901 struct spi_transfer *xfers, unsigned int num_xfers) 902 { 903 unsigned int i; 904 905 spi_message_init(m); 906 for (i = 0; i < num_xfers; ++i) 907 spi_message_add_tail(&xfers[i], m); 908 } 909 910 /* It's fine to embed message and transaction structures in other data 911 * structures so long as you don't free them while they're in use. 912 */ 913 914 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) 915 { 916 struct spi_message *m; 917 918 m = kzalloc(sizeof(struct spi_message) 919 + ntrans * sizeof(struct spi_transfer), 920 flags); 921 if (m) { 922 unsigned i; 923 struct spi_transfer *t = (struct spi_transfer *)(m + 1); 924 925 spi_message_init_no_memset(m); 926 for (i = 0; i < ntrans; i++, t++) 927 spi_message_add_tail(t, m); 928 } 929 return m; 930 } 931 932 static inline void spi_message_free(struct spi_message *m) 933 { 934 kfree(m); 935 } 936 937 extern int spi_setup(struct spi_device *spi); 938 extern int spi_async(struct spi_device *spi, struct spi_message *message); 939 extern int spi_async_locked(struct spi_device *spi, 940 struct spi_message *message); 941 extern int spi_slave_abort(struct spi_device *spi); 942 943 static inline size_t 944 spi_max_message_size(struct spi_device *spi) 945 { 946 struct spi_controller *ctlr = spi->controller; 947 948 if (!ctlr->max_message_size) 949 return SIZE_MAX; 950 return ctlr->max_message_size(spi); 951 } 952 953 static inline size_t 954 spi_max_transfer_size(struct spi_device *spi) 955 { 956 struct spi_controller *ctlr = spi->controller; 957 size_t tr_max = SIZE_MAX; 958 size_t msg_max = spi_max_message_size(spi); 959 960 if (ctlr->max_transfer_size) 961 tr_max = ctlr->max_transfer_size(spi); 962 963 /* transfer size limit must not be greater than messsage size limit */ 964 return min(tr_max, msg_max); 965 } 966 967 /*---------------------------------------------------------------------------*/ 968 969 /* SPI transfer replacement methods which make use of spi_res */ 970 971 struct spi_replaced_transfers; 972 typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr, 973 struct spi_message *msg, 974 struct spi_replaced_transfers *res); 975 /** 976 * struct spi_replaced_transfers - structure describing the spi_transfer 977 * replacements that have occurred 978 * so that they can get reverted 979 * @release: some extra release code to get executed prior to 980 * relasing this structure 981 * @extradata: pointer to some extra data if requested or NULL 982 * @replaced_transfers: transfers that have been replaced and which need 983 * to get restored 984 * @replaced_after: the transfer after which the @replaced_transfers 985 * are to get re-inserted 986 * @inserted: number of transfers inserted 987 * @inserted_transfers: array of spi_transfers of array-size @inserted, 988 * that have been replacing replaced_transfers 989 * 990 * note: that @extradata will point to @inserted_transfers[@inserted] 991 * if some extra allocation is requested, so alignment will be the same 992 * as for spi_transfers 993 */ 994 struct spi_replaced_transfers { 995 spi_replaced_release_t release; 996 void *extradata; 997 struct list_head replaced_transfers; 998 struct list_head *replaced_after; 999 size_t inserted; 1000 struct spi_transfer inserted_transfers[]; 1001 }; 1002 1003 extern struct spi_replaced_transfers *spi_replace_transfers( 1004 struct spi_message *msg, 1005 struct spi_transfer *xfer_first, 1006 size_t remove, 1007 size_t insert, 1008 spi_replaced_release_t release, 1009 size_t extradatasize, 1010 gfp_t gfp); 1011 1012 /*---------------------------------------------------------------------------*/ 1013 1014 /* SPI transfer transformation methods */ 1015 1016 extern int spi_split_transfers_maxsize(struct spi_controller *ctlr, 1017 struct spi_message *msg, 1018 size_t maxsize, 1019 gfp_t gfp); 1020 1021 /*---------------------------------------------------------------------------*/ 1022 1023 /* All these synchronous SPI transfer routines are utilities layered 1024 * over the core async transfer primitive. Here, "synchronous" means 1025 * they will sleep uninterruptibly until the async transfer completes. 1026 */ 1027 1028 extern int spi_sync(struct spi_device *spi, struct spi_message *message); 1029 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message); 1030 extern int spi_bus_lock(struct spi_controller *ctlr); 1031 extern int spi_bus_unlock(struct spi_controller *ctlr); 1032 1033 /** 1034 * spi_sync_transfer - synchronous SPI data transfer 1035 * @spi: device with which data will be exchanged 1036 * @xfers: An array of spi_transfers 1037 * @num_xfers: Number of items in the xfer array 1038 * Context: can sleep 1039 * 1040 * Does a synchronous SPI data transfer of the given spi_transfer array. 1041 * 1042 * For more specific semantics see spi_sync(). 1043 * 1044 * Return: Return: zero on success, else a negative error code. 1045 */ 1046 static inline int 1047 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers, 1048 unsigned int num_xfers) 1049 { 1050 struct spi_message msg; 1051 1052 spi_message_init_with_transfers(&msg, xfers, num_xfers); 1053 1054 return spi_sync(spi, &msg); 1055 } 1056 1057 /** 1058 * spi_write - SPI synchronous write 1059 * @spi: device to which data will be written 1060 * @buf: data buffer 1061 * @len: data buffer size 1062 * Context: can sleep 1063 * 1064 * This function writes the buffer @buf. 1065 * Callable only from contexts that can sleep. 1066 * 1067 * Return: zero on success, else a negative error code. 1068 */ 1069 static inline int 1070 spi_write(struct spi_device *spi, const void *buf, size_t len) 1071 { 1072 struct spi_transfer t = { 1073 .tx_buf = buf, 1074 .len = len, 1075 }; 1076 1077 return spi_sync_transfer(spi, &t, 1); 1078 } 1079 1080 /** 1081 * spi_read - SPI synchronous read 1082 * @spi: device from which data will be read 1083 * @buf: data buffer 1084 * @len: data buffer size 1085 * Context: can sleep 1086 * 1087 * This function reads the buffer @buf. 1088 * Callable only from contexts that can sleep. 1089 * 1090 * Return: zero on success, else a negative error code. 1091 */ 1092 static inline int 1093 spi_read(struct spi_device *spi, void *buf, size_t len) 1094 { 1095 struct spi_transfer t = { 1096 .rx_buf = buf, 1097 .len = len, 1098 }; 1099 1100 return spi_sync_transfer(spi, &t, 1); 1101 } 1102 1103 /* this copies txbuf and rxbuf data; for small transfers only! */ 1104 extern int spi_write_then_read(struct spi_device *spi, 1105 const void *txbuf, unsigned n_tx, 1106 void *rxbuf, unsigned n_rx); 1107 1108 /** 1109 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read 1110 * @spi: device with which data will be exchanged 1111 * @cmd: command to be written before data is read back 1112 * Context: can sleep 1113 * 1114 * Callable only from contexts that can sleep. 1115 * 1116 * Return: the (unsigned) eight bit number returned by the 1117 * device, or else a negative error code. 1118 */ 1119 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) 1120 { 1121 ssize_t status; 1122 u8 result; 1123 1124 status = spi_write_then_read(spi, &cmd, 1, &result, 1); 1125 1126 /* return negative errno or unsigned value */ 1127 return (status < 0) ? status : result; 1128 } 1129 1130 /** 1131 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read 1132 * @spi: device with which data will be exchanged 1133 * @cmd: command to be written before data is read back 1134 * Context: can sleep 1135 * 1136 * The number is returned in wire-order, which is at least sometimes 1137 * big-endian. 1138 * 1139 * Callable only from contexts that can sleep. 1140 * 1141 * Return: the (unsigned) sixteen bit number returned by the 1142 * device, or else a negative error code. 1143 */ 1144 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) 1145 { 1146 ssize_t status; 1147 u16 result; 1148 1149 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1150 1151 /* return negative errno or unsigned value */ 1152 return (status < 0) ? status : result; 1153 } 1154 1155 /** 1156 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read 1157 * @spi: device with which data will be exchanged 1158 * @cmd: command to be written before data is read back 1159 * Context: can sleep 1160 * 1161 * This function is similar to spi_w8r16, with the exception that it will 1162 * convert the read 16 bit data word from big-endian to native endianness. 1163 * 1164 * Callable only from contexts that can sleep. 1165 * 1166 * Return: the (unsigned) sixteen bit number returned by the device in cpu 1167 * endianness, or else a negative error code. 1168 */ 1169 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd) 1170 1171 { 1172 ssize_t status; 1173 __be16 result; 1174 1175 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1176 if (status < 0) 1177 return status; 1178 1179 return be16_to_cpu(result); 1180 } 1181 1182 /*---------------------------------------------------------------------------*/ 1183 1184 /* 1185 * INTERFACE between board init code and SPI infrastructure. 1186 * 1187 * No SPI driver ever sees these SPI device table segments, but 1188 * it's how the SPI core (or adapters that get hotplugged) grows 1189 * the driver model tree. 1190 * 1191 * As a rule, SPI devices can't be probed. Instead, board init code 1192 * provides a table listing the devices which are present, with enough 1193 * information to bind and set up the device's driver. There's basic 1194 * support for nonstatic configurations too; enough to handle adding 1195 * parport adapters, or microcontrollers acting as USB-to-SPI bridges. 1196 */ 1197 1198 /** 1199 * struct spi_board_info - board-specific template for a SPI device 1200 * @modalias: Initializes spi_device.modalias; identifies the driver. 1201 * @platform_data: Initializes spi_device.platform_data; the particular 1202 * data stored there is driver-specific. 1203 * @properties: Additional device properties for the device. 1204 * @controller_data: Initializes spi_device.controller_data; some 1205 * controllers need hints about hardware setup, e.g. for DMA. 1206 * @irq: Initializes spi_device.irq; depends on how the board is wired. 1207 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits 1208 * from the chip datasheet and board-specific signal quality issues. 1209 * @bus_num: Identifies which spi_controller parents the spi_device; unused 1210 * by spi_new_device(), and otherwise depends on board wiring. 1211 * @chip_select: Initializes spi_device.chip_select; depends on how 1212 * the board is wired. 1213 * @mode: Initializes spi_device.mode; based on the chip datasheet, board 1214 * wiring (some devices support both 3WIRE and standard modes), and 1215 * possibly presence of an inverter in the chipselect path. 1216 * 1217 * When adding new SPI devices to the device tree, these structures serve 1218 * as a partial device template. They hold information which can't always 1219 * be determined by drivers. Information that probe() can establish (such 1220 * as the default transfer wordsize) is not included here. 1221 * 1222 * These structures are used in two places. Their primary role is to 1223 * be stored in tables of board-specific device descriptors, which are 1224 * declared early in board initialization and then used (much later) to 1225 * populate a controller's device tree after the that controller's driver 1226 * initializes. A secondary (and atypical) role is as a parameter to 1227 * spi_new_device() call, which happens after those controller drivers 1228 * are active in some dynamic board configuration models. 1229 */ 1230 struct spi_board_info { 1231 /* the device name and module name are coupled, like platform_bus; 1232 * "modalias" is normally the driver name. 1233 * 1234 * platform_data goes to spi_device.dev.platform_data, 1235 * controller_data goes to spi_device.controller_data, 1236 * device properties are copied and attached to spi_device, 1237 * irq is copied too 1238 */ 1239 char modalias[SPI_NAME_SIZE]; 1240 const void *platform_data; 1241 const struct property_entry *properties; 1242 void *controller_data; 1243 int irq; 1244 1245 /* slower signaling on noisy or low voltage boards */ 1246 u32 max_speed_hz; 1247 1248 1249 /* bus_num is board specific and matches the bus_num of some 1250 * spi_controller that will probably be registered later. 1251 * 1252 * chip_select reflects how this chip is wired to that master; 1253 * it's less than num_chipselect. 1254 */ 1255 u16 bus_num; 1256 u16 chip_select; 1257 1258 /* mode becomes spi_device.mode, and is essential for chips 1259 * where the default of SPI_CS_HIGH = 0 is wrong. 1260 */ 1261 u16 mode; 1262 1263 /* ... may need additional spi_device chip config data here. 1264 * avoid stuff protocol drivers can set; but include stuff 1265 * needed to behave without being bound to a driver: 1266 * - quirks like clock rate mattering when not selected 1267 */ 1268 }; 1269 1270 #ifdef CONFIG_SPI 1271 extern int 1272 spi_register_board_info(struct spi_board_info const *info, unsigned n); 1273 #else 1274 /* board init code may ignore whether SPI is configured or not */ 1275 static inline int 1276 spi_register_board_info(struct spi_board_info const *info, unsigned n) 1277 { return 0; } 1278 #endif 1279 1280 1281 /* If you're hotplugging an adapter with devices (parport, usb, etc) 1282 * use spi_new_device() to describe each device. You can also call 1283 * spi_unregister_device() to start making that device vanish, but 1284 * normally that would be handled by spi_unregister_controller(). 1285 * 1286 * You can also use spi_alloc_device() and spi_add_device() to use a two 1287 * stage registration sequence for each spi_device. This gives the caller 1288 * some more control over the spi_device structure before it is registered, 1289 * but requires that caller to initialize fields that would otherwise 1290 * be defined using the board info. 1291 */ 1292 extern struct spi_device * 1293 spi_alloc_device(struct spi_controller *ctlr); 1294 1295 extern int 1296 spi_add_device(struct spi_device *spi); 1297 1298 extern struct spi_device * 1299 spi_new_device(struct spi_controller *, struct spi_board_info *); 1300 1301 extern void spi_unregister_device(struct spi_device *spi); 1302 1303 extern const struct spi_device_id * 1304 spi_get_device_id(const struct spi_device *sdev); 1305 1306 static inline bool 1307 spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer) 1308 { 1309 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers); 1310 } 1311 1312 1313 /* Compatibility layer */ 1314 #define spi_master spi_controller 1315 1316 #define SPI_MASTER_HALF_DUPLEX SPI_CONTROLLER_HALF_DUPLEX 1317 #define SPI_MASTER_NO_RX SPI_CONTROLLER_NO_RX 1318 #define SPI_MASTER_NO_TX SPI_CONTROLLER_NO_TX 1319 #define SPI_MASTER_MUST_RX SPI_CONTROLLER_MUST_RX 1320 #define SPI_MASTER_MUST_TX SPI_CONTROLLER_MUST_TX 1321 1322 #define spi_master_get_devdata(_ctlr) spi_controller_get_devdata(_ctlr) 1323 #define spi_master_set_devdata(_ctlr, _data) \ 1324 spi_controller_set_devdata(_ctlr, _data) 1325 #define spi_master_get(_ctlr) spi_controller_get(_ctlr) 1326 #define spi_master_put(_ctlr) spi_controller_put(_ctlr) 1327 #define spi_master_suspend(_ctlr) spi_controller_suspend(_ctlr) 1328 #define spi_master_resume(_ctlr) spi_controller_resume(_ctlr) 1329 1330 #define spi_register_master(_ctlr) spi_register_controller(_ctlr) 1331 #define devm_spi_register_master(_dev, _ctlr) \ 1332 devm_spi_register_controller(_dev, _ctlr) 1333 #define spi_unregister_master(_ctlr) spi_unregister_controller(_ctlr) 1334 1335 #endif /* __LINUX_SPI_H */ 1336