1 /* SPDX-License-Identifier: GPL-2.0-or-later 2 * 3 * Copyright (C) 2005 David Brownell 4 */ 5 6 #ifndef __LINUX_SPI_H 7 #define __LINUX_SPI_H 8 9 #include <linux/bits.h> 10 #include <linux/device.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/slab.h> 13 #include <linux/kthread.h> 14 #include <linux/completion.h> 15 #include <linux/scatterlist.h> 16 #include <linux/gpio/consumer.h> 17 18 #include <uapi/linux/spi/spi.h> 19 #include <linux/acpi.h> 20 #include <linux/u64_stats_sync.h> 21 22 struct dma_chan; 23 struct software_node; 24 struct ptp_system_timestamp; 25 struct spi_controller; 26 struct spi_transfer; 27 struct spi_controller_mem_ops; 28 struct spi_controller_mem_caps; 29 30 /* 31 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, 32 * and SPI infrastructure. 33 */ 34 extern struct bus_type spi_bus_type; 35 36 /** 37 * struct spi_statistics - statistics for spi transfers 38 * @syncp: seqcount to protect members in this struct for per-cpu udate 39 * on 32-bit systems 40 * 41 * @messages: number of spi-messages handled 42 * @transfers: number of spi_transfers handled 43 * @errors: number of errors during spi_transfer 44 * @timedout: number of timeouts during spi_transfer 45 * 46 * @spi_sync: number of times spi_sync is used 47 * @spi_sync_immediate: 48 * number of times spi_sync is executed immediately 49 * in calling context without queuing and scheduling 50 * @spi_async: number of times spi_async is used 51 * 52 * @bytes: number of bytes transferred to/from device 53 * @bytes_tx: number of bytes sent to device 54 * @bytes_rx: number of bytes received from device 55 * 56 * @transfer_bytes_histo: 57 * transfer bytes histogramm 58 * 59 * @transfers_split_maxsize: 60 * number of transfers that have been split because of 61 * maxsize limit 62 */ 63 struct spi_statistics { 64 struct u64_stats_sync syncp; 65 66 u64_stats_t messages; 67 u64_stats_t transfers; 68 u64_stats_t errors; 69 u64_stats_t timedout; 70 71 u64_stats_t spi_sync; 72 u64_stats_t spi_sync_immediate; 73 u64_stats_t spi_async; 74 75 u64_stats_t bytes; 76 u64_stats_t bytes_rx; 77 u64_stats_t bytes_tx; 78 79 #define SPI_STATISTICS_HISTO_SIZE 17 80 u64_stats_t transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE]; 81 82 u64_stats_t transfers_split_maxsize; 83 }; 84 85 #define SPI_STATISTICS_ADD_TO_FIELD(pcpu_stats, field, count) \ 86 do { \ 87 struct spi_statistics *__lstats; \ 88 get_cpu(); \ 89 __lstats = this_cpu_ptr(pcpu_stats); \ 90 u64_stats_update_begin(&__lstats->syncp); \ 91 u64_stats_add(&__lstats->field, count); \ 92 u64_stats_update_end(&__lstats->syncp); \ 93 put_cpu(); \ 94 } while (0) 95 96 #define SPI_STATISTICS_INCREMENT_FIELD(pcpu_stats, field) \ 97 do { \ 98 struct spi_statistics *__lstats; \ 99 get_cpu(); \ 100 __lstats = this_cpu_ptr(pcpu_stats); \ 101 u64_stats_update_begin(&__lstats->syncp); \ 102 u64_stats_inc(&__lstats->field); \ 103 u64_stats_update_end(&__lstats->syncp); \ 104 put_cpu(); \ 105 } while (0) 106 107 /** 108 * struct spi_delay - SPI delay information 109 * @value: Value for the delay 110 * @unit: Unit for the delay 111 */ 112 struct spi_delay { 113 #define SPI_DELAY_UNIT_USECS 0 114 #define SPI_DELAY_UNIT_NSECS 1 115 #define SPI_DELAY_UNIT_SCK 2 116 u16 value; 117 u8 unit; 118 }; 119 120 extern int spi_delay_to_ns(struct spi_delay *_delay, struct spi_transfer *xfer); 121 extern int spi_delay_exec(struct spi_delay *_delay, struct spi_transfer *xfer); 122 123 /** 124 * struct spi_device - Controller side proxy for an SPI slave device 125 * @dev: Driver model representation of the device. 126 * @controller: SPI controller used with the device. 127 * @master: Copy of controller, for backwards compatibility. 128 * @max_speed_hz: Maximum clock rate to be used with this chip 129 * (on this board); may be changed by the device's driver. 130 * The spi_transfer.speed_hz can override this for each transfer. 131 * @chip_select: Chipselect, distinguishing chips handled by @controller. 132 * @mode: The spi mode defines how data is clocked out and in. 133 * This may be changed by the device's driver. 134 * The "active low" default for chipselect mode can be overridden 135 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for 136 * each word in a transfer (by specifying SPI_LSB_FIRST). 137 * @bits_per_word: Data transfers involve one or more words; word sizes 138 * like eight or 12 bits are common. In-memory wordsizes are 139 * powers of two bytes (e.g. 20 bit samples use 32 bits). 140 * This may be changed by the device's driver, or left at the 141 * default (0) indicating protocol words are eight bit bytes. 142 * The spi_transfer.bits_per_word can override this for each transfer. 143 * @rt: Make the pump thread real time priority. 144 * @irq: Negative, or the number passed to request_irq() to receive 145 * interrupts from this device. 146 * @controller_state: Controller's runtime state 147 * @controller_data: Board-specific definitions for controller, such as 148 * FIFO initialization parameters; from board_info.controller_data 149 * @modalias: Name of the driver to use with this device, or an alias 150 * for that name. This appears in the sysfs "modalias" attribute 151 * for driver coldplugging, and in uevents used for hotplugging 152 * @driver_override: If the name of a driver is written to this attribute, then 153 * the device will bind to the named driver and only the named driver. 154 * Do not set directly, because core frees it; use driver_set_override() to 155 * set or clear it. 156 * @cs_gpiod: gpio descriptor of the chipselect line (optional, NULL when 157 * not using a GPIO line) 158 * @word_delay: delay to be inserted between consecutive 159 * words of a transfer 160 * @cs_setup: delay to be introduced by the controller after CS is asserted 161 * @cs_hold: delay to be introduced by the controller before CS is deasserted 162 * @cs_inactive: delay to be introduced by the controller after CS is 163 * deasserted. If @cs_change_delay is used from @spi_transfer, then the 164 * two delays will be added up. 165 * @pcpu_statistics: statistics for the spi_device 166 * 167 * A @spi_device is used to interchange data between an SPI slave 168 * (usually a discrete chip) and CPU memory. 169 * 170 * In @dev, the platform_data is used to hold information about this 171 * device that's meaningful to the device's protocol driver, but not 172 * to its controller. One example might be an identifier for a chip 173 * variant with slightly different functionality; another might be 174 * information about how this particular board wires the chip's pins. 175 */ 176 struct spi_device { 177 struct device dev; 178 struct spi_controller *controller; 179 struct spi_controller *master; /* Compatibility layer */ 180 u32 max_speed_hz; 181 u8 chip_select; 182 u8 bits_per_word; 183 bool rt; 184 #define SPI_NO_TX BIT(31) /* No transmit wire */ 185 #define SPI_NO_RX BIT(30) /* No receive wire */ 186 /* 187 * All bits defined above should be covered by SPI_MODE_KERNEL_MASK. 188 * The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart, 189 * which is defined in 'include/uapi/linux/spi/spi.h'. 190 * The bits defined here are from bit 31 downwards, while in 191 * SPI_MODE_USER_MASK are from 0 upwards. 192 * These bits must not overlap. A static assert check should make sure of that. 193 * If adding extra bits, make sure to decrease the bit index below as well. 194 */ 195 #define SPI_MODE_KERNEL_MASK (~(BIT(30) - 1)) 196 u32 mode; 197 int irq; 198 void *controller_state; 199 void *controller_data; 200 char modalias[SPI_NAME_SIZE]; 201 const char *driver_override; 202 struct gpio_desc *cs_gpiod; /* Chip select gpio desc */ 203 struct spi_delay word_delay; /* Inter-word delay */ 204 /* CS delays */ 205 struct spi_delay cs_setup; 206 struct spi_delay cs_hold; 207 struct spi_delay cs_inactive; 208 209 /* The statistics */ 210 struct spi_statistics __percpu *pcpu_statistics; 211 212 /* 213 * likely need more hooks for more protocol options affecting how 214 * the controller talks to each chip, like: 215 * - memory packing (12 bit samples into low bits, others zeroed) 216 * - priority 217 * - chipselect delays 218 * - ... 219 */ 220 }; 221 222 /* Make sure that SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK don't overlap */ 223 static_assert((SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK) == 0, 224 "SPI_MODE_USER_MASK & SPI_MODE_KERNEL_MASK must not overlap"); 225 226 static inline struct spi_device *to_spi_device(struct device *dev) 227 { 228 return dev ? container_of(dev, struct spi_device, dev) : NULL; 229 } 230 231 /* Most drivers won't need to care about device refcounting */ 232 static inline struct spi_device *spi_dev_get(struct spi_device *spi) 233 { 234 return (spi && get_device(&spi->dev)) ? spi : NULL; 235 } 236 237 static inline void spi_dev_put(struct spi_device *spi) 238 { 239 if (spi) 240 put_device(&spi->dev); 241 } 242 243 /* ctldata is for the bus_controller driver's runtime state */ 244 static inline void *spi_get_ctldata(struct spi_device *spi) 245 { 246 return spi->controller_state; 247 } 248 249 static inline void spi_set_ctldata(struct spi_device *spi, void *state) 250 { 251 spi->controller_state = state; 252 } 253 254 /* Device driver data */ 255 256 static inline void spi_set_drvdata(struct spi_device *spi, void *data) 257 { 258 dev_set_drvdata(&spi->dev, data); 259 } 260 261 static inline void *spi_get_drvdata(struct spi_device *spi) 262 { 263 return dev_get_drvdata(&spi->dev); 264 } 265 266 struct spi_message; 267 268 /** 269 * struct spi_driver - Host side "protocol" driver 270 * @id_table: List of SPI devices supported by this driver 271 * @probe: Binds this driver to the spi device. Drivers can verify 272 * that the device is actually present, and may need to configure 273 * characteristics (such as bits_per_word) which weren't needed for 274 * the initial configuration done during system setup. 275 * @remove: Unbinds this driver from the spi device 276 * @shutdown: Standard shutdown callback used during system state 277 * transitions such as powerdown/halt and kexec 278 * @driver: SPI device drivers should initialize the name and owner 279 * field of this structure. 280 * 281 * This represents the kind of device driver that uses SPI messages to 282 * interact with the hardware at the other end of a SPI link. It's called 283 * a "protocol" driver because it works through messages rather than talking 284 * directly to SPI hardware (which is what the underlying SPI controller 285 * driver does to pass those messages). These protocols are defined in the 286 * specification for the device(s) supported by the driver. 287 * 288 * As a rule, those device protocols represent the lowest level interface 289 * supported by a driver, and it will support upper level interfaces too. 290 * Examples of such upper levels include frameworks like MTD, networking, 291 * MMC, RTC, filesystem character device nodes, and hardware monitoring. 292 */ 293 struct spi_driver { 294 const struct spi_device_id *id_table; 295 int (*probe)(struct spi_device *spi); 296 void (*remove)(struct spi_device *spi); 297 void (*shutdown)(struct spi_device *spi); 298 struct device_driver driver; 299 }; 300 301 static inline struct spi_driver *to_spi_driver(struct device_driver *drv) 302 { 303 return drv ? container_of(drv, struct spi_driver, driver) : NULL; 304 } 305 306 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv); 307 308 /** 309 * spi_unregister_driver - reverse effect of spi_register_driver 310 * @sdrv: the driver to unregister 311 * Context: can sleep 312 */ 313 static inline void spi_unregister_driver(struct spi_driver *sdrv) 314 { 315 if (sdrv) 316 driver_unregister(&sdrv->driver); 317 } 318 319 extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 chip_select); 320 321 /* Use a define to avoid include chaining to get THIS_MODULE */ 322 #define spi_register_driver(driver) \ 323 __spi_register_driver(THIS_MODULE, driver) 324 325 /** 326 * module_spi_driver() - Helper macro for registering a SPI driver 327 * @__spi_driver: spi_driver struct 328 * 329 * Helper macro for SPI drivers which do not do anything special in module 330 * init/exit. This eliminates a lot of boilerplate. Each module may only 331 * use this macro once, and calling it replaces module_init() and module_exit() 332 */ 333 #define module_spi_driver(__spi_driver) \ 334 module_driver(__spi_driver, spi_register_driver, \ 335 spi_unregister_driver) 336 337 /** 338 * struct spi_controller - interface to SPI master or slave controller 339 * @dev: device interface to this driver 340 * @list: link with the global spi_controller list 341 * @bus_num: board-specific (and often SOC-specific) identifier for a 342 * given SPI controller. 343 * @num_chipselect: chipselects are used to distinguish individual 344 * SPI slaves, and are numbered from zero to num_chipselects. 345 * each slave has a chipselect signal, but it's common that not 346 * every chipselect is connected to a slave. 347 * @dma_alignment: SPI controller constraint on DMA buffers alignment. 348 * @mode_bits: flags understood by this controller driver 349 * @buswidth_override_bits: flags to override for this controller driver 350 * @bits_per_word_mask: A mask indicating which values of bits_per_word are 351 * supported by the driver. Bit n indicates that a bits_per_word n+1 is 352 * supported. If set, the SPI core will reject any transfer with an 353 * unsupported bits_per_word. If not set, this value is simply ignored, 354 * and it's up to the individual driver to perform any validation. 355 * @min_speed_hz: Lowest supported transfer speed 356 * @max_speed_hz: Highest supported transfer speed 357 * @flags: other constraints relevant to this driver 358 * @slave: indicates that this is an SPI slave controller 359 * @target: indicates that this is an SPI target controller 360 * @devm_allocated: whether the allocation of this struct is devres-managed 361 * @max_transfer_size: function that returns the max transfer size for 362 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 363 * @max_message_size: function that returns the max message size for 364 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 365 * @io_mutex: mutex for physical bus access 366 * @add_lock: mutex to avoid adding devices to the same chipselect 367 * @bus_lock_spinlock: spinlock for SPI bus locking 368 * @bus_lock_mutex: mutex for exclusion of multiple callers 369 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use 370 * @setup: updates the device mode and clocking records used by a 371 * device's SPI controller; protocol code may call this. This 372 * must fail if an unrecognized or unsupported mode is requested. 373 * It's always safe to call this unless transfers are pending on 374 * the device whose settings are being modified. 375 * @set_cs_timing: optional hook for SPI devices to request SPI master 376 * controller for configuring specific CS setup time, hold time and inactive 377 * delay interms of clock counts 378 * @transfer: adds a message to the controller's transfer queue. 379 * @cleanup: frees controller-specific state 380 * @can_dma: determine whether this controller supports DMA 381 * @dma_map_dev: device which can be used for DMA mapping 382 * @cur_rx_dma_dev: device which is currently used for RX DMA mapping 383 * @cur_tx_dma_dev: device which is currently used for TX DMA mapping 384 * @queued: whether this controller is providing an internal message queue 385 * @kworker: pointer to thread struct for message pump 386 * @pump_messages: work struct for scheduling work to the message pump 387 * @queue_lock: spinlock to syncronise access to message queue 388 * @queue: message queue 389 * @cur_msg: the currently in-flight message 390 * @cur_msg_completion: a completion for the current in-flight message 391 * @cur_msg_incomplete: Flag used internally to opportunistically skip 392 * the @cur_msg_completion. This flag is used to check if the driver has 393 * already called spi_finalize_current_message(). 394 * @cur_msg_need_completion: Flag used internally to opportunistically skip 395 * the @cur_msg_completion. This flag is used to signal the context that 396 * is running spi_finalize_current_message() that it needs to complete() 397 * @cur_msg_mapped: message has been mapped for DMA 398 * @last_cs: the last chip_select that is recorded by set_cs, -1 on non chip 399 * selected 400 * @last_cs_mode_high: was (mode & SPI_CS_HIGH) true on the last call to set_cs. 401 * @xfer_completion: used by core transfer_one_message() 402 * @busy: message pump is busy 403 * @running: message pump is running 404 * @rt: whether this queue is set to run as a realtime task 405 * @auto_runtime_pm: the core should ensure a runtime PM reference is held 406 * while the hardware is prepared, using the parent 407 * device for the spidev 408 * @max_dma_len: Maximum length of a DMA transfer for the device. 409 * @prepare_transfer_hardware: a message will soon arrive from the queue 410 * so the subsystem requests the driver to prepare the transfer hardware 411 * by issuing this call 412 * @transfer_one_message: the subsystem calls the driver to transfer a single 413 * message while queuing transfers that arrive in the meantime. When the 414 * driver is finished with this message, it must call 415 * spi_finalize_current_message() so the subsystem can issue the next 416 * message 417 * @unprepare_transfer_hardware: there are currently no more messages on the 418 * queue so the subsystem notifies the driver that it may relax the 419 * hardware by issuing this call 420 * 421 * @set_cs: set the logic level of the chip select line. May be called 422 * from interrupt context. 423 * @prepare_message: set up the controller to transfer a single message, 424 * for example doing DMA mapping. Called from threaded 425 * context. 426 * @transfer_one: transfer a single spi_transfer. 427 * 428 * - return 0 if the transfer is finished, 429 * - return 1 if the transfer is still in progress. When 430 * the driver is finished with this transfer it must 431 * call spi_finalize_current_transfer() so the subsystem 432 * can issue the next transfer. Note: transfer_one and 433 * transfer_one_message are mutually exclusive; when both 434 * are set, the generic subsystem does not call your 435 * transfer_one callback. 436 * @handle_err: the subsystem calls the driver to handle an error that occurs 437 * in the generic implementation of transfer_one_message(). 438 * @mem_ops: optimized/dedicated operations for interactions with SPI memory. 439 * This field is optional and should only be implemented if the 440 * controller has native support for memory like operations. 441 * @mem_caps: controller capabilities for the handling of memory operations. 442 * @unprepare_message: undo any work done by prepare_message(). 443 * @slave_abort: abort the ongoing transfer request on an SPI slave controller 444 * @target_abort: abort the ongoing transfer request on an SPI target controller 445 * @cs_gpiods: Array of GPIO descs to use as chip select lines; one per CS 446 * number. Any individual value may be NULL for CS lines that 447 * are not GPIOs (driven by the SPI controller itself). 448 * @use_gpio_descriptors: Turns on the code in the SPI core to parse and grab 449 * GPIO descriptors. This will fill in @cs_gpiods and SPI devices will have 450 * the cs_gpiod assigned if a GPIO line is found for the chipselect. 451 * @unused_native_cs: When cs_gpiods is used, spi_register_controller() will 452 * fill in this field with the first unused native CS, to be used by SPI 453 * controller drivers that need to drive a native CS when using GPIO CS. 454 * @max_native_cs: When cs_gpiods is used, and this field is filled in, 455 * spi_register_controller() will validate all native CS (including the 456 * unused native CS) against this value. 457 * @pcpu_statistics: statistics for the spi_controller 458 * @dma_tx: DMA transmit channel 459 * @dma_rx: DMA receive channel 460 * @dummy_rx: dummy receive buffer for full-duplex devices 461 * @dummy_tx: dummy transmit buffer for full-duplex devices 462 * @fw_translate_cs: If the boot firmware uses different numbering scheme 463 * what Linux expects, this optional hook can be used to translate 464 * between the two. 465 * @ptp_sts_supported: If the driver sets this to true, it must provide a 466 * time snapshot in @spi_transfer->ptp_sts as close as possible to the 467 * moment in time when @spi_transfer->ptp_sts_word_pre and 468 * @spi_transfer->ptp_sts_word_post were transmitted. 469 * If the driver does not set this, the SPI core takes the snapshot as 470 * close to the driver hand-over as possible. 471 * @irq_flags: Interrupt enable state during PTP system timestamping 472 * @fallback: fallback to pio if dma transfer return failure with 473 * SPI_TRANS_FAIL_NO_START. 474 * @queue_empty: signal green light for opportunistically skipping the queue 475 * for spi_sync transfers. 476 * @must_async: disable all fast paths in the core 477 * 478 * Each SPI controller can communicate with one or more @spi_device 479 * children. These make a small bus, sharing MOSI, MISO and SCK signals 480 * but not chip select signals. Each device may be configured to use a 481 * different clock rate, since those shared signals are ignored unless 482 * the chip is selected. 483 * 484 * The driver for an SPI controller manages access to those devices through 485 * a queue of spi_message transactions, copying data between CPU memory and 486 * an SPI slave device. For each such message it queues, it calls the 487 * message's completion function when the transaction completes. 488 */ 489 struct spi_controller { 490 struct device dev; 491 492 struct list_head list; 493 494 /* Other than negative (== assign one dynamically), bus_num is fully 495 * board-specific. usually that simplifies to being SOC-specific. 496 * example: one SOC has three SPI controllers, numbered 0..2, 497 * and one board's schematics might show it using SPI-2. software 498 * would normally use bus_num=2 for that controller. 499 */ 500 s16 bus_num; 501 502 /* chipselects will be integral to many controllers; some others 503 * might use board-specific GPIOs. 504 */ 505 u16 num_chipselect; 506 507 /* Some SPI controllers pose alignment requirements on DMAable 508 * buffers; let protocol drivers know about these requirements. 509 */ 510 u16 dma_alignment; 511 512 /* spi_device.mode flags understood by this controller driver */ 513 u32 mode_bits; 514 515 /* spi_device.mode flags override flags for this controller */ 516 u32 buswidth_override_bits; 517 518 /* Bitmask of supported bits_per_word for transfers */ 519 u32 bits_per_word_mask; 520 #define SPI_BPW_MASK(bits) BIT((bits) - 1) 521 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1) 522 523 /* Limits on transfer speed */ 524 u32 min_speed_hz; 525 u32 max_speed_hz; 526 527 /* Other constraints relevant to this driver */ 528 u16 flags; 529 #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* Can't do full duplex */ 530 #define SPI_CONTROLLER_NO_RX BIT(1) /* Can't do buffer read */ 531 #define SPI_CONTROLLER_NO_TX BIT(2) /* Can't do buffer write */ 532 #define SPI_CONTROLLER_MUST_RX BIT(3) /* Requires rx */ 533 #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx */ 534 535 #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */ 536 537 /* Flag indicating if the allocation of this struct is devres-managed */ 538 bool devm_allocated; 539 540 union { 541 /* Flag indicating this is an SPI slave controller */ 542 bool slave; 543 /* Flag indicating this is an SPI target controller */ 544 bool target; 545 }; 546 547 /* 548 * on some hardware transfer / message size may be constrained 549 * the limit may depend on device transfer settings 550 */ 551 size_t (*max_transfer_size)(struct spi_device *spi); 552 size_t (*max_message_size)(struct spi_device *spi); 553 554 /* I/O mutex */ 555 struct mutex io_mutex; 556 557 /* Used to avoid adding the same CS twice */ 558 struct mutex add_lock; 559 560 /* Lock and mutex for SPI bus locking */ 561 spinlock_t bus_lock_spinlock; 562 struct mutex bus_lock_mutex; 563 564 /* Flag indicating that the SPI bus is locked for exclusive use */ 565 bool bus_lock_flag; 566 567 /* Setup mode and clock, etc (spi driver may call many times). 568 * 569 * IMPORTANT: this may be called when transfers to another 570 * device are active. DO NOT UPDATE SHARED REGISTERS in ways 571 * which could break those transfers. 572 */ 573 int (*setup)(struct spi_device *spi); 574 575 /* 576 * set_cs_timing() method is for SPI controllers that supports 577 * configuring CS timing. 578 * 579 * This hook allows SPI client drivers to request SPI controllers 580 * to configure specific CS timing through spi_set_cs_timing() after 581 * spi_setup(). 582 */ 583 int (*set_cs_timing)(struct spi_device *spi); 584 585 /* Bidirectional bulk transfers 586 * 587 * + The transfer() method may not sleep; its main role is 588 * just to add the message to the queue. 589 * + For now there's no remove-from-queue operation, or 590 * any other request management 591 * + To a given spi_device, message queueing is pure fifo 592 * 593 * + The controller's main job is to process its message queue, 594 * selecting a chip (for masters), then transferring data 595 * + If there are multiple spi_device children, the i/o queue 596 * arbitration algorithm is unspecified (round robin, fifo, 597 * priority, reservations, preemption, etc) 598 * 599 * + Chipselect stays active during the entire message 600 * (unless modified by spi_transfer.cs_change != 0). 601 * + The message transfers use clock and SPI mode parameters 602 * previously established by setup() for this device 603 */ 604 int (*transfer)(struct spi_device *spi, 605 struct spi_message *mesg); 606 607 /* Called on release() to free memory provided by spi_controller */ 608 void (*cleanup)(struct spi_device *spi); 609 610 /* 611 * Used to enable core support for DMA handling, if can_dma() 612 * exists and returns true then the transfer will be mapped 613 * prior to transfer_one() being called. The driver should 614 * not modify or store xfer and dma_tx and dma_rx must be set 615 * while the device is prepared. 616 */ 617 bool (*can_dma)(struct spi_controller *ctlr, 618 struct spi_device *spi, 619 struct spi_transfer *xfer); 620 struct device *dma_map_dev; 621 struct device *cur_rx_dma_dev; 622 struct device *cur_tx_dma_dev; 623 624 /* 625 * These hooks are for drivers that want to use the generic 626 * controller transfer queueing mechanism. If these are used, the 627 * transfer() function above must NOT be specified by the driver. 628 * Over time we expect SPI drivers to be phased over to this API. 629 */ 630 bool queued; 631 struct kthread_worker *kworker; 632 struct kthread_work pump_messages; 633 spinlock_t queue_lock; 634 struct list_head queue; 635 struct spi_message *cur_msg; 636 struct completion cur_msg_completion; 637 bool cur_msg_incomplete; 638 bool cur_msg_need_completion; 639 bool busy; 640 bool running; 641 bool rt; 642 bool auto_runtime_pm; 643 bool cur_msg_mapped; 644 char last_cs; 645 bool last_cs_mode_high; 646 bool fallback; 647 struct completion xfer_completion; 648 size_t max_dma_len; 649 650 int (*prepare_transfer_hardware)(struct spi_controller *ctlr); 651 int (*transfer_one_message)(struct spi_controller *ctlr, 652 struct spi_message *mesg); 653 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr); 654 int (*prepare_message)(struct spi_controller *ctlr, 655 struct spi_message *message); 656 int (*unprepare_message)(struct spi_controller *ctlr, 657 struct spi_message *message); 658 union { 659 int (*slave_abort)(struct spi_controller *ctlr); 660 int (*target_abort)(struct spi_controller *ctlr); 661 }; 662 663 /* 664 * These hooks are for drivers that use a generic implementation 665 * of transfer_one_message() provided by the core. 666 */ 667 void (*set_cs)(struct spi_device *spi, bool enable); 668 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi, 669 struct spi_transfer *transfer); 670 void (*handle_err)(struct spi_controller *ctlr, 671 struct spi_message *message); 672 673 /* Optimized handlers for SPI memory-like operations. */ 674 const struct spi_controller_mem_ops *mem_ops; 675 const struct spi_controller_mem_caps *mem_caps; 676 677 /* gpio chip select */ 678 struct gpio_desc **cs_gpiods; 679 bool use_gpio_descriptors; 680 s8 unused_native_cs; 681 s8 max_native_cs; 682 683 /* Statistics */ 684 struct spi_statistics __percpu *pcpu_statistics; 685 686 /* DMA channels for use with core dmaengine helpers */ 687 struct dma_chan *dma_tx; 688 struct dma_chan *dma_rx; 689 690 /* Dummy data for full duplex devices */ 691 void *dummy_rx; 692 void *dummy_tx; 693 694 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); 695 696 /* 697 * Driver sets this field to indicate it is able to snapshot SPI 698 * transfers (needed e.g. for reading the time of POSIX clocks) 699 */ 700 bool ptp_sts_supported; 701 702 /* Interrupt enable state during PTP system timestamping */ 703 unsigned long irq_flags; 704 705 /* Flag for enabling opportunistic skipping of the queue in spi_sync */ 706 bool queue_empty; 707 bool must_async; 708 }; 709 710 static inline void *spi_controller_get_devdata(struct spi_controller *ctlr) 711 { 712 return dev_get_drvdata(&ctlr->dev); 713 } 714 715 static inline void spi_controller_set_devdata(struct spi_controller *ctlr, 716 void *data) 717 { 718 dev_set_drvdata(&ctlr->dev, data); 719 } 720 721 static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr) 722 { 723 if (!ctlr || !get_device(&ctlr->dev)) 724 return NULL; 725 return ctlr; 726 } 727 728 static inline void spi_controller_put(struct spi_controller *ctlr) 729 { 730 if (ctlr) 731 put_device(&ctlr->dev); 732 } 733 734 static inline bool spi_controller_is_slave(struct spi_controller *ctlr) 735 { 736 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave; 737 } 738 739 static inline bool spi_controller_is_target(struct spi_controller *ctlr) 740 { 741 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->target; 742 } 743 744 /* PM calls that need to be issued by the driver */ 745 extern int spi_controller_suspend(struct spi_controller *ctlr); 746 extern int spi_controller_resume(struct spi_controller *ctlr); 747 748 /* Calls the driver make to interact with the message queue */ 749 extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr); 750 extern void spi_finalize_current_message(struct spi_controller *ctlr); 751 extern void spi_finalize_current_transfer(struct spi_controller *ctlr); 752 753 /* Helper calls for driver to timestamp transfer */ 754 void spi_take_timestamp_pre(struct spi_controller *ctlr, 755 struct spi_transfer *xfer, 756 size_t progress, bool irqs_off); 757 void spi_take_timestamp_post(struct spi_controller *ctlr, 758 struct spi_transfer *xfer, 759 size_t progress, bool irqs_off); 760 761 /* The spi driver core manages memory for the spi_controller classdev */ 762 extern struct spi_controller *__spi_alloc_controller(struct device *host, 763 unsigned int size, bool slave); 764 765 static inline struct spi_controller *spi_alloc_master(struct device *host, 766 unsigned int size) 767 { 768 return __spi_alloc_controller(host, size, false); 769 } 770 771 static inline struct spi_controller *spi_alloc_slave(struct device *host, 772 unsigned int size) 773 { 774 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 775 return NULL; 776 777 return __spi_alloc_controller(host, size, true); 778 } 779 780 static inline struct spi_controller *spi_alloc_host(struct device *dev, 781 unsigned int size) 782 { 783 return __spi_alloc_controller(dev, size, false); 784 } 785 786 static inline struct spi_controller *spi_alloc_target(struct device *dev, 787 unsigned int size) 788 { 789 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 790 return NULL; 791 792 return __spi_alloc_controller(dev, size, true); 793 } 794 795 struct spi_controller *__devm_spi_alloc_controller(struct device *dev, 796 unsigned int size, 797 bool slave); 798 799 static inline struct spi_controller *devm_spi_alloc_master(struct device *dev, 800 unsigned int size) 801 { 802 return __devm_spi_alloc_controller(dev, size, false); 803 } 804 805 static inline struct spi_controller *devm_spi_alloc_slave(struct device *dev, 806 unsigned int size) 807 { 808 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 809 return NULL; 810 811 return __devm_spi_alloc_controller(dev, size, true); 812 } 813 814 static inline struct spi_controller *devm_spi_alloc_host(struct device *dev, 815 unsigned int size) 816 { 817 return __devm_spi_alloc_controller(dev, size, false); 818 } 819 820 static inline struct spi_controller *devm_spi_alloc_target(struct device *dev, 821 unsigned int size) 822 { 823 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 824 return NULL; 825 826 return __devm_spi_alloc_controller(dev, size, true); 827 } 828 829 extern int spi_register_controller(struct spi_controller *ctlr); 830 extern int devm_spi_register_controller(struct device *dev, 831 struct spi_controller *ctlr); 832 extern void spi_unregister_controller(struct spi_controller *ctlr); 833 834 #if IS_ENABLED(CONFIG_ACPI) 835 extern struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr, 836 struct acpi_device *adev, 837 int index); 838 int acpi_spi_count_resources(struct acpi_device *adev); 839 #endif 840 841 /* 842 * SPI resource management while processing a SPI message 843 */ 844 845 typedef void (*spi_res_release_t)(struct spi_controller *ctlr, 846 struct spi_message *msg, 847 void *res); 848 849 /** 850 * struct spi_res - spi resource management structure 851 * @entry: list entry 852 * @release: release code called prior to freeing this resource 853 * @data: extra data allocated for the specific use-case 854 * 855 * this is based on ideas from devres, but focused on life-cycle 856 * management during spi_message processing 857 */ 858 struct spi_res { 859 struct list_head entry; 860 spi_res_release_t release; 861 unsigned long long data[]; /* Guarantee ull alignment */ 862 }; 863 864 /*---------------------------------------------------------------------------*/ 865 866 /* 867 * I/O INTERFACE between SPI controller and protocol drivers 868 * 869 * Protocol drivers use a queue of spi_messages, each transferring data 870 * between the controller and memory buffers. 871 * 872 * The spi_messages themselves consist of a series of read+write transfer 873 * segments. Those segments always read the same number of bits as they 874 * write; but one or the other is easily ignored by passing a null buffer 875 * pointer. (This is unlike most types of I/O API, because SPI hardware 876 * is full duplex.) 877 * 878 * NOTE: Allocation of spi_transfer and spi_message memory is entirely 879 * up to the protocol driver, which guarantees the integrity of both (as 880 * well as the data buffers) for as long as the message is queued. 881 */ 882 883 /** 884 * struct spi_transfer - a read/write buffer pair 885 * @tx_buf: data to be written (dma-safe memory), or NULL 886 * @rx_buf: data to be read (dma-safe memory), or NULL 887 * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped 888 * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped 889 * @tx_nbits: number of bits used for writing. If 0 the default 890 * (SPI_NBITS_SINGLE) is used. 891 * @rx_nbits: number of bits used for reading. If 0 the default 892 * (SPI_NBITS_SINGLE) is used. 893 * @len: size of rx and tx buffers (in bytes) 894 * @speed_hz: Select a speed other than the device default for this 895 * transfer. If 0 the default (from @spi_device) is used. 896 * @bits_per_word: select a bits_per_word other than the device default 897 * for this transfer. If 0 the default (from @spi_device) is used. 898 * @dummy_data: indicates transfer is dummy bytes transfer. 899 * @cs_off: performs the transfer with chipselect off. 900 * @cs_change: affects chipselect after this transfer completes 901 * @cs_change_delay: delay between cs deassert and assert when 902 * @cs_change is set and @spi_transfer is not the last in @spi_message 903 * @delay: delay to be introduced after this transfer before 904 * (optionally) changing the chipselect status, then starting 905 * the next transfer or completing this @spi_message. 906 * @word_delay: inter word delay to be introduced after each word size 907 * (set by bits_per_word) transmission. 908 * @effective_speed_hz: the effective SCK-speed that was used to 909 * transfer this transfer. Set to 0 if the spi bus driver does 910 * not support it. 911 * @transfer_list: transfers are sequenced through @spi_message.transfers 912 * @tx_sg: Scatterlist for transmit, currently not for client use 913 * @rx_sg: Scatterlist for receive, currently not for client use 914 * @ptp_sts_word_pre: The word (subject to bits_per_word semantics) offset 915 * within @tx_buf for which the SPI device is requesting that the time 916 * snapshot for this transfer begins. Upon completing the SPI transfer, 917 * this value may have changed compared to what was requested, depending 918 * on the available snapshotting resolution (DMA transfer, 919 * @ptp_sts_supported is false, etc). 920 * @ptp_sts_word_post: See @ptp_sts_word_post. The two can be equal (meaning 921 * that a single byte should be snapshotted). 922 * If the core takes care of the timestamp (if @ptp_sts_supported is false 923 * for this controller), it will set @ptp_sts_word_pre to 0, and 924 * @ptp_sts_word_post to the length of the transfer. This is done 925 * purposefully (instead of setting to spi_transfer->len - 1) to denote 926 * that a transfer-level snapshot taken from within the driver may still 927 * be of higher quality. 928 * @ptp_sts: Pointer to a memory location held by the SPI slave device where a 929 * PTP system timestamp structure may lie. If drivers use PIO or their 930 * hardware has some sort of assist for retrieving exact transfer timing, 931 * they can (and should) assert @ptp_sts_supported and populate this 932 * structure using the ptp_read_system_*ts helper functions. 933 * The timestamp must represent the time at which the SPI slave device has 934 * processed the word, i.e. the "pre" timestamp should be taken before 935 * transmitting the "pre" word, and the "post" timestamp after receiving 936 * transmit confirmation from the controller for the "post" word. 937 * @timestamped: true if the transfer has been timestamped 938 * @error: Error status logged by spi controller driver. 939 * 940 * SPI transfers always write the same number of bytes as they read. 941 * Protocol drivers should always provide @rx_buf and/or @tx_buf. 942 * In some cases, they may also want to provide DMA addresses for 943 * the data being transferred; that may reduce overhead, when the 944 * underlying driver uses dma. 945 * 946 * If the transmit buffer is null, zeroes will be shifted out 947 * while filling @rx_buf. If the receive buffer is null, the data 948 * shifted in will be discarded. Only "len" bytes shift out (or in). 949 * It's an error to try to shift out a partial word. (For example, by 950 * shifting out three bytes with word size of sixteen or twenty bits; 951 * the former uses two bytes per word, the latter uses four bytes.) 952 * 953 * In-memory data values are always in native CPU byte order, translated 954 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So 955 * for example when bits_per_word is sixteen, buffers are 2N bytes long 956 * (@len = 2N) and hold N sixteen bit words in CPU byte order. 957 * 958 * When the word size of the SPI transfer is not a power-of-two multiple 959 * of eight bits, those in-memory words include extra bits. In-memory 960 * words are always seen by protocol drivers as right-justified, so the 961 * undefined (rx) or unused (tx) bits are always the most significant bits. 962 * 963 * All SPI transfers start with the relevant chipselect active. Normally 964 * it stays selected until after the last transfer in a message. Drivers 965 * can affect the chipselect signal using cs_change. 966 * 967 * (i) If the transfer isn't the last one in the message, this flag is 968 * used to make the chipselect briefly go inactive in the middle of the 969 * message. Toggling chipselect in this way may be needed to terminate 970 * a chip command, letting a single spi_message perform all of group of 971 * chip transactions together. 972 * 973 * (ii) When the transfer is the last one in the message, the chip may 974 * stay selected until the next transfer. On multi-device SPI busses 975 * with nothing blocking messages going to other devices, this is just 976 * a performance hint; starting a message to another device deselects 977 * this one. But in other cases, this can be used to ensure correctness. 978 * Some devices need protocol transactions to be built from a series of 979 * spi_message submissions, where the content of one message is determined 980 * by the results of previous messages and where the whole transaction 981 * ends when the chipselect goes intactive. 982 * 983 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information 984 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these 985 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x) 986 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer. 987 * 988 * The code that submits an spi_message (and its spi_transfers) 989 * to the lower layers is responsible for managing its memory. 990 * Zero-initialize every field you don't set up explicitly, to 991 * insulate against future API updates. After you submit a message 992 * and its transfers, ignore them until its completion callback. 993 */ 994 struct spi_transfer { 995 /* It's ok if tx_buf == rx_buf (right?) 996 * for MicroWire, one buffer must be null 997 * buffers must work with dma_*map_single() calls, unless 998 * spi_message.is_dma_mapped reports a pre-existing mapping 999 */ 1000 const void *tx_buf; 1001 void *rx_buf; 1002 unsigned len; 1003 1004 dma_addr_t tx_dma; 1005 dma_addr_t rx_dma; 1006 struct sg_table tx_sg; 1007 struct sg_table rx_sg; 1008 1009 unsigned dummy_data:1; 1010 unsigned cs_off:1; 1011 unsigned cs_change:1; 1012 unsigned tx_nbits:3; 1013 unsigned rx_nbits:3; 1014 #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */ 1015 #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */ 1016 #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */ 1017 u8 bits_per_word; 1018 struct spi_delay delay; 1019 struct spi_delay cs_change_delay; 1020 struct spi_delay word_delay; 1021 u32 speed_hz; 1022 1023 u32 effective_speed_hz; 1024 1025 unsigned int ptp_sts_word_pre; 1026 unsigned int ptp_sts_word_post; 1027 1028 struct ptp_system_timestamp *ptp_sts; 1029 1030 bool timestamped; 1031 1032 struct list_head transfer_list; 1033 1034 #define SPI_TRANS_FAIL_NO_START BIT(0) 1035 u16 error; 1036 }; 1037 1038 /** 1039 * struct spi_message - one multi-segment SPI transaction 1040 * @transfers: list of transfer segments in this transaction 1041 * @spi: SPI device to which the transaction is queued 1042 * @is_dma_mapped: if true, the caller provided both dma and cpu virtual 1043 * addresses for each transfer buffer 1044 * @complete: called to report transaction completions 1045 * @context: the argument to complete() when it's called 1046 * @frame_length: the total number of bytes in the message 1047 * @actual_length: the total number of bytes that were transferred in all 1048 * successful segments 1049 * @status: zero for success, else negative errno 1050 * @queue: for use by whichever driver currently owns the message 1051 * @state: for use by whichever driver currently owns the message 1052 * @resources: for resource management when the spi message is processed 1053 * @prepared: spi_prepare_message was called for the this message 1054 * 1055 * A @spi_message is used to execute an atomic sequence of data transfers, 1056 * each represented by a struct spi_transfer. The sequence is "atomic" 1057 * in the sense that no other spi_message may use that SPI bus until that 1058 * sequence completes. On some systems, many such sequences can execute as 1059 * a single programmed DMA transfer. On all systems, these messages are 1060 * queued, and might complete after transactions to other devices. Messages 1061 * sent to a given spi_device are always executed in FIFO order. 1062 * 1063 * The code that submits an spi_message (and its spi_transfers) 1064 * to the lower layers is responsible for managing its memory. 1065 * Zero-initialize every field you don't set up explicitly, to 1066 * insulate against future API updates. After you submit a message 1067 * and its transfers, ignore them until its completion callback. 1068 */ 1069 struct spi_message { 1070 struct list_head transfers; 1071 1072 struct spi_device *spi; 1073 1074 unsigned is_dma_mapped:1; 1075 1076 /* REVISIT: we might want a flag affecting the behavior of the 1077 * last transfer ... allowing things like "read 16 bit length L" 1078 * immediately followed by "read L bytes". Basically imposing 1079 * a specific message scheduling algorithm. 1080 * 1081 * Some controller drivers (message-at-a-time queue processing) 1082 * could provide that as their default scheduling algorithm. But 1083 * others (with multi-message pipelines) could need a flag to 1084 * tell them about such special cases. 1085 */ 1086 1087 /* Completion is reported through a callback */ 1088 void (*complete)(void *context); 1089 void *context; 1090 unsigned frame_length; 1091 unsigned actual_length; 1092 int status; 1093 1094 /* For optional use by whatever driver currently owns the 1095 * spi_message ... between calls to spi_async and then later 1096 * complete(), that's the spi_controller controller driver. 1097 */ 1098 struct list_head queue; 1099 void *state; 1100 1101 /* List of spi_res reources when the spi message is processed */ 1102 struct list_head resources; 1103 1104 /* spi_prepare_message() was called for this message */ 1105 bool prepared; 1106 }; 1107 1108 static inline void spi_message_init_no_memset(struct spi_message *m) 1109 { 1110 INIT_LIST_HEAD(&m->transfers); 1111 INIT_LIST_HEAD(&m->resources); 1112 } 1113 1114 static inline void spi_message_init(struct spi_message *m) 1115 { 1116 memset(m, 0, sizeof *m); 1117 spi_message_init_no_memset(m); 1118 } 1119 1120 static inline void 1121 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) 1122 { 1123 list_add_tail(&t->transfer_list, &m->transfers); 1124 } 1125 1126 static inline void 1127 spi_transfer_del(struct spi_transfer *t) 1128 { 1129 list_del(&t->transfer_list); 1130 } 1131 1132 static inline int 1133 spi_transfer_delay_exec(struct spi_transfer *t) 1134 { 1135 return spi_delay_exec(&t->delay, t); 1136 } 1137 1138 /** 1139 * spi_message_init_with_transfers - Initialize spi_message and append transfers 1140 * @m: spi_message to be initialized 1141 * @xfers: An array of spi transfers 1142 * @num_xfers: Number of items in the xfer array 1143 * 1144 * This function initializes the given spi_message and adds each spi_transfer in 1145 * the given array to the message. 1146 */ 1147 static inline void 1148 spi_message_init_with_transfers(struct spi_message *m, 1149 struct spi_transfer *xfers, unsigned int num_xfers) 1150 { 1151 unsigned int i; 1152 1153 spi_message_init(m); 1154 for (i = 0; i < num_xfers; ++i) 1155 spi_message_add_tail(&xfers[i], m); 1156 } 1157 1158 /* It's fine to embed message and transaction structures in other data 1159 * structures so long as you don't free them while they're in use. 1160 */ 1161 1162 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) 1163 { 1164 struct spi_message *m; 1165 1166 m = kzalloc(sizeof(struct spi_message) 1167 + ntrans * sizeof(struct spi_transfer), 1168 flags); 1169 if (m) { 1170 unsigned i; 1171 struct spi_transfer *t = (struct spi_transfer *)(m + 1); 1172 1173 spi_message_init_no_memset(m); 1174 for (i = 0; i < ntrans; i++, t++) 1175 spi_message_add_tail(t, m); 1176 } 1177 return m; 1178 } 1179 1180 static inline void spi_message_free(struct spi_message *m) 1181 { 1182 kfree(m); 1183 } 1184 1185 extern int spi_setup(struct spi_device *spi); 1186 extern int spi_async(struct spi_device *spi, struct spi_message *message); 1187 extern int spi_slave_abort(struct spi_device *spi); 1188 extern int spi_target_abort(struct spi_device *spi); 1189 1190 static inline size_t 1191 spi_max_message_size(struct spi_device *spi) 1192 { 1193 struct spi_controller *ctlr = spi->controller; 1194 1195 if (!ctlr->max_message_size) 1196 return SIZE_MAX; 1197 return ctlr->max_message_size(spi); 1198 } 1199 1200 static inline size_t 1201 spi_max_transfer_size(struct spi_device *spi) 1202 { 1203 struct spi_controller *ctlr = spi->controller; 1204 size_t tr_max = SIZE_MAX; 1205 size_t msg_max = spi_max_message_size(spi); 1206 1207 if (ctlr->max_transfer_size) 1208 tr_max = ctlr->max_transfer_size(spi); 1209 1210 /* Transfer size limit must not be greater than message size limit */ 1211 return min(tr_max, msg_max); 1212 } 1213 1214 /** 1215 * spi_is_bpw_supported - Check if bits per word is supported 1216 * @spi: SPI device 1217 * @bpw: Bits per word 1218 * 1219 * This function checks to see if the SPI controller supports @bpw. 1220 * 1221 * Returns: 1222 * True if @bpw is supported, false otherwise. 1223 */ 1224 static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw) 1225 { 1226 u32 bpw_mask = spi->master->bits_per_word_mask; 1227 1228 if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw))) 1229 return true; 1230 1231 return false; 1232 } 1233 1234 /*---------------------------------------------------------------------------*/ 1235 1236 /* SPI transfer replacement methods which make use of spi_res */ 1237 1238 struct spi_replaced_transfers; 1239 typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr, 1240 struct spi_message *msg, 1241 struct spi_replaced_transfers *res); 1242 /** 1243 * struct spi_replaced_transfers - structure describing the spi_transfer 1244 * replacements that have occurred 1245 * so that they can get reverted 1246 * @release: some extra release code to get executed prior to 1247 * relasing this structure 1248 * @extradata: pointer to some extra data if requested or NULL 1249 * @replaced_transfers: transfers that have been replaced and which need 1250 * to get restored 1251 * @replaced_after: the transfer after which the @replaced_transfers 1252 * are to get re-inserted 1253 * @inserted: number of transfers inserted 1254 * @inserted_transfers: array of spi_transfers of array-size @inserted, 1255 * that have been replacing replaced_transfers 1256 * 1257 * note: that @extradata will point to @inserted_transfers[@inserted] 1258 * if some extra allocation is requested, so alignment will be the same 1259 * as for spi_transfers 1260 */ 1261 struct spi_replaced_transfers { 1262 spi_replaced_release_t release; 1263 void *extradata; 1264 struct list_head replaced_transfers; 1265 struct list_head *replaced_after; 1266 size_t inserted; 1267 struct spi_transfer inserted_transfers[]; 1268 }; 1269 1270 /*---------------------------------------------------------------------------*/ 1271 1272 /* SPI transfer transformation methods */ 1273 1274 extern int spi_split_transfers_maxsize(struct spi_controller *ctlr, 1275 struct spi_message *msg, 1276 size_t maxsize, 1277 gfp_t gfp); 1278 1279 /*---------------------------------------------------------------------------*/ 1280 1281 /* All these synchronous SPI transfer routines are utilities layered 1282 * over the core async transfer primitive. Here, "synchronous" means 1283 * they will sleep uninterruptibly until the async transfer completes. 1284 */ 1285 1286 extern int spi_sync(struct spi_device *spi, struct spi_message *message); 1287 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message); 1288 extern int spi_bus_lock(struct spi_controller *ctlr); 1289 extern int spi_bus_unlock(struct spi_controller *ctlr); 1290 1291 /** 1292 * spi_sync_transfer - synchronous SPI data transfer 1293 * @spi: device with which data will be exchanged 1294 * @xfers: An array of spi_transfers 1295 * @num_xfers: Number of items in the xfer array 1296 * Context: can sleep 1297 * 1298 * Does a synchronous SPI data transfer of the given spi_transfer array. 1299 * 1300 * For more specific semantics see spi_sync(). 1301 * 1302 * Return: zero on success, else a negative error code. 1303 */ 1304 static inline int 1305 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers, 1306 unsigned int num_xfers) 1307 { 1308 struct spi_message msg; 1309 1310 spi_message_init_with_transfers(&msg, xfers, num_xfers); 1311 1312 return spi_sync(spi, &msg); 1313 } 1314 1315 /** 1316 * spi_write - SPI synchronous write 1317 * @spi: device to which data will be written 1318 * @buf: data buffer 1319 * @len: data buffer size 1320 * Context: can sleep 1321 * 1322 * This function writes the buffer @buf. 1323 * Callable only from contexts that can sleep. 1324 * 1325 * Return: zero on success, else a negative error code. 1326 */ 1327 static inline int 1328 spi_write(struct spi_device *spi, const void *buf, size_t len) 1329 { 1330 struct spi_transfer t = { 1331 .tx_buf = buf, 1332 .len = len, 1333 }; 1334 1335 return spi_sync_transfer(spi, &t, 1); 1336 } 1337 1338 /** 1339 * spi_read - SPI synchronous read 1340 * @spi: device from which data will be read 1341 * @buf: data buffer 1342 * @len: data buffer size 1343 * Context: can sleep 1344 * 1345 * This function reads the buffer @buf. 1346 * Callable only from contexts that can sleep. 1347 * 1348 * Return: zero on success, else a negative error code. 1349 */ 1350 static inline int 1351 spi_read(struct spi_device *spi, void *buf, size_t len) 1352 { 1353 struct spi_transfer t = { 1354 .rx_buf = buf, 1355 .len = len, 1356 }; 1357 1358 return spi_sync_transfer(spi, &t, 1); 1359 } 1360 1361 /* This copies txbuf and rxbuf data; for small transfers only! */ 1362 extern int spi_write_then_read(struct spi_device *spi, 1363 const void *txbuf, unsigned n_tx, 1364 void *rxbuf, unsigned n_rx); 1365 1366 /** 1367 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read 1368 * @spi: device with which data will be exchanged 1369 * @cmd: command to be written before data is read back 1370 * Context: can sleep 1371 * 1372 * Callable only from contexts that can sleep. 1373 * 1374 * Return: the (unsigned) eight bit number returned by the 1375 * device, or else a negative error code. 1376 */ 1377 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) 1378 { 1379 ssize_t status; 1380 u8 result; 1381 1382 status = spi_write_then_read(spi, &cmd, 1, &result, 1); 1383 1384 /* Return negative errno or unsigned value */ 1385 return (status < 0) ? status : result; 1386 } 1387 1388 /** 1389 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read 1390 * @spi: device with which data will be exchanged 1391 * @cmd: command to be written before data is read back 1392 * Context: can sleep 1393 * 1394 * The number is returned in wire-order, which is at least sometimes 1395 * big-endian. 1396 * 1397 * Callable only from contexts that can sleep. 1398 * 1399 * Return: the (unsigned) sixteen bit number returned by the 1400 * device, or else a negative error code. 1401 */ 1402 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) 1403 { 1404 ssize_t status; 1405 u16 result; 1406 1407 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1408 1409 /* Return negative errno or unsigned value */ 1410 return (status < 0) ? status : result; 1411 } 1412 1413 /** 1414 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read 1415 * @spi: device with which data will be exchanged 1416 * @cmd: command to be written before data is read back 1417 * Context: can sleep 1418 * 1419 * This function is similar to spi_w8r16, with the exception that it will 1420 * convert the read 16 bit data word from big-endian to native endianness. 1421 * 1422 * Callable only from contexts that can sleep. 1423 * 1424 * Return: the (unsigned) sixteen bit number returned by the device in cpu 1425 * endianness, or else a negative error code. 1426 */ 1427 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd) 1428 1429 { 1430 ssize_t status; 1431 __be16 result; 1432 1433 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1434 if (status < 0) 1435 return status; 1436 1437 return be16_to_cpu(result); 1438 } 1439 1440 /*---------------------------------------------------------------------------*/ 1441 1442 /* 1443 * INTERFACE between board init code and SPI infrastructure. 1444 * 1445 * No SPI driver ever sees these SPI device table segments, but 1446 * it's how the SPI core (or adapters that get hotplugged) grows 1447 * the driver model tree. 1448 * 1449 * As a rule, SPI devices can't be probed. Instead, board init code 1450 * provides a table listing the devices which are present, with enough 1451 * information to bind and set up the device's driver. There's basic 1452 * support for nonstatic configurations too; enough to handle adding 1453 * parport adapters, or microcontrollers acting as USB-to-SPI bridges. 1454 */ 1455 1456 /** 1457 * struct spi_board_info - board-specific template for a SPI device 1458 * @modalias: Initializes spi_device.modalias; identifies the driver. 1459 * @platform_data: Initializes spi_device.platform_data; the particular 1460 * data stored there is driver-specific. 1461 * @swnode: Software node for the device. 1462 * @controller_data: Initializes spi_device.controller_data; some 1463 * controllers need hints about hardware setup, e.g. for DMA. 1464 * @irq: Initializes spi_device.irq; depends on how the board is wired. 1465 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits 1466 * from the chip datasheet and board-specific signal quality issues. 1467 * @bus_num: Identifies which spi_controller parents the spi_device; unused 1468 * by spi_new_device(), and otherwise depends on board wiring. 1469 * @chip_select: Initializes spi_device.chip_select; depends on how 1470 * the board is wired. 1471 * @mode: Initializes spi_device.mode; based on the chip datasheet, board 1472 * wiring (some devices support both 3WIRE and standard modes), and 1473 * possibly presence of an inverter in the chipselect path. 1474 * 1475 * When adding new SPI devices to the device tree, these structures serve 1476 * as a partial device template. They hold information which can't always 1477 * be determined by drivers. Information that probe() can establish (such 1478 * as the default transfer wordsize) is not included here. 1479 * 1480 * These structures are used in two places. Their primary role is to 1481 * be stored in tables of board-specific device descriptors, which are 1482 * declared early in board initialization and then used (much later) to 1483 * populate a controller's device tree after the that controller's driver 1484 * initializes. A secondary (and atypical) role is as a parameter to 1485 * spi_new_device() call, which happens after those controller drivers 1486 * are active in some dynamic board configuration models. 1487 */ 1488 struct spi_board_info { 1489 /* The device name and module name are coupled, like platform_bus; 1490 * "modalias" is normally the driver name. 1491 * 1492 * platform_data goes to spi_device.dev.platform_data, 1493 * controller_data goes to spi_device.controller_data, 1494 * irq is copied too 1495 */ 1496 char modalias[SPI_NAME_SIZE]; 1497 const void *platform_data; 1498 const struct software_node *swnode; 1499 void *controller_data; 1500 int irq; 1501 1502 /* Slower signaling on noisy or low voltage boards */ 1503 u32 max_speed_hz; 1504 1505 1506 /* bus_num is board specific and matches the bus_num of some 1507 * spi_controller that will probably be registered later. 1508 * 1509 * chip_select reflects how this chip is wired to that master; 1510 * it's less than num_chipselect. 1511 */ 1512 u16 bus_num; 1513 u16 chip_select; 1514 1515 /* mode becomes spi_device.mode, and is essential for chips 1516 * where the default of SPI_CS_HIGH = 0 is wrong. 1517 */ 1518 u32 mode; 1519 1520 /* ... may need additional spi_device chip config data here. 1521 * avoid stuff protocol drivers can set; but include stuff 1522 * needed to behave without being bound to a driver: 1523 * - quirks like clock rate mattering when not selected 1524 */ 1525 }; 1526 1527 #ifdef CONFIG_SPI 1528 extern int 1529 spi_register_board_info(struct spi_board_info const *info, unsigned n); 1530 #else 1531 /* Board init code may ignore whether SPI is configured or not */ 1532 static inline int 1533 spi_register_board_info(struct spi_board_info const *info, unsigned n) 1534 { return 0; } 1535 #endif 1536 1537 /* If you're hotplugging an adapter with devices (parport, usb, etc) 1538 * use spi_new_device() to describe each device. You can also call 1539 * spi_unregister_device() to start making that device vanish, but 1540 * normally that would be handled by spi_unregister_controller(). 1541 * 1542 * You can also use spi_alloc_device() and spi_add_device() to use a two 1543 * stage registration sequence for each spi_device. This gives the caller 1544 * some more control over the spi_device structure before it is registered, 1545 * but requires that caller to initialize fields that would otherwise 1546 * be defined using the board info. 1547 */ 1548 extern struct spi_device * 1549 spi_alloc_device(struct spi_controller *ctlr); 1550 1551 extern int 1552 spi_add_device(struct spi_device *spi); 1553 1554 extern struct spi_device * 1555 spi_new_device(struct spi_controller *, struct spi_board_info *); 1556 1557 extern void spi_unregister_device(struct spi_device *spi); 1558 1559 extern const struct spi_device_id * 1560 spi_get_device_id(const struct spi_device *sdev); 1561 1562 extern const void * 1563 spi_get_device_match_data(const struct spi_device *sdev); 1564 1565 static inline bool 1566 spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer) 1567 { 1568 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers); 1569 } 1570 1571 /* Compatibility layer */ 1572 #define spi_master spi_controller 1573 1574 #define SPI_MASTER_HALF_DUPLEX SPI_CONTROLLER_HALF_DUPLEX 1575 #define SPI_MASTER_NO_RX SPI_CONTROLLER_NO_RX 1576 #define SPI_MASTER_NO_TX SPI_CONTROLLER_NO_TX 1577 #define SPI_MASTER_MUST_RX SPI_CONTROLLER_MUST_RX 1578 #define SPI_MASTER_MUST_TX SPI_CONTROLLER_MUST_TX 1579 1580 #define spi_master_get_devdata(_ctlr) spi_controller_get_devdata(_ctlr) 1581 #define spi_master_set_devdata(_ctlr, _data) \ 1582 spi_controller_set_devdata(_ctlr, _data) 1583 #define spi_master_get(_ctlr) spi_controller_get(_ctlr) 1584 #define spi_master_put(_ctlr) spi_controller_put(_ctlr) 1585 #define spi_master_suspend(_ctlr) spi_controller_suspend(_ctlr) 1586 #define spi_master_resume(_ctlr) spi_controller_resume(_ctlr) 1587 1588 #define spi_register_master(_ctlr) spi_register_controller(_ctlr) 1589 #define devm_spi_register_master(_dev, _ctlr) \ 1590 devm_spi_register_controller(_dev, _ctlr) 1591 #define spi_unregister_master(_ctlr) spi_unregister_controller(_ctlr) 1592 1593 #endif /* __LINUX_SPI_H */ 1594