1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
3 
4 #ifndef __SDW_INTEL_H
5 #define __SDW_INTEL_H
6 
7 #include <linux/irqreturn.h>
8 #include <linux/soundwire/sdw.h>
9 
10 #define SDW_SHIM_BASE			0x2C000
11 #define SDW_ALH_BASE			0x2C800
12 #define SDW_LINK_BASE			0x30000
13 #define SDW_LINK_SIZE			0x10000
14 
15 /* Intel SHIM Registers Definition */
16 #define SDW_SHIM_LCAP			0x0
17 #define SDW_SHIM_LCTL			0x4
18 #define SDW_SHIM_IPPTR			0x8
19 #define SDW_SHIM_SYNC			0xC
20 
21 #define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
22 #define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
23 #define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
24 #define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
25 #define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))
26 #define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))
27 
28 #define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 * (y)))
29 #define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 * (y)))
30 #define SDW_SHIM_PDMSCAP(x)		(0x062 + 0x60 * (x))
31 #define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))
32 #define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))
33 
34 #define SDW_SHIM_WAKEEN			0x190
35 #define SDW_SHIM_WAKESTS		0x192
36 
37 #define SDW_SHIM_LCTL_SPA		BIT(0)
38 #define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
39 #define SDW_SHIM_LCTL_CPA		BIT(8)
40 #define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)
41 
42 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 / SDW_CADENCE_GSYNC_KHZ - 1)
43 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 / SDW_CADENCE_GSYNC_KHZ - 1)
44 #define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
45 #define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
46 #define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
47 #define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
48 #define SDW_SHIM_SYNC_SYNCGO		BIT(24)
49 
50 #define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
51 #define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
52 #define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)
53 
54 #define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
55 #define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
56 #define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
57 #define SDW_SHIM_PCMSYCM_DIR		BIT(15)
58 
59 #define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)
60 #define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)
61 #define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)
62 #define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)
63 
64 #define SDW_SHIM_IOCTL_MIF		BIT(0)
65 #define SDW_SHIM_IOCTL_CO		BIT(1)
66 #define SDW_SHIM_IOCTL_COE		BIT(2)
67 #define SDW_SHIM_IOCTL_DO		BIT(3)
68 #define SDW_SHIM_IOCTL_DOE		BIT(4)
69 #define SDW_SHIM_IOCTL_BKE		BIT(5)
70 #define SDW_SHIM_IOCTL_WPDD		BIT(6)
71 #define SDW_SHIM_IOCTL_CIBD		BIT(8)
72 #define SDW_SHIM_IOCTL_DIBD		BIT(9)
73 
74 #define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
75 #define SDW_SHIM_CTMCTL_DODS		BIT(1)
76 #define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)
77 
78 #define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
79 #define SDW_SHIM_WAKESTS_STATUS		BIT(0)
80 
81 /* Intel ALH Register definitions */
82 #define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
83 #define SDW_ALH_NUM_STREAMS		64
84 
85 #define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
86 #define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
87 #define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)
88 
89 /**
90  * struct sdw_intel_stream_params_data: configuration passed during
91  * the @params_stream callback, e.g. for interaction with DSP
92  * firmware.
93  */
94 struct sdw_intel_stream_params_data {
95 	struct snd_pcm_substream *substream;
96 	struct snd_soc_dai *dai;
97 	struct snd_pcm_hw_params *hw_params;
98 	int link_id;
99 	int alh_stream_id;
100 };
101 
102 /**
103  * struct sdw_intel_stream_free_data: configuration passed during
104  * the @free_stream callback, e.g. for interaction with DSP
105  * firmware.
106  */
107 struct sdw_intel_stream_free_data {
108 	struct snd_pcm_substream *substream;
109 	struct snd_soc_dai *dai;
110 	int link_id;
111 };
112 
113 /**
114  * struct sdw_intel_ops: Intel audio driver callback ops
115  *
116  */
117 struct sdw_intel_ops {
118 	int (*params_stream)(struct device *dev,
119 			     struct sdw_intel_stream_params_data *params_data);
120 	int (*free_stream)(struct device *dev,
121 			   struct sdw_intel_stream_free_data *free_data);
122 };
123 
124 /**
125  * struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables
126  * @handle: ACPI controller handle
127  * @count: link count found with "sdw-master-count" property
128  * @link_mask: bit-wise mask listing links enabled by BIOS menu
129  *
130  * this structure could be expanded to e.g. provide all the _ADR
131  * information in case the link_mask is not sufficient to identify
132  * platform capabilities.
133  */
134 struct sdw_intel_acpi_info {
135 	acpi_handle handle;
136 	int count;
137 	u32 link_mask;
138 };
139 
140 struct sdw_intel_link_dev;
141 
142 /* Intel clock-stop/pm_runtime quirk definitions */
143 
144 /*
145  * Force the clock to remain on during pm_runtime suspend. This might
146  * be needed if Slave devices do not have an alternate clock source or
147  * if the latency requirements are very strict.
148  */
149 #define SDW_INTEL_CLK_STOP_NOT_ALLOWED		BIT(0)
150 
151 /*
152  * Stop the bus during pm_runtime suspend. If set, a complete bus
153  * reset and re-enumeration will be performed when the bus
154  * restarts. This mode shall not be used if Slave devices can generate
155  * in-band wakes.
156  */
157 #define SDW_INTEL_CLK_STOP_TEARDOWN		BIT(1)
158 
159 /*
160  * Stop the bus during pm_suspend if Slaves are not wake capable
161  * (e.g. speaker amplifiers). The clock-stop mode is typically
162  * slightly higher power than when the IP is completely powered-off.
163  */
164 #define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY	BIT(2)
165 
166 /*
167  * Require a bus reset (and complete re-enumeration) when exiting
168  * clock stop modes. This may be needed if the controller power was
169  * turned off and all context lost. This quirk shall not be used if a
170  * Slave device needs to remain enumerated and keep its context,
171  * e.g. to provide the reasons for the wake, report acoustic events or
172  * pass a history buffer.
173  */
174 #define SDW_INTEL_CLK_STOP_BUS_RESET		BIT(3)
175 
176 struct sdw_intel_slave_id {
177 	int link_id;
178 	struct sdw_slave_id id;
179 };
180 
181 /**
182  * struct sdw_intel_ctx - context allocated by the controller
183  * driver probe
184  * @count: link count
185  * @mmio_base: mmio base of SoundWire registers, only used to check
186  * hardware capabilities after all power dependencies are settled.
187  * @link_mask: bit-wise mask listing SoundWire links reported by the
188  * Controller
189  * @num_slaves: total number of devices exposed across all enabled links
190  * @handle: ACPI parent handle
191  * @ldev: information for each link (controller-specific and kept
192  * opaque here)
193  * @ids: array of slave_id, representing Slaves exposed across all enabled
194  * links
195  * @link_list: list to handle interrupts across all links
196  * @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
197  * @shim_mask: flags to track initialization of SHIM shared registers
198  * @shim_base: sdw shim base.
199  * @alh_base: sdw alh base.
200  */
201 struct sdw_intel_ctx {
202 	int count;
203 	void __iomem *mmio_base;
204 	u32 link_mask;
205 	int num_slaves;
206 	acpi_handle handle;
207 	struct sdw_intel_link_dev **ldev;
208 	struct sdw_intel_slave_id *ids;
209 	struct list_head link_list;
210 	struct mutex shim_lock; /* lock for access to shared SHIM registers */
211 	u32 shim_mask;
212 	u32 shim_base;
213 	u32 alh_base;
214 };
215 
216 /**
217  * struct sdw_intel_res - Soundwire Intel global resource structure,
218  * typically populated by the DSP driver
219  *
220  * @count: link count
221  * @mmio_base: mmio base of SoundWire registers
222  * @irq: interrupt number
223  * @handle: ACPI parent handle
224  * @parent: parent device
225  * @ops: callback ops
226  * @dev: device implementing hwparams and free callbacks
227  * @link_mask: bit-wise mask listing links selected by the DSP driver
228  * This mask may be a subset of the one reported by the controller since
229  * machine-specific quirks are handled in the DSP driver.
230  * @clock_stop_quirks: mask array of possible behaviors requested by the
231  * DSP driver. The quirks are common for all links for now.
232  * @shim_base: sdw shim base.
233  * @alh_base: sdw alh base.
234  */
235 struct sdw_intel_res {
236 	int count;
237 	void __iomem *mmio_base;
238 	int irq;
239 	acpi_handle handle;
240 	struct device *parent;
241 	const struct sdw_intel_ops *ops;
242 	struct device *dev;
243 	u32 link_mask;
244 	u32 clock_stop_quirks;
245 	u32 shim_base;
246 	u32 alh_base;
247 };
248 
249 /*
250  * On Intel platforms, the SoundWire IP has dependencies on power
251  * rails shared with the DSP, and the initialization steps are split
252  * in three. First an ACPI scan to check what the firmware describes
253  * in DSDT tables, then an allocation step (with no hardware
254  * configuration but with all the relevant devices created) and last
255  * the actual hardware configuration. The final stage is a global
256  * interrupt enable which is controlled by the DSP driver. Splitting
257  * these phases helps simplify the boot flow and make early decisions
258  * on e.g. which machine driver to select (I2S mode, HDaudio or
259  * SoundWire).
260  */
261 int sdw_intel_acpi_scan(acpi_handle *parent_handle,
262 			struct sdw_intel_acpi_info *info);
263 
264 void sdw_intel_process_wakeen_event(struct sdw_intel_ctx *ctx);
265 
266 struct sdw_intel_ctx *
267 sdw_intel_probe(struct sdw_intel_res *res);
268 
269 int sdw_intel_startup(struct sdw_intel_ctx *ctx);
270 
271 void sdw_intel_exit(struct sdw_intel_ctx *ctx);
272 
273 void sdw_intel_enable_irq(void __iomem *mmio_base, bool enable);
274 
275 irqreturn_t sdw_intel_thread(int irq, void *dev_id);
276 
277 #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE      BIT(1)
278 
279 #endif
280