1804775dfSFelix Fietkau #ifndef __MTK_WED_H 2804775dfSFelix Fietkau #define __MTK_WED_H 3804775dfSFelix Fietkau 4804775dfSFelix Fietkau #include <linux/kernel.h> 5804775dfSFelix Fietkau #include <linux/rcupdate.h> 6804775dfSFelix Fietkau #include <linux/regmap.h> 7804775dfSFelix Fietkau #include <linux/pci.h> 8*4c5de09eSLorenzo Bianconi #include <linux/skbuff.h> 9804775dfSFelix Fietkau 10804775dfSFelix Fietkau #define MTK_WED_TX_QUEUES 2 11084d60ceSLorenzo Bianconi #define MTK_WED_RX_QUEUES 2 12804775dfSFelix Fietkau 13*4c5de09eSLorenzo Bianconi #define WED_WO_STA_REC 0x6 14*4c5de09eSLorenzo Bianconi 15804775dfSFelix Fietkau struct mtk_wed_hw; 16804775dfSFelix Fietkau struct mtk_wdma_desc; 17804775dfSFelix Fietkau 18cc514101SSujuan Chen enum mtk_wed_wo_cmd { 19cc514101SSujuan Chen MTK_WED_WO_CMD_WED_CFG, 20cc514101SSujuan Chen MTK_WED_WO_CMD_WED_RX_STAT, 21cc514101SSujuan Chen MTK_WED_WO_CMD_RRO_SER, 22cc514101SSujuan Chen MTK_WED_WO_CMD_DBG_INFO, 23cc514101SSujuan Chen MTK_WED_WO_CMD_DEV_INFO, 24cc514101SSujuan Chen MTK_WED_WO_CMD_BSS_INFO, 25cc514101SSujuan Chen MTK_WED_WO_CMD_STA_REC, 26cc514101SSujuan Chen MTK_WED_WO_CMD_DEV_INFO_DUMP, 27cc514101SSujuan Chen MTK_WED_WO_CMD_BSS_INFO_DUMP, 28cc514101SSujuan Chen MTK_WED_WO_CMD_STA_REC_DUMP, 29cc514101SSujuan Chen MTK_WED_WO_CMD_BA_INFO_DUMP, 30cc514101SSujuan Chen MTK_WED_WO_CMD_FBCMD_Q_DUMP, 31cc514101SSujuan Chen MTK_WED_WO_CMD_FW_LOG_CTRL, 32cc514101SSujuan Chen MTK_WED_WO_CMD_LOG_FLUSH, 33cc514101SSujuan Chen MTK_WED_WO_CMD_CHANGE_STATE, 34cc514101SSujuan Chen MTK_WED_WO_CMD_CPU_STATS_ENABLE, 35cc514101SSujuan Chen MTK_WED_WO_CMD_CPU_STATS_DUMP, 36cc514101SSujuan Chen MTK_WED_WO_CMD_EXCEPTION_INIT, 37cc514101SSujuan Chen MTK_WED_WO_CMD_PROF_CTRL, 38cc514101SSujuan Chen MTK_WED_WO_CMD_STA_BA_DUMP, 39cc514101SSujuan Chen MTK_WED_WO_CMD_BA_CTRL_DUMP, 40cc514101SSujuan Chen MTK_WED_WO_CMD_RXCNT_CTRL, 41cc514101SSujuan Chen MTK_WED_WO_CMD_RXCNT_INFO, 42cc514101SSujuan Chen MTK_WED_WO_CMD_SET_CAP, 43cc514101SSujuan Chen MTK_WED_WO_CMD_CCIF_RING_DUMP, 44cc514101SSujuan Chen MTK_WED_WO_CMD_WED_END 45cc514101SSujuan Chen }; 46cc514101SSujuan Chen 47*4c5de09eSLorenzo Bianconi struct mtk_rxbm_desc { 48*4c5de09eSLorenzo Bianconi __le32 buf0; 49*4c5de09eSLorenzo Bianconi __le32 token; 50*4c5de09eSLorenzo Bianconi } __packed __aligned(4); 51*4c5de09eSLorenzo Bianconi 522b2ba3ecSLorenzo Bianconi enum mtk_wed_bus_tye { 532b2ba3ecSLorenzo Bianconi MTK_WED_BUS_PCIE, 542b2ba3ecSLorenzo Bianconi MTK_WED_BUS_AXI, 552b2ba3ecSLorenzo Bianconi }; 562b2ba3ecSLorenzo Bianconi 57*4c5de09eSLorenzo Bianconi #define MTK_WED_RING_CONFIGURED BIT(0) 58804775dfSFelix Fietkau struct mtk_wed_ring { 59804775dfSFelix Fietkau struct mtk_wdma_desc *desc; 60804775dfSFelix Fietkau dma_addr_t desc_phys; 61de84a090SLorenzo Bianconi u32 desc_size; 62804775dfSFelix Fietkau int size; 63*4c5de09eSLorenzo Bianconi u32 flags; 64804775dfSFelix Fietkau 65804775dfSFelix Fietkau u32 reg_base; 66804775dfSFelix Fietkau void __iomem *wpdma; 67804775dfSFelix Fietkau }; 68804775dfSFelix Fietkau 69*4c5de09eSLorenzo Bianconi struct mtk_wed_wo_rx_stats { 70*4c5de09eSLorenzo Bianconi __le16 wlan_idx; 71*4c5de09eSLorenzo Bianconi __le16 tid; 72*4c5de09eSLorenzo Bianconi __le32 rx_pkt_cnt; 73*4c5de09eSLorenzo Bianconi __le32 rx_byte_cnt; 74*4c5de09eSLorenzo Bianconi __le32 rx_err_cnt; 75*4c5de09eSLorenzo Bianconi __le32 rx_drop_cnt; 76*4c5de09eSLorenzo Bianconi }; 77*4c5de09eSLorenzo Bianconi 78804775dfSFelix Fietkau struct mtk_wed_device { 79804775dfSFelix Fietkau #ifdef CONFIG_NET_MEDIATEK_SOC_WED 80804775dfSFelix Fietkau const struct mtk_wed_ops *ops; 81804775dfSFelix Fietkau struct device *dev; 82804775dfSFelix Fietkau struct mtk_wed_hw *hw; 83804775dfSFelix Fietkau bool init_done, running; 84804775dfSFelix Fietkau int wdma_idx; 85804775dfSFelix Fietkau int irq; 86*4c5de09eSLorenzo Bianconi u8 version; 87804775dfSFelix Fietkau 88804775dfSFelix Fietkau struct mtk_wed_ring tx_ring[MTK_WED_TX_QUEUES]; 89*4c5de09eSLorenzo Bianconi struct mtk_wed_ring rx_ring[MTK_WED_RX_QUEUES]; 90804775dfSFelix Fietkau struct mtk_wed_ring txfree_ring; 91*4c5de09eSLorenzo Bianconi struct mtk_wed_ring tx_wdma[MTK_WED_TX_QUEUES]; 92084d60ceSLorenzo Bianconi struct mtk_wed_ring rx_wdma[MTK_WED_RX_QUEUES]; 93804775dfSFelix Fietkau 94804775dfSFelix Fietkau struct { 95804775dfSFelix Fietkau int size; 96804775dfSFelix Fietkau void **pages; 97804775dfSFelix Fietkau struct mtk_wdma_desc *desc; 98804775dfSFelix Fietkau dma_addr_t desc_phys; 99*4c5de09eSLorenzo Bianconi } tx_buf_ring; 100*4c5de09eSLorenzo Bianconi 101*4c5de09eSLorenzo Bianconi struct { 102*4c5de09eSLorenzo Bianconi int size; 103*4c5de09eSLorenzo Bianconi struct page_frag_cache rx_page; 104*4c5de09eSLorenzo Bianconi struct mtk_rxbm_desc *desc; 105*4c5de09eSLorenzo Bianconi dma_addr_t desc_phys; 106*4c5de09eSLorenzo Bianconi } rx_buf_ring; 107*4c5de09eSLorenzo Bianconi 108*4c5de09eSLorenzo Bianconi struct { 109*4c5de09eSLorenzo Bianconi struct mtk_wed_ring ring; 110*4c5de09eSLorenzo Bianconi dma_addr_t miod_phys; 111*4c5de09eSLorenzo Bianconi dma_addr_t fdbk_phys; 112*4c5de09eSLorenzo Bianconi } rro; 113804775dfSFelix Fietkau 114804775dfSFelix Fietkau /* filled by driver: */ 115804775dfSFelix Fietkau struct { 1162b2ba3ecSLorenzo Bianconi union { 1172b2ba3ecSLorenzo Bianconi struct platform_device *platform_dev; 118804775dfSFelix Fietkau struct pci_dev *pci_dev; 1192b2ba3ecSLorenzo Bianconi }; 1202b2ba3ecSLorenzo Bianconi enum mtk_wed_bus_tye bus_type; 121*4c5de09eSLorenzo Bianconi void __iomem *base; 122*4c5de09eSLorenzo Bianconi u32 phy_base; 123804775dfSFelix Fietkau 124804775dfSFelix Fietkau u32 wpdma_phys; 125de84a090SLorenzo Bianconi u32 wpdma_int; 126de84a090SLorenzo Bianconi u32 wpdma_mask; 127de84a090SLorenzo Bianconi u32 wpdma_tx; 128de84a090SLorenzo Bianconi u32 wpdma_txfree; 129*4c5de09eSLorenzo Bianconi u32 wpdma_rx_glo; 130*4c5de09eSLorenzo Bianconi u32 wpdma_rx; 131*4c5de09eSLorenzo Bianconi 132*4c5de09eSLorenzo Bianconi bool wcid_512; 133804775dfSFelix Fietkau 134804775dfSFelix Fietkau u16 token_start; 135804775dfSFelix Fietkau unsigned int nbuf; 136*4c5de09eSLorenzo Bianconi unsigned int rx_nbuf; 137*4c5de09eSLorenzo Bianconi unsigned int rx_npkt; 138*4c5de09eSLorenzo Bianconi unsigned int rx_size; 139804775dfSFelix Fietkau 140de84a090SLorenzo Bianconi u8 tx_tbit[MTK_WED_TX_QUEUES]; 141*4c5de09eSLorenzo Bianconi u8 rx_tbit[MTK_WED_RX_QUEUES]; 142de84a090SLorenzo Bianconi u8 txfree_tbit; 143de84a090SLorenzo Bianconi 144804775dfSFelix Fietkau u32 (*init_buf)(void *ptr, dma_addr_t phys, int token_id); 145804775dfSFelix Fietkau int (*offload_enable)(struct mtk_wed_device *wed); 146804775dfSFelix Fietkau void (*offload_disable)(struct mtk_wed_device *wed); 147*4c5de09eSLorenzo Bianconi u32 (*init_rx_buf)(struct mtk_wed_device *wed, int size); 148*4c5de09eSLorenzo Bianconi void (*release_rx_buf)(struct mtk_wed_device *wed); 149*4c5de09eSLorenzo Bianconi void (*update_wo_rx_stats)(struct mtk_wed_device *wed, 150*4c5de09eSLorenzo Bianconi struct mtk_wed_wo_rx_stats *stats); 151804775dfSFelix Fietkau } wlan; 152804775dfSFelix Fietkau #endif 153804775dfSFelix Fietkau }; 154804775dfSFelix Fietkau 155804775dfSFelix Fietkau struct mtk_wed_ops { 156804775dfSFelix Fietkau int (*attach)(struct mtk_wed_device *dev); 157804775dfSFelix Fietkau int (*tx_ring_setup)(struct mtk_wed_device *dev, int ring, 158804775dfSFelix Fietkau void __iomem *regs); 159*4c5de09eSLorenzo Bianconi int (*rx_ring_setup)(struct mtk_wed_device *dev, int ring, 160*4c5de09eSLorenzo Bianconi void __iomem *regs); 161804775dfSFelix Fietkau int (*txfree_ring_setup)(struct mtk_wed_device *dev, 162804775dfSFelix Fietkau void __iomem *regs); 163*4c5de09eSLorenzo Bianconi int (*msg_update)(struct mtk_wed_device *dev, int cmd_id, 164*4c5de09eSLorenzo Bianconi void *data, int len); 165804775dfSFelix Fietkau void (*detach)(struct mtk_wed_device *dev); 166*4c5de09eSLorenzo Bianconi void (*ppe_check)(struct mtk_wed_device *dev, struct sk_buff *skb, 167*4c5de09eSLorenzo Bianconi u32 reason, u32 hash); 168804775dfSFelix Fietkau 169804775dfSFelix Fietkau void (*stop)(struct mtk_wed_device *dev); 170804775dfSFelix Fietkau void (*start)(struct mtk_wed_device *dev, u32 irq_mask); 171804775dfSFelix Fietkau void (*reset_dma)(struct mtk_wed_device *dev); 172804775dfSFelix Fietkau 173804775dfSFelix Fietkau u32 (*reg_read)(struct mtk_wed_device *dev, u32 reg); 174804775dfSFelix Fietkau void (*reg_write)(struct mtk_wed_device *dev, u32 reg, u32 val); 175804775dfSFelix Fietkau 176804775dfSFelix Fietkau u32 (*irq_get)(struct mtk_wed_device *dev, u32 mask); 177804775dfSFelix Fietkau void (*irq_set_mask)(struct mtk_wed_device *dev, u32 mask); 178804775dfSFelix Fietkau }; 179804775dfSFelix Fietkau 180804775dfSFelix Fietkau extern const struct mtk_wed_ops __rcu *mtk_soc_wed_ops; 181804775dfSFelix Fietkau 182804775dfSFelix Fietkau static inline int 183804775dfSFelix Fietkau mtk_wed_device_attach(struct mtk_wed_device *dev) 184804775dfSFelix Fietkau { 185804775dfSFelix Fietkau int ret = -ENODEV; 186804775dfSFelix Fietkau 187804775dfSFelix Fietkau #ifdef CONFIG_NET_MEDIATEK_SOC_WED 188804775dfSFelix Fietkau rcu_read_lock(); 189804775dfSFelix Fietkau dev->ops = rcu_dereference(mtk_soc_wed_ops); 190804775dfSFelix Fietkau if (dev->ops) 191804775dfSFelix Fietkau ret = dev->ops->attach(dev); 192804775dfSFelix Fietkau else 193804775dfSFelix Fietkau rcu_read_unlock(); 194804775dfSFelix Fietkau 195804775dfSFelix Fietkau if (ret) 196804775dfSFelix Fietkau dev->ops = NULL; 197804775dfSFelix Fietkau #endif 198804775dfSFelix Fietkau 199804775dfSFelix Fietkau return ret; 200804775dfSFelix Fietkau } 201804775dfSFelix Fietkau 202*4c5de09eSLorenzo Bianconi static inline bool 203*4c5de09eSLorenzo Bianconi mtk_wed_get_rx_capa(struct mtk_wed_device *dev) 204*4c5de09eSLorenzo Bianconi { 205*4c5de09eSLorenzo Bianconi #ifdef CONFIG_NET_MEDIATEK_SOC_WED 206*4c5de09eSLorenzo Bianconi return dev->version != 1; 207*4c5de09eSLorenzo Bianconi #else 208*4c5de09eSLorenzo Bianconi return false; 209*4c5de09eSLorenzo Bianconi #endif 210*4c5de09eSLorenzo Bianconi } 211*4c5de09eSLorenzo Bianconi 212804775dfSFelix Fietkau #ifdef CONFIG_NET_MEDIATEK_SOC_WED 213804775dfSFelix Fietkau #define mtk_wed_device_active(_dev) !!(_dev)->ops 214804775dfSFelix Fietkau #define mtk_wed_device_detach(_dev) (_dev)->ops->detach(_dev) 215804775dfSFelix Fietkau #define mtk_wed_device_start(_dev, _mask) (_dev)->ops->start(_dev, _mask) 216804775dfSFelix Fietkau #define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) \ 217804775dfSFelix Fietkau (_dev)->ops->tx_ring_setup(_dev, _ring, _regs) 218804775dfSFelix Fietkau #define mtk_wed_device_txfree_ring_setup(_dev, _regs) \ 219804775dfSFelix Fietkau (_dev)->ops->txfree_ring_setup(_dev, _regs) 220804775dfSFelix Fietkau #define mtk_wed_device_reg_read(_dev, _reg) \ 221804775dfSFelix Fietkau (_dev)->ops->reg_read(_dev, _reg) 222804775dfSFelix Fietkau #define mtk_wed_device_reg_write(_dev, _reg, _val) \ 223804775dfSFelix Fietkau (_dev)->ops->reg_write(_dev, _reg, _val) 224804775dfSFelix Fietkau #define mtk_wed_device_irq_get(_dev, _mask) \ 225804775dfSFelix Fietkau (_dev)->ops->irq_get(_dev, _mask) 226804775dfSFelix Fietkau #define mtk_wed_device_irq_set_mask(_dev, _mask) \ 227804775dfSFelix Fietkau (_dev)->ops->irq_set_mask(_dev, _mask) 228*4c5de09eSLorenzo Bianconi #define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs) \ 229*4c5de09eSLorenzo Bianconi (_dev)->ops->rx_ring_setup(_dev, _ring, _regs) 230*4c5de09eSLorenzo Bianconi #define mtk_wed_device_ppe_check(_dev, _skb, _reason, _hash) \ 231*4c5de09eSLorenzo Bianconi (_dev)->ops->ppe_check(_dev, _skb, _reason, _hash) 232*4c5de09eSLorenzo Bianconi #define mtk_wed_device_update_msg(_dev, _id, _msg, _len) \ 233*4c5de09eSLorenzo Bianconi (_dev)->ops->msg_update(_dev, _id, _msg, _len) 234804775dfSFelix Fietkau #else 235804775dfSFelix Fietkau static inline bool mtk_wed_device_active(struct mtk_wed_device *dev) 236804775dfSFelix Fietkau { 237804775dfSFelix Fietkau return false; 238804775dfSFelix Fietkau } 239804775dfSFelix Fietkau #define mtk_wed_device_detach(_dev) do {} while (0) 240804775dfSFelix Fietkau #define mtk_wed_device_start(_dev, _mask) do {} while (0) 241804775dfSFelix Fietkau #define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) -ENODEV 242804775dfSFelix Fietkau #define mtk_wed_device_txfree_ring_setup(_dev, _ring, _regs) -ENODEV 243804775dfSFelix Fietkau #define mtk_wed_device_reg_read(_dev, _reg) 0 244804775dfSFelix Fietkau #define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0) 245804775dfSFelix Fietkau #define mtk_wed_device_irq_get(_dev, _mask) 0 246804775dfSFelix Fietkau #define mtk_wed_device_irq_set_mask(_dev, _mask) do {} while (0) 247*4c5de09eSLorenzo Bianconi #define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs) -ENODEV 248*4c5de09eSLorenzo Bianconi #define mtk_wed_device_ppe_check(_dev, _skb, _reason, _hash) do {} while (0) 249*4c5de09eSLorenzo Bianconi #define mtk_wed_device_update_msg(_dev, _id, _msg, _len) -ENODEV 250804775dfSFelix Fietkau #endif 251804775dfSFelix Fietkau 252804775dfSFelix Fietkau #endif 253