1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2b2623a61SMagnus Damm /* 3b2623a61SMagnus Damm * Header for the new SH dmaengine driver 4b2623a61SMagnus Damm * 5b2623a61SMagnus Damm * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 6b2623a61SMagnus Damm */ 7b2623a61SMagnus Damm #ifndef SH_DMA_H 8b2623a61SMagnus Damm #define SH_DMA_H 9b2623a61SMagnus Damm 10b2623a61SMagnus Damm #include <linux/dmaengine.h> 115902c9a7SGuennadi Liakhovetski #include <linux/list.h> 125902c9a7SGuennadi Liakhovetski #include <linux/shdma-base.h> 13ce3a1ab7SGuennadi Liakhovetski #include <linux/types.h> 14ce3a1ab7SGuennadi Liakhovetski 15ce3a1ab7SGuennadi Liakhovetski struct device; 16b2623a61SMagnus Damm 17b2623a61SMagnus Damm /* Used by slave DMA clients to request DMA to/from a specific peripheral */ 18b2623a61SMagnus Damm struct sh_dmae_slave { 19ce3a1ab7SGuennadi Liakhovetski struct shdma_slave shdma_slave; /* Set by the platform */ 20b2623a61SMagnus Damm }; 21b2623a61SMagnus Damm 22ce3a1ab7SGuennadi Liakhovetski /* 23ce3a1ab7SGuennadi Liakhovetski * Supplied by platforms to specify, how a DMA channel has to be configured for 24ce3a1ab7SGuennadi Liakhovetski * a certain peripheral 25ce3a1ab7SGuennadi Liakhovetski */ 26b2623a61SMagnus Damm struct sh_dmae_slave_config { 27c2cdb7e4SGuennadi Liakhovetski int slave_id; 28b2623a61SMagnus Damm dma_addr_t addr; 29b2623a61SMagnus Damm u32 chcr; 30b2623a61SMagnus Damm char mid_rid; 31b2623a61SMagnus Damm }; 32b2623a61SMagnus Damm 33ca8b3878SGuennadi Liakhovetski /** 34ca8b3878SGuennadi Liakhovetski * struct sh_dmae_channel - DMAC channel platform data 35ca8b3878SGuennadi Liakhovetski * @offset: register offset within the main IOMEM resource 36ca8b3878SGuennadi Liakhovetski * @dmars: channel DMARS register offset 37ca8b3878SGuennadi Liakhovetski * @chclr_offset: channel CHCLR register offset 38ca8b3878SGuennadi Liakhovetski * @dmars_bit: channel DMARS field offset within the register 39ca8b3878SGuennadi Liakhovetski * @chclr_bit: bit position, to be set to reset the channel 40ca8b3878SGuennadi Liakhovetski */ 41b2623a61SMagnus Damm struct sh_dmae_channel { 42b2623a61SMagnus Damm unsigned int offset; 43b2623a61SMagnus Damm unsigned int dmars; 44c11b46c3SGuennadi Liakhovetski unsigned int chclr_offset; 45ca8b3878SGuennadi Liakhovetski unsigned char dmars_bit; 46ca8b3878SGuennadi Liakhovetski unsigned char chclr_bit; 47b2623a61SMagnus Damm }; 48b2623a61SMagnus Damm 49ca8b3878SGuennadi Liakhovetski /** 50ca8b3878SGuennadi Liakhovetski * struct sh_dmae_pdata - DMAC platform data 51ca8b3878SGuennadi Liakhovetski * @slave: array of slaves 52ca8b3878SGuennadi Liakhovetski * @slave_num: number of slaves in the above array 53ca8b3878SGuennadi Liakhovetski * @channel: array of DMA channels 54ca8b3878SGuennadi Liakhovetski * @channel_num: number of channels in the above array 55ca8b3878SGuennadi Liakhovetski * @ts_low_shift: shift of the low part of the TS field 56ca8b3878SGuennadi Liakhovetski * @ts_low_mask: low TS field mask 57ca8b3878SGuennadi Liakhovetski * @ts_high_shift: additional shift of the high part of the TS field 58ca8b3878SGuennadi Liakhovetski * @ts_high_mask: high TS field mask 59ca8b3878SGuennadi Liakhovetski * @ts_shift: array of Transfer Size shifts, indexed by TS value 60ca8b3878SGuennadi Liakhovetski * @ts_shift_num: number of shifts in the above array 61ca8b3878SGuennadi Liakhovetski * @dmaor_init: DMAOR initialisation value 62ca8b3878SGuennadi Liakhovetski * @chcr_offset: CHCR address offset 63ca8b3878SGuennadi Liakhovetski * @chcr_ie_bit: CHCR Interrupt Enable bit 64ca8b3878SGuennadi Liakhovetski * @dmaor_is_32bit: DMAOR is a 32-bit register 65ca8b3878SGuennadi Liakhovetski * @needs_tend_set: the TEND register has to be set 66ca8b3878SGuennadi Liakhovetski * @no_dmars: DMAC has no DMARS registers 67ca8b3878SGuennadi Liakhovetski * @chclr_present: DMAC has one or several CHCLR registers 68ca8b3878SGuennadi Liakhovetski * @chclr_bitwise: channel CHCLR registers are bitwise 69ca8b3878SGuennadi Liakhovetski * @slave_only: DMAC cannot be used for MEMCPY 70ca8b3878SGuennadi Liakhovetski */ 71b2623a61SMagnus Damm struct sh_dmae_pdata { 725bac942dSGuennadi Liakhovetski const struct sh_dmae_slave_config *slave; 73b2623a61SMagnus Damm int slave_num; 745bac942dSGuennadi Liakhovetski const struct sh_dmae_channel *channel; 75b2623a61SMagnus Damm int channel_num; 76b2623a61SMagnus Damm unsigned int ts_low_shift; 77b2623a61SMagnus Damm unsigned int ts_low_mask; 78b2623a61SMagnus Damm unsigned int ts_high_shift; 79b2623a61SMagnus Damm unsigned int ts_high_mask; 805bac942dSGuennadi Liakhovetski const unsigned int *ts_shift; 81b2623a61SMagnus Damm int ts_shift_num; 82b2623a61SMagnus Damm u16 dmaor_init; 835899a723SKuninori Morimoto unsigned int chcr_offset; 8467c6269eSKuninori Morimoto u32 chcr_ie_bit; 85e76c3af8SKuninori Morimoto 86e76c3af8SKuninori Morimoto unsigned int dmaor_is_32bit:1; 87260bf2c5SKuninori Morimoto unsigned int needs_tend_set:1; 88260bf2c5SKuninori Morimoto unsigned int no_dmars:1; 89c11b46c3SGuennadi Liakhovetski unsigned int chclr_present:1; 90ca8b3878SGuennadi Liakhovetski unsigned int chclr_bitwise:1; 91e9c8d7a0SGuennadi Liakhovetski unsigned int slave_only:1; 92b2623a61SMagnus Damm }; 93b2623a61SMagnus Damm 94b2623a61SMagnus Damm /* DMAOR definitions */ 956b32fafeSGeert Uytterhoeven #define DMAOR_AE 0x00000004 /* Address Error Flag */ 96b2623a61SMagnus Damm #define DMAOR_NMIF 0x00000002 976b32fafeSGeert Uytterhoeven #define DMAOR_DME 0x00000001 /* DMA Master Enable */ 98b2623a61SMagnus Damm 99b2623a61SMagnus Damm /* Definitions for the SuperH DMAC */ 1006b32fafeSGeert Uytterhoeven #define DM_INC 0x00004000 /* Destination addresses are incremented */ 1016b32fafeSGeert Uytterhoeven #define DM_DEC 0x00008000 /* Destination addresses are decremented */ 1026b32fafeSGeert Uytterhoeven #define DM_FIX 0x0000c000 /* Destination address is fixed */ 1036b32fafeSGeert Uytterhoeven #define SM_INC 0x00001000 /* Source addresses are incremented */ 1046b32fafeSGeert Uytterhoeven #define SM_DEC 0x00002000 /* Source addresses are decremented */ 1056b32fafeSGeert Uytterhoeven #define SM_FIX 0x00003000 /* Source address is fixed */ 1066b32fafeSGeert Uytterhoeven #define RS_AUTO 0x00000400 /* Auto Request */ 1076b32fafeSGeert Uytterhoeven #define RS_ERS 0x00000800 /* DMA extended resource selector */ 1086b32fafeSGeert Uytterhoeven #define CHCR_DE 0x00000001 /* DMA Enable */ 1096b32fafeSGeert Uytterhoeven #define CHCR_TE 0x00000002 /* Transfer End Flag */ 1106b32fafeSGeert Uytterhoeven #define CHCR_IE 0x00000004 /* Interrupt Enable */ 111b2623a61SMagnus Damm 112b2623a61SMagnus Damm #endif 113