1 #ifndef __LINUX_SERIAL_SCI_H 2 #define __LINUX_SERIAL_SCI_H 3 4 #include <linux/serial_core.h> 5 #include <linux/sh_dma.h> 6 7 /* 8 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts) 9 */ 10 11 #define SCIx_NOT_SUPPORTED (-1) 12 13 enum { 14 SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */ 15 SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */ 16 SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */ 17 SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */ 18 SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */ 19 }; 20 21 #define SCSCR_TIE (1 << 7) 22 #define SCSCR_RIE (1 << 6) 23 #define SCSCR_TE (1 << 5) 24 #define SCSCR_RE (1 << 4) 25 #define SCSCR_REIE (1 << 3) /* not supported by all parts */ 26 #define SCSCR_TOIE (1 << 2) /* not supported by all parts */ 27 #define SCSCR_CKE1 (1 << 1) 28 #define SCSCR_CKE0 (1 << 0) 29 30 /* SCxSR SCI */ 31 #define SCI_TDRE 0x80 32 #define SCI_RDRF 0x40 33 #define SCI_ORER 0x20 34 #define SCI_FER 0x10 35 #define SCI_PER 0x08 36 #define SCI_TEND 0x04 37 38 #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER) 39 40 /* SCxSR SCIF */ 41 #define SCIF_ER 0x0080 42 #define SCIF_TEND 0x0040 43 #define SCIF_TDFE 0x0020 44 #define SCIF_BRK 0x0010 45 #define SCIF_FER 0x0008 46 #define SCIF_PER 0x0004 47 #define SCIF_RDF 0x0002 48 #define SCIF_DR 0x0001 49 50 #define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 51 52 /* SCSPTR, optional */ 53 #define SCSPTR_RTSIO (1 << 7) 54 #define SCSPTR_CTSIO (1 << 5) 55 #define SCSPTR_SPB2IO (1 << 1) 56 #define SCSPTR_SPB2DT (1 << 0) 57 58 /* Offsets into the sci_port->irqs array */ 59 enum { 60 SCIx_ERI_IRQ, 61 SCIx_RXI_IRQ, 62 SCIx_TXI_IRQ, 63 SCIx_BRI_IRQ, 64 SCIx_NR_IRQS, 65 66 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 67 }; 68 69 /* Offsets into the sci_port->gpios array */ 70 enum { 71 SCIx_SCK, 72 SCIx_RXD, 73 SCIx_TXD, 74 SCIx_CTS, 75 SCIx_RTS, 76 77 SCIx_NR_FNS, 78 }; 79 80 enum { 81 SCIx_PROBE_REGTYPE, 82 83 SCIx_SCI_REGTYPE, 84 SCIx_IRDA_REGTYPE, 85 SCIx_SCIFA_REGTYPE, 86 SCIx_SCIFB_REGTYPE, 87 SCIx_SH2_SCIF_FIFODATA_REGTYPE, 88 SCIx_SH3_SCIF_REGTYPE, 89 SCIx_SH4_SCIF_REGTYPE, 90 SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 91 SCIx_SH4_SCIF_FIFODATA_REGTYPE, 92 SCIx_SH7705_SCIF_REGTYPE, 93 94 SCIx_NR_REGTYPES, 95 }; 96 97 #define SCIx_IRQ_MUXED(irq) \ 98 { \ 99 [SCIx_ERI_IRQ] = (irq), \ 100 [SCIx_RXI_IRQ] = (irq), \ 101 [SCIx_TXI_IRQ] = (irq), \ 102 [SCIx_BRI_IRQ] = (irq), \ 103 } 104 105 #define SCIx_IRQ_IS_MUXED(port) \ 106 ((port)->cfg->irqs[SCIx_ERI_IRQ] == \ 107 (port)->cfg->irqs[SCIx_RXI_IRQ]) || \ 108 ((port)->cfg->irqs[SCIx_ERI_IRQ] && \ 109 !(port)->cfg->irqs[SCIx_RXI_IRQ]) 110 /* 111 * SCI register subset common for all port types. 112 * Not all registers will exist on all parts. 113 */ 114 enum { 115 SCSMR, SCBRR, SCSCR, SCxSR, 116 SCFCR, SCFDR, SCxTDR, SCxRDR, 117 SCLSR, SCTFDR, SCRFDR, SCSPTR, 118 119 SCIx_NR_REGS, 120 }; 121 122 struct device; 123 124 struct plat_sci_port_ops { 125 void (*init_pins)(struct uart_port *, unsigned int cflag); 126 }; 127 128 /* 129 * Port-specific capabilities 130 */ 131 #define SCIx_HAVE_RTSCTS (1 << 0) 132 133 /* 134 * Platform device specific platform_data struct 135 */ 136 struct plat_sci_port { 137 unsigned long mapbase; /* resource base */ 138 unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */ 139 unsigned int gpios[SCIx_NR_FNS]; /* SCK, RXD, TXD, CTS, RTS */ 140 unsigned int type; /* SCI / SCIF / IRDA */ 141 upf_t flags; /* UPF_* flags */ 142 unsigned long capabilities; /* Port features/capabilities */ 143 144 unsigned int scbrr_algo_id; /* SCBRR calculation algo */ 145 unsigned int scscr; /* SCSCR initialization */ 146 147 /* 148 * Platform overrides if necessary, defaults otherwise. 149 */ 150 int overrun_bit; 151 unsigned int error_mask; 152 153 int port_reg; 154 unsigned char regshift; 155 unsigned char regtype; 156 157 struct plat_sci_port_ops *ops; 158 159 unsigned int dma_slave_tx; 160 unsigned int dma_slave_rx; 161 }; 162 163 #endif /* __LINUX_SERIAL_SCI_H */ 164