1aaf4989bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
2e455b69dSRui Feng /* Driver for Realtek PCI-Express card reader
3e455b69dSRui Feng *
4e455b69dSRui Feng * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5e455b69dSRui Feng *
6e455b69dSRui Feng * Author:
7e455b69dSRui Feng * Wei WANG <wei_wang@realsil.com.cn>
8e455b69dSRui Feng */
9e455b69dSRui Feng
10e455b69dSRui Feng #ifndef __RTSX_PCI_H
11e455b69dSRui Feng #define __RTSX_PCI_H
12e455b69dSRui Feng
13e455b69dSRui Feng #include <linux/sched.h>
14e455b69dSRui Feng #include <linux/pci.h>
15e455b69dSRui Feng #include <linux/rtsx_common.h>
16e455b69dSRui Feng
17e455b69dSRui Feng #define MAX_RW_REG_CNT 1024
18e455b69dSRui Feng
19e455b69dSRui Feng #define RTSX_HCBAR 0x00
20e455b69dSRui Feng #define RTSX_HCBCTLR 0x04
21e455b69dSRui Feng #define STOP_CMD (0x01 << 28)
22e455b69dSRui Feng #define READ_REG_CMD 0
23e455b69dSRui Feng #define WRITE_REG_CMD 1
24e455b69dSRui Feng #define CHECK_REG_CMD 2
25e455b69dSRui Feng
26e455b69dSRui Feng #define RTSX_HDBAR 0x08
27f16ee7c7SArnd Bergmann #define RTSX_SG_INT 0x04
28f16ee7c7SArnd Bergmann #define RTSX_SG_END 0x02
29f16ee7c7SArnd Bergmann #define RTSX_SG_VALID 0x01
30f16ee7c7SArnd Bergmann #define RTSX_SG_NO_OP 0x00
31f16ee7c7SArnd Bergmann #define RTSX_SG_TRANS_DATA (0x02 << 4)
32f16ee7c7SArnd Bergmann #define RTSX_SG_LINK_DESC (0x03 << 4)
33e455b69dSRui Feng #define RTSX_HDBCTLR 0x0C
34e455b69dSRui Feng #define SDMA_MODE 0x00
35e455b69dSRui Feng #define ADMA_MODE (0x02 << 26)
36e455b69dSRui Feng #define STOP_DMA (0x01 << 28)
37e455b69dSRui Feng #define TRIG_DMA (0x01 << 31)
38e455b69dSRui Feng
39e455b69dSRui Feng #define RTSX_HAIMR 0x10
40e455b69dSRui Feng #define HAIMR_TRANS_START (0x01 << 31)
41e455b69dSRui Feng #define HAIMR_READ 0x00
42e455b69dSRui Feng #define HAIMR_WRITE (0x01 << 30)
43e455b69dSRui Feng #define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ)
44e455b69dSRui Feng #define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE)
45e455b69dSRui Feng #define HAIMR_TRANS_END (HAIMR_TRANS_START)
46e455b69dSRui Feng
47e455b69dSRui Feng #define RTSX_BIPR 0x14
48e455b69dSRui Feng #define CMD_DONE_INT (1 << 31)
49e455b69dSRui Feng #define DATA_DONE_INT (1 << 30)
50e455b69dSRui Feng #define TRANS_OK_INT (1 << 29)
51e455b69dSRui Feng #define TRANS_FAIL_INT (1 << 28)
52e455b69dSRui Feng #define XD_INT (1 << 27)
53e455b69dSRui Feng #define MS_INT (1 << 26)
54e455b69dSRui Feng #define SD_INT (1 << 25)
55e455b69dSRui Feng #define GPIO0_INT (1 << 24)
56e455b69dSRui Feng #define OC_INT (1 << 23)
57e455b69dSRui Feng #define SD_WRITE_PROTECT (1 << 19)
58e455b69dSRui Feng #define XD_EXIST (1 << 18)
59e455b69dSRui Feng #define MS_EXIST (1 << 17)
60e455b69dSRui Feng #define SD_EXIST (1 << 16)
61e455b69dSRui Feng #define DELINK_INT GPIO0_INT
62e455b69dSRui Feng #define MS_OC_INT (1 << 23)
63e455b69dSRui Feng #define SD_OC_INT (1 << 22)
64e455b69dSRui Feng
65e455b69dSRui Feng #define CARD_INT (XD_INT | MS_INT | SD_INT)
66e455b69dSRui Feng #define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
67e455b69dSRui Feng #define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \
68e455b69dSRui Feng CARD_INT | GPIO0_INT | OC_INT)
69e455b69dSRui Feng #define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST)
70e455b69dSRui Feng
71e455b69dSRui Feng #define RTSX_BIER 0x18
72e455b69dSRui Feng #define CMD_DONE_INT_EN (1 << 31)
73e455b69dSRui Feng #define DATA_DONE_INT_EN (1 << 30)
74e455b69dSRui Feng #define TRANS_OK_INT_EN (1 << 29)
75e455b69dSRui Feng #define TRANS_FAIL_INT_EN (1 << 28)
76e455b69dSRui Feng #define XD_INT_EN (1 << 27)
77e455b69dSRui Feng #define MS_INT_EN (1 << 26)
78e455b69dSRui Feng #define SD_INT_EN (1 << 25)
79e455b69dSRui Feng #define GPIO0_INT_EN (1 << 24)
80e455b69dSRui Feng #define OC_INT_EN (1 << 23)
81e455b69dSRui Feng #define DELINK_INT_EN GPIO0_INT_EN
82e455b69dSRui Feng #define MS_OC_INT_EN (1 << 23)
83e455b69dSRui Feng #define SD_OC_INT_EN (1 << 22)
84e455b69dSRui Feng
851672617dSRui Feng #define RTSX_DUM_REG 0x1C
86e455b69dSRui Feng
87e455b69dSRui Feng /*
88e455b69dSRui Feng * macros for easy use
89e455b69dSRui Feng */
90e455b69dSRui Feng #define rtsx_pci_writel(pcr, reg, value) \
91e455b69dSRui Feng iowrite32(value, (pcr)->remap_addr + reg)
92e455b69dSRui Feng #define rtsx_pci_readl(pcr, reg) \
93e455b69dSRui Feng ioread32((pcr)->remap_addr + reg)
94e455b69dSRui Feng #define rtsx_pci_writew(pcr, reg, value) \
95e455b69dSRui Feng iowrite16(value, (pcr)->remap_addr + reg)
96e455b69dSRui Feng #define rtsx_pci_readw(pcr, reg) \
97e455b69dSRui Feng ioread16((pcr)->remap_addr + reg)
98e455b69dSRui Feng #define rtsx_pci_writeb(pcr, reg, value) \
99e455b69dSRui Feng iowrite8(value, (pcr)->remap_addr + reg)
100e455b69dSRui Feng #define rtsx_pci_readb(pcr, reg) \
101e455b69dSRui Feng ioread8((pcr)->remap_addr + reg)
102e455b69dSRui Feng
103e455b69dSRui Feng #define STATE_TRANS_NONE 0
104e455b69dSRui Feng #define STATE_TRANS_CMD 1
105e455b69dSRui Feng #define STATE_TRANS_BUF 2
106e455b69dSRui Feng #define STATE_TRANS_SG 3
107e455b69dSRui Feng
108e455b69dSRui Feng #define TRANS_NOT_READY 0
109e455b69dSRui Feng #define TRANS_RESULT_OK 1
110e455b69dSRui Feng #define TRANS_RESULT_FAIL 2
111e455b69dSRui Feng #define TRANS_NO_DEVICE 3
112e455b69dSRui Feng
113e455b69dSRui Feng #define RTSX_RESV_BUF_LEN 4096
114e455b69dSRui Feng #define HOST_CMDS_BUF_LEN 1024
115e455b69dSRui Feng #define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
116e455b69dSRui Feng #define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8)
117e455b69dSRui Feng #define MAX_SG_ITEM_LEN 0x80000
118e455b69dSRui Feng #define HOST_TO_DEVICE 0
119e455b69dSRui Feng #define DEVICE_TO_HOST 1
120e455b69dSRui Feng
121e455b69dSRui Feng #define OUTPUT_3V3 0
122e455b69dSRui Feng #define OUTPUT_1V8 1
123e455b69dSRui Feng
124e455b69dSRui Feng #define RTSX_PHASE_MAX 32
125e455b69dSRui Feng #define RX_TUNING_CNT 3
126e455b69dSRui Feng
127e455b69dSRui Feng #define MS_CFG 0xFD40
128e455b69dSRui Feng #define SAMPLE_TIME_RISING 0x00
129e455b69dSRui Feng #define SAMPLE_TIME_FALLING 0x80
130e455b69dSRui Feng #define PUSH_TIME_DEFAULT 0x00
131e455b69dSRui Feng #define PUSH_TIME_ODD 0x40
132e455b69dSRui Feng #define NO_EXTEND_TOGGLE 0x00
133e455b69dSRui Feng #define EXTEND_TOGGLE_CHK 0x20
134e455b69dSRui Feng #define MS_BUS_WIDTH_1 0x00
135e455b69dSRui Feng #define MS_BUS_WIDTH_4 0x10
136e455b69dSRui Feng #define MS_BUS_WIDTH_8 0x18
137e455b69dSRui Feng #define MS_2K_SECTOR_MODE 0x04
138e455b69dSRui Feng #define MS_512_SECTOR_MODE 0x00
139e455b69dSRui Feng #define MS_TOGGLE_TIMEOUT_EN 0x00
140e455b69dSRui Feng #define MS_TOGGLE_TIMEOUT_DISEN 0x01
141e455b69dSRui Feng #define MS_NO_CHECK_INT 0x02
142e455b69dSRui Feng #define MS_TPC 0xFD41
143e455b69dSRui Feng #define MS_TRANS_CFG 0xFD42
144e455b69dSRui Feng #define WAIT_INT 0x80
145e455b69dSRui Feng #define NO_WAIT_INT 0x00
146e455b69dSRui Feng #define NO_AUTO_READ_INT_REG 0x00
147e455b69dSRui Feng #define AUTO_READ_INT_REG 0x40
148e455b69dSRui Feng #define MS_CRC16_ERR 0x20
149e455b69dSRui Feng #define MS_RDY_TIMEOUT 0x10
150e455b69dSRui Feng #define MS_INT_CMDNK 0x08
151e455b69dSRui Feng #define MS_INT_BREQ 0x04
152e455b69dSRui Feng #define MS_INT_ERR 0x02
153e455b69dSRui Feng #define MS_INT_CED 0x01
154e455b69dSRui Feng #define MS_TRANSFER 0xFD43
155e455b69dSRui Feng #define MS_TRANSFER_START 0x80
156e455b69dSRui Feng #define MS_TRANSFER_END 0x40
157e455b69dSRui Feng #define MS_TRANSFER_ERR 0x20
158e455b69dSRui Feng #define MS_BS_STATE 0x10
159e455b69dSRui Feng #define MS_TM_READ_BYTES 0x00
160e455b69dSRui Feng #define MS_TM_NORMAL_READ 0x01
161e455b69dSRui Feng #define MS_TM_WRITE_BYTES 0x04
162e455b69dSRui Feng #define MS_TM_NORMAL_WRITE 0x05
163e455b69dSRui Feng #define MS_TM_AUTO_READ 0x08
164e455b69dSRui Feng #define MS_TM_AUTO_WRITE 0x0C
165e455b69dSRui Feng #define MS_INT_REG 0xFD44
166e455b69dSRui Feng #define MS_BYTE_CNT 0xFD45
167e455b69dSRui Feng #define MS_SECTOR_CNT_L 0xFD46
168e455b69dSRui Feng #define MS_SECTOR_CNT_H 0xFD47
169e455b69dSRui Feng #define MS_DBUS_H 0xFD48
170e455b69dSRui Feng
171e455b69dSRui Feng #define SD_CFG1 0xFDA0
172e455b69dSRui Feng #define SD_CLK_DIVIDE_0 0x00
173e455b69dSRui Feng #define SD_CLK_DIVIDE_256 0xC0
174e455b69dSRui Feng #define SD_CLK_DIVIDE_128 0x80
175e455b69dSRui Feng #define SD_BUS_WIDTH_1BIT 0x00
176e455b69dSRui Feng #define SD_BUS_WIDTH_4BIT 0x01
177e455b69dSRui Feng #define SD_BUS_WIDTH_8BIT 0x02
178e455b69dSRui Feng #define SD_ASYNC_FIFO_NOT_RST 0x10
179e455b69dSRui Feng #define SD_20_MODE 0x00
180e455b69dSRui Feng #define SD_DDR_MODE 0x04
181e455b69dSRui Feng #define SD_30_MODE 0x08
182e455b69dSRui Feng #define SD_CLK_DIVIDE_MASK 0xC0
1835da4e04aSRui Feng #define SD_MODE_SELECT_MASK 0x0C
184e455b69dSRui Feng #define SD_CFG2 0xFDA1
185e455b69dSRui Feng #define SD_CALCULATE_CRC7 0x00
186e455b69dSRui Feng #define SD_NO_CALCULATE_CRC7 0x80
187e455b69dSRui Feng #define SD_CHECK_CRC16 0x00
188e455b69dSRui Feng #define SD_NO_CHECK_CRC16 0x40
189e455b69dSRui Feng #define SD_NO_CHECK_WAIT_CRC_TO 0x20
190e455b69dSRui Feng #define SD_WAIT_BUSY_END 0x08
191e455b69dSRui Feng #define SD_NO_WAIT_BUSY_END 0x00
192e455b69dSRui Feng #define SD_CHECK_CRC7 0x00
193e455b69dSRui Feng #define SD_NO_CHECK_CRC7 0x04
194e455b69dSRui Feng #define SD_RSP_LEN_0 0x00
195e455b69dSRui Feng #define SD_RSP_LEN_6 0x01
196e455b69dSRui Feng #define SD_RSP_LEN_17 0x02
197e455b69dSRui Feng #define SD_RSP_TYPE_R0 0x04
198e455b69dSRui Feng #define SD_RSP_TYPE_R1 0x01
199e455b69dSRui Feng #define SD_RSP_TYPE_R1b 0x09
200e455b69dSRui Feng #define SD_RSP_TYPE_R2 0x02
201e455b69dSRui Feng #define SD_RSP_TYPE_R3 0x05
202e455b69dSRui Feng #define SD_RSP_TYPE_R4 0x05
203e455b69dSRui Feng #define SD_RSP_TYPE_R5 0x01
204e455b69dSRui Feng #define SD_RSP_TYPE_R6 0x01
205e455b69dSRui Feng #define SD_RSP_TYPE_R7 0x01
206e455b69dSRui Feng #define SD_CFG3 0xFDA2
2075da4e04aSRui Feng #define SD30_CLK_END_EN 0x10
208e455b69dSRui Feng #define SD_RSP_80CLK_TIMEOUT_EN 0x01
209e455b69dSRui Feng
210e455b69dSRui Feng #define SD_STAT1 0xFDA3
211e455b69dSRui Feng #define SD_CRC7_ERR 0x80
212e455b69dSRui Feng #define SD_CRC16_ERR 0x40
213e455b69dSRui Feng #define SD_CRC_WRITE_ERR 0x20
214e455b69dSRui Feng #define SD_CRC_WRITE_ERR_MASK 0x1C
215e455b69dSRui Feng #define GET_CRC_TIME_OUT 0x02
216e455b69dSRui Feng #define SD_TUNING_COMPARE_ERR 0x01
217e455b69dSRui Feng #define SD_STAT2 0xFDA4
218e455b69dSRui Feng #define SD_RSP_80CLK_TIMEOUT 0x01
219e455b69dSRui Feng
220e455b69dSRui Feng #define SD_BUS_STAT 0xFDA5
221e455b69dSRui Feng #define SD_CLK_TOGGLE_EN 0x80
222e455b69dSRui Feng #define SD_CLK_FORCE_STOP 0x40
223e455b69dSRui Feng #define SD_DAT3_STATUS 0x10
224e455b69dSRui Feng #define SD_DAT2_STATUS 0x08
225e455b69dSRui Feng #define SD_DAT1_STATUS 0x04
226e455b69dSRui Feng #define SD_DAT0_STATUS 0x02
227e455b69dSRui Feng #define SD_CMD_STATUS 0x01
228e455b69dSRui Feng #define SD_PAD_CTL 0xFDA6
229e455b69dSRui Feng #define SD_IO_USING_1V8 0x80
230e455b69dSRui Feng #define SD_IO_USING_3V3 0x7F
231e455b69dSRui Feng #define TYPE_A_DRIVING 0x00
232e455b69dSRui Feng #define TYPE_B_DRIVING 0x01
233e455b69dSRui Feng #define TYPE_C_DRIVING 0x02
234e455b69dSRui Feng #define TYPE_D_DRIVING 0x03
235e455b69dSRui Feng #define SD_SAMPLE_POINT_CTL 0xFDA7
236e455b69dSRui Feng #define DDR_FIX_RX_DAT 0x00
237e455b69dSRui Feng #define DDR_VAR_RX_DAT 0x80
238e455b69dSRui Feng #define DDR_FIX_RX_DAT_EDGE 0x00
239e455b69dSRui Feng #define DDR_FIX_RX_DAT_14_DELAY 0x40
240e455b69dSRui Feng #define DDR_FIX_RX_CMD 0x00
241e455b69dSRui Feng #define DDR_VAR_RX_CMD 0x20
242e455b69dSRui Feng #define DDR_FIX_RX_CMD_POS_EDGE 0x00
243e455b69dSRui Feng #define DDR_FIX_RX_CMD_14_DELAY 0x10
244e455b69dSRui Feng #define SD20_RX_POS_EDGE 0x00
245e455b69dSRui Feng #define SD20_RX_14_DELAY 0x08
246e455b69dSRui Feng #define SD20_RX_SEL_MASK 0x08
247e455b69dSRui Feng #define SD_PUSH_POINT_CTL 0xFDA8
248e455b69dSRui Feng #define DDR_FIX_TX_CMD_DAT 0x00
249e455b69dSRui Feng #define DDR_VAR_TX_CMD_DAT 0x80
250e455b69dSRui Feng #define DDR_FIX_TX_DAT_14_TSU 0x00
251e455b69dSRui Feng #define DDR_FIX_TX_DAT_12_TSU 0x40
252e455b69dSRui Feng #define DDR_FIX_TX_CMD_NEG_EDGE 0x00
253e455b69dSRui Feng #define DDR_FIX_TX_CMD_14_AHEAD 0x20
254e455b69dSRui Feng #define SD20_TX_NEG_EDGE 0x00
255e455b69dSRui Feng #define SD20_TX_14_AHEAD 0x10
256e455b69dSRui Feng #define SD20_TX_SEL_MASK 0x10
257e455b69dSRui Feng #define DDR_VAR_SDCLK_POL_SWAP 0x01
258e455b69dSRui Feng #define SD_CMD0 0xFDA9
259e455b69dSRui Feng #define SD_CMD_START 0x40
260e455b69dSRui Feng #define SD_CMD1 0xFDAA
261e455b69dSRui Feng #define SD_CMD2 0xFDAB
262e455b69dSRui Feng #define SD_CMD3 0xFDAC
263e455b69dSRui Feng #define SD_CMD4 0xFDAD
264e455b69dSRui Feng #define SD_CMD5 0xFDAE
265e455b69dSRui Feng #define SD_BYTE_CNT_L 0xFDAF
266e455b69dSRui Feng #define SD_BYTE_CNT_H 0xFDB0
267e455b69dSRui Feng #define SD_BLOCK_CNT_L 0xFDB1
268e455b69dSRui Feng #define SD_BLOCK_CNT_H 0xFDB2
269e455b69dSRui Feng #define SD_TRANSFER 0xFDB3
270e455b69dSRui Feng #define SD_TRANSFER_START 0x80
271e455b69dSRui Feng #define SD_TRANSFER_END 0x40
272e455b69dSRui Feng #define SD_STAT_IDLE 0x20
273e455b69dSRui Feng #define SD_TRANSFER_ERR 0x10
274e455b69dSRui Feng #define SD_TM_NORMAL_WRITE 0x00
275e455b69dSRui Feng #define SD_TM_AUTO_WRITE_3 0x01
276e455b69dSRui Feng #define SD_TM_AUTO_WRITE_4 0x02
277e455b69dSRui Feng #define SD_TM_AUTO_READ_3 0x05
278e455b69dSRui Feng #define SD_TM_AUTO_READ_4 0x06
279e455b69dSRui Feng #define SD_TM_CMD_RSP 0x08
280e455b69dSRui Feng #define SD_TM_AUTO_WRITE_1 0x09
281e455b69dSRui Feng #define SD_TM_AUTO_WRITE_2 0x0A
282e455b69dSRui Feng #define SD_TM_NORMAL_READ 0x0C
283e455b69dSRui Feng #define SD_TM_AUTO_READ_1 0x0D
284e455b69dSRui Feng #define SD_TM_AUTO_READ_2 0x0E
285e455b69dSRui Feng #define SD_TM_AUTO_TUNING 0x0F
286e455b69dSRui Feng #define SD_CMD_STATE 0xFDB5
287e455b69dSRui Feng #define SD_CMD_IDLE 0x80
288e455b69dSRui Feng
289e455b69dSRui Feng #define SD_DATA_STATE 0xFDB6
290e455b69dSRui Feng #define SD_DATA_IDLE 0x80
2915da4e04aSRui Feng #define REG_SD_STOP_SDCLK_CFG 0xFDB8
2925da4e04aSRui Feng #define SD30_CLK_STOP_CFG_EN 0x04
2935da4e04aSRui Feng #define SD30_CLK_STOP_CFG1 0x02
2945da4e04aSRui Feng #define SD30_CLK_STOP_CFG0 0x01
2955da4e04aSRui Feng #define REG_PRE_RW_MODE 0xFD70
2965da4e04aSRui Feng #define EN_INFINITE_MODE 0x01
297849a9366SRicky Wu #define REG_CRC_DUMMY_0 0xFD71
298849a9366SRicky Wu #define CFG_SD_POW_AUTO_PD (1<<0)
299e455b69dSRui Feng
300e455b69dSRui Feng #define SRCTL 0xFC13
301e455b69dSRui Feng
302e455b69dSRui Feng #define DCM_DRP_CTL 0xFC23
303e455b69dSRui Feng #define DCM_RESET 0x08
304e455b69dSRui Feng #define DCM_LOCKED 0x04
305e455b69dSRui Feng #define DCM_208M 0x00
306e455b69dSRui Feng #define DCM_TX 0x01
307e455b69dSRui Feng #define DCM_RX 0x02
308e455b69dSRui Feng #define DCM_DRP_TRIG 0xFC24
309e455b69dSRui Feng #define DRP_START 0x80
310e455b69dSRui Feng #define DRP_DONE 0x40
311e455b69dSRui Feng #define DCM_DRP_CFG 0xFC25
312e455b69dSRui Feng #define DRP_WRITE 0x80
313e455b69dSRui Feng #define DRP_READ 0x00
314e455b69dSRui Feng #define DCM_WRITE_ADDRESS_50 0x50
315e455b69dSRui Feng #define DCM_WRITE_ADDRESS_51 0x51
316e455b69dSRui Feng #define DCM_READ_ADDRESS_00 0x00
317e455b69dSRui Feng #define DCM_READ_ADDRESS_51 0x51
318e455b69dSRui Feng #define DCM_DRP_WR_DATA_L 0xFC26
319e455b69dSRui Feng #define DCM_DRP_WR_DATA_H 0xFC27
320e455b69dSRui Feng #define DCM_DRP_RD_DATA_L 0xFC28
321e455b69dSRui Feng #define DCM_DRP_RD_DATA_H 0xFC29
322e455b69dSRui Feng #define SD_VPCLK0_CTL 0xFC2A
323e455b69dSRui Feng #define SD_VPCLK1_CTL 0xFC2B
324e455b69dSRui Feng #define PHASE_SELECT_MASK 0x1F
325e455b69dSRui Feng #define SD_DCMPS0_CTL 0xFC2C
326e455b69dSRui Feng #define SD_DCMPS1_CTL 0xFC2D
327e455b69dSRui Feng #define SD_VPTX_CTL SD_VPCLK0_CTL
328e455b69dSRui Feng #define SD_VPRX_CTL SD_VPCLK1_CTL
329e455b69dSRui Feng #define PHASE_CHANGE 0x80
330e455b69dSRui Feng #define PHASE_NOT_RESET 0x40
331e455b69dSRui Feng #define SD_DCMPS_TX_CTL SD_DCMPS0_CTL
332e455b69dSRui Feng #define SD_DCMPS_RX_CTL SD_DCMPS1_CTL
333e455b69dSRui Feng #define DCMPS_CHANGE 0x80
334e455b69dSRui Feng #define DCMPS_CHANGE_DONE 0x40
335e455b69dSRui Feng #define DCMPS_ERROR 0x20
336e455b69dSRui Feng #define DCMPS_CURRENT_PHASE 0x1F
337e455b69dSRui Feng #define CARD_CLK_SOURCE 0xFC2E
338e455b69dSRui Feng #define CRC_FIX_CLK (0x00 << 0)
339e455b69dSRui Feng #define CRC_VAR_CLK0 (0x01 << 0)
340e455b69dSRui Feng #define CRC_VAR_CLK1 (0x02 << 0)
341e455b69dSRui Feng #define SD30_FIX_CLK (0x00 << 2)
342e455b69dSRui Feng #define SD30_VAR_CLK0 (0x01 << 2)
343e455b69dSRui Feng #define SD30_VAR_CLK1 (0x02 << 2)
344e455b69dSRui Feng #define SAMPLE_FIX_CLK (0x00 << 4)
345e455b69dSRui Feng #define SAMPLE_VAR_CLK0 (0x01 << 4)
346e455b69dSRui Feng #define SAMPLE_VAR_CLK1 (0x02 << 4)
347e455b69dSRui Feng #define CARD_PWR_CTL 0xFD50
348e455b69dSRui Feng #define PMOS_STRG_MASK 0x10
349e455b69dSRui Feng #define PMOS_STRG_800mA 0x10
350e455b69dSRui Feng #define PMOS_STRG_400mA 0x00
351e455b69dSRui Feng #define SD_POWER_OFF 0x03
352e455b69dSRui Feng #define SD_PARTIAL_POWER_ON 0x01
353e455b69dSRui Feng #define SD_POWER_ON 0x00
354e455b69dSRui Feng #define SD_POWER_MASK 0x03
355e455b69dSRui Feng #define MS_POWER_OFF 0x0C
356e455b69dSRui Feng #define MS_PARTIAL_POWER_ON 0x04
357e455b69dSRui Feng #define MS_POWER_ON 0x00
358e455b69dSRui Feng #define MS_POWER_MASK 0x0C
359e455b69dSRui Feng #define BPP_POWER_OFF 0x0F
360e455b69dSRui Feng #define BPP_POWER_5_PERCENT_ON 0x0E
361e455b69dSRui Feng #define BPP_POWER_10_PERCENT_ON 0x0C
362e455b69dSRui Feng #define BPP_POWER_15_PERCENT_ON 0x08
363e455b69dSRui Feng #define BPP_POWER_ON 0x00
364e455b69dSRui Feng #define BPP_POWER_MASK 0x0F
365e455b69dSRui Feng #define SD_VCC_PARTIAL_POWER_ON 0x02
366e455b69dSRui Feng #define SD_VCC_POWER_ON 0x00
367e455b69dSRui Feng #define CARD_CLK_SWITCH 0xFD51
368e455b69dSRui Feng #define RTL8411B_PACKAGE_MODE 0xFD51
369e455b69dSRui Feng #define CARD_SHARE_MODE 0xFD52
370e455b69dSRui Feng #define CARD_SHARE_MASK 0x0F
371e455b69dSRui Feng #define CARD_SHARE_MULTI_LUN 0x00
372e455b69dSRui Feng #define CARD_SHARE_NORMAL 0x00
373e455b69dSRui Feng #define CARD_SHARE_48_SD 0x04
374e455b69dSRui Feng #define CARD_SHARE_48_MS 0x08
375e455b69dSRui Feng #define CARD_SHARE_BAROSSA_SD 0x01
376e455b69dSRui Feng #define CARD_SHARE_BAROSSA_MS 0x02
377e455b69dSRui Feng #define CARD_DRIVE_SEL 0xFD53
378e455b69dSRui Feng #define MS_DRIVE_8mA (0x01 << 6)
379e455b69dSRui Feng #define MMC_DRIVE_8mA (0x01 << 4)
380e455b69dSRui Feng #define XD_DRIVE_8mA (0x01 << 2)
381e455b69dSRui Feng #define GPIO_DRIVE_8mA 0x01
382e455b69dSRui Feng #define RTS5209_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
383e455b69dSRui Feng XD_DRIVE_8mA | GPIO_DRIVE_8mA)
384e455b69dSRui Feng #define RTL8411_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
385e455b69dSRui Feng XD_DRIVE_8mA)
386e455b69dSRui Feng #define RTSX_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | GPIO_DRIVE_8mA)
387e455b69dSRui Feng
388e455b69dSRui Feng #define CARD_STOP 0xFD54
389e455b69dSRui Feng #define SPI_STOP 0x01
390e455b69dSRui Feng #define XD_STOP 0x02
391e455b69dSRui Feng #define SD_STOP 0x04
392e455b69dSRui Feng #define MS_STOP 0x08
393e455b69dSRui Feng #define SPI_CLR_ERR 0x10
394e455b69dSRui Feng #define XD_CLR_ERR 0x20
395e455b69dSRui Feng #define SD_CLR_ERR 0x40
396e455b69dSRui Feng #define MS_CLR_ERR 0x80
397e455b69dSRui Feng #define CARD_OE 0xFD55
398e455b69dSRui Feng #define SD_OUTPUT_EN 0x04
399e455b69dSRui Feng #define MS_OUTPUT_EN 0x08
400e455b69dSRui Feng #define CARD_AUTO_BLINK 0xFD56
401e455b69dSRui Feng #define CARD_GPIO_DIR 0xFD57
402e455b69dSRui Feng #define CARD_GPIO 0xFD58
403e455b69dSRui Feng #define CARD_DATA_SOURCE 0xFD5B
404e455b69dSRui Feng #define PINGPONG_BUFFER 0x01
405e455b69dSRui Feng #define RING_BUFFER 0x00
406e455b69dSRui Feng #define SD30_CLK_DRIVE_SEL 0xFD5A
407e455b69dSRui Feng #define DRIVER_TYPE_A 0x05
408e455b69dSRui Feng #define DRIVER_TYPE_B 0x03
409e455b69dSRui Feng #define DRIVER_TYPE_C 0x02
410e455b69dSRui Feng #define DRIVER_TYPE_D 0x01
411e455b69dSRui Feng #define CARD_SELECT 0xFD5C
412e455b69dSRui Feng #define SD_MOD_SEL 2
413e455b69dSRui Feng #define MS_MOD_SEL 3
414e455b69dSRui Feng #define SD30_DRIVE_SEL 0xFD5E
415e455b69dSRui Feng #define CFG_DRIVER_TYPE_A 0x02
416e455b69dSRui Feng #define CFG_DRIVER_TYPE_B 0x03
417e455b69dSRui Feng #define CFG_DRIVER_TYPE_C 0x01
418e455b69dSRui Feng #define CFG_DRIVER_TYPE_D 0x00
419e455b69dSRui Feng #define SD30_CMD_DRIVE_SEL 0xFD5E
420e455b69dSRui Feng #define SD30_DAT_DRIVE_SEL 0xFD5F
421e455b69dSRui Feng #define CARD_CLK_EN 0xFD69
422e455b69dSRui Feng #define SD_CLK_EN 0x04
423e455b69dSRui Feng #define MS_CLK_EN 0x08
4245da4e04aSRui Feng #define SD40_CLK_EN 0x10
425e455b69dSRui Feng #define SDIO_CTRL 0xFD6B
426e455b69dSRui Feng #define CD_PAD_CTL 0xFD73
427e455b69dSRui Feng #define CD_DISABLE_MASK 0x07
428e455b69dSRui Feng #define MS_CD_DISABLE 0x04
429e455b69dSRui Feng #define SD_CD_DISABLE 0x02
430e455b69dSRui Feng #define XD_CD_DISABLE 0x01
431e455b69dSRui Feng #define CD_DISABLE 0x07
432e455b69dSRui Feng #define CD_ENABLE 0x00
433e455b69dSRui Feng #define MS_CD_EN_ONLY 0x03
434e455b69dSRui Feng #define SD_CD_EN_ONLY 0x05
435e455b69dSRui Feng #define XD_CD_EN_ONLY 0x06
436e455b69dSRui Feng #define FORCE_CD_LOW_MASK 0x38
437e455b69dSRui Feng #define FORCE_CD_XD_LOW 0x08
438e455b69dSRui Feng #define FORCE_CD_SD_LOW 0x10
439e455b69dSRui Feng #define FORCE_CD_MS_LOW 0x20
440e455b69dSRui Feng #define CD_AUTO_DISABLE 0x40
441e455b69dSRui Feng #define FPDCTL 0xFC00
442e455b69dSRui Feng #define SSC_POWER_DOWN 0x01
443e455b69dSRui Feng #define SD_OC_POWER_DOWN 0x02
4445da4e04aSRui Feng #define ALL_POWER_DOWN 0x03
4455da4e04aSRui Feng #define OC_POWER_DOWN 0x02
446e455b69dSRui Feng #define PDINFO 0xFC01
447e455b69dSRui Feng
448e455b69dSRui Feng #define CLK_CTL 0xFC02
449e455b69dSRui Feng #define CHANGE_CLK 0x01
450e455b69dSRui Feng #define CLK_LOW_FREQ 0x01
451e455b69dSRui Feng
452e455b69dSRui Feng #define CLK_DIV 0xFC03
453e455b69dSRui Feng #define CLK_DIV_1 0x01
454e455b69dSRui Feng #define CLK_DIV_2 0x02
455e455b69dSRui Feng #define CLK_DIV_4 0x03
456e455b69dSRui Feng #define CLK_DIV_8 0x04
457e455b69dSRui Feng #define CLK_SEL 0xFC04
458e455b69dSRui Feng
459e455b69dSRui Feng #define SSC_DIV_N_0 0xFC0F
460e455b69dSRui Feng #define SSC_DIV_N_1 0xFC10
461e455b69dSRui Feng #define SSC_CTL1 0xFC11
462e455b69dSRui Feng #define SSC_RSTB 0x80
463e455b69dSRui Feng #define SSC_8X_EN 0x40
464e455b69dSRui Feng #define SSC_FIX_FRAC 0x20
465e455b69dSRui Feng #define SSC_SEL_1M 0x00
466e455b69dSRui Feng #define SSC_SEL_2M 0x08
467e455b69dSRui Feng #define SSC_SEL_4M 0x10
468e455b69dSRui Feng #define SSC_SEL_8M 0x18
469e455b69dSRui Feng #define SSC_CTL2 0xFC12
470e455b69dSRui Feng #define SSC_DEPTH_MASK 0x07
471e455b69dSRui Feng #define SSC_DEPTH_DISALBE 0x00
472e455b69dSRui Feng #define SSC_DEPTH_4M 0x01
473e455b69dSRui Feng #define SSC_DEPTH_2M 0x02
474e455b69dSRui Feng #define SSC_DEPTH_1M 0x03
475e455b69dSRui Feng #define SSC_DEPTH_500K 0x04
476e455b69dSRui Feng #define SSC_DEPTH_250K 0x05
477e455b69dSRui Feng #define RCCTL 0xFC14
478e455b69dSRui Feng
479e455b69dSRui Feng #define FPGA_PULL_CTL 0xFC1D
480e455b69dSRui Feng #define OLT_LED_CTL 0xFC1E
4815da4e04aSRui Feng #define LED_SHINE_MASK 0x08
4825da4e04aSRui Feng #define LED_SHINE_EN 0x08
4835da4e04aSRui Feng #define LED_SHINE_DISABLE 0x00
484e455b69dSRui Feng #define GPIO_CTL 0xFC1F
485e455b69dSRui Feng
486e455b69dSRui Feng #define LDO_CTL 0xFC1E
487e455b69dSRui Feng #define BPP_ASIC_1V7 0x00
488e455b69dSRui Feng #define BPP_ASIC_1V8 0x01
489e455b69dSRui Feng #define BPP_ASIC_1V9 0x02
490e455b69dSRui Feng #define BPP_ASIC_2V0 0x03
491e455b69dSRui Feng #define BPP_ASIC_2V7 0x04
492e455b69dSRui Feng #define BPP_ASIC_2V8 0x05
493e455b69dSRui Feng #define BPP_ASIC_3V2 0x06
494e455b69dSRui Feng #define BPP_ASIC_3V3 0x07
495e455b69dSRui Feng #define BPP_REG_TUNED18 0x07
496e455b69dSRui Feng #define BPP_TUNED18_SHIFT_8402 5
497e455b69dSRui Feng #define BPP_TUNED18_SHIFT_8411 4
498e455b69dSRui Feng #define BPP_PAD_MASK 0x04
499e455b69dSRui Feng #define BPP_PAD_3V3 0x04
500e455b69dSRui Feng #define BPP_PAD_1V8 0x00
501e455b69dSRui Feng #define BPP_LDO_POWB 0x03
502e455b69dSRui Feng #define BPP_LDO_ON 0x00
503e455b69dSRui Feng #define BPP_LDO_SUSPEND 0x02
504e455b69dSRui Feng #define BPP_LDO_OFF 0x03
5055da4e04aSRui Feng #define EFUSE_CTL 0xFC30
5065da4e04aSRui Feng #define EFUSE_ADD 0xFC31
507e455b69dSRui Feng #define SYS_VER 0xFC32
5085da4e04aSRui Feng #define EFUSE_DATAL 0xFC34
5095da4e04aSRui Feng #define EFUSE_DATAH 0xFC35
510e455b69dSRui Feng
511e455b69dSRui Feng #define CARD_PULL_CTL1 0xFD60
512e455b69dSRui Feng #define CARD_PULL_CTL2 0xFD61
513e455b69dSRui Feng #define CARD_PULL_CTL3 0xFD62
514e455b69dSRui Feng #define CARD_PULL_CTL4 0xFD63
515e455b69dSRui Feng #define CARD_PULL_CTL5 0xFD64
516e455b69dSRui Feng #define CARD_PULL_CTL6 0xFD65
517e455b69dSRui Feng
518e455b69dSRui Feng /* PCI Express Related Registers */
519e455b69dSRui Feng #define IRQEN0 0xFE20
520e455b69dSRui Feng #define IRQSTAT0 0xFE21
521e455b69dSRui Feng #define DMA_DONE_INT 0x80
522e455b69dSRui Feng #define SUSPEND_INT 0x40
523e455b69dSRui Feng #define LINK_RDY_INT 0x20
524e455b69dSRui Feng #define LINK_DOWN_INT 0x10
525e455b69dSRui Feng #define IRQEN1 0xFE22
526e455b69dSRui Feng #define IRQSTAT1 0xFE23
527e455b69dSRui Feng #define TLPRIEN 0xFE24
528e455b69dSRui Feng #define TLPRISTAT 0xFE25
529e455b69dSRui Feng #define TLPTIEN 0xFE26
530e455b69dSRui Feng #define TLPTISTAT 0xFE27
531e455b69dSRui Feng #define DMATC0 0xFE28
532e455b69dSRui Feng #define DMATC1 0xFE29
533e455b69dSRui Feng #define DMATC2 0xFE2A
534e455b69dSRui Feng #define DMATC3 0xFE2B
535e455b69dSRui Feng #define DMACTL 0xFE2C
536e455b69dSRui Feng #define DMA_RST 0x80
537e455b69dSRui Feng #define DMA_BUSY 0x04
538e455b69dSRui Feng #define DMA_DIR_TO_CARD 0x00
539e455b69dSRui Feng #define DMA_DIR_FROM_CARD 0x02
540e455b69dSRui Feng #define DMA_EN 0x01
541e455b69dSRui Feng #define DMA_128 (0 << 4)
542e455b69dSRui Feng #define DMA_256 (1 << 4)
543e455b69dSRui Feng #define DMA_512 (2 << 4)
544e455b69dSRui Feng #define DMA_1024 (3 << 4)
545e455b69dSRui Feng #define DMA_PACK_SIZE_MASK 0x30
546e455b69dSRui Feng #define BCTL 0xFE2D
547e455b69dSRui Feng #define RBBC0 0xFE2E
548e455b69dSRui Feng #define RBBC1 0xFE2F
549e455b69dSRui Feng #define RBDAT 0xFE30
550e455b69dSRui Feng #define RBCTL 0xFE34
5515da4e04aSRui Feng #define U_AUTO_DMA_EN_MASK 0x20
5525da4e04aSRui Feng #define U_AUTO_DMA_DISABLE 0x00
5535da4e04aSRui Feng #define RB_FLUSH 0x80
554e455b69dSRui Feng #define CFGADDR0 0xFE35
555e455b69dSRui Feng #define CFGADDR1 0xFE36
556e455b69dSRui Feng #define CFGDATA0 0xFE37
557e455b69dSRui Feng #define CFGDATA1 0xFE38
558e455b69dSRui Feng #define CFGDATA2 0xFE39
559e455b69dSRui Feng #define CFGDATA3 0xFE3A
560e455b69dSRui Feng #define CFGRWCTL 0xFE3B
561e455b69dSRui Feng #define PHYRWCTL 0xFE3C
562e455b69dSRui Feng #define PHYDATA0 0xFE3D
563e455b69dSRui Feng #define PHYDATA1 0xFE3E
564e455b69dSRui Feng #define PHYADDR 0xFE3F
565e455b69dSRui Feng #define MSGRXDATA0 0xFE40
566e455b69dSRui Feng #define MSGRXDATA1 0xFE41
567e455b69dSRui Feng #define MSGRXDATA2 0xFE42
568e455b69dSRui Feng #define MSGRXDATA3 0xFE43
569e455b69dSRui Feng #define MSGTXDATA0 0xFE44
570e455b69dSRui Feng #define MSGTXDATA1 0xFE45
571e455b69dSRui Feng #define MSGTXDATA2 0xFE46
572e455b69dSRui Feng #define MSGTXDATA3 0xFE47
573e455b69dSRui Feng #define MSGTXCTL 0xFE48
574e455b69dSRui Feng #define LTR_CTL 0xFE4A
575e455b69dSRui Feng #define LTR_TX_EN_MASK BIT(7)
576e455b69dSRui Feng #define LTR_TX_EN_1 BIT(7)
577e455b69dSRui Feng #define LTR_TX_EN_0 0
578e455b69dSRui Feng #define LTR_LATENCY_MODE_MASK BIT(6)
579e455b69dSRui Feng #define LTR_LATENCY_MODE_HW 0
580e455b69dSRui Feng #define LTR_LATENCY_MODE_SW BIT(6)
581e455b69dSRui Feng #define OBFF_CFG 0xFE4C
5825da4e04aSRui Feng #define OBFF_EN_MASK 0x03
5835da4e04aSRui Feng #define OBFF_DISABLE 0x00
584e455b69dSRui Feng
585e455b69dSRui Feng #define CDRESUMECTL 0xFE52
586e455b69dSRui Feng #define WAKE_SEL_CTL 0xFE54
587e455b69dSRui Feng #define PCLK_CTL 0xFE55
588e455b69dSRui Feng #define PCLK_MODE_SEL 0x20
589e455b69dSRui Feng #define PME_FORCE_CTL 0xFE56
590e455b69dSRui Feng
591e455b69dSRui Feng #define ASPM_FORCE_CTL 0xFE57
592e455b69dSRui Feng #define FORCE_ASPM_CTL0 0x10
593849a9366SRicky Wu #define FORCE_ASPM_CTL1 0x20
594e455b69dSRui Feng #define FORCE_ASPM_VAL_MASK 0x03
595e455b69dSRui Feng #define FORCE_ASPM_L1_EN 0x02
596e455b69dSRui Feng #define FORCE_ASPM_L0_EN 0x01
597e455b69dSRui Feng #define FORCE_ASPM_NO_ASPM 0x00
598e455b69dSRui Feng #define PM_CLK_FORCE_CTL 0xFE58
5995da4e04aSRui Feng #define CLK_PM_EN 0x01
600e455b69dSRui Feng #define FUNC_FORCE_CTL 0xFE59
601e455b69dSRui Feng #define FUNC_FORCE_UPME_XMT_DBG 0x02
602e455b69dSRui Feng #define PERST_GLITCH_WIDTH 0xFE5C
603e455b69dSRui Feng #define CHANGE_LINK_STATE 0xFE5B
604e455b69dSRui Feng #define RESET_LOAD_REG 0xFE5E
605e455b69dSRui Feng #define EFUSE_CONTENT 0xFE5F
606e455b69dSRui Feng #define HOST_SLEEP_STATE 0xFE60
607e455b69dSRui Feng #define HOST_ENTER_S1 1
608e455b69dSRui Feng #define HOST_ENTER_S3 2
609e455b69dSRui Feng
610e455b69dSRui Feng #define SDIO_CFG 0xFE70
611e455b69dSRui Feng #define PM_EVENT_DEBUG 0xFE71
612e455b69dSRui Feng #define PME_DEBUG_0 0x08
613e455b69dSRui Feng #define NFTS_TX_CTRL 0xFE72
614e455b69dSRui Feng
615e455b69dSRui Feng #define PWR_GATE_CTRL 0xFE75
616e455b69dSRui Feng #define PWR_GATE_EN 0x01
617e455b69dSRui Feng #define LDO3318_PWR_MASK 0x06
618e455b69dSRui Feng #define LDO_ON 0x00
619e455b69dSRui Feng #define LDO_SUSPEND 0x04
620e455b69dSRui Feng #define LDO_OFF 0x06
621e455b69dSRui Feng #define PWD_SUSPEND_EN 0xFE76
622e455b69dSRui Feng #define LDO_PWR_SEL 0xFE78
623e455b69dSRui Feng
624e455b69dSRui Feng #define L1SUB_CONFIG1 0xFE8D
6255da4e04aSRui Feng #define AUX_CLK_ACTIVE_SEL_MASK 0x01
6265da4e04aSRui Feng #define MAC_CKSW_DONE 0x00
627e455b69dSRui Feng #define L1SUB_CONFIG2 0xFE8E
628e455b69dSRui Feng #define L1SUB_AUTO_CFG 0x02
629e455b69dSRui Feng #define L1SUB_CONFIG3 0xFE8F
630e455b69dSRui Feng #define L1OFF_MBIAS2_EN_5250 BIT(7)
631e455b69dSRui Feng
632e455b69dSRui Feng #define DUMMY_REG_RESET_0 0xFE90
6335da4e04aSRui Feng #define IC_VERSION_MASK 0x0F
634e455b69dSRui Feng
6355da4e04aSRui Feng #define REG_VREF 0xFE97
6365da4e04aSRui Feng #define PWD_SUSPND_EN 0x10
6375da4e04aSRui Feng #define RTS5260_DMA_RST_CTL_0 0xFEBF
6385da4e04aSRui Feng #define RTS5260_DMA_RST 0x80
6395da4e04aSRui Feng #define RTS5260_ADMA3_RST 0x40
640e455b69dSRui Feng #define AUTOLOAD_CFG_BASE 0xFF00
6415da4e04aSRui Feng #define RELINK_TIME_MASK 0x01
642e455b69dSRui Feng #define PETXCFG 0xFF03
643e455b69dSRui Feng #define FORCE_CLKREQ_DELINK_MASK BIT(7)
644e455b69dSRui Feng #define FORCE_CLKREQ_LOW 0x80
645e455b69dSRui Feng #define FORCE_CLKREQ_HIGH 0x00
646e455b69dSRui Feng
647e455b69dSRui Feng #define PM_CTRL1 0xFF44
648e455b69dSRui Feng #define CD_RESUME_EN_MASK 0xF0
649e455b69dSRui Feng
650e455b69dSRui Feng #define PM_CTRL2 0xFF45
651e455b69dSRui Feng #define PM_CTRL3 0xFF46
652e455b69dSRui Feng #define SDIO_SEND_PME_EN 0x80
653e455b69dSRui Feng #define FORCE_RC_MODE_ON 0x40
654e455b69dSRui Feng #define FORCE_RX50_LINK_ON 0x20
655e455b69dSRui Feng #define D3_DELINK_MODE_EN 0x10
656e455b69dSRui Feng #define USE_PESRTB_CTL_DELINK 0x08
657e455b69dSRui Feng #define DELAY_PIN_WAKE 0x04
658e455b69dSRui Feng #define RESET_PIN_WAKE 0x02
659e455b69dSRui Feng #define PM_WAKE_EN 0x01
660e455b69dSRui Feng #define PM_CTRL4 0xFF47
661e455b69dSRui Feng
6626b7b58f4SRui Feng /* FW config info register */
6636b7b58f4SRui Feng #define RTS5261_FW_CFG_INFO0 0xFF50
6646b7b58f4SRui Feng #define RTS5261_FW_EXPRESS_TEST_MASK (0x01 << 0)
6656b7b58f4SRui Feng #define RTS5261_FW_EA_MODE_MASK (0x01 << 5)
6665afe8021SRui Feng #define RTS5261_FW_CFG0 0xFF54
6675afe8021SRui Feng #define RTS5261_FW_ENTER_EXPRESS (0x01 << 0)
6685afe8021SRui Feng
6695afe8021SRui Feng #define RTS5261_FW_CFG1 0xFF55
6705afe8021SRui Feng #define RTS5261_SYS_CLK_SEL_MCU_CLK (0x01 << 7)
6715afe8021SRui Feng #define RTS5261_CRC_CLK_SEL_MCU_CLK (0x01 << 6)
6725afe8021SRui Feng #define RTS5261_FAKE_MCU_CLOCK_GATING (0x01 << 5)
6735afe8021SRui Feng #define RTS5261_MCU_BUS_SEL_MASK (0x01 << 4)
6745afe8021SRui Feng #define RTS5261_MCU_CLOCK_SEL_MASK (0x03 << 2)
6755afe8021SRui Feng #define RTS5261_MCU_CLOCK_SEL_16M (0x01 << 2)
6765afe8021SRui Feng #define RTS5261_MCU_CLOCK_GATING (0x01 << 1)
6775afe8021SRui Feng #define RTS5261_DRIVER_ENABLE_FW (0x01 << 0)
6785afe8021SRui Feng
679849a9366SRicky Wu #define REG_CFG_OOBS_OFF_TIMER 0xFEA6
680849a9366SRicky Wu #define REG_CFG_OOBS_ON_TIMER 0xFEA7
681849a9366SRicky Wu #define REG_CFG_VCM_ON_TIMER 0xFEA8
682849a9366SRicky Wu #define REG_CFG_OOBS_POLLING 0xFEA9
683849a9366SRicky Wu
684e455b69dSRui Feng /* Memory mapping */
685e455b69dSRui Feng #define SRAM_BASE 0xE600
686e455b69dSRui Feng #define RBUF_BASE 0xF400
687e455b69dSRui Feng #define PPBUF_BASE1 0xF800
688e455b69dSRui Feng #define PPBUF_BASE2 0xFA00
689e455b69dSRui Feng #define IMAGE_FLAG_ADDR0 0xCE80
690e455b69dSRui Feng #define IMAGE_FLAG_ADDR1 0xCE81
691e455b69dSRui Feng
692e455b69dSRui Feng #define RREF_CFG 0xFF6C
693e455b69dSRui Feng #define RREF_VBGSEL_MASK 0x38
694e455b69dSRui Feng #define RREF_VBGSEL_1V25 0x28
695e455b69dSRui Feng
696e455b69dSRui Feng #define OOBS_CONFIG 0xFF6E
697e455b69dSRui Feng #define OOBS_AUTOK_DIS 0x80
698e455b69dSRui Feng #define OOBS_VAL_MASK 0x1F
699e455b69dSRui Feng
700e455b69dSRui Feng #define LDO_DV18_CFG 0xFF70
701e455b69dSRui Feng #define LDO_DV18_SR_MASK 0xC0
702e455b69dSRui Feng #define LDO_DV18_SR_DF 0x40
7035da4e04aSRui Feng #define DV331812_MASK 0x70
7045da4e04aSRui Feng #define DV331812_33 0x70
7055da4e04aSRui Feng #define DV331812_17 0x30
706e455b69dSRui Feng
707e455b69dSRui Feng #define LDO_CONFIG2 0xFF71
708e455b69dSRui Feng #define LDO_D3318_MASK 0x07
709e455b69dSRui Feng #define LDO_D3318_33V 0x07
710e455b69dSRui Feng #define LDO_D3318_18V 0x02
7115da4e04aSRui Feng #define DV331812_VDD1 0x04
7125da4e04aSRui Feng #define DV331812_POWERON 0x08
7135da4e04aSRui Feng #define DV331812_POWEROFF 0x00
714e455b69dSRui Feng
715e455b69dSRui Feng #define LDO_VCC_CFG0 0xFF72
716e455b69dSRui Feng #define LDO_VCC_LMTVTH_MASK 0x30
717e455b69dSRui Feng #define LDO_VCC_LMTVTH_2A 0x10
7185da4e04aSRui Feng /*RTS5260*/
7195da4e04aSRui Feng #define RTS5260_DVCC_TUNE_MASK 0x70
7205da4e04aSRui Feng #define RTS5260_DVCC_33 0x70
721e455b69dSRui Feng
7225afe8021SRui Feng /*RTS5261*/
7235afe8021SRui Feng #define RTS5261_LDO1_CFG0 0xFF72
7245afe8021SRui Feng #define RTS5261_LDO1_OCP_THD_MASK (0x07 << 5)
7255afe8021SRui Feng #define RTS5261_LDO1_OCP_EN (0x01 << 4)
7265afe8021SRui Feng #define RTS5261_LDO1_OCP_LMT_THD_MASK (0x03 << 2)
7275afe8021SRui Feng #define RTS5261_LDO1_OCP_LMT_EN (0x01 << 1)
7285afe8021SRui Feng
729e455b69dSRui Feng #define LDO_VCC_CFG1 0xFF73
730e455b69dSRui Feng #define LDO_VCC_REF_TUNE_MASK 0x30
731e455b69dSRui Feng #define LDO_VCC_REF_1V2 0x20
732e455b69dSRui Feng #define LDO_VCC_TUNE_MASK 0x07
733e455b69dSRui Feng #define LDO_VCC_1V8 0x04
734e455b69dSRui Feng #define LDO_VCC_3V3 0x07
735e455b69dSRui Feng #define LDO_VCC_LMT_EN 0x08
7365da4e04aSRui Feng /*RTS5260*/
7375da4e04aSRui Feng #define LDO_POW_SDVDD1_MASK 0x08
7385da4e04aSRui Feng #define LDO_POW_SDVDD1_ON 0x08
7395da4e04aSRui Feng #define LDO_POW_SDVDD1_OFF 0x00
740e455b69dSRui Feng
741e455b69dSRui Feng #define LDO_VIO_CFG 0xFF75
742e455b69dSRui Feng #define LDO_VIO_SR_MASK 0xC0
743e455b69dSRui Feng #define LDO_VIO_SR_DF 0x40
744e455b69dSRui Feng #define LDO_VIO_REF_TUNE_MASK 0x30
745e455b69dSRui Feng #define LDO_VIO_REF_1V2 0x20
746e455b69dSRui Feng #define LDO_VIO_TUNE_MASK 0x07
747e455b69dSRui Feng #define LDO_VIO_1V7 0x03
748e455b69dSRui Feng #define LDO_VIO_1V8 0x04
749e455b69dSRui Feng #define LDO_VIO_3V3 0x07
750e455b69dSRui Feng
751e455b69dSRui Feng #define LDO_DV12S_CFG 0xFF76
752e455b69dSRui Feng #define LDO_REF12_TUNE_MASK 0x18
753e455b69dSRui Feng #define LDO_REF12_TUNE_DF 0x10
754e455b69dSRui Feng #define LDO_D12_TUNE_MASK 0x07
755e455b69dSRui Feng #define LDO_D12_TUNE_DF 0x04
756e455b69dSRui Feng
757e455b69dSRui Feng #define LDO_AV12S_CFG 0xFF77
758e455b69dSRui Feng #define LDO_AV12S_TUNE_MASK 0x07
759e455b69dSRui Feng #define LDO_AV12S_TUNE_DF 0x04
760e455b69dSRui Feng
761e455b69dSRui Feng #define SD40_LDO_CTL1 0xFE7D
762e455b69dSRui Feng #define SD40_VIO_TUNE_MASK 0x70
763e455b69dSRui Feng #define SD40_VIO_TUNE_1V7 0x30
764e455b69dSRui Feng #define SD_VIO_LDO_1V8 0x40
765e455b69dSRui Feng #define SD_VIO_LDO_3V3 0x70
766e455b69dSRui Feng
7675da4e04aSRui Feng #define RTS5260_AUTOLOAD_CFG4 0xFF7F
7685da4e04aSRui Feng #define RTS5260_MIMO_DISABLE 0x8A
7695afe8021SRui Feng /*RTS5261*/
7705afe8021SRui Feng #define RTS5261_AUX_CLK_16M_EN (1 << 5)
7715da4e04aSRui Feng
7725da4e04aSRui Feng #define RTS5260_REG_GPIO_CTL0 0xFC1A
7735da4e04aSRui Feng #define RTS5260_REG_GPIO_MASK 0x01
7745da4e04aSRui Feng #define RTS5260_REG_GPIO_ON 0x01
7755da4e04aSRui Feng #define RTS5260_REG_GPIO_OFF 0x00
7765da4e04aSRui Feng
7775da4e04aSRui Feng #define PWR_GLOBAL_CTRL 0xF200
7785da4e04aSRui Feng #define PCIE_L1_2_EN 0x0C
7795da4e04aSRui Feng #define PCIE_L1_1_EN 0x0A
7805da4e04aSRui Feng #define PCIE_L1_0_EN 0x09
7815da4e04aSRui Feng #define PWR_FE_CTL 0xF201
7825da4e04aSRui Feng #define PCIE_L1_2_PD_FE_EN 0x0C
7835da4e04aSRui Feng #define PCIE_L1_1_PD_FE_EN 0x0A
7845da4e04aSRui Feng #define PCIE_L1_0_PD_FE_EN 0x09
7855da4e04aSRui Feng #define CFG_PCIE_APHY_OFF_0 0xF204
7865da4e04aSRui Feng #define CFG_PCIE_APHY_OFF_0_DEFAULT 0xBF
7875da4e04aSRui Feng #define CFG_PCIE_APHY_OFF_1 0xF205
7885da4e04aSRui Feng #define CFG_PCIE_APHY_OFF_1_DEFAULT 0xFF
7895da4e04aSRui Feng #define CFG_PCIE_APHY_OFF_2 0xF206
7905da4e04aSRui Feng #define CFG_PCIE_APHY_OFF_2_DEFAULT 0x01
7915da4e04aSRui Feng #define CFG_PCIE_APHY_OFF_3 0xF207
7925da4e04aSRui Feng #define CFG_PCIE_APHY_OFF_3_DEFAULT 0x00
7935da4e04aSRui Feng #define CFG_L1_0_PCIE_MAC_RET_VALUE 0xF20C
7945da4e04aSRui Feng #define CFG_L1_0_PCIE_DPHY_RET_VALUE 0xF20E
7955da4e04aSRui Feng #define CFG_L1_0_SYS_RET_VALUE 0xF210
7965da4e04aSRui Feng #define CFG_L1_0_CRC_MISC_RET_VALUE 0xF212
7975da4e04aSRui Feng #define CFG_L1_0_CRC_SD30_RET_VALUE 0xF214
7985da4e04aSRui Feng #define CFG_L1_0_CRC_SD40_RET_VALUE 0xF216
7995da4e04aSRui Feng #define CFG_LP_FPWM_VALUE 0xF219
8005da4e04aSRui Feng #define CFG_LP_FPWM_VALUE_DEFAULT 0x18
8015da4e04aSRui Feng #define PWC_CDR 0xF253
8025da4e04aSRui Feng #define PWC_CDR_DEFAULT 0x03
8035da4e04aSRui Feng #define CFG_L1_0_RET_VALUE_DEFAULT 0x1B
8045da4e04aSRui Feng #define CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT 0x0C
8055da4e04aSRui Feng
8065da4e04aSRui Feng /* OCPCTL */
8075da4e04aSRui Feng #define SD_DETECT_EN 0x08
8085da4e04aSRui Feng #define SD_OCP_INT_EN 0x04
8095da4e04aSRui Feng #define SD_OCP_INT_CLR 0x02
8105da4e04aSRui Feng #define SD_OC_CLR 0x01
8115da4e04aSRui Feng
8125da4e04aSRui Feng #define SDVIO_DETECT_EN (1 << 7)
8135da4e04aSRui Feng #define SDVIO_OCP_INT_EN (1 << 6)
8145da4e04aSRui Feng #define SDVIO_OCP_INT_CLR (1 << 5)
8155da4e04aSRui Feng #define SDVIO_OC_CLR (1 << 4)
8165da4e04aSRui Feng
8175da4e04aSRui Feng /* OCPSTAT */
8185da4e04aSRui Feng #define SD_OCP_DETECT 0x08
8195da4e04aSRui Feng #define SD_OC_NOW 0x04
8205da4e04aSRui Feng #define SD_OC_EVER 0x02
8215da4e04aSRui Feng
8225da4e04aSRui Feng #define SDVIO_OC_NOW (1 << 6)
8235da4e04aSRui Feng #define SDVIO_OC_EVER (1 << 5)
8245da4e04aSRui Feng
8255da4e04aSRui Feng #define REG_OCPCTL 0xFD6A
8265da4e04aSRui Feng #define REG_OCPSTAT 0xFD6E
8275da4e04aSRui Feng #define REG_OCPGLITCH 0xFD6C
8285da4e04aSRui Feng #define REG_OCPPARA1 0xFD6B
8295da4e04aSRui Feng #define REG_OCPPARA2 0xFD6D
8305da4e04aSRui Feng
8315da4e04aSRui Feng /* rts5260 DV3318 OCP-related registers */
8325da4e04aSRui Feng #define REG_DV3318_OCPCTL 0xFD89
8335da4e04aSRui Feng #define DV3318_OCP_TIME_MASK 0xF0
8345da4e04aSRui Feng #define DV3318_DETECT_EN 0x08
8355da4e04aSRui Feng #define DV3318_OCP_INT_EN 0x04
8365da4e04aSRui Feng #define DV3318_OCP_INT_CLR 0x02
8375da4e04aSRui Feng #define DV3318_OCP_CLR 0x01
8385da4e04aSRui Feng
8395da4e04aSRui Feng #define REG_DV3318_OCPSTAT 0xFD8A
8405da4e04aSRui Feng #define DV3318_OCP_GlITCH_TIME_MASK 0xF0
8415da4e04aSRui Feng #define DV3318_OCP_DETECT 0x08
8425da4e04aSRui Feng #define DV3318_OCP_NOW 0x04
8435da4e04aSRui Feng #define DV3318_OCP_EVER 0x02
8445da4e04aSRui Feng
8455da4e04aSRui Feng #define SD_OCP_GLITCH_MASK 0x0F
8465da4e04aSRui Feng
8475da4e04aSRui Feng /* OCPPARA1 */
8485da4e04aSRui Feng #define SDVIO_OCP_TIME_60 0x00
8495da4e04aSRui Feng #define SDVIO_OCP_TIME_100 0x10
8505da4e04aSRui Feng #define SDVIO_OCP_TIME_200 0x20
8515da4e04aSRui Feng #define SDVIO_OCP_TIME_400 0x30
8525da4e04aSRui Feng #define SDVIO_OCP_TIME_600 0x40
8535da4e04aSRui Feng #define SDVIO_OCP_TIME_800 0x50
8545da4e04aSRui Feng #define SDVIO_OCP_TIME_1100 0x60
8555da4e04aSRui Feng #define SDVIO_OCP_TIME_MASK 0x70
8565da4e04aSRui Feng
8575da4e04aSRui Feng #define SD_OCP_TIME_60 0x00
8585da4e04aSRui Feng #define SD_OCP_TIME_100 0x01
8595da4e04aSRui Feng #define SD_OCP_TIME_200 0x02
8605da4e04aSRui Feng #define SD_OCP_TIME_400 0x03
8615da4e04aSRui Feng #define SD_OCP_TIME_600 0x04
8625da4e04aSRui Feng #define SD_OCP_TIME_800 0x05
8635da4e04aSRui Feng #define SD_OCP_TIME_1100 0x06
8645da4e04aSRui Feng #define SD_OCP_TIME_MASK 0x07
8655da4e04aSRui Feng
8665da4e04aSRui Feng /* OCPPARA2 */
8675da4e04aSRui Feng #define SDVIO_OCP_THD_190 0x00
8685da4e04aSRui Feng #define SDVIO_OCP_THD_250 0x10
8695da4e04aSRui Feng #define SDVIO_OCP_THD_320 0x20
8705da4e04aSRui Feng #define SDVIO_OCP_THD_380 0x30
8715da4e04aSRui Feng #define SDVIO_OCP_THD_440 0x40
8725da4e04aSRui Feng #define SDVIO_OCP_THD_500 0x50
8735da4e04aSRui Feng #define SDVIO_OCP_THD_570 0x60
8745da4e04aSRui Feng #define SDVIO_OCP_THD_630 0x70
8755da4e04aSRui Feng #define SDVIO_OCP_THD_MASK 0x70
8765da4e04aSRui Feng
8775da4e04aSRui Feng #define SD_OCP_THD_450 0x00
8785da4e04aSRui Feng #define SD_OCP_THD_550 0x01
8795da4e04aSRui Feng #define SD_OCP_THD_650 0x02
8805da4e04aSRui Feng #define SD_OCP_THD_750 0x03
8815da4e04aSRui Feng #define SD_OCP_THD_850 0x04
8825da4e04aSRui Feng #define SD_OCP_THD_950 0x05
8835da4e04aSRui Feng #define SD_OCP_THD_1050 0x06
8845da4e04aSRui Feng #define SD_OCP_THD_1150 0x07
8855da4e04aSRui Feng #define SD_OCP_THD_MASK 0x07
8865da4e04aSRui Feng
8875da4e04aSRui Feng #define SDVIO_OCP_GLITCH_MASK 0xF0
8885da4e04aSRui Feng #define SDVIO_OCP_GLITCH_NONE 0x00
8895da4e04aSRui Feng #define SDVIO_OCP_GLITCH_50U 0x10
8905da4e04aSRui Feng #define SDVIO_OCP_GLITCH_100U 0x20
8915da4e04aSRui Feng #define SDVIO_OCP_GLITCH_200U 0x30
8925da4e04aSRui Feng #define SDVIO_OCP_GLITCH_600U 0x40
8935da4e04aSRui Feng #define SDVIO_OCP_GLITCH_800U 0x50
8945da4e04aSRui Feng #define SDVIO_OCP_GLITCH_1M 0x60
8955da4e04aSRui Feng #define SDVIO_OCP_GLITCH_2M 0x70
8965da4e04aSRui Feng #define SDVIO_OCP_GLITCH_3M 0x80
8975da4e04aSRui Feng #define SDVIO_OCP_GLITCH_4M 0x90
8985da4e04aSRui Feng #define SDVIO_OCP_GLIVCH_5M 0xA0
8995da4e04aSRui Feng #define SDVIO_OCP_GLITCH_6M 0xB0
9005da4e04aSRui Feng #define SDVIO_OCP_GLITCH_7M 0xC0
9015da4e04aSRui Feng #define SDVIO_OCP_GLITCH_8M 0xD0
9025da4e04aSRui Feng #define SDVIO_OCP_GLITCH_9M 0xE0
9035da4e04aSRui Feng #define SDVIO_OCP_GLITCH_10M 0xF0
9045da4e04aSRui Feng
9055da4e04aSRui Feng #define SD_OCP_GLITCH_MASK 0x0F
9065da4e04aSRui Feng #define SD_OCP_GLITCH_NONE 0x00
9075da4e04aSRui Feng #define SD_OCP_GLITCH_50U 0x01
9085da4e04aSRui Feng #define SD_OCP_GLITCH_100U 0x02
9095da4e04aSRui Feng #define SD_OCP_GLITCH_200U 0x03
9105da4e04aSRui Feng #define SD_OCP_GLITCH_600U 0x04
9115da4e04aSRui Feng #define SD_OCP_GLITCH_800U 0x05
9125da4e04aSRui Feng #define SD_OCP_GLITCH_1M 0x06
9135da4e04aSRui Feng #define SD_OCP_GLITCH_2M 0x07
9145da4e04aSRui Feng #define SD_OCP_GLITCH_3M 0x08
9155da4e04aSRui Feng #define SD_OCP_GLITCH_4M 0x09
9165da4e04aSRui Feng #define SD_OCP_GLIVCH_5M 0x0A
9175da4e04aSRui Feng #define SD_OCP_GLITCH_6M 0x0B
9185da4e04aSRui Feng #define SD_OCP_GLITCH_7M 0x0C
9195da4e04aSRui Feng #define SD_OCP_GLITCH_8M 0x0D
9205da4e04aSRui Feng #define SD_OCP_GLITCH_9M 0x0E
9215da4e04aSRui Feng #define SD_OCP_GLITCH_10M 0x0F
9225da4e04aSRui Feng
923e455b69dSRui Feng /* Phy register */
924e455b69dSRui Feng #define PHY_PCR 0x00
925e455b69dSRui Feng #define PHY_PCR_FORCE_CODE 0xB000
926e455b69dSRui Feng #define PHY_PCR_OOBS_CALI_50 0x0800
927e455b69dSRui Feng #define PHY_PCR_OOBS_VCM_08 0x0200
928e455b69dSRui Feng #define PHY_PCR_OOBS_SEN_90 0x0040
929e455b69dSRui Feng #define PHY_PCR_RSSI_EN 0x0002
930e455b69dSRui Feng #define PHY_PCR_RX10K 0x0001
931e455b69dSRui Feng
932e455b69dSRui Feng #define PHY_RCR0 0x01
933e455b69dSRui Feng #define PHY_RCR1 0x02
934e455b69dSRui Feng #define PHY_RCR1_ADP_TIME_4 0x0400
935e455b69dSRui Feng #define PHY_RCR1_VCO_COARSE 0x001F
936e455b69dSRui Feng #define PHY_RCR1_INIT_27S 0x0A1F
937e455b69dSRui Feng #define PHY_SSCCR2 0x02
938e455b69dSRui Feng #define PHY_SSCCR2_PLL_NCODE 0x0A00
939e455b69dSRui Feng #define PHY_SSCCR2_TIME0 0x001C
940e455b69dSRui Feng #define PHY_SSCCR2_TIME2_WIDTH 0x0003
941e455b69dSRui Feng
942e455b69dSRui Feng #define PHY_RCR2 0x03
943e455b69dSRui Feng #define PHY_RCR2_EMPHASE_EN 0x8000
944e455b69dSRui Feng #define PHY_RCR2_NADJR 0x4000
945e455b69dSRui Feng #define PHY_RCR2_CDR_SR_2 0x0100
946e455b69dSRui Feng #define PHY_RCR2_FREQSEL_12 0x0040
947e455b69dSRui Feng #define PHY_RCR2_CDR_SC_12P 0x0010
948e455b69dSRui Feng #define PHY_RCR2_CALIB_LATE 0x0002
949e455b69dSRui Feng #define PHY_RCR2_INIT_27S 0xC152
950e455b69dSRui Feng #define PHY_SSCCR3 0x03
951e455b69dSRui Feng #define PHY_SSCCR3_STEP_IN 0x2740
952e455b69dSRui Feng #define PHY_SSCCR3_CHECK_DELAY 0x0008
953e455b69dSRui Feng #define _PHY_ANA03 0x03
954e455b69dSRui Feng #define _PHY_ANA03_TIMER_MAX 0x2700
955e455b69dSRui Feng #define _PHY_ANA03_OOBS_DEB_EN 0x0040
956e455b69dSRui Feng #define _PHY_CMU_DEBUG_EN 0x0008
957e455b69dSRui Feng
958e455b69dSRui Feng #define PHY_RTCR 0x04
959e455b69dSRui Feng #define PHY_RDR 0x05
960e455b69dSRui Feng #define PHY_RDR_RXDSEL_1_9 0x4000
961e455b69dSRui Feng #define PHY_SSC_AUTO_PWD 0x0600
962e455b69dSRui Feng #define PHY_TCR0 0x06
963e455b69dSRui Feng #define PHY_TCR1 0x07
964e455b69dSRui Feng #define PHY_TUNE 0x08
965e455b69dSRui Feng #define PHY_TUNE_TUNEREF_1_0 0x4000
966e455b69dSRui Feng #define PHY_TUNE_VBGSEL_1252 0x0C00
967e455b69dSRui Feng #define PHY_TUNE_SDBUS_33 0x0200
968e455b69dSRui Feng #define PHY_TUNE_TUNED18 0x01C0
969e455b69dSRui Feng #define PHY_TUNE_TUNED12 0X0020
970e455b69dSRui Feng #define PHY_TUNE_TUNEA12 0x0004
971e455b69dSRui Feng #define PHY_TUNE_VOLTAGE_MASK 0xFC3F
972e455b69dSRui Feng #define PHY_TUNE_VOLTAGE_3V3 0x03C0
973e455b69dSRui Feng #define PHY_TUNE_D18_1V8 0x0100
974e455b69dSRui Feng #define PHY_TUNE_D18_1V7 0x0080
975e455b69dSRui Feng #define PHY_ANA08 0x08
976e455b69dSRui Feng #define PHY_ANA08_RX_EQ_DCGAIN 0x5000
977e455b69dSRui Feng #define PHY_ANA08_SEL_RX_EN 0x0400
978e455b69dSRui Feng #define PHY_ANA08_RX_EQ_VAL 0x03C0
979e455b69dSRui Feng #define PHY_ANA08_SCP 0x0020
980e455b69dSRui Feng #define PHY_ANA08_SEL_IPI 0x0004
981e455b69dSRui Feng
982e455b69dSRui Feng #define PHY_IMR 0x09
983e455b69dSRui Feng #define PHY_BPCR 0x0A
984e455b69dSRui Feng #define PHY_BPCR_IBRXSEL 0x0400
985e455b69dSRui Feng #define PHY_BPCR_IBTXSEL 0x0100
986e455b69dSRui Feng #define PHY_BPCR_IB_FILTER 0x0080
987e455b69dSRui Feng #define PHY_BPCR_CMIRROR_EN 0x0040
988e455b69dSRui Feng
989e455b69dSRui Feng #define PHY_BIST 0x0B
990e455b69dSRui Feng #define PHY_RAW_L 0x0C
991e455b69dSRui Feng #define PHY_RAW_H 0x0D
992e455b69dSRui Feng #define PHY_RAW_DATA 0x0E
993e455b69dSRui Feng #define PHY_HOST_CLK_CTRL 0x0F
994e455b69dSRui Feng #define PHY_DMR 0x10
995e455b69dSRui Feng #define PHY_BACR 0x11
996e455b69dSRui Feng #define PHY_BACR_BASIC_MASK 0xFFF3
997e455b69dSRui Feng #define PHY_IER 0x12
998e455b69dSRui Feng #define PHY_BCSR 0x13
999e455b69dSRui Feng #define PHY_BPR 0x14
1000e455b69dSRui Feng #define PHY_BPNR2 0x15
1001e455b69dSRui Feng #define PHY_BPNR 0x16
1002e455b69dSRui Feng #define PHY_BRNR2 0x17
1003e455b69dSRui Feng #define PHY_BENR 0x18
1004e455b69dSRui Feng #define PHY_REV 0x19
1005e455b69dSRui Feng #define PHY_REV_RESV 0xE000
1006e455b69dSRui Feng #define PHY_REV_RXIDLE_LATCHED 0x1000
1007e455b69dSRui Feng #define PHY_REV_P1_EN 0x0800
1008e455b69dSRui Feng #define PHY_REV_RXIDLE_EN 0x0400
1009e455b69dSRui Feng #define PHY_REV_CLKREQ_TX_EN 0x0200
1010e455b69dSRui Feng #define PHY_REV_CLKREQ_RX_EN 0x0100
1011e455b69dSRui Feng #define PHY_REV_CLKREQ_DT_1_0 0x0040
1012e455b69dSRui Feng #define PHY_REV_STOP_CLKRD 0x0020
1013e455b69dSRui Feng #define PHY_REV_RX_PWST 0x0008
1014e455b69dSRui Feng #define PHY_REV_STOP_CLKWR 0x0004
1015e455b69dSRui Feng #define _PHY_REV0 0x19
1016e455b69dSRui Feng #define _PHY_REV0_FILTER_OUT 0x3800
1017e455b69dSRui Feng #define _PHY_REV0_CDR_BYPASS_PFD 0x0100
1018e455b69dSRui Feng #define _PHY_REV0_CDR_RX_IDLE_BYPASS 0x0002
1019e455b69dSRui Feng
1020e455b69dSRui Feng #define PHY_FLD0 0x1A
1021e455b69dSRui Feng #define PHY_ANA1A 0x1A
1022e455b69dSRui Feng #define PHY_ANA1A_TXR_LOOPBACK 0x2000
1023e455b69dSRui Feng #define PHY_ANA1A_RXT_BIST 0x0500
1024e455b69dSRui Feng #define PHY_ANA1A_TXR_BIST 0x0040
1025e455b69dSRui Feng #define PHY_ANA1A_REV 0x0006
1026e455b69dSRui Feng #define PHY_FLD0_INIT_27S 0x2546
1027e455b69dSRui Feng #define PHY_FLD1 0x1B
1028e455b69dSRui Feng #define PHY_FLD2 0x1C
1029e455b69dSRui Feng #define PHY_FLD3 0x1D
1030e455b69dSRui Feng #define PHY_FLD3_TIMER_4 0x0800
1031e455b69dSRui Feng #define PHY_FLD3_TIMER_6 0x0020
1032e455b69dSRui Feng #define PHY_FLD3_RXDELINK 0x0004
1033e455b69dSRui Feng #define PHY_FLD3_INIT_27S 0x0004
1034e455b69dSRui Feng #define PHY_ANA1D 0x1D
1035e455b69dSRui Feng #define PHY_ANA1D_DEBUG_ADDR 0x0004
1036e455b69dSRui Feng #define _PHY_FLD0 0x1D
1037e455b69dSRui Feng #define _PHY_FLD0_CLK_REQ_20C 0x8000
1038e455b69dSRui Feng #define _PHY_FLD0_RX_IDLE_EN 0x1000
1039e455b69dSRui Feng #define _PHY_FLD0_BIT_ERR_RSTN 0x0800
1040e455b69dSRui Feng #define _PHY_FLD0_BER_COUNT 0x01E0
1041e455b69dSRui Feng #define _PHY_FLD0_BER_TIMER 0x001E
1042e455b69dSRui Feng #define _PHY_FLD0_CHECK_EN 0x0001
1043e455b69dSRui Feng
1044e455b69dSRui Feng #define PHY_FLD4 0x1E
1045e455b69dSRui Feng #define PHY_FLD4_FLDEN_SEL 0x4000
1046e455b69dSRui Feng #define PHY_FLD4_REQ_REF 0x2000
1047e455b69dSRui Feng #define PHY_FLD4_RXAMP_OFF 0x1000
1048e455b69dSRui Feng #define PHY_FLD4_REQ_ADDA 0x0800
1049e455b69dSRui Feng #define PHY_FLD4_BER_COUNT 0x00E0
1050e455b69dSRui Feng #define PHY_FLD4_BER_TIMER 0x000A
1051e455b69dSRui Feng #define PHY_FLD4_BER_CHK_EN 0x0001
1052e455b69dSRui Feng #define PHY_FLD4_INIT_27S 0x5C7F
1053e455b69dSRui Feng #define PHY_DIG1E 0x1E
1054e455b69dSRui Feng #define PHY_DIG1E_REV 0x4000
1055e455b69dSRui Feng #define PHY_DIG1E_D0_X_D1 0x1000
1056e455b69dSRui Feng #define PHY_DIG1E_RX_ON_HOST 0x0800
1057e455b69dSRui Feng #define PHY_DIG1E_RCLK_REF_HOST 0x0400
1058e455b69dSRui Feng #define PHY_DIG1E_RCLK_TX_EN_KEEP 0x0040
1059e455b69dSRui Feng #define PHY_DIG1E_RCLK_TX_TERM_KEEP 0x0020
1060e455b69dSRui Feng #define PHY_DIG1E_RCLK_RX_EIDLE_ON 0x0010
1061e455b69dSRui Feng #define PHY_DIG1E_TX_TERM_KEEP 0x0008
1062e455b69dSRui Feng #define PHY_DIG1E_RX_TERM_KEEP 0x0004
1063e455b69dSRui Feng #define PHY_DIG1E_TX_EN_KEEP 0x0002
1064e455b69dSRui Feng #define PHY_DIG1E_RX_EN_KEEP 0x0001
1065e455b69dSRui Feng #define PHY_DUM_REG 0x1F
1066e455b69dSRui Feng
1067e455b69dSRui Feng #define PCR_SETTING_REG1 0x724
1068e455b69dSRui Feng #define PCR_SETTING_REG2 0x814
1069e455b69dSRui Feng #define PCR_SETTING_REG3 0x747
1070*b1c5f308SRicky WU #define PCR_SETTING_REG4 0x818
1071*b1c5f308SRicky WU #define PCR_SETTING_REG5 0x81C
1072*b1c5f308SRicky WU
1073e455b69dSRui Feng
1074e455b69dSRui Feng #define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
1075e455b69dSRui Feng
1076e455b69dSRui Feng #define RTS5227_DEVICE_ID 0x5227
1077e455b69dSRui Feng #define RTS_MAX_TIMES_FREQ_REDUCTION 8
1078e455b69dSRui Feng
1079e455b69dSRui Feng struct rtsx_pcr;
1080e455b69dSRui Feng
1081e455b69dSRui Feng struct pcr_handle {
1082e455b69dSRui Feng struct rtsx_pcr *pcr;
1083e455b69dSRui Feng };
1084e455b69dSRui Feng
1085e455b69dSRui Feng struct pcr_ops {
1086e455b69dSRui Feng int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
1087e455b69dSRui Feng int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
1088e455b69dSRui Feng int (*extra_init_hw)(struct rtsx_pcr *pcr);
1089e455b69dSRui Feng int (*optimize_phy)(struct rtsx_pcr *pcr);
1090e455b69dSRui Feng int (*turn_on_led)(struct rtsx_pcr *pcr);
1091e455b69dSRui Feng int (*turn_off_led)(struct rtsx_pcr *pcr);
1092e455b69dSRui Feng int (*enable_auto_blink)(struct rtsx_pcr *pcr);
1093e455b69dSRui Feng int (*disable_auto_blink)(struct rtsx_pcr *pcr);
1094e455b69dSRui Feng int (*card_power_on)(struct rtsx_pcr *pcr, int card);
1095e455b69dSRui Feng int (*card_power_off)(struct rtsx_pcr *pcr, int card);
1096e455b69dSRui Feng int (*switch_output_voltage)(struct rtsx_pcr *pcr,
1097e455b69dSRui Feng u8 voltage);
1098e455b69dSRui Feng unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr);
1099e455b69dSRui Feng int (*conv_clk_and_div_n)(int clk, int dir);
1100e455b69dSRui Feng void (*fetch_vendor_settings)(struct rtsx_pcr *pcr);
110171732e24SKai-Heng Feng void (*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state, bool runtime);
11025da4e04aSRui Feng void (*stop_cmd)(struct rtsx_pcr *pcr);
1103e455b69dSRui Feng
1104e455b69dSRui Feng void (*set_aspm)(struct rtsx_pcr *pcr, bool enable);
1105e455b69dSRui Feng void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active);
11065da4e04aSRui Feng void (*enable_ocp)(struct rtsx_pcr *pcr);
11075da4e04aSRui Feng void (*disable_ocp)(struct rtsx_pcr *pcr);
11085da4e04aSRui Feng void (*init_ocp)(struct rtsx_pcr *pcr);
11095da4e04aSRui Feng void (*process_ocp)(struct rtsx_pcr *pcr);
11105da4e04aSRui Feng int (*get_ocpstat)(struct rtsx_pcr *pcr, u8 *val);
11115da4e04aSRui Feng void (*clear_ocpstat)(struct rtsx_pcr *pcr);
1112e455b69dSRui Feng };
1113e455b69dSRui Feng
1114e455b69dSRui Feng enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
11153df4fce7SRicky Wu enum ASPM_MODE {ASPM_MODE_CFG, ASPM_MODE_REG};
1116e455b69dSRui Feng
1117e455b69dSRui Feng #define ASPM_L1_1_EN BIT(0)
1118e455b69dSRui Feng #define ASPM_L1_2_EN BIT(1)
1119e455b69dSRui Feng #define PM_L1_1_EN BIT(2)
1120e455b69dSRui Feng #define PM_L1_2_EN BIT(3)
1121e455b69dSRui Feng #define LTR_L1SS_PWR_GATE_EN BIT(4)
1122e455b69dSRui Feng #define L1_SNOOZE_TEST_EN BIT(5)
1123e455b69dSRui Feng #define LTR_L1SS_PWR_GATE_CHECK_CARD_EN BIT(6)
1124e455b69dSRui Feng
1125e455b69dSRui Feng /*
1126e455b69dSRui Feng * struct rtsx_cr_option - card reader option
1127e455b69dSRui Feng * @dev_flags: device flags
1128e455b69dSRui Feng * @force_clkreq_0: force clock request
1129e455b69dSRui Feng * @ltr_en: enable ltr mode flag
1130e455b69dSRui Feng * @ltr_enabled: ltr mode in configure space flag
1131e455b69dSRui Feng * @ltr_active: ltr mode status
1132e455b69dSRui Feng * @ltr_active_latency: ltr mode active latency
1133e455b69dSRui Feng * @ltr_idle_latency: ltr mode idle latency
1134e455b69dSRui Feng * @ltr_l1off_latency: ltr mode l1off latency
1135e455b69dSRui Feng * @l1_snooze_delay: l1 snooze delay
1136e455b69dSRui Feng * @ltr_l1off_sspwrgate: ltr l1off sspwrgate
1137e455b69dSRui Feng * @ltr_l1off_snooze_sspwrgate: ltr l1off snooze sspwrgate
11385da4e04aSRui Feng * @ocp_en: enable ocp flag
11395da4e04aSRui Feng * @sd_400mA_ocp_thd: 400mA ocp thd
11405da4e04aSRui Feng * @sd_800mA_ocp_thd: 800mA ocp thd
1141e455b69dSRui Feng */
1142e455b69dSRui Feng struct rtsx_cr_option {
1143e455b69dSRui Feng u32 dev_flags;
1144e455b69dSRui Feng bool force_clkreq_0;
1145e455b69dSRui Feng bool ltr_en;
1146e455b69dSRui Feng bool ltr_enabled;
1147e455b69dSRui Feng bool ltr_active;
1148e455b69dSRui Feng u32 ltr_active_latency;
1149e455b69dSRui Feng u32 ltr_idle_latency;
1150e455b69dSRui Feng u32 ltr_l1off_latency;
1151e455b69dSRui Feng u32 l1_snooze_delay;
1152e455b69dSRui Feng u8 ltr_l1off_sspwrgate;
1153e455b69dSRui Feng u8 ltr_l1off_snooze_sspwrgate;
11545da4e04aSRui Feng bool ocp_en;
11555da4e04aSRui Feng u8 sd_400mA_ocp_thd;
11565da4e04aSRui Feng u8 sd_800mA_ocp_thd;
11575da4e04aSRui Feng };
11585da4e04aSRui Feng
11595da4e04aSRui Feng /*
11605da4e04aSRui Feng * struct rtsx_hw_param - card reader hardware param
11615da4e04aSRui Feng * @interrupt_en: indicate which interrutp enable
11625da4e04aSRui Feng * @ocp_glitch: ocp glitch time
11635da4e04aSRui Feng */
11645da4e04aSRui Feng struct rtsx_hw_param {
11655da4e04aSRui Feng u32 interrupt_en;
11665da4e04aSRui Feng u8 ocp_glitch;
1167e455b69dSRui Feng };
1168e455b69dSRui Feng
1169e455b69dSRui Feng #define rtsx_set_dev_flag(cr, flag) \
1170e455b69dSRui Feng ((cr)->option.dev_flags |= (flag))
1171e455b69dSRui Feng #define rtsx_clear_dev_flag(cr, flag) \
1172e455b69dSRui Feng ((cr)->option.dev_flags &= ~(flag))
1173e455b69dSRui Feng #define rtsx_check_dev_flag(cr, flag) \
1174e455b69dSRui Feng ((cr)->option.dev_flags & (flag))
1175e455b69dSRui Feng
1176e455b69dSRui Feng struct rtsx_pcr {
1177e455b69dSRui Feng struct pci_dev *pci;
1178e455b69dSRui Feng unsigned int id;
1179e455b69dSRui Feng struct rtsx_cr_option option;
11805da4e04aSRui Feng struct rtsx_hw_param hw_param;
1181e455b69dSRui Feng
1182e455b69dSRui Feng /* pci resources */
1183e455b69dSRui Feng unsigned long addr;
1184e455b69dSRui Feng void __iomem *remap_addr;
1185e455b69dSRui Feng int irq;
1186e455b69dSRui Feng
1187e455b69dSRui Feng /* host reserved buffer */
1188e455b69dSRui Feng void *rtsx_resv_buf;
1189e455b69dSRui Feng dma_addr_t rtsx_resv_buf_addr;
1190e455b69dSRui Feng
1191e455b69dSRui Feng void *host_cmds_ptr;
1192e455b69dSRui Feng dma_addr_t host_cmds_addr;
1193e455b69dSRui Feng int ci;
1194e455b69dSRui Feng
1195e455b69dSRui Feng void *host_sg_tbl_ptr;
1196e455b69dSRui Feng dma_addr_t host_sg_tbl_addr;
1197e455b69dSRui Feng int sgi;
1198e455b69dSRui Feng
1199e455b69dSRui Feng u32 bier;
1200e455b69dSRui Feng char trans_result;
1201e455b69dSRui Feng
1202e455b69dSRui Feng unsigned int card_inserted;
1203e455b69dSRui Feng unsigned int card_removed;
1204e455b69dSRui Feng unsigned int card_exist;
1205e455b69dSRui Feng
1206e455b69dSRui Feng struct delayed_work carddet_work;
1207e455b69dSRui Feng
1208e455b69dSRui Feng spinlock_t lock;
1209e455b69dSRui Feng struct mutex pcr_mutex;
1210e455b69dSRui Feng struct completion *done;
1211e455b69dSRui Feng struct completion *finish_me;
1212e455b69dSRui Feng
1213e455b69dSRui Feng unsigned int cur_clock;
1214e455b69dSRui Feng bool remove_pci;
1215e455b69dSRui Feng bool msi_en;
1216e455b69dSRui Feng
1217e455b69dSRui Feng #define EXTRA_CAPS_SD_SDR50 (1 << 0)
1218e455b69dSRui Feng #define EXTRA_CAPS_SD_SDR104 (1 << 1)
1219e455b69dSRui Feng #define EXTRA_CAPS_SD_DDR50 (1 << 2)
1220e455b69dSRui Feng #define EXTRA_CAPS_MMC_HSDDR (1 << 3)
1221e455b69dSRui Feng #define EXTRA_CAPS_MMC_HS200 (1 << 4)
1222e455b69dSRui Feng #define EXTRA_CAPS_MMC_8BIT (1 << 5)
1223849a9366SRicky Wu #define EXTRA_CAPS_NO_MMC (1 << 7)
12245afe8021SRui Feng #define EXTRA_CAPS_SD_EXPRESS (1 << 8)
1225e455b69dSRui Feng u32 extra_caps;
1226e455b69dSRui Feng
1227e455b69dSRui Feng #define IC_VER_A 0
1228e455b69dSRui Feng #define IC_VER_B 1
1229e455b69dSRui Feng #define IC_VER_C 2
1230e455b69dSRui Feng #define IC_VER_D 3
1231e455b69dSRui Feng u8 ic_version;
1232e455b69dSRui Feng
1233e455b69dSRui Feng u8 sd30_drive_sel_1v8;
1234e455b69dSRui Feng u8 sd30_drive_sel_3v3;
1235e455b69dSRui Feng u8 card_drive_sel;
1236e455b69dSRui Feng #define ASPM_L1_EN 0x02
1237e455b69dSRui Feng u8 aspm_en;
12383df4fce7SRicky Wu enum ASPM_MODE aspm_mode;
1239e455b69dSRui Feng bool aspm_enabled;
1240e455b69dSRui Feng
1241e455b69dSRui Feng #define PCR_MS_PMOS (1 << 0)
1242e455b69dSRui Feng #define PCR_REVERSE_SOCKET (1 << 1)
1243e455b69dSRui Feng u32 flags;
1244e455b69dSRui Feng
1245e455b69dSRui Feng u32 tx_initial_phase;
1246e455b69dSRui Feng u32 rx_initial_phase;
1247e455b69dSRui Feng
1248e455b69dSRui Feng const u32 *sd_pull_ctl_enable_tbl;
1249e455b69dSRui Feng const u32 *sd_pull_ctl_disable_tbl;
1250e455b69dSRui Feng const u32 *ms_pull_ctl_enable_tbl;
1251e455b69dSRui Feng const u32 *ms_pull_ctl_disable_tbl;
1252e455b69dSRui Feng
1253e455b69dSRui Feng const struct pcr_ops *ops;
1254e455b69dSRui Feng enum PDEV_STAT state;
1255e455b69dSRui Feng
1256e455b69dSRui Feng u16 reg_pm_ctrl3;
1257e455b69dSRui Feng
1258e455b69dSRui Feng int num_slots;
1259e455b69dSRui Feng struct rtsx_slot *slots;
1260e455b69dSRui Feng
1261e455b69dSRui Feng u8 dma_error_count;
12625da4e04aSRui Feng u8 ocp_stat;
12635da4e04aSRui Feng u8 ocp_stat2;
1264849a9366SRicky Wu u8 rtd3_en;
1265e455b69dSRui Feng };
1266e455b69dSRui Feng
1267e455b69dSRui Feng #define PID_524A 0x524A
1268e455b69dSRui Feng #define PID_5249 0x5249
1269e455b69dSRui Feng #define PID_5250 0x5250
1270e455b69dSRui Feng #define PID_525A 0x525A
12715da4e04aSRui Feng #define PID_5260 0x5260
1272c0e5f4e7SRui Feng #define PID_5261 0x5261
1273849a9366SRicky Wu #define PID_5228 0x5228
1274e455b69dSRui Feng
1275e455b69dSRui Feng #define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid))
1276e455b69dSRui Feng #define PCI_VID(pcr) ((pcr)->pci->vendor)
1277e455b69dSRui Feng #define PCI_PID(pcr) ((pcr)->pci->device)
1278e455b69dSRui Feng #define is_version(pcr, pid, ver) \
1279e455b69dSRui Feng (CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
12801672617dSRui Feng #define is_version_higher_than(pcr, pid, ver) \
12811672617dSRui Feng (CHK_PCI_PID(pcr, pid) && (pcr)->ic_version > (ver))
1282e455b69dSRui Feng #define pcr_dbg(pcr, fmt, arg...) \
1283e455b69dSRui Feng dev_dbg(&(pcr)->pci->dev, fmt, ##arg)
1284e455b69dSRui Feng
1285e455b69dSRui Feng #define SDR104_PHASE(val) ((val) & 0xFF)
1286e455b69dSRui Feng #define SDR50_PHASE(val) (((val) >> 8) & 0xFF)
1287e455b69dSRui Feng #define DDR50_PHASE(val) (((val) >> 16) & 0xFF)
1288e455b69dSRui Feng #define SDR104_TX_PHASE(pcr) SDR104_PHASE((pcr)->tx_initial_phase)
1289e455b69dSRui Feng #define SDR50_TX_PHASE(pcr) SDR50_PHASE((pcr)->tx_initial_phase)
1290e455b69dSRui Feng #define DDR50_TX_PHASE(pcr) DDR50_PHASE((pcr)->tx_initial_phase)
1291e455b69dSRui Feng #define SDR104_RX_PHASE(pcr) SDR104_PHASE((pcr)->rx_initial_phase)
1292e455b69dSRui Feng #define SDR50_RX_PHASE(pcr) SDR50_PHASE((pcr)->rx_initial_phase)
1293e455b69dSRui Feng #define DDR50_RX_PHASE(pcr) DDR50_PHASE((pcr)->rx_initial_phase)
1294e455b69dSRui Feng #define SET_CLOCK_PHASE(sdr104, sdr50, ddr50) \
1295e455b69dSRui Feng (((ddr50) << 16) | ((sdr50) << 8) | (sdr104))
1296e455b69dSRui Feng
1297e455b69dSRui Feng void rtsx_pci_start_run(struct rtsx_pcr *pcr);
1298e455b69dSRui Feng int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
1299e455b69dSRui Feng int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
1300e455b69dSRui Feng int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
1301e455b69dSRui Feng int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
1302e455b69dSRui Feng void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
1303e455b69dSRui Feng void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
1304e455b69dSRui Feng u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
1305e455b69dSRui Feng void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
1306e455b69dSRui Feng int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
1307e455b69dSRui Feng int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1308e455b69dSRui Feng int num_sg, bool read, int timeout);
1309e455b69dSRui Feng int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1310e455b69dSRui Feng int num_sg, bool read);
1311e455b69dSRui Feng void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1312e455b69dSRui Feng int num_sg, bool read);
1313e455b69dSRui Feng int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1314e455b69dSRui Feng int count, bool read, int timeout);
1315e455b69dSRui Feng int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
1316e455b69dSRui Feng int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
1317e455b69dSRui Feng int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
1318e455b69dSRui Feng int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
1319e455b69dSRui Feng int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
1320e455b69dSRui Feng u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
1321e455b69dSRui Feng int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
1322e455b69dSRui Feng int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
1323e455b69dSRui Feng int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card);
1324e455b69dSRui Feng int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage);
1325e455b69dSRui Feng unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
1326e455b69dSRui Feng void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
1327e455b69dSRui Feng
rtsx_pci_get_cmd_data(struct rtsx_pcr * pcr)1328e455b69dSRui Feng static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
1329e455b69dSRui Feng {
1330e455b69dSRui Feng return (u8 *)(pcr->host_cmds_ptr);
1331e455b69dSRui Feng }
1332e455b69dSRui Feng
rtsx_pci_write_be32(struct rtsx_pcr * pcr,u16 reg,u32 val)1333e455b69dSRui Feng static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
1334e455b69dSRui Feng {
1335e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24);
1336e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16);
1337e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8);
1338e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);
1339e455b69dSRui Feng }
1340e455b69dSRui Feng
rtsx_pci_update_phy(struct rtsx_pcr * pcr,u8 addr,u16 mask,u16 append)1341e455b69dSRui Feng static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,
1342e455b69dSRui Feng u16 mask, u16 append)
1343e455b69dSRui Feng {
1344e455b69dSRui Feng int err;
1345e455b69dSRui Feng u16 val;
1346e455b69dSRui Feng
1347e455b69dSRui Feng err = rtsx_pci_read_phy_register(pcr, addr, &val);
1348e455b69dSRui Feng if (err < 0)
1349e455b69dSRui Feng return err;
1350e455b69dSRui Feng
1351e455b69dSRui Feng return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);
1352e455b69dSRui Feng }
1353e455b69dSRui Feng
1354e455b69dSRui Feng #endif
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