1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #ifndef __FCOE_COMMON__ 10 #define __FCOE_COMMON__ 11 /*********************/ 12 /* FCOE FW CONSTANTS */ 13 /*********************/ 14 15 #define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12 16 #define FCOE_MAX_SIZE_FCP_DATA_SUPER (8600) 17 18 struct fcoe_abts_pkt { 19 __le32 abts_rsp_fc_payload_lo; 20 __le16 abts_rsp_rx_id; 21 u8 abts_rsp_rctl; 22 u8 reserved2; 23 }; 24 25 /* FCoE additional WQE (Sq/XferQ) information */ 26 union fcoe_additional_info_union { 27 __le32 previous_tid; 28 __le32 parent_tid; 29 __le32 burst_length; 30 __le32 seq_rec_updated_offset; 31 }; 32 33 struct fcoe_exp_ro { 34 __le32 data_offset; 35 __le32 reserved; 36 }; 37 38 union fcoe_cleanup_addr_exp_ro_union { 39 struct regpair abts_rsp_fc_payload_hi; 40 struct fcoe_exp_ro exp_ro; 41 }; 42 43 /* FCoE Ramrod Command IDs */ 44 enum fcoe_completion_status { 45 FCOE_COMPLETION_STATUS_SUCCESS, 46 FCOE_COMPLETION_STATUS_FCOE_VER_ERR, 47 FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR, 48 MAX_FCOE_COMPLETION_STATUS 49 }; 50 51 struct fc_addr_nw { 52 u8 addr_lo; 53 u8 addr_mid; 54 u8 addr_hi; 55 }; 56 57 /* FCoE connection offload */ 58 struct fcoe_conn_offload_ramrod_data { 59 struct regpair sq_pbl_addr; 60 struct regpair sq_curr_page_addr; 61 struct regpair sq_next_page_addr; 62 struct regpair xferq_pbl_addr; 63 struct regpair xferq_curr_page_addr; 64 struct regpair xferq_next_page_addr; 65 struct regpair respq_pbl_addr; 66 struct regpair respq_curr_page_addr; 67 struct regpair respq_next_page_addr; 68 __le16 dst_mac_addr_lo; 69 __le16 dst_mac_addr_mid; 70 __le16 dst_mac_addr_hi; 71 __le16 src_mac_addr_lo; 72 __le16 src_mac_addr_mid; 73 __le16 src_mac_addr_hi; 74 __le16 tx_max_fc_pay_len; 75 __le16 e_d_tov_timer_val; 76 __le16 rx_max_fc_pay_len; 77 __le16 vlan_tag; 78 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF 79 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0 80 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1 81 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12 82 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7 83 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13 84 __le16 physical_q0; 85 __le16 rec_rr_tov_timer_val; 86 struct fc_addr_nw s_id; 87 u8 max_conc_seqs_c3; 88 struct fc_addr_nw d_id; 89 u8 flags; 90 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1 91 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0 92 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1 93 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1 94 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1 95 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2 96 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1 97 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3 98 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3 99 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 4 100 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x3 101 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 6 102 __le16 conn_id; 103 u8 def_q_idx; 104 u8 reserved[5]; 105 }; 106 107 /* FCoE terminate connection request */ 108 struct fcoe_conn_terminate_ramrod_data { 109 struct regpair terminate_params_addr; 110 }; 111 112 struct fcoe_fast_sgl_ctx { 113 struct regpair sgl_start_addr; 114 __le32 sgl_byte_offset; 115 __le16 task_reuse_cnt; 116 __le16 init_offset_in_first_sge; 117 }; 118 119 struct fcoe_slow_sgl_ctx { 120 struct regpair base_sgl_addr; 121 __le16 curr_sge_off; 122 __le16 remainder_num_sges; 123 __le16 curr_sgl_index; 124 __le16 reserved; 125 }; 126 127 struct fcoe_sge { 128 struct regpair sge_addr; 129 __le16 size; 130 __le16 reserved0; 131 u8 reserved1[3]; 132 u8 is_valid_sge; 133 }; 134 135 union fcoe_data_desc_ctx { 136 struct fcoe_fast_sgl_ctx fast; 137 struct fcoe_slow_sgl_ctx slow; 138 struct fcoe_sge single_sge; 139 }; 140 141 union fcoe_dix_desc_ctx { 142 struct fcoe_slow_sgl_ctx dix_sgl; 143 struct fcoe_sge cached_dix_sge; 144 }; 145 146 struct fcoe_fcp_cmd_payload { 147 __le32 opaque[8]; 148 }; 149 150 struct fcoe_fcp_rsp_payload { 151 __le32 opaque[6]; 152 }; 153 154 struct fcoe_fcp_xfer_payload { 155 __le32 opaque[3]; 156 }; 157 158 /* FCoE firmware function init */ 159 struct fcoe_init_func_ramrod_data { 160 struct scsi_init_func_params func_params; 161 struct scsi_init_func_queues q_params; 162 __le16 mtu; 163 __le16 sq_num_pages_in_pbl; 164 __le32 reserved; 165 }; 166 167 /* FCoE: Mode of the connection: Target or Initiator or both */ 168 enum fcoe_mode_type { 169 FCOE_INITIATOR_MODE = 0x0, 170 FCOE_TARGET_MODE = 0x1, 171 FCOE_BOTH_OR_NOT_CHOSEN = 0x3, 172 MAX_FCOE_MODE_TYPE 173 }; 174 175 struct fcoe_mstorm_fcoe_task_st_ctx_fp { 176 __le16 flags; 177 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_FP_RSRV0_MASK 0x7FFF 178 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_FP_RSRV0_SHIFT 0 179 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_FP_MP_INCLUDE_FC_HEADER_MASK 0x1 180 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_FP_MP_INCLUDE_FC_HEADER_SHIFT 15 181 __le16 difDataResidue; 182 __le16 parent_id; 183 __le16 single_sge_saved_offset; 184 __le32 data_2_trns_rem; 185 __le32 offset_in_io; 186 union fcoe_dix_desc_ctx dix_desc; 187 union fcoe_data_desc_ctx data_desc; 188 }; 189 190 struct fcoe_mstorm_fcoe_task_st_ctx_non_fp { 191 __le16 flags; 192 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_HOST_INTERFACE_MASK 0x3 193 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_HOST_INTERFACE_SHIFT 0 194 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIF_TO_PEER_MASK 0x1 195 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIF_TO_PEER_SHIFT 2 196 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_VALIDATE_DIX_APP_TAG_MASK 0x1 197 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_VALIDATE_DIX_APP_TAG_SHIFT 3 198 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_INTERVAL_SIZE_LOG_MASK 0xF 199 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_INTERVAL_SIZE_LOG_SHIFT 4 200 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIX_BLOCK_SIZE_MASK 0x3 201 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIX_BLOCK_SIZE_SHIFT 8 202 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RESERVED_MASK 0x1 203 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RESERVED_SHIFT 10 204 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_HAS_FIRST_PACKET_ARRIVED_MASK 0x1 205 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_HAS_FIRST_PACKET_ARRIVED_SHIFT 11 206 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_VALIDATE_DIX_REF_TAG_MASK 0x1 207 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_VALIDATE_DIX_REF_TAG_SHIFT 12 208 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIX_CACHED_SGE_FLG_MASK 0x1 209 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIX_CACHED_SGE_FLG_SHIFT 13 210 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_OFFSET_IN_IO_VALID_MASK 0x1 211 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_OFFSET_IN_IO_VALID_SHIFT 14 212 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIF_SUPPORTED_MASK 0x1 213 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIF_SUPPORTED_SHIFT 15 214 u8 tx_rx_sgl_mode; 215 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_TX_SGL_MODE_MASK 0x7 216 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_TX_SGL_MODE_SHIFT 0 217 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RX_SGL_MODE_MASK 0x7 218 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RX_SGL_MODE_SHIFT 3 219 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RSRV1_MASK 0x3 220 #define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RSRV1_SHIFT 6 221 u8 rsrv2; 222 __le32 num_prm_zero_read; 223 struct regpair rsp_buf_addr; 224 }; 225 226 struct fcoe_rx_stat { 227 struct regpair fcoe_rx_byte_cnt; 228 struct regpair fcoe_rx_data_pkt_cnt; 229 struct regpair fcoe_rx_xfer_pkt_cnt; 230 struct regpair fcoe_rx_other_pkt_cnt; 231 __le32 fcoe_silent_drop_pkt_cmdq_full_cnt; 232 __le32 fcoe_silent_drop_pkt_rq_full_cnt; 233 __le32 fcoe_silent_drop_pkt_crc_error_cnt; 234 __le32 fcoe_silent_drop_pkt_task_invalid_cnt; 235 __le32 fcoe_silent_drop_total_pkt_cnt; 236 __le32 rsrv; 237 }; 238 239 enum fcoe_sgl_mode { 240 FCOE_SLOW_SGL, 241 FCOE_SINGLE_FAST_SGE, 242 FCOE_2_FAST_SGE, 243 FCOE_3_FAST_SGE, 244 FCOE_4_FAST_SGE, 245 FCOE_MUL_FAST_SGES, 246 MAX_FCOE_SGL_MODE 247 }; 248 249 struct fcoe_stat_ramrod_data { 250 struct regpair stat_params_addr; 251 }; 252 253 struct protection_info_ctx { 254 __le16 flags; 255 #define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3 256 #define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0 257 #define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1 258 #define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2 259 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1 260 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3 261 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF 262 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4 263 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1 264 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8 265 #define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F 266 #define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9 267 u8 dix_block_size; 268 u8 dst_size; 269 }; 270 271 union protection_info_union_ctx { 272 struct protection_info_ctx info; 273 __le32 value; 274 }; 275 276 struct fcp_rsp_payload_padded { 277 struct fcoe_fcp_rsp_payload rsp_payload; 278 __le32 reserved[2]; 279 }; 280 281 struct fcp_xfer_payload_padded { 282 struct fcoe_fcp_xfer_payload xfer_payload; 283 __le32 reserved[5]; 284 }; 285 286 struct fcoe_tx_data_params { 287 __le32 data_offset; 288 __le32 offset_in_io; 289 u8 flags; 290 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1 291 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0 292 #define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1 293 #define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1 294 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1 295 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2 296 #define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F 297 #define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3 298 u8 dif_residual; 299 __le16 seq_cnt; 300 __le16 single_sge_saved_offset; 301 __le16 next_dif_offset; 302 __le16 seq_id; 303 __le16 reserved3; 304 }; 305 306 struct fcoe_tx_mid_path_params { 307 __le32 parameter; 308 u8 r_ctl; 309 u8 type; 310 u8 cs_ctl; 311 u8 df_ctl; 312 __le16 rx_id; 313 __le16 ox_id; 314 }; 315 316 struct fcoe_tx_params { 317 struct fcoe_tx_data_params data; 318 struct fcoe_tx_mid_path_params mid_path; 319 }; 320 321 union fcoe_tx_info_union_ctx { 322 struct fcoe_fcp_cmd_payload fcp_cmd_payload; 323 struct fcp_rsp_payload_padded fcp_rsp_payload; 324 struct fcp_xfer_payload_padded fcp_xfer_payload; 325 struct fcoe_tx_params tx_params; 326 }; 327 328 struct ystorm_fcoe_task_st_ctx { 329 u8 task_type; 330 u8 sgl_mode; 331 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x7 332 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0 333 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x1F 334 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 3 335 u8 cached_dix_sge; 336 u8 expect_first_xfer; 337 __le32 num_pbf_zero_write; 338 union protection_info_union_ctx protection_info_union; 339 __le32 data_2_trns_rem; 340 union fcoe_tx_info_union_ctx tx_info_union; 341 union fcoe_dix_desc_ctx dix_desc; 342 union fcoe_data_desc_ctx data_desc; 343 __le16 ox_id; 344 __le16 rx_id; 345 __le32 task_rety_identifier; 346 __le32 reserved1[2]; 347 }; 348 349 struct ystorm_fcoe_task_ag_ctx { 350 u8 byte0; 351 u8 byte1; 352 __le16 word0; 353 u8 flags0; 354 #define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF 355 #define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0 356 #define YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1 357 #define YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4 358 #define YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 359 #define YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 360 #define YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 361 #define YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 362 #define YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 363 #define YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 364 u8 flags1; 365 #define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 366 #define YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0 367 #define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 368 #define YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 369 #define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 370 #define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 371 #define YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 372 #define YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6 373 #define YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 374 #define YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 375 u8 flags2; 376 #define YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1 377 #define YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0 378 #define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 379 #define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 380 #define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 381 #define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 382 #define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 383 #define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 384 #define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 385 #define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 386 #define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 387 #define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 388 #define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 389 #define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6 390 #define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 391 #define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 392 u8 byte2; 393 __le32 reg0; 394 u8 byte3; 395 u8 byte4; 396 __le16 rx_id; 397 __le16 word2; 398 __le16 word3; 399 __le16 word4; 400 __le16 word5; 401 __le32 reg1; 402 __le32 reg2; 403 }; 404 405 struct tstorm_fcoe_task_ag_ctx { 406 u8 reserved; 407 u8 byte1; 408 __le16 icid; 409 u8 flags0; 410 #define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 411 #define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 412 #define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 413 #define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 414 #define TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 415 #define TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 416 #define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1 417 #define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6 418 #define TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1 419 #define TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7 420 u8 flags1; 421 #define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1 422 #define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0 423 #define TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1 424 #define TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1 425 #define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3 426 #define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2 427 #define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3 428 #define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4 429 #define TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 430 #define TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6 431 u8 flags2; 432 #define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3 433 #define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0 434 #define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 435 #define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2 436 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3 437 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4 438 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3 439 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6 440 u8 flags3; 441 #define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3 442 #define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0 443 #define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1 444 #define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2 445 #define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1 446 #define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3 447 #define TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 448 #define TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4 449 #define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 450 #define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5 451 #define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 452 #define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 453 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1 454 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7 455 u8 flags4; 456 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1 457 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0 458 #define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1 459 #define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1 460 #define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 461 #define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2 462 #define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 463 #define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3 464 #define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 465 #define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4 466 #define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 467 #define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5 468 #define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 469 #define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6 470 #define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 471 #define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7 472 u8 cleanup_state; 473 __le16 last_sent_tid; 474 __le32 rec_rr_tov_exp_timeout; 475 u8 byte3; 476 u8 byte4; 477 __le16 word2; 478 __le16 word3; 479 __le16 word4; 480 __le32 data_offset_end_of_seq; 481 __le32 data_offset_next; 482 }; 483 484 struct fcoe_tstorm_fcoe_task_st_ctx_read_write { 485 union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union; 486 __le16 flags; 487 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x7 488 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0 489 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1 490 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 3 491 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1 492 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 4 493 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1 494 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 5 495 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1 496 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 6 497 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1 498 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 7 499 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3 500 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 8 501 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0x3F 502 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 10 503 __le16 seq_cnt; 504 u8 seq_id; 505 u8 ooo_rx_seq_id; 506 __le16 rx_id; 507 struct fcoe_abts_pkt abts_data; 508 __le32 e_d_tov_exp_timeout_val; 509 __le16 ooo_rx_seq_cnt; 510 __le16 reserved1; 511 }; 512 513 struct fcoe_tstorm_fcoe_task_st_ctx_read_only { 514 u8 task_type; 515 u8 dev_type; 516 u8 conf_supported; 517 u8 glbl_q_num; 518 __le32 cid; 519 __le32 fcp_cmd_trns_size; 520 __le32 rsrv; 521 }; 522 523 struct tstorm_fcoe_task_st_ctx { 524 struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write; 525 struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only; 526 }; 527 528 struct mstorm_fcoe_task_ag_ctx { 529 u8 byte0; 530 u8 byte1; 531 __le16 icid; 532 u8 flags0; 533 #define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 534 #define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 535 #define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 536 #define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 537 #define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1 538 #define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5 539 #define MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 540 #define MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 541 #define MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 542 #define MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 543 u8 flags1; 544 #define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 545 #define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0 546 #define MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 547 #define MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 548 #define MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 549 #define MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4 550 #define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 551 #define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 552 #define MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 553 #define MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 554 u8 flags2; 555 #define MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 556 #define MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0 557 #define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 558 #define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 559 #define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 560 #define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 561 #define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 562 #define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 563 #define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 564 #define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 565 #define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 566 #define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 567 #define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1 568 #define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6 569 #define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 570 #define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 571 u8 cleanup_state; 572 __le32 received_bytes; 573 u8 byte3; 574 u8 glbl_q_num; 575 __le16 word1; 576 __le16 tid_to_xfer; 577 __le16 word3; 578 __le16 word4; 579 __le16 word5; 580 __le32 expected_bytes; 581 __le32 reg2; 582 }; 583 584 struct mstorm_fcoe_task_st_ctx { 585 struct fcoe_mstorm_fcoe_task_st_ctx_non_fp non_fp; 586 struct fcoe_mstorm_fcoe_task_st_ctx_fp fp; 587 }; 588 589 struct ustorm_fcoe_task_ag_ctx { 590 u8 reserved; 591 u8 byte1; 592 __le16 icid; 593 u8 flags0; 594 #define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 595 #define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 596 #define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 597 #define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 598 #define USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 599 #define USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 600 #define USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 601 #define USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6 602 u8 flags1; 603 #define USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 604 #define USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0 605 #define USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 606 #define USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2 607 #define USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3 608 #define USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4 609 #define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 610 #define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 611 u8 flags2; 612 #define USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 613 #define USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0 614 #define USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 615 #define USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1 616 #define USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 617 #define USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2 618 #define USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1 619 #define USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3 620 #define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 621 #define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 622 #define USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 623 #define USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5 624 #define USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 625 #define USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6 626 #define USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 627 #define USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7 628 u8 flags3; 629 #define USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 630 #define USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0 631 #define USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 632 #define USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1 633 #define USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 634 #define USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2 635 #define USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 636 #define USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3 637 #define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF 638 #define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 639 __le32 dif_err_intervals; 640 __le32 dif_error_1st_interval; 641 __le32 global_cq_num; 642 __le32 reg3; 643 __le32 reg4; 644 __le32 reg5; 645 }; 646 647 struct fcoe_task_context { 648 struct ystorm_fcoe_task_st_ctx ystorm_st_context; 649 struct tdif_task_context tdif_context; 650 struct ystorm_fcoe_task_ag_ctx ystorm_ag_context; 651 struct tstorm_fcoe_task_ag_ctx tstorm_ag_context; 652 struct timers_context timer_context; 653 struct tstorm_fcoe_task_st_ctx tstorm_st_context; 654 struct regpair tstorm_st_padding[2]; 655 struct mstorm_fcoe_task_ag_ctx mstorm_ag_context; 656 struct mstorm_fcoe_task_st_ctx mstorm_st_context; 657 struct ustorm_fcoe_task_ag_ctx ustorm_ag_context; 658 struct rdif_task_context rdif_context; 659 }; 660 661 struct fcoe_tx_stat { 662 struct regpair fcoe_tx_byte_cnt; 663 struct regpair fcoe_tx_data_pkt_cnt; 664 struct regpair fcoe_tx_xfer_pkt_cnt; 665 struct regpair fcoe_tx_other_pkt_cnt; 666 }; 667 668 struct fcoe_wqe { 669 __le16 task_id; 670 __le16 flags; 671 #define FCOE_WQE_REQ_TYPE_MASK 0xF 672 #define FCOE_WQE_REQ_TYPE_SHIFT 0 673 #define FCOE_WQE_SGL_MODE_MASK 0x7 674 #define FCOE_WQE_SGL_MODE_SHIFT 4 675 #define FCOE_WQE_CONTINUATION_MASK 0x1 676 #define FCOE_WQE_CONTINUATION_SHIFT 7 677 #define FCOE_WQE_INVALIDATE_PTU_MASK 0x1 678 #define FCOE_WQE_INVALIDATE_PTU_SHIFT 8 679 #define FCOE_WQE_SUPER_IO_MASK 0x1 680 #define FCOE_WQE_SUPER_IO_SHIFT 9 681 #define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1 682 #define FCOE_WQE_SEND_AUTO_RSP_SHIFT 10 683 #define FCOE_WQE_RESERVED0_MASK 0x1F 684 #define FCOE_WQE_RESERVED0_SHIFT 11 685 union fcoe_additional_info_union additional_info_union; 686 }; 687 688 struct xfrqe_prot_flags { 689 u8 flags; 690 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF 691 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0 692 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1 693 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4 694 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3 695 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5 696 #define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1 697 #define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7 698 }; 699 700 struct fcoe_db_data { 701 u8 params; 702 #define FCOE_DB_DATA_DEST_MASK 0x3 703 #define FCOE_DB_DATA_DEST_SHIFT 0 704 #define FCOE_DB_DATA_AGG_CMD_MASK 0x3 705 #define FCOE_DB_DATA_AGG_CMD_SHIFT 2 706 #define FCOE_DB_DATA_BYPASS_EN_MASK 0x1 707 #define FCOE_DB_DATA_BYPASS_EN_SHIFT 4 708 #define FCOE_DB_DATA_RESERVED_MASK 0x1 709 #define FCOE_DB_DATA_RESERVED_SHIFT 5 710 #define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3 711 #define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6 712 u8 agg_flags; 713 __le16 sq_prod; 714 }; 715 #endif /* __FCOE_COMMON__ */ 716