1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2016 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _COMMON_HSI_H 34 #define _COMMON_HSI_H 35 36 #include <linux/types.h> 37 #include <asm/byteorder.h> 38 #include <linux/bitops.h> 39 #include <linux/slab.h> 40 41 /* dma_addr_t manip */ 42 #define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff)) 43 #define PTR_HI(x) ((u32)((((uintptr_t)(x)) >> 16) >> 16)) 44 #define DMA_LO_LE(x) cpu_to_le32(lower_32_bits(x)) 45 #define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x)) 46 #define DMA_REGPAIR_LE(x, val) do { \ 47 (x).hi = DMA_HI_LE((val)); \ 48 (x).lo = DMA_LO_LE((val)); \ 49 } while (0) 50 51 #define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo)) 52 #define HILO_64(hi, lo) \ 53 HILO_GEN(le32_to_cpu(hi), le32_to_cpu(lo), u64) 54 #define HILO_64_REGPAIR(regpair) ({ \ 55 typeof(regpair) __regpair = (regpair); \ 56 HILO_64(__regpair.hi, __regpair.lo); }) 57 #define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair)) 58 59 #ifndef __COMMON_HSI__ 60 #define __COMMON_HSI__ 61 62 /********************************/ 63 /* PROTOCOL COMMON FW CONSTANTS */ 64 /********************************/ 65 66 #define X_FINAL_CLEANUP_AGG_INT 1 67 68 #define EVENT_RING_PAGE_SIZE_BYTES 4096 69 70 #define NUM_OF_GLOBAL_QUEUES 128 71 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 72 73 #define ISCSI_CDU_TASK_SEG_TYPE 0 74 #define FCOE_CDU_TASK_SEG_TYPE 0 75 #define RDMA_CDU_TASK_SEG_TYPE 1 76 77 #define FW_ASSERT_GENERAL_ATTN_IDX 32 78 79 80 /* Queue Zone sizes in bytes */ 81 #define TSTORM_QZONE_SIZE 8 82 #define MSTORM_QZONE_SIZE 16 83 #define USTORM_QZONE_SIZE 8 84 #define XSTORM_QZONE_SIZE 8 85 #define YSTORM_QZONE_SIZE 0 86 #define PSTORM_QZONE_SIZE 0 87 88 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 89 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 90 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 91 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 92 93 /********************************/ 94 /* CORE (LIGHT L2) FW CONSTANTS */ 95 /********************************/ 96 97 #define CORE_LL2_MAX_RAMROD_PER_CON 8 98 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 99 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 100 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 101 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 102 103 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 104 105 #define CORE_SPQE_PAGE_SIZE_BYTES 4096 106 107 /* Number of LL2 RAM based queues */ 108 #define MAX_NUM_LL2_RX_RAM_QUEUES 32 109 110 /* Number of LL2 context based queues */ 111 #define MAX_NUM_LL2_RX_CTX_QUEUES 208 112 #define MAX_NUM_LL2_RX_QUEUES \ 113 (MAX_NUM_LL2_RX_RAM_QUEUES + MAX_NUM_LL2_RX_CTX_QUEUES) 114 115 #define MAX_NUM_LL2_TX_STATS_COUNTERS 48 116 117 #define FW_MAJOR_VERSION 8 118 #define FW_MINOR_VERSION 42 119 #define FW_REVISION_VERSION 2 120 #define FW_ENGINEERING_VERSION 0 121 122 /***********************/ 123 /* COMMON HW CONSTANTS */ 124 /***********************/ 125 126 /* PCI functions */ 127 #define MAX_NUM_PORTS_K2 (4) 128 #define MAX_NUM_PORTS_BB (2) 129 #define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) 130 131 #define MAX_NUM_PFS_K2 (16) 132 #define MAX_NUM_PFS_BB (8) 133 #define MAX_NUM_PFS (MAX_NUM_PFS_K2) 134 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 135 136 #define MAX_NUM_VFS_K2 (192) 137 #define MAX_NUM_VFS_BB (120) 138 #define MAX_NUM_VFS (MAX_NUM_VFS_K2) 139 140 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) 141 142 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) 143 #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2) 144 #define MAX_NUM_FUNCTIONS (MAX_FUNCTION_NUMBER_K2) 145 146 #define MAX_NUM_VPORTS_K2 (208) 147 #define MAX_NUM_VPORTS_BB (160) 148 #define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2) 149 150 #define MAX_NUM_L2_QUEUES_K2 (320) 151 #define MAX_NUM_L2_QUEUES_BB (256) 152 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2) 153 154 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ 155 #define NUM_PHYS_TCS_4PORT_K2 (4) 156 #define NUM_OF_PHYS_TCS (8) 157 #define PURE_LB_TC NUM_OF_PHYS_TCS 158 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) 159 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) 160 161 /* CIDs */ 162 #define NUM_OF_CONNECTION_TYPES_E4 (8) 163 #define NUM_OF_LCIDS (320) 164 #define NUM_OF_LTIDS (320) 165 166 /* Global PXP windows (GTT) */ 167 #define NUM_OF_GTT 19 168 #define GTT_DWORD_SIZE_BITS 10 169 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2) 170 #define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS) 171 172 /* Tools Version */ 173 #define TOOLS_VERSION 10 174 175 /*****************/ 176 /* CDU CONSTANTS */ 177 /*****************/ 178 179 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 180 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 181 182 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) 183 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) 184 185 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0) 186 #define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1) 187 #define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE (2) 188 #define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3) 189 #define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4) 190 #define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5) 191 192 /*****************/ 193 /* DQ CONSTANTS */ 194 /*****************/ 195 196 /* DEMS */ 197 #define DQ_DEMS_LEGACY 0 198 #define DQ_DEMS_TOE_MORE_TO_SEND 3 199 #define DQ_DEMS_TOE_LOCAL_ADV_WND 4 200 #define DQ_DEMS_ROCE_CQ_CONS 7 201 202 /* XCM agg val selection (HW) */ 203 #define DQ_XCM_AGG_VAL_SEL_WORD2 0 204 #define DQ_XCM_AGG_VAL_SEL_WORD3 1 205 #define DQ_XCM_AGG_VAL_SEL_WORD4 2 206 #define DQ_XCM_AGG_VAL_SEL_WORD5 3 207 #define DQ_XCM_AGG_VAL_SEL_REG3 4 208 #define DQ_XCM_AGG_VAL_SEL_REG4 5 209 #define DQ_XCM_AGG_VAL_SEL_REG5 6 210 #define DQ_XCM_AGG_VAL_SEL_REG6 7 211 212 /* XCM agg val selection (FW) */ 213 #define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 214 #define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 215 #define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 216 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2 217 #define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 218 #define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 219 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 220 #define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 221 #define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 222 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5 223 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 224 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 225 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 226 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 227 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 228 #define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 229 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 230 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4 231 #define DQ_XCM_ROCE_ACK_EDPM_DORQ_SEQ_CMD DQ_XCM_AGG_VAL_SEL_WORD5 232 233 /* UCM agg val selection (HW) */ 234 #define DQ_UCM_AGG_VAL_SEL_WORD0 0 235 #define DQ_UCM_AGG_VAL_SEL_WORD1 1 236 #define DQ_UCM_AGG_VAL_SEL_WORD2 2 237 #define DQ_UCM_AGG_VAL_SEL_WORD3 3 238 #define DQ_UCM_AGG_VAL_SEL_REG0 4 239 #define DQ_UCM_AGG_VAL_SEL_REG1 5 240 #define DQ_UCM_AGG_VAL_SEL_REG2 6 241 #define DQ_UCM_AGG_VAL_SEL_REG3 7 242 243 /* UCM agg val selection (FW) */ 244 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 245 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 246 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 247 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 248 249 /* TCM agg val selection (HW) */ 250 #define DQ_TCM_AGG_VAL_SEL_WORD0 0 251 #define DQ_TCM_AGG_VAL_SEL_WORD1 1 252 #define DQ_TCM_AGG_VAL_SEL_WORD2 2 253 #define DQ_TCM_AGG_VAL_SEL_WORD3 3 254 #define DQ_TCM_AGG_VAL_SEL_REG1 4 255 #define DQ_TCM_AGG_VAL_SEL_REG2 5 256 #define DQ_TCM_AGG_VAL_SEL_REG6 6 257 #define DQ_TCM_AGG_VAL_SEL_REG9 7 258 259 /* TCM agg val selection (FW) */ 260 #define DQ_TCM_L2B_BD_PROD_CMD \ 261 DQ_TCM_AGG_VAL_SEL_WORD1 262 #define DQ_TCM_ROCE_RQ_PROD_CMD \ 263 DQ_TCM_AGG_VAL_SEL_WORD0 264 265 /* XCM agg counter flag selection (HW) */ 266 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 267 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 268 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 269 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 270 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 271 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 272 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 273 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 274 275 /* XCM agg counter flag selection (FW) */ 276 #define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) 277 #define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 278 #define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 279 #define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) 280 #define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 281 #define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 282 #define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) 283 #define DQ_XCM_FCOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 284 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 285 #define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 286 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) 287 #define DQ_XCM_TOE_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 288 #define DQ_XCM_TOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 289 290 /* UCM agg counter flag selection (HW) */ 291 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0 292 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1 293 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2 294 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3 295 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4 296 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5 297 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 298 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 299 300 /* UCM agg counter flag selection (FW) */ 301 #define DQ_UCM_ETH_PMD_TX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4) 302 #define DQ_UCM_ETH_PMD_RX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5) 303 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4) 304 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5) 305 #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF3) 306 #define DQ_UCM_TOE_SLOW_PATH_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4) 307 #define DQ_UCM_TOE_DQ_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5) 308 309 /* TCM agg counter flag selection (HW) */ 310 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0 311 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1 312 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2 313 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3 314 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4 315 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5 316 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6 317 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7 318 /* TCM agg counter flag selection (FW) */ 319 #define DQ_TCM_FCOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 320 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF2) 321 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) 322 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 323 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) 324 #define DQ_TCM_TOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 325 #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) 326 #define DQ_TCM_IWARP_POST_RQ_CF_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 327 328 /* PWM address mapping */ 329 #define DQ_PWM_OFFSET_DPM_BASE 0x0 330 #define DQ_PWM_OFFSET_DPM_END 0x27 331 #define DQ_PWM_OFFSET_XCM16_BASE 0x40 332 #define DQ_PWM_OFFSET_XCM32_BASE 0x44 333 #define DQ_PWM_OFFSET_UCM16_BASE 0x48 334 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C 335 #define DQ_PWM_OFFSET_UCM16_4 0x50 336 #define DQ_PWM_OFFSET_TCM16_BASE 0x58 337 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C 338 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68 339 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69 340 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B 341 342 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) 343 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) 344 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4) 345 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2) 346 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) 347 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) 348 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) 349 350 /* DQ_DEMS_AGG_VAL_BASE */ 351 #define DQ_PWM_OFFSET_TCM_LL2_PROD_UPDATE \ 352 (DQ_PWM_OFFSET_TCM32_BASE + DQ_TCM_AGG_VAL_SEL_REG9 - 4) 353 354 #define DQ_REGION_SHIFT (12) 355 356 /* DPM */ 357 #define DQ_DPM_WQE_BUFF_SIZE (320) 358 359 /* Conn type ranges */ 360 #define DQ_CONN_TYPE_RANGE_SHIFT (4) 361 362 /*****************/ 363 /* QM CONSTANTS */ 364 /*****************/ 365 366 /* Number of TX queues in the QM */ 367 #define MAX_QM_TX_QUEUES_K2 512 368 #define MAX_QM_TX_QUEUES_BB 448 369 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 370 371 /* Number of Other queues in the QM */ 372 #define MAX_QM_OTHER_QUEUES_BB 64 373 #define MAX_QM_OTHER_QUEUES_K2 128 374 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 375 376 /* Number of queues in a PF queue group */ 377 #define QM_PF_QUEUE_GROUP_SIZE 8 378 379 /* The size of a single queue element in bytes */ 380 #define QM_PQ_ELEMENT_SIZE 4 381 382 /* Base number of Tx PQs in the CM PQ representation. 383 * Should be used when storing PQ IDs in CM PQ registers and context. 384 */ 385 #define CM_TX_PQ_BASE 0x200 386 387 /* Number of global Vport/QCN rate limiters */ 388 #define MAX_QM_GLOBAL_RLS 256 389 390 /* QM registers data */ 391 #define QM_LINE_CRD_REG_WIDTH 16 392 #define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1)) 393 #define QM_BYTE_CRD_REG_WIDTH 24 394 #define QM_BYTE_CRD_REG_SIGN_BIT BIT((QM_BYTE_CRD_REG_WIDTH - 1)) 395 #define QM_WFQ_CRD_REG_WIDTH 32 396 #define QM_WFQ_CRD_REG_SIGN_BIT BIT((QM_WFQ_CRD_REG_WIDTH - 1)) 397 #define QM_RL_CRD_REG_WIDTH 32 398 #define QM_RL_CRD_REG_SIGN_BIT BIT((QM_RL_CRD_REG_WIDTH - 1)) 399 400 /*****************/ 401 /* CAU CONSTANTS */ 402 /*****************/ 403 404 #define CAU_FSM_ETH_RX 0 405 #define CAU_FSM_ETH_TX 1 406 407 /* Number of Protocol Indices per Status Block */ 408 #define PIS_PER_SB_E4 12 409 #define MAX_PIS_PER_SB PIS_PER_SB 410 411 #define CAU_HC_STOPPED_STATE 3 412 #define CAU_HC_DISABLE_STATE 4 413 #define CAU_HC_ENABLE_STATE 0 414 415 /*****************/ 416 /* IGU CONSTANTS */ 417 /*****************/ 418 419 #define MAX_SB_PER_PATH_K2 (368) 420 #define MAX_SB_PER_PATH_BB (288) 421 #define MAX_TOT_SB_PER_PATH \ 422 MAX_SB_PER_PATH_K2 423 424 #define MAX_SB_PER_PF_MIMD 129 425 #define MAX_SB_PER_PF_SIMD 64 426 #define MAX_SB_PER_VF 64 427 428 /* Memory addresses on the BAR for the IGU Sub Block */ 429 #define IGU_MEM_BASE 0x0000 430 431 #define IGU_MEM_MSIX_BASE 0x0000 432 #define IGU_MEM_MSIX_UPPER 0x0101 433 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 434 435 #define IGU_MEM_PBA_MSIX_BASE 0x0200 436 #define IGU_MEM_PBA_MSIX_UPPER 0x0202 437 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 438 439 #define IGU_CMD_INT_ACK_BASE 0x0400 440 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 441 442 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 443 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 444 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 445 446 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 447 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 448 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 449 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 450 451 #define IGU_CMD_PROD_UPD_BASE 0x0600 452 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 453 454 /*****************/ 455 /* PXP CONSTANTS */ 456 /*****************/ 457 458 /* Bars for Blocks */ 459 #define PXP_BAR_GRC 0 460 #define PXP_BAR_TSDM 0 461 #define PXP_BAR_USDM 0 462 #define PXP_BAR_XSDM 0 463 #define PXP_BAR_MSDM 0 464 #define PXP_BAR_YSDM 0 465 #define PXP_BAR_PSDM 0 466 #define PXP_BAR_IGU 0 467 #define PXP_BAR_DQ 1 468 469 /* PTT and GTT */ 470 #define PXP_PER_PF_ENTRY_SIZE 8 471 #define PXP_NUM_GLOBAL_WINDOWS 243 472 #define PXP_GLOBAL_ENTRY_SIZE 4 473 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 474 #define PXP_PF_WINDOW_ADMIN_START 0 475 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 476 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \ 477 PXP_PF_WINDOW_ADMIN_LENGTH - 1) 478 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 479 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \ 480 PXP_PER_PF_ENTRY_SIZE) 481 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \ 482 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) 483 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 484 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \ 485 PXP_GLOBAL_ENTRY_SIZE) 486 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \ 487 (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \ 488 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) 489 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 490 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 491 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 492 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc 493 494 #define PXP_NUM_PF_WINDOWS 12 495 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 496 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS 497 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 498 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \ 499 (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \ 500 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) 501 #define PXP_EXTERNAL_BAR_PF_WINDOW_END \ 502 (PXP_EXTERNAL_BAR_PF_WINDOW_START + \ 503 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) 504 505 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \ 506 (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) 507 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS 508 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 509 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \ 510 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \ 511 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) 512 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \ 513 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \ 514 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 515 516 /* PF BAR */ 517 #define PXP_BAR0_START_GRC 0x0000 518 #define PXP_BAR0_GRC_LENGTH 0x1C00000 519 #define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \ 520 PXP_BAR0_GRC_LENGTH - 1) 521 522 #define PXP_BAR0_START_IGU 0x1C00000 523 #define PXP_BAR0_IGU_LENGTH 0x10000 524 #define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \ 525 PXP_BAR0_IGU_LENGTH - 1) 526 527 #define PXP_BAR0_START_TSDM 0x1C80000 528 #define PXP_BAR0_SDM_LENGTH 0x40000 529 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 530 #define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \ 531 PXP_BAR0_SDM_LENGTH - 1) 532 533 #define PXP_BAR0_START_MSDM 0x1D00000 534 #define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \ 535 PXP_BAR0_SDM_LENGTH - 1) 536 537 #define PXP_BAR0_START_USDM 0x1D80000 538 #define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \ 539 PXP_BAR0_SDM_LENGTH - 1) 540 541 #define PXP_BAR0_START_XSDM 0x1E00000 542 #define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \ 543 PXP_BAR0_SDM_LENGTH - 1) 544 545 #define PXP_BAR0_START_YSDM 0x1E80000 546 #define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \ 547 PXP_BAR0_SDM_LENGTH - 1) 548 549 #define PXP_BAR0_START_PSDM 0x1F00000 550 #define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \ 551 PXP_BAR0_SDM_LENGTH - 1) 552 553 #define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1) 554 555 /* VF BAR */ 556 #define PXP_VF_BAR0 0 557 558 #define PXP_VF_BAR0_START_IGU 0 559 #define PXP_VF_BAR0_IGU_LENGTH 0x3000 560 #define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \ 561 PXP_VF_BAR0_IGU_LENGTH - 1) 562 563 #define PXP_VF_BAR0_START_DQ 0x3000 564 #define PXP_VF_BAR0_DQ_LENGTH 0x200 565 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 566 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + \ 567 PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 568 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \ 569 + 4) 570 #define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + \ 571 PXP_VF_BAR0_DQ_LENGTH - 1) 572 573 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 574 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 575 #define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B + \ 576 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 577 578 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 579 #define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B + \ 580 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 581 582 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 583 #define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B + \ 584 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 585 586 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 587 #define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B + \ 588 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 589 590 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 591 #define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B + \ 592 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 593 594 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 595 #define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B + \ 596 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 597 598 #define PXP_VF_BAR0_START_GRC 0x3E00 599 #define PXP_VF_BAR0_GRC_LENGTH 0x200 600 #define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \ 601 PXP_VF_BAR0_GRC_LENGTH - 1) 602 603 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000 604 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000 605 606 #define PXP_VF_BAR0_START_IGU2 0x10000 607 #define PXP_VF_BAR0_IGU2_LENGTH 0xD000 608 #define PXP_VF_BAR0_END_IGU2 (PXP_VF_BAR0_START_IGU2 + \ 609 PXP_VF_BAR0_IGU2_LENGTH - 1) 610 611 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32 612 613 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 614 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 615 616 /* ILT Records */ 617 #define PXP_NUM_ILT_RECORDS_BB 7600 618 #define PXP_NUM_ILT_RECORDS_K2 11000 619 #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2) 620 621 /* Host Interface */ 622 #define PXP_QUEUES_ZONE_MAX_NUM 320 623 624 /*****************/ 625 /* PRM CONSTANTS */ 626 /*****************/ 627 #define PRM_DMA_PAD_BYTES_NUM 2 628 629 /*****************/ 630 /* SDMs CONSTANTS */ 631 /*****************/ 632 633 #define SDM_OP_GEN_TRIG_NONE 0 634 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1 635 #define SDM_OP_GEN_TRIG_AGG_INT 2 636 #define SDM_OP_GEN_TRIG_LOADER 4 637 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 638 #define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9 639 640 /********************/ 641 /* Completion types */ 642 /********************/ 643 644 #define SDM_COMP_TYPE_NONE 0 645 #define SDM_COMP_TYPE_WAKE_THREAD 1 646 #define SDM_COMP_TYPE_AGG_INT 2 647 #define SDM_COMP_TYPE_CM 3 648 #define SDM_COMP_TYPE_LOADER 4 649 #define SDM_COMP_TYPE_PXP 5 650 #define SDM_COMP_TYPE_INDICATE_ERROR 6 651 #define SDM_COMP_TYPE_RELEASE_THREAD 7 652 #define SDM_COMP_TYPE_RAM 8 653 #define SDM_COMP_TYPE_INC_ORDER_CNT 9 654 655 /*****************/ 656 /* PBF CONSTANTS */ 657 /*****************/ 658 659 /* Number of PBF command queue lines. Each line is 32B. */ 660 #define PBF_MAX_CMD_LINES 3328 661 662 /* Number of BTB blocks. Each block is 256B. */ 663 #define BTB_MAX_BLOCKS_BB 1440 664 #define BTB_MAX_BLOCKS_K2 1840 665 /*****************/ 666 /* PRS CONSTANTS */ 667 /*****************/ 668 669 #define PRS_GFT_CAM_LINES_NO_MATCH 31 670 671 /* Interrupt coalescing TimeSet */ 672 struct coalescing_timeset { 673 u8 value; 674 #define COALESCING_TIMESET_TIMESET_MASK 0x7F 675 #define COALESCING_TIMESET_TIMESET_SHIFT 0 676 #define COALESCING_TIMESET_VALID_MASK 0x1 677 #define COALESCING_TIMESET_VALID_SHIFT 7 678 }; 679 680 struct common_queue_zone { 681 __le16 ring_drv_data_consumer; 682 __le16 reserved; 683 }; 684 685 /* ETH Rx producers data */ 686 struct eth_rx_prod_data { 687 __le16 bd_prod; 688 __le16 cqe_prod; 689 }; 690 691 struct tcp_ulp_connect_done_params { 692 __le16 mss; 693 u8 snd_wnd_scale; 694 u8 flags; 695 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK 0x1 696 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT 0 697 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK 0x7F 698 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT 1 699 }; 700 701 struct iscsi_connect_done_results { 702 __le16 icid; 703 __le16 conn_id; 704 struct tcp_ulp_connect_done_params params; 705 }; 706 707 struct iscsi_eqe_data { 708 __le16 icid; 709 __le16 conn_id; 710 __le16 reserved; 711 u8 error_code; 712 u8 error_pdu_opcode_reserved; 713 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F 714 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0 715 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1 716 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6 717 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1 718 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 719 }; 720 721 /* Multi function mode */ 722 enum mf_mode { 723 ERROR_MODE /* Unsupported mode */, 724 MF_OVLAN, 725 MF_NPAR, 726 MAX_MF_MODE 727 }; 728 729 /* Per-protocol connection types */ 730 enum protocol_type { 731 PROTOCOLID_ISCSI, 732 PROTOCOLID_FCOE, 733 PROTOCOLID_ROCE, 734 PROTOCOLID_CORE, 735 PROTOCOLID_ETH, 736 PROTOCOLID_IWARP, 737 PROTOCOLID_RESERVED0, 738 PROTOCOLID_PREROCE, 739 PROTOCOLID_COMMON, 740 PROTOCOLID_RESERVED1, 741 PROTOCOLID_RDMA, 742 PROTOCOLID_SCSI, 743 MAX_PROTOCOL_TYPE 744 }; 745 746 struct regpair { 747 __le32 lo; 748 __le32 hi; 749 }; 750 751 /* RoCE Destroy Event Data */ 752 struct rdma_eqe_destroy_qp { 753 __le32 cid; 754 u8 reserved[4]; 755 }; 756 757 /* RDMA Event Data Union */ 758 union rdma_eqe_data { 759 struct regpair async_handle; 760 struct rdma_eqe_destroy_qp rdma_destroy_qp_data; 761 }; 762 763 struct tstorm_queue_zone { 764 __le32 reserved[2]; 765 }; 766 767 /* Ustorm Queue Zone */ 768 struct ustorm_eth_queue_zone { 769 struct coalescing_timeset int_coalescing_timeset; 770 u8 reserved[3]; 771 }; 772 773 struct ustorm_queue_zone { 774 struct ustorm_eth_queue_zone eth; 775 struct common_queue_zone common; 776 }; 777 778 /* Status block structure */ 779 struct cau_pi_entry { 780 __le32 prod; 781 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF 782 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 783 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F 784 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 785 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 786 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 787 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF 788 #define CAU_PI_ENTRY_RESERVED_SHIFT 24 789 }; 790 791 /* Status block structure */ 792 struct cau_sb_entry { 793 __le32 data; 794 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF 795 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 796 #define CAU_SB_ENTRY_STATE0_MASK 0xF 797 #define CAU_SB_ENTRY_STATE0_SHIFT 24 798 #define CAU_SB_ENTRY_STATE1_MASK 0xF 799 #define CAU_SB_ENTRY_STATE1_SHIFT 28 800 __le32 params; 801 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F 802 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 803 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F 804 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 805 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 806 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 807 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 808 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 809 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 810 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 811 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 812 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 813 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 814 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 815 #define CAU_SB_ENTRY_TPH_MASK 0x1 816 #define CAU_SB_ENTRY_TPH_SHIFT 31 817 }; 818 819 /* Igu cleanup bit values to distinguish between clean or producer consumer 820 * update. 821 */ 822 enum command_type_bit { 823 IGU_COMMAND_TYPE_NOP = 0, 824 IGU_COMMAND_TYPE_SET = 1, 825 MAX_COMMAND_TYPE_BIT 826 }; 827 828 /* Core doorbell data */ 829 struct core_db_data { 830 u8 params; 831 #define CORE_DB_DATA_DEST_MASK 0x3 832 #define CORE_DB_DATA_DEST_SHIFT 0 833 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 834 #define CORE_DB_DATA_AGG_CMD_SHIFT 2 835 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 836 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 837 #define CORE_DB_DATA_RESERVED_MASK 0x1 838 #define CORE_DB_DATA_RESERVED_SHIFT 5 839 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 840 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 841 u8 agg_flags; 842 __le16 spq_prod; 843 }; 844 845 /* Enum of doorbell aggregative command selection */ 846 enum db_agg_cmd_sel { 847 DB_AGG_CMD_NOP, 848 DB_AGG_CMD_SET, 849 DB_AGG_CMD_ADD, 850 DB_AGG_CMD_MAX, 851 MAX_DB_AGG_CMD_SEL 852 }; 853 854 /* Enum of doorbell destination */ 855 enum db_dest { 856 DB_DEST_XCM, 857 DB_DEST_UCM, 858 DB_DEST_TCM, 859 DB_NUM_DESTINATIONS, 860 MAX_DB_DEST 861 }; 862 863 /* Enum of doorbell DPM types */ 864 enum db_dpm_type { 865 DPM_LEGACY, 866 DPM_RDMA, 867 DPM_L2_INLINE, 868 DPM_L2_BD, 869 MAX_DB_DPM_TYPE 870 }; 871 872 /* Structure for doorbell data, in L2 DPM mode, for 1st db in a DPM burst */ 873 struct db_l2_dpm_data { 874 __le16 icid; 875 __le16 bd_prod; 876 __le32 params; 877 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F 878 #define DB_L2_DPM_DATA_SIZE_SHIFT 0 879 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 880 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 881 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF 882 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 883 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF 884 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 885 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 886 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 887 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 888 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 889 #define DB_L2_DPM_DATA_TGFS_SRC_EN_MASK 0x1 890 #define DB_L2_DPM_DATA_TGFS_SRC_EN_SHIFT 31 891 }; 892 893 /* Structure for SGE in a DPM doorbell of type DPM_L2_BD */ 894 struct db_l2_dpm_sge { 895 struct regpair addr; 896 __le16 nbytes; 897 __le16 bitfields; 898 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF 899 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 900 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 901 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 902 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 903 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 904 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF 905 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 906 __le32 reserved2; 907 }; 908 909 /* Structure for doorbell address, in legacy mode */ 910 struct db_legacy_addr { 911 __le32 addr; 912 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 913 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 914 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 915 #define DB_LEGACY_ADDR_DEMS_SHIFT 2 916 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF 917 #define DB_LEGACY_ADDR_ICID_SHIFT 5 918 }; 919 920 /* Structure for doorbell address, in PWM mode */ 921 struct db_pwm_addr { 922 __le32 addr; 923 #define DB_PWM_ADDR_RESERVED0_MASK 0x7 924 #define DB_PWM_ADDR_RESERVED0_SHIFT 0 925 #define DB_PWM_ADDR_OFFSET_MASK 0x7F 926 #define DB_PWM_ADDR_OFFSET_SHIFT 3 927 #define DB_PWM_ADDR_WID_MASK 0x3 928 #define DB_PWM_ADDR_WID_SHIFT 10 929 #define DB_PWM_ADDR_DPI_MASK 0xFFFF 930 #define DB_PWM_ADDR_DPI_SHIFT 12 931 #define DB_PWM_ADDR_RESERVED1_MASK 0xF 932 #define DB_PWM_ADDR_RESERVED1_SHIFT 28 933 }; 934 935 /* Parameters to RDMA firmware, passed in EDPM doorbell */ 936 struct db_rdma_dpm_params { 937 __le32 params; 938 #define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F 939 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0 940 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 941 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6 942 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF 943 #define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8 944 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF 945 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16 946 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1 947 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27 948 #define DB_RDMA_DPM_PARAMS_ACK_REQUEST_MASK 0x1 949 #define DB_RDMA_DPM_PARAMS_ACK_REQUEST_SHIFT 28 950 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 951 #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29 952 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 953 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 30 954 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 955 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31 956 }; 957 958 /* Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a 959 * DPM burst. 960 */ 961 struct db_rdma_dpm_data { 962 __le16 icid; 963 __le16 prod_val; 964 struct db_rdma_dpm_params params; 965 }; 966 967 /* Igu interrupt command */ 968 enum igu_int_cmd { 969 IGU_INT_ENABLE = 0, 970 IGU_INT_DISABLE = 1, 971 IGU_INT_NOP = 2, 972 IGU_INT_NOP2 = 3, 973 MAX_IGU_INT_CMD 974 }; 975 976 /* IGU producer or consumer update command */ 977 struct igu_prod_cons_update { 978 __le32 sb_id_and_flags; 979 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 980 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 981 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 982 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 983 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 984 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 985 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 986 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 987 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 988 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 989 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 990 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 991 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 992 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 993 __le32 reserved1; 994 }; 995 996 /* Igu segments access for default status block only */ 997 enum igu_seg_access { 998 IGU_SEG_ACCESS_REG = 0, 999 IGU_SEG_ACCESS_ATTN = 1, 1000 MAX_IGU_SEG_ACCESS 1001 }; 1002 1003 /* Enumeration for L3 type field of parsing_and_err_flags. 1004 * L3Type: 0 - unknown (not ip), 1 - Ipv4, 2 - Ipv6 1005 * (This field can be filled according to the last-ethertype) 1006 */ 1007 enum l3_type { 1008 e_l3_type_unknown, 1009 e_l3_type_ipv4, 1010 e_l3_type_ipv6, 1011 MAX_L3_TYPE 1012 }; 1013 1014 /* Enumeration for l4Protocol field of parsing_and_err_flags. 1015 * L4-protocol: 0 - none, 1 - TCP, 2 - UDP. 1016 * If the packet is IPv4 fragment, and its not the first fragment, the 1017 * protocol-type should be set to none. 1018 */ 1019 enum l4_protocol { 1020 e_l4_protocol_none, 1021 e_l4_protocol_tcp, 1022 e_l4_protocol_udp, 1023 MAX_L4_PROTOCOL 1024 }; 1025 1026 /* Parsing and error flags field */ 1027 struct parsing_and_err_flags { 1028 __le16 flags; 1029 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 1030 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 1031 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 1032 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 1033 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 1034 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 1035 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 1036 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 1037 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 1038 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 1039 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 1040 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 1041 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 1042 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 1043 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 1044 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 1045 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 1046 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 1047 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 1048 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 1049 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 1050 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 1051 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 1052 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 1053 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 1054 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 1055 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 1056 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 1057 }; 1058 1059 /* Parsing error flags bitmap */ 1060 struct parsing_err_flags { 1061 __le16 flags; 1062 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1 1063 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0 1064 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1 1065 #define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT 1 1066 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1 1067 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT 2 1068 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1 1069 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT 3 1070 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1 1071 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT 4 1072 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1 1073 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT 5 1074 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1 1075 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT 6 1076 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1 1077 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT 7 1078 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1 1079 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT 8 1080 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1 1081 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT 9 1082 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1 1083 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT 10 1084 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1 1085 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT 11 1086 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1 1087 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT 12 1088 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1 1089 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT 13 1090 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1 1091 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT 14 1092 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1 1093 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15 1094 }; 1095 1096 /* Pb context */ 1097 struct pb_context { 1098 __le32 crc[4]; 1099 }; 1100 1101 /* Concrete Function ID */ 1102 struct pxp_concrete_fid { 1103 __le16 fid; 1104 #define PXP_CONCRETE_FID_PFID_MASK 0xF 1105 #define PXP_CONCRETE_FID_PFID_SHIFT 0 1106 #define PXP_CONCRETE_FID_PORT_MASK 0x3 1107 #define PXP_CONCRETE_FID_PORT_SHIFT 4 1108 #define PXP_CONCRETE_FID_PATH_MASK 0x1 1109 #define PXP_CONCRETE_FID_PATH_SHIFT 6 1110 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 1111 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 1112 #define PXP_CONCRETE_FID_VFID_MASK 0xFF 1113 #define PXP_CONCRETE_FID_VFID_SHIFT 8 1114 }; 1115 1116 /* Concrete Function ID */ 1117 struct pxp_pretend_concrete_fid { 1118 __le16 fid; 1119 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF 1120 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 1121 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 1122 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 1123 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 1124 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 1125 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 1126 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 1127 }; 1128 1129 /* Function ID */ 1130 union pxp_pretend_fid { 1131 struct pxp_pretend_concrete_fid concrete_fid; 1132 __le16 opaque_fid; 1133 }; 1134 1135 /* Pxp Pretend Command Register */ 1136 struct pxp_pretend_cmd { 1137 union pxp_pretend_fid fid; 1138 __le16 control; 1139 #define PXP_PRETEND_CMD_PATH_MASK 0x1 1140 #define PXP_PRETEND_CMD_PATH_SHIFT 0 1141 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 1142 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 1143 #define PXP_PRETEND_CMD_PORT_MASK 0x3 1144 #define PXP_PRETEND_CMD_PORT_SHIFT 2 1145 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 1146 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 1147 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 1148 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 1149 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 1150 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 1151 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 1152 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 1153 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 1154 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 1155 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 1156 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 1157 }; 1158 1159 /* PTT Record in PXP Admin Window */ 1160 struct pxp_ptt_entry { 1161 __le32 offset; 1162 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 1163 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 1164 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 1165 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 1166 struct pxp_pretend_cmd pretend; 1167 }; 1168 1169 /* VF Zone A Permission Register */ 1170 struct pxp_vf_zone_a_permission { 1171 __le32 control; 1172 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF 1173 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 1174 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 1175 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 1176 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F 1177 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 1178 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF 1179 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 1180 }; 1181 1182 /* Rdif context */ 1183 struct rdif_task_context { 1184 __le32 initial_ref_tag; 1185 __le16 app_tag_value; 1186 __le16 app_tag_mask; 1187 u8 flags0; 1188 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1 1189 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0 1190 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1 1191 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1 1192 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 1193 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2 1194 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1 1195 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3 1196 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 1197 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4 1198 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1199 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1200 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 1201 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 7 1202 u8 partial_dif_data[7]; 1203 __le16 partial_crc_value; 1204 __le16 partial_checksum_value; 1205 __le32 offset_in_io; 1206 __le16 flags1; 1207 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1 1208 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0 1209 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1 1210 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1 1211 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1 1212 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2 1213 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1 1214 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3 1215 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1 1216 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4 1217 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1 1218 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5 1219 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 1220 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6 1221 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 1222 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9 1223 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 1224 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11 1225 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 1226 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 1227 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 1228 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13 1229 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 1230 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14 1231 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 1232 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15 1233 __le16 state; 1234 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF 1235 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0 1236 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF 1237 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4 1238 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1 1239 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT 8 1240 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1 1241 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT 9 1242 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF 1243 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 10 1244 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 1245 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 1246 __le32 reserved2; 1247 }; 1248 1249 /* Status block structure */ 1250 struct status_block_e4 { 1251 __le16 pi_array[PIS_PER_SB_E4]; 1252 __le32 sb_num; 1253 #define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF 1254 #define STATUS_BLOCK_E4_SB_NUM_SHIFT 0 1255 #define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F 1256 #define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9 1257 #define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF 1258 #define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16 1259 __le32 prod_index; 1260 #define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF 1261 #define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0 1262 #define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF 1263 #define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24 1264 }; 1265 1266 /* Tdif context */ 1267 struct tdif_task_context { 1268 __le32 initial_ref_tag; 1269 __le16 app_tag_value; 1270 __le16 app_tag_mask; 1271 __le16 partial_crc_value_b; 1272 __le16 partial_checksum_value_b; 1273 __le16 stateB; 1274 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF 1275 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0 1276 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF 1277 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4 1278 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1 1279 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT 8 1280 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1 1281 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT 9 1282 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 1283 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 1284 u8 reserved1; 1285 u8 flags0; 1286 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1 1287 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0 1288 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1 1289 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1 1290 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 1291 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2 1292 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1 1293 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3 1294 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 1295 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4 1296 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1297 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1298 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 1299 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 1300 __le32 flags1; 1301 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1 1302 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0 1303 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1 1304 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1 1305 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1 1306 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2 1307 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1 1308 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3 1309 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1 1310 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4 1311 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1 1312 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5 1313 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 1314 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6 1315 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 1316 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9 1317 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 1318 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11 1319 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 1320 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 1321 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 1322 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13 1323 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF 1324 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT 14 1325 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF 1326 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18 1327 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1 1328 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT 22 1329 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1 1330 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT 23 1331 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF 1332 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 24 1333 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 1334 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 28 1335 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 1336 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 29 1337 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 1338 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 30 1339 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 1340 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 1341 __le32 offset_in_io_b; 1342 __le16 partial_crc_value_a; 1343 __le16 partial_checksum_value_a; 1344 __le32 offset_in_io_a; 1345 u8 partial_dif_data_a[8]; 1346 u8 partial_dif_data_b[8]; 1347 }; 1348 1349 /* Timers context */ 1350 struct timers_context { 1351 __le32 logical_client_0; 1352 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF 1353 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0 1354 #define TIMERS_CONTEXT_RESERVED0_MASK 0x1 1355 #define TIMERS_CONTEXT_RESERVED0_SHIFT 27 1356 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 1357 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28 1358 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 1359 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29 1360 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3 1361 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30 1362 __le32 logical_client_1; 1363 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF 1364 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0 1365 #define TIMERS_CONTEXT_RESERVED2_MASK 0x1 1366 #define TIMERS_CONTEXT_RESERVED2_SHIFT 27 1367 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 1368 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28 1369 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 1370 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29 1371 #define TIMERS_CONTEXT_RESERVED3_MASK 0x3 1372 #define TIMERS_CONTEXT_RESERVED3_SHIFT 30 1373 __le32 logical_client_2; 1374 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF 1375 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0 1376 #define TIMERS_CONTEXT_RESERVED4_MASK 0x1 1377 #define TIMERS_CONTEXT_RESERVED4_SHIFT 27 1378 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 1379 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28 1380 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 1381 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29 1382 #define TIMERS_CONTEXT_RESERVED5_MASK 0x3 1383 #define TIMERS_CONTEXT_RESERVED5_SHIFT 30 1384 __le32 host_expiration_fields; 1385 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF 1386 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0 1387 #define TIMERS_CONTEXT_RESERVED6_MASK 0x1 1388 #define TIMERS_CONTEXT_RESERVED6_SHIFT 27 1389 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 1390 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28 1391 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7 1392 #define TIMERS_CONTEXT_RESERVED7_SHIFT 29 1393 }; 1394 1395 /* Enum for next_protocol field of tunnel_parsing_flags / tunnelTypeDesc */ 1396 enum tunnel_next_protocol { 1397 e_unknown = 0, 1398 e_l2 = 1, 1399 e_ipv4 = 2, 1400 e_ipv6 = 3, 1401 MAX_TUNNEL_NEXT_PROTOCOL 1402 }; 1403 1404 #endif /* __COMMON_HSI__ */ 1405 #endif 1406