1*2025cf9eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 21141d9d0SIrina Tirdea /* 31141d9d0SIrina Tirdea * Intel Atom platform clocks for BayTrail and CherryTrail SoC. 41141d9d0SIrina Tirdea * 51141d9d0SIrina Tirdea * Copyright (C) 2016, Intel Corporation 61141d9d0SIrina Tirdea * Author: Irina Tirdea <irina.tirdea@intel.com> 71141d9d0SIrina Tirdea */ 81141d9d0SIrina Tirdea 91141d9d0SIrina Tirdea #ifndef __PLATFORM_DATA_X86_CLK_PMC_ATOM_H 101141d9d0SIrina Tirdea #define __PLATFORM_DATA_X86_CLK_PMC_ATOM_H 111141d9d0SIrina Tirdea 121141d9d0SIrina Tirdea /** 131141d9d0SIrina Tirdea * struct pmc_clk - PMC platform clock configuration 141141d9d0SIrina Tirdea * 151141d9d0SIrina Tirdea * @name: identified, typically pmc_plt_clk_<x>, x=[0..5] 161141d9d0SIrina Tirdea * @freq: in Hz, 19.2MHz and 25MHz (Baytrail only) supported 171141d9d0SIrina Tirdea * @parent_name: one of 'xtal' or 'osc' 181141d9d0SIrina Tirdea */ 191141d9d0SIrina Tirdea struct pmc_clk { 201141d9d0SIrina Tirdea const char *name; 211141d9d0SIrina Tirdea unsigned long freq; 221141d9d0SIrina Tirdea const char *parent_name; 231141d9d0SIrina Tirdea }; 241141d9d0SIrina Tirdea 251141d9d0SIrina Tirdea /** 261141d9d0SIrina Tirdea * struct pmc_clk_data - common PMC clock configuration 271141d9d0SIrina Tirdea * 281141d9d0SIrina Tirdea * @base: PMC clock register base offset 291141d9d0SIrina Tirdea * @clks: pointer to set of registered clocks, typically 0..5 307c2e0713SDavid Müller * @critical: flag to indicate if firmware enabled pmc_plt_clks 317c2e0713SDavid Müller * should be marked as critial or not 321141d9d0SIrina Tirdea */ 331141d9d0SIrina Tirdea struct pmc_clk_data { 341141d9d0SIrina Tirdea void __iomem *base; 351141d9d0SIrina Tirdea const struct pmc_clk *clks; 367c2e0713SDavid Müller bool critical; 371141d9d0SIrina Tirdea }; 381141d9d0SIrina Tirdea 391141d9d0SIrina Tirdea #endif /* __PLATFORM_DATA_X86_CLK_PMC_ATOM_H */ 40