1293b2da1SArnd Bergmann /* 2293b2da1SArnd Bergmann * arch/arm/mach-pxa/include/mach/pxafb.h 3293b2da1SArnd Bergmann * 4293b2da1SArnd Bergmann * Support for the xscale frame buffer. 5293b2da1SArnd Bergmann * 6293b2da1SArnd Bergmann * Author: Jean-Frederic Clere 7293b2da1SArnd Bergmann * Created: Sep 22, 2003 8293b2da1SArnd Bergmann * Copyright: jfclere@sinix.net 9293b2da1SArnd Bergmann * 10293b2da1SArnd Bergmann * This program is free software; you can redistribute it and/or modify 11293b2da1SArnd Bergmann * it under the terms of the GNU General Public License version 2 as 12293b2da1SArnd Bergmann * published by the Free Software Foundation. 13293b2da1SArnd Bergmann */ 14293b2da1SArnd Bergmann 15293b2da1SArnd Bergmann #include <linux/fb.h> 16293b2da1SArnd Bergmann #include <mach/regs-lcd.h> 17293b2da1SArnd Bergmann 18293b2da1SArnd Bergmann /* 19293b2da1SArnd Bergmann * Supported LCD connections 20293b2da1SArnd Bergmann * 21293b2da1SArnd Bergmann * bits 0 - 3: for LCD panel type: 22293b2da1SArnd Bergmann * 23293b2da1SArnd Bergmann * STN - for passive matrix 24293b2da1SArnd Bergmann * DSTN - for dual scan passive matrix 25293b2da1SArnd Bergmann * TFT - for active matrix 26293b2da1SArnd Bergmann * 27293b2da1SArnd Bergmann * bits 4 - 9 : for bus width 28293b2da1SArnd Bergmann * bits 10-17 : for AC Bias Pin Frequency 29293b2da1SArnd Bergmann * bit 18 : for output enable polarity 30293b2da1SArnd Bergmann * bit 19 : for pixel clock edge 31293b2da1SArnd Bergmann * bit 20 : for output pixel format when base is RGBT16 32293b2da1SArnd Bergmann */ 33293b2da1SArnd Bergmann #define LCD_CONN_TYPE(_x) ((_x) & 0x0f) 34293b2da1SArnd Bergmann #define LCD_CONN_WIDTH(_x) (((_x) >> 4) & 0x1f) 35293b2da1SArnd Bergmann 36293b2da1SArnd Bergmann #define LCD_TYPE_MASK 0xf 37293b2da1SArnd Bergmann #define LCD_TYPE_UNKNOWN 0 38293b2da1SArnd Bergmann #define LCD_TYPE_MONO_STN 1 39293b2da1SArnd Bergmann #define LCD_TYPE_MONO_DSTN 2 40293b2da1SArnd Bergmann #define LCD_TYPE_COLOR_STN 3 41293b2da1SArnd Bergmann #define LCD_TYPE_COLOR_DSTN 4 42293b2da1SArnd Bergmann #define LCD_TYPE_COLOR_TFT 5 43293b2da1SArnd Bergmann #define LCD_TYPE_SMART_PANEL 6 44293b2da1SArnd Bergmann #define LCD_TYPE_MAX 7 45293b2da1SArnd Bergmann 46293b2da1SArnd Bergmann #define LCD_MONO_STN_4BPP ((4 << 4) | LCD_TYPE_MONO_STN) 47293b2da1SArnd Bergmann #define LCD_MONO_STN_8BPP ((8 << 4) | LCD_TYPE_MONO_STN) 48293b2da1SArnd Bergmann #define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN) 49293b2da1SArnd Bergmann #define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN) 50293b2da1SArnd Bergmann #define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN) 51293b2da1SArnd Bergmann #define LCD_COLOR_TFT_8BPP ((8 << 4) | LCD_TYPE_COLOR_TFT) 52293b2da1SArnd Bergmann #define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT) 53293b2da1SArnd Bergmann #define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT) 54293b2da1SArnd Bergmann #define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL) 55293b2da1SArnd Bergmann #define LCD_SMART_PANEL_16BPP ((16 << 4) | LCD_TYPE_SMART_PANEL) 56293b2da1SArnd Bergmann #define LCD_SMART_PANEL_18BPP ((18 << 4) | LCD_TYPE_SMART_PANEL) 57293b2da1SArnd Bergmann 58293b2da1SArnd Bergmann #define LCD_AC_BIAS_FREQ(x) (((x) & 0xff) << 10) 59293b2da1SArnd Bergmann #define LCD_BIAS_ACTIVE_HIGH (0 << 18) 60293b2da1SArnd Bergmann #define LCD_BIAS_ACTIVE_LOW (1 << 18) 61293b2da1SArnd Bergmann #define LCD_PCLK_EDGE_RISE (0 << 19) 62293b2da1SArnd Bergmann #define LCD_PCLK_EDGE_FALL (1 << 19) 63293b2da1SArnd Bergmann #define LCD_ALTERNATE_MAPPING (1 << 20) 64293b2da1SArnd Bergmann 65293b2da1SArnd Bergmann /* 66293b2da1SArnd Bergmann * This structure describes the machine which we are running on. 67293b2da1SArnd Bergmann * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine 68293b2da1SArnd Bergmann * of linux/drivers/video/pxafb.c 69293b2da1SArnd Bergmann */ 70293b2da1SArnd Bergmann struct pxafb_mode_info { 71293b2da1SArnd Bergmann u_long pixclock; 72293b2da1SArnd Bergmann 73293b2da1SArnd Bergmann u_short xres; 74293b2da1SArnd Bergmann u_short yres; 75293b2da1SArnd Bergmann 76293b2da1SArnd Bergmann u_char bpp; 77293b2da1SArnd Bergmann u_int cmap_greyscale:1, 78293b2da1SArnd Bergmann depth:8, 79293b2da1SArnd Bergmann transparency:1, 80293b2da1SArnd Bergmann unused:22; 81293b2da1SArnd Bergmann 82293b2da1SArnd Bergmann /* Parallel Mode Timing */ 83293b2da1SArnd Bergmann u_char hsync_len; 84293b2da1SArnd Bergmann u_char left_margin; 85293b2da1SArnd Bergmann u_char right_margin; 86293b2da1SArnd Bergmann 87293b2da1SArnd Bergmann u_char vsync_len; 88293b2da1SArnd Bergmann u_char upper_margin; 89293b2da1SArnd Bergmann u_char lower_margin; 90293b2da1SArnd Bergmann u_char sync; 91293b2da1SArnd Bergmann 92293b2da1SArnd Bergmann /* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details 93293b2da1SArnd Bergmann * Note: 94293b2da1SArnd Bergmann * 1. all parameters in nanosecond (ns) 95293b2da1SArnd Bergmann * 2. a0cs{rd,wr}_set_hld are controlled by the same register bits 96293b2da1SArnd Bergmann * in pxa27x and pxa3xx, initialize them to the same value or 97293b2da1SArnd Bergmann * the larger one will be used 98293b2da1SArnd Bergmann * 3. same to {rd,wr}_pulse_width 99293b2da1SArnd Bergmann * 100293b2da1SArnd Bergmann * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity 101293b2da1SArnd Bergmann * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0 102293b2da1SArnd Bergmann * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD 103293b2da1SArnd Bergmann */ 104293b2da1SArnd Bergmann unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */ 105293b2da1SArnd Bergmann unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */ 106293b2da1SArnd Bergmann unsigned wr_pulse_width; /* L_PCLK_WR pulse width */ 107293b2da1SArnd Bergmann unsigned rd_pulse_width; /* L_FCLK_RD pulse width */ 108293b2da1SArnd Bergmann unsigned cmd_inh_time; /* Command Inhibit time between two writes */ 109293b2da1SArnd Bergmann unsigned op_hold_time; /* Output Hold time from L_FCLK_RD negation */ 110293b2da1SArnd Bergmann }; 111293b2da1SArnd Bergmann 112293b2da1SArnd Bergmann struct pxafb_mach_info { 113293b2da1SArnd Bergmann struct pxafb_mode_info *modes; 114293b2da1SArnd Bergmann unsigned int num_modes; 115293b2da1SArnd Bergmann 116293b2da1SArnd Bergmann unsigned int lcd_conn; 117293b2da1SArnd Bergmann unsigned long video_mem_size; 118293b2da1SArnd Bergmann 119293b2da1SArnd Bergmann u_int fixed_modes:1, 120293b2da1SArnd Bergmann cmap_inverse:1, 121293b2da1SArnd Bergmann cmap_static:1, 122293b2da1SArnd Bergmann acceleration_enabled:1, 123293b2da1SArnd Bergmann unused:28; 124293b2da1SArnd Bergmann 125293b2da1SArnd Bergmann /* The following should be defined in LCCR0 126293b2da1SArnd Bergmann * LCCR0_Act or LCCR0_Pas Active or Passive 127293b2da1SArnd Bergmann * LCCR0_Sngl or LCCR0_Dual Single/Dual panel 128293b2da1SArnd Bergmann * LCCR0_Mono or LCCR0_Color Mono/Color 129293b2da1SArnd Bergmann * LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode) 130293b2da1SArnd Bergmann * LCCR0_DMADel(Tcpu) (optional) DMA request delay 131293b2da1SArnd Bergmann * 132293b2da1SArnd Bergmann * The following should not be defined in LCCR0: 133293b2da1SArnd Bergmann * LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM 134293b2da1SArnd Bergmann * LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB 135293b2da1SArnd Bergmann */ 136293b2da1SArnd Bergmann u_int lccr0; 137293b2da1SArnd Bergmann /* The following should be defined in LCCR3 138293b2da1SArnd Bergmann * LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity 139293b2da1SArnd Bergmann * LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type 140293b2da1SArnd Bergmann * LCCR3_Acb(X) AB Bias pin frequency 141293b2da1SArnd Bergmann * LCCR3_DPC (optional) Double Pixel Clock mode (untested) 142293b2da1SArnd Bergmann * 143293b2da1SArnd Bergmann * The following should not be defined in LCCR3 144293b2da1SArnd Bergmann * LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp 145293b2da1SArnd Bergmann */ 146293b2da1SArnd Bergmann u_int lccr3; 147293b2da1SArnd Bergmann /* The following should be defined in LCCR4 148293b2da1SArnd Bergmann * LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2 149293b2da1SArnd Bergmann * 150293b2da1SArnd Bergmann * All other bits in LCCR4 should be left alone. 151293b2da1SArnd Bergmann */ 152293b2da1SArnd Bergmann u_int lccr4; 153293b2da1SArnd Bergmann void (*pxafb_backlight_power)(int); 154293b2da1SArnd Bergmann void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); 155293b2da1SArnd Bergmann void (*smart_update)(struct fb_info *); 156293b2da1SArnd Bergmann }; 157293b2da1SArnd Bergmann 158293b2da1SArnd Bergmann void pxa_set_fb_info(struct device *, struct pxafb_mach_info *); 159293b2da1SArnd Bergmann unsigned long pxafb_get_hsync_time(struct device *dev); 160293b2da1SArnd Bergmann 161293b2da1SArnd Bergmann #ifdef CONFIG_FB_PXA_SMARTPANEL 162293b2da1SArnd Bergmann extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int); 163293b2da1SArnd Bergmann extern int pxafb_smart_flush(struct fb_info *info); 164293b2da1SArnd Bergmann #else 165293b2da1SArnd Bergmann static inline int pxafb_smart_queue(struct fb_info *info, 166293b2da1SArnd Bergmann uint16_t *cmds, int n) 167293b2da1SArnd Bergmann { 168293b2da1SArnd Bergmann return 0; 169293b2da1SArnd Bergmann } 170293b2da1SArnd Bergmann 171293b2da1SArnd Bergmann static inline int pxafb_smart_flush(struct fb_info *info) 172293b2da1SArnd Bergmann { 173293b2da1SArnd Bergmann return 0; 174293b2da1SArnd Bergmann } 175293b2da1SArnd Bergmann #endif 176