1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef __TI_SYSC_DATA_H__ 4 #define __TI_SYSC_DATA_H__ 5 6 enum ti_sysc_module_type { 7 TI_SYSC_OMAP2, 8 TI_SYSC_OMAP2_TIMER, 9 TI_SYSC_OMAP3_SHAM, 10 TI_SYSC_OMAP3_AES, 11 TI_SYSC_OMAP4, 12 TI_SYSC_OMAP4_TIMER, 13 TI_SYSC_OMAP4_SIMPLE, 14 TI_SYSC_OMAP34XX_SR, 15 TI_SYSC_OMAP36XX_SR, 16 TI_SYSC_OMAP4_SR, 17 TI_SYSC_OMAP4_MCASP, 18 TI_SYSC_OMAP4_USB_HOST_FS, 19 TI_SYSC_DRA7_MCAN, 20 TI_SYSC_PRUSS, 21 }; 22 23 struct ti_sysc_cookie { 24 void *data; 25 void *clkdm; 26 }; 27 28 /** 29 * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets 30 * @midle_shift: Offset of the midle bit 31 * @clkact_shift: Offset of the clockactivity bit 32 * @sidle_shift: Offset of the sidle bit 33 * @enwkup_shift: Offset of the enawakeup bit 34 * @srst_shift: Offset of the softreset bit 35 * @autoidle_shift: Offset of the autoidle bit 36 * @dmadisable_shift: Offset of the dmadisable bit 37 * @emufree_shift; Offset of the emufree bit 38 * 39 * Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a 40 * feature is not available. 41 */ 42 struct sysc_regbits { 43 s8 midle_shift; 44 s8 clkact_shift; 45 s8 sidle_shift; 46 s8 enwkup_shift; 47 s8 srst_shift; 48 s8 autoidle_shift; 49 s8 dmadisable_shift; 50 s8 emufree_shift; 51 }; 52 53 #define SYSC_QUIRK_GPMC_DEBUG BIT(26) 54 #define SYSC_MODULE_QUIRK_ENA_RESETDONE BIT(25) 55 #define SYSC_MODULE_QUIRK_PRUSS BIT(24) 56 #define SYSC_MODULE_QUIRK_DSS_RESET BIT(23) 57 #define SYSC_MODULE_QUIRK_RTC_UNLOCK BIT(22) 58 #define SYSC_QUIRK_CLKDM_NOAUTO BIT(21) 59 #define SYSC_QUIRK_FORCE_MSTANDBY BIT(20) 60 #define SYSC_MODULE_QUIRK_AESS BIT(19) 61 #define SYSC_MODULE_QUIRK_SGX BIT(18) 62 #define SYSC_MODULE_QUIRK_HDQ1W BIT(17) 63 #define SYSC_MODULE_QUIRK_I2C BIT(16) 64 #define SYSC_MODULE_QUIRK_WDT BIT(15) 65 #define SYSS_QUIRK_RESETDONE_INVERTED BIT(14) 66 #define SYSC_QUIRK_SWSUP_MSTANDBY BIT(13) 67 #define SYSC_QUIRK_SWSUP_SIDLE_ACT BIT(12) 68 #define SYSC_QUIRK_SWSUP_SIDLE BIT(11) 69 #define SYSC_QUIRK_EXT_OPT_CLOCK BIT(10) 70 #define SYSC_QUIRK_LEGACY_IDLE BIT(9) 71 #define SYSC_QUIRK_RESET_STATUS BIT(8) 72 #define SYSC_QUIRK_NO_IDLE BIT(7) 73 #define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6) 74 #define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5) 75 #define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4) 76 #define SYSC_QUIRK_OPT_CLKS_IN_RESET BIT(3) 77 #define SYSC_QUIRK_16BIT BIT(2) 78 #define SYSC_QUIRK_UNCACHED BIT(1) 79 #define SYSC_QUIRK_USE_CLOCKACT BIT(0) 80 81 #define SYSC_NR_IDLEMODES 4 82 83 /** 84 * struct sysc_capabilities - capabilities for an interconnect target module 85 * @type: sysc type identifier for the module 86 * @sysc_mask: bitmask of supported SYSCONFIG register bits 87 * @regbits: bitmask of SYSCONFIG register bits 88 * @mod_quirks: bitmask of module specific quirks 89 */ 90 struct sysc_capabilities { 91 const enum ti_sysc_module_type type; 92 const u32 sysc_mask; 93 const struct sysc_regbits *regbits; 94 const u32 mod_quirks; 95 }; 96 97 /** 98 * struct sysc_config - configuration for an interconnect target module 99 * @sysc_val: configured value for sysc register 100 * @syss_mask: configured mask value for SYSSTATUS register 101 * @midlemodes: bitmask of supported master idle modes 102 * @sidlemodes: bitmask of supported slave idle modes 103 * @srst_udelay: optional delay needed after OCP soft reset 104 * @quirks: bitmask of enabled quirks 105 */ 106 struct sysc_config { 107 u32 sysc_val; 108 u32 syss_mask; 109 u8 midlemodes; 110 u8 sidlemodes; 111 u8 srst_udelay; 112 u32 quirks; 113 }; 114 115 enum sysc_registers { 116 SYSC_REVISION, 117 SYSC_SYSCONFIG, 118 SYSC_SYSSTATUS, 119 SYSC_MAX_REGS, 120 }; 121 122 /** 123 * struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module 124 * @name: legacy "ti,hwmods" module name 125 * @module_pa: physical address of the interconnect target module 126 * @module_size: size of the interconnect target module 127 * @offsets: array of register offsets as listed in enum sysc_registers 128 * @nr_offsets: number of registers 129 * @cap: interconnect target module capabilities 130 * @cfg: interconnect target module configuration 131 * 132 * This data is enough to allocate a new struct omap_hwmod_class_sysconfig 133 * based on device tree data parsed by ti-sysc driver. 134 */ 135 struct ti_sysc_module_data { 136 const char *name; 137 u64 module_pa; 138 u32 module_size; 139 int *offsets; 140 int nr_offsets; 141 const struct sysc_capabilities *cap; 142 struct sysc_config *cfg; 143 }; 144 145 struct device; 146 struct clk; 147 148 struct ti_sysc_platform_data { 149 struct of_dev_auxdata *auxdata; 150 bool (*soc_type_gp)(void); 151 int (*init_clockdomain)(struct device *dev, struct clk *fck, 152 struct clk *ick, struct ti_sysc_cookie *cookie); 153 void (*clkdm_deny_idle)(struct device *dev, 154 const struct ti_sysc_cookie *cookie); 155 void (*clkdm_allow_idle)(struct device *dev, 156 const struct ti_sysc_cookie *cookie); 157 int (*init_module)(struct device *dev, 158 const struct ti_sysc_module_data *data, 159 struct ti_sysc_cookie *cookie); 160 int (*enable_module)(struct device *dev, 161 const struct ti_sysc_cookie *cookie); 162 int (*idle_module)(struct device *dev, 163 const struct ti_sysc_cookie *cookie); 164 int (*shutdown_module)(struct device *dev, 165 const struct ti_sysc_cookie *cookie); 166 }; 167 168 #endif /* __TI_SYSC_DATA_H__ */ 169