1 /* 2 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 3 * Steven J. Hill <sjhill@realitydiluted.com> 4 * Thomas Gleixner <tglx@linutronix.de> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Info: 11 * Contains standard defines and IDs for NAND flash devices 12 * 13 * Changelog: 14 * See git changelog. 15 */ 16 #ifndef __LINUX_MTD_RAWNAND_H 17 #define __LINUX_MTD_RAWNAND_H 18 19 #include <linux/wait.h> 20 #include <linux/spinlock.h> 21 #include <linux/mtd/mtd.h> 22 #include <linux/mtd/flashchip.h> 23 #include <linux/mtd/bbm.h> 24 #include <linux/mtd/jedec.h> 25 #include <linux/mtd/onfi.h> 26 #include <linux/of.h> 27 #include <linux/types.h> 28 29 struct nand_chip; 30 31 /* The maximum number of NAND chips in an array */ 32 #define NAND_MAX_CHIPS 8 33 34 /* 35 * Constants for hardware specific CLE/ALE/NCE function 36 * 37 * These are bits which can be or'ed to set/clear multiple 38 * bits in one go. 39 */ 40 /* Select the chip by setting nCE to low */ 41 #define NAND_NCE 0x01 42 /* Select the command latch by setting CLE to high */ 43 #define NAND_CLE 0x02 44 /* Select the address latch by setting ALE to high */ 45 #define NAND_ALE 0x04 46 47 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 48 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 49 #define NAND_CTRL_CHANGE 0x80 50 51 /* 52 * Standard NAND flash commands 53 */ 54 #define NAND_CMD_READ0 0 55 #define NAND_CMD_READ1 1 56 #define NAND_CMD_RNDOUT 5 57 #define NAND_CMD_PAGEPROG 0x10 58 #define NAND_CMD_READOOB 0x50 59 #define NAND_CMD_ERASE1 0x60 60 #define NAND_CMD_STATUS 0x70 61 #define NAND_CMD_SEQIN 0x80 62 #define NAND_CMD_RNDIN 0x85 63 #define NAND_CMD_READID 0x90 64 #define NAND_CMD_ERASE2 0xd0 65 #define NAND_CMD_PARAM 0xec 66 #define NAND_CMD_GET_FEATURES 0xee 67 #define NAND_CMD_SET_FEATURES 0xef 68 #define NAND_CMD_RESET 0xff 69 70 /* Extended commands for large page devices */ 71 #define NAND_CMD_READSTART 0x30 72 #define NAND_CMD_RNDOUTSTART 0xE0 73 #define NAND_CMD_CACHEDPROG 0x15 74 75 #define NAND_CMD_NONE -1 76 77 /* Status bits */ 78 #define NAND_STATUS_FAIL 0x01 79 #define NAND_STATUS_FAIL_N1 0x02 80 #define NAND_STATUS_TRUE_READY 0x20 81 #define NAND_STATUS_READY 0x40 82 #define NAND_STATUS_WP 0x80 83 84 #define NAND_DATA_IFACE_CHECK_ONLY -1 85 86 /* 87 * Constants for ECC_MODES 88 */ 89 typedef enum { 90 NAND_ECC_NONE, 91 NAND_ECC_SOFT, 92 NAND_ECC_HW, 93 NAND_ECC_HW_SYNDROME, 94 NAND_ECC_HW_OOB_FIRST, 95 NAND_ECC_ON_DIE, 96 } nand_ecc_modes_t; 97 98 enum nand_ecc_algo { 99 NAND_ECC_UNKNOWN, 100 NAND_ECC_HAMMING, 101 NAND_ECC_BCH, 102 NAND_ECC_RS, 103 }; 104 105 /* 106 * Constants for Hardware ECC 107 */ 108 /* Reset Hardware ECC for read */ 109 #define NAND_ECC_READ 0 110 /* Reset Hardware ECC for write */ 111 #define NAND_ECC_WRITE 1 112 /* Enable Hardware ECC before syndrome is read back from flash */ 113 #define NAND_ECC_READSYN 2 114 115 /* 116 * Enable generic NAND 'page erased' check. This check is only done when 117 * ecc.correct() returns -EBADMSG. 118 * Set this flag if your implementation does not fix bitflips in erased 119 * pages and you want to rely on the default implementation. 120 */ 121 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 122 #define NAND_ECC_MAXIMIZE BIT(1) 123 124 /* 125 * When using software implementation of Hamming, we can specify which byte 126 * ordering should be used. 127 */ 128 #define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2) 129 130 /* 131 * Option constants for bizarre disfunctionality and real 132 * features. 133 */ 134 /* Buswidth is 16 bit */ 135 #define NAND_BUSWIDTH_16 0x00000002 136 /* Chip has cache program function */ 137 #define NAND_CACHEPRG 0x00000008 138 /* 139 * Chip requires ready check on read (for auto-incremented sequential read). 140 * True only for small page devices; large page devices do not support 141 * autoincrement. 142 */ 143 #define NAND_NEED_READRDY 0x00000100 144 145 /* Chip does not allow subpage writes */ 146 #define NAND_NO_SUBPAGE_WRITE 0x00000200 147 148 /* Device is one of 'new' xD cards that expose fake nand command set */ 149 #define NAND_BROKEN_XD 0x00000400 150 151 /* Device behaves just like nand, but is readonly */ 152 #define NAND_ROM 0x00000800 153 154 /* Device supports subpage reads */ 155 #define NAND_SUBPAGE_READ 0x00001000 156 157 /* 158 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 159 * patterns. 160 */ 161 #define NAND_NEED_SCRAMBLING 0x00002000 162 163 /* Device needs 3rd row address cycle */ 164 #define NAND_ROW_ADDR_3 0x00004000 165 166 /* Options valid for Samsung large page devices */ 167 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 168 169 /* Macros to identify the above */ 170 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 171 172 /* Non chip related options */ 173 /* This option skips the bbt scan during initialization. */ 174 #define NAND_SKIP_BBTSCAN 0x00010000 175 /* Chip may not exist, so silence any errors in scan */ 176 #define NAND_SCAN_SILENT_NODEV 0x00040000 177 /* 178 * Autodetect nand buswidth with readid/onfi. 179 * This suppose the driver will configure the hardware in 8 bits mode 180 * when calling nand_scan_ident, and update its configuration 181 * before calling nand_scan_tail. 182 */ 183 #define NAND_BUSWIDTH_AUTO 0x00080000 184 /* 185 * This option could be defined by controller drivers to protect against 186 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 187 */ 188 #define NAND_USE_BOUNCE_BUFFER 0x00100000 189 190 /* 191 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying 192 * on the default ->cmdfunc() implementation, you may want to let the core 193 * handle the tCCS delay which is required when a column change (RNDIN or 194 * RNDOUT) is requested. 195 * If your controller already takes care of this delay, you don't need to set 196 * this flag. 197 */ 198 #define NAND_WAIT_TCCS 0x00200000 199 200 /* 201 * Whether the NAND chip is a boot medium. Drivers might use this information 202 * to select ECC algorithms supported by the boot ROM or similar restrictions. 203 */ 204 #define NAND_IS_BOOT_MEDIUM 0x00400000 205 206 /* Options set by nand scan */ 207 /* Nand scan has allocated controller struct */ 208 #define NAND_CONTROLLER_ALLOC 0x80000000 209 210 /* Cell info constants */ 211 #define NAND_CI_CHIPNR_MSK 0x03 212 #define NAND_CI_CELLTYPE_MSK 0x0C 213 #define NAND_CI_CELLTYPE_SHIFT 2 214 215 /** 216 * struct nand_parameters - NAND generic parameters from the parameter page 217 * @model: Model name 218 * @supports_set_get_features: The NAND chip supports setting/getting features 219 * @set_feature_list: Bitmap of features that can be set 220 * @get_feature_list: Bitmap of features that can be get 221 * @onfi: ONFI specific parameters 222 */ 223 struct nand_parameters { 224 /* Generic parameters */ 225 const char *model; 226 bool supports_set_get_features; 227 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER); 228 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER); 229 230 /* ONFI parameters */ 231 struct onfi_params *onfi; 232 }; 233 234 /* The maximum expected count of bytes in the NAND ID sequence */ 235 #define NAND_MAX_ID_LEN 8 236 237 /** 238 * struct nand_id - NAND id structure 239 * @data: buffer containing the id bytes. 240 * @len: ID length. 241 */ 242 struct nand_id { 243 u8 data[NAND_MAX_ID_LEN]; 244 int len; 245 }; 246 247 /** 248 * struct nand_controller_ops - Controller operations 249 * 250 * @attach_chip: this method is called after the NAND detection phase after 251 * flash ID and MTD fields such as erase size, page size and OOB 252 * size have been set up. ECC requirements are available if 253 * provided by the NAND chip or device tree. Typically used to 254 * choose the appropriate ECC configuration and allocate 255 * associated resources. 256 * This hook is optional. 257 * @detach_chip: free all resources allocated/claimed in 258 * nand_controller_ops->attach_chip(). 259 * This hook is optional. 260 */ 261 struct nand_controller_ops { 262 int (*attach_chip)(struct nand_chip *chip); 263 void (*detach_chip)(struct nand_chip *chip); 264 }; 265 266 /** 267 * struct nand_controller - Structure used to describe a NAND controller 268 * 269 * @lock: protection lock 270 * @active: the mtd device which holds the controller currently 271 * @wq: wait queue to sleep on if a NAND operation is in 272 * progress used instead of the per chip wait queue 273 * when a hw controller is available. 274 * @ops: NAND controller operations. 275 */ 276 struct nand_controller { 277 spinlock_t lock; 278 struct nand_chip *active; 279 wait_queue_head_t wq; 280 const struct nand_controller_ops *ops; 281 }; 282 283 static inline void nand_controller_init(struct nand_controller *nfc) 284 { 285 nfc->active = NULL; 286 spin_lock_init(&nfc->lock); 287 init_waitqueue_head(&nfc->wq); 288 } 289 290 /** 291 * struct nand_ecc_step_info - ECC step information of ECC engine 292 * @stepsize: data bytes per ECC step 293 * @strengths: array of supported strengths 294 * @nstrengths: number of supported strengths 295 */ 296 struct nand_ecc_step_info { 297 int stepsize; 298 const int *strengths; 299 int nstrengths; 300 }; 301 302 /** 303 * struct nand_ecc_caps - capability of ECC engine 304 * @stepinfos: array of ECC step information 305 * @nstepinfos: number of ECC step information 306 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 307 */ 308 struct nand_ecc_caps { 309 const struct nand_ecc_step_info *stepinfos; 310 int nstepinfos; 311 int (*calc_ecc_bytes)(int step_size, int strength); 312 }; 313 314 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ 315 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ 316 static const int __name##_strengths[] = { __VA_ARGS__ }; \ 317 static const struct nand_ecc_step_info __name##_stepinfo = { \ 318 .stepsize = __step, \ 319 .strengths = __name##_strengths, \ 320 .nstrengths = ARRAY_SIZE(__name##_strengths), \ 321 }; \ 322 static const struct nand_ecc_caps __name = { \ 323 .stepinfos = &__name##_stepinfo, \ 324 .nstepinfos = 1, \ 325 .calc_ecc_bytes = __calc, \ 326 } 327 328 /** 329 * struct nand_ecc_ctrl - Control structure for ECC 330 * @mode: ECC mode 331 * @algo: ECC algorithm 332 * @steps: number of ECC steps per page 333 * @size: data bytes per ECC step 334 * @bytes: ECC bytes per step 335 * @strength: max number of correctible bits per ECC step 336 * @total: total number of ECC bytes per page 337 * @prepad: padding information for syndrome based ECC generators 338 * @postpad: padding information for syndrome based ECC generators 339 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 340 * @priv: pointer to private ECC control data 341 * @calc_buf: buffer for calculated ECC, size is oobsize. 342 * @code_buf: buffer for ECC read from flash, size is oobsize. 343 * @hwctl: function to control hardware ECC generator. Must only 344 * be provided if an hardware ECC is available 345 * @calculate: function for ECC calculation or readback from ECC hardware 346 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 347 * Should return a positive number representing the number of 348 * corrected bitflips, -EBADMSG if the number of bitflips exceed 349 * ECC strength, or any other error code if the error is not 350 * directly related to correction. 351 * If -EBADMSG is returned the input buffers should be left 352 * untouched. 353 * @read_page_raw: function to read a raw page without ECC. This function 354 * should hide the specific layout used by the ECC 355 * controller and always return contiguous in-band and 356 * out-of-band data even if they're not stored 357 * contiguously on the NAND chip (e.g. 358 * NAND_ECC_HW_SYNDROME interleaves in-band and 359 * out-of-band data). 360 * @write_page_raw: function to write a raw page without ECC. This function 361 * should hide the specific layout used by the ECC 362 * controller and consider the passed data as contiguous 363 * in-band and out-of-band data. ECC controller is 364 * responsible for doing the appropriate transformations 365 * to adapt to its specific layout (e.g. 366 * NAND_ECC_HW_SYNDROME interleaves in-band and 367 * out-of-band data). 368 * @read_page: function to read a page according to the ECC generator 369 * requirements; returns maximum number of bitflips corrected in 370 * any single ECC step, -EIO hw error 371 * @read_subpage: function to read parts of the page covered by ECC; 372 * returns same as read_page() 373 * @write_subpage: function to write parts of the page covered by ECC. 374 * @write_page: function to write a page according to the ECC generator 375 * requirements. 376 * @write_oob_raw: function to write chip OOB data without ECC 377 * @read_oob_raw: function to read chip OOB data without ECC 378 * @read_oob: function to read chip OOB data 379 * @write_oob: function to write chip OOB data 380 */ 381 struct nand_ecc_ctrl { 382 nand_ecc_modes_t mode; 383 enum nand_ecc_algo algo; 384 int steps; 385 int size; 386 int bytes; 387 int total; 388 int strength; 389 int prepad; 390 int postpad; 391 unsigned int options; 392 void *priv; 393 u8 *calc_buf; 394 u8 *code_buf; 395 void (*hwctl)(struct nand_chip *chip, int mode); 396 int (*calculate)(struct nand_chip *chip, const uint8_t *dat, 397 uint8_t *ecc_code); 398 int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, 399 uint8_t *calc_ecc); 400 int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf, 401 int oob_required, int page); 402 int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf, 403 int oob_required, int page); 404 int (*read_page)(struct nand_chip *chip, uint8_t *buf, 405 int oob_required, int page); 406 int (*read_subpage)(struct nand_chip *chip, uint32_t offs, 407 uint32_t len, uint8_t *buf, int page); 408 int (*write_subpage)(struct nand_chip *chip, uint32_t offset, 409 uint32_t data_len, const uint8_t *data_buf, 410 int oob_required, int page); 411 int (*write_page)(struct nand_chip *chip, const uint8_t *buf, 412 int oob_required, int page); 413 int (*write_oob_raw)(struct nand_chip *chip, int page); 414 int (*read_oob_raw)(struct nand_chip *chip, int page); 415 int (*read_oob)(struct nand_chip *chip, int page); 416 int (*write_oob)(struct nand_chip *chip, int page); 417 }; 418 419 /** 420 * struct nand_sdr_timings - SDR NAND chip timings 421 * 422 * This struct defines the timing requirements of a SDR NAND chip. 423 * These information can be found in every NAND datasheets and the timings 424 * meaning are described in the ONFI specifications: 425 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 426 * Parameters) 427 * 428 * All these timings are expressed in picoseconds. 429 * 430 * @tBERS_max: Block erase time 431 * @tCCS_min: Change column setup time 432 * @tPROG_max: Page program time 433 * @tR_max: Page read time 434 * @tALH_min: ALE hold time 435 * @tADL_min: ALE to data loading time 436 * @tALS_min: ALE setup time 437 * @tAR_min: ALE to RE# delay 438 * @tCEA_max: CE# access time 439 * @tCEH_min: CE# high hold time 440 * @tCH_min: CE# hold time 441 * @tCHZ_max: CE# high to output hi-Z 442 * @tCLH_min: CLE hold time 443 * @tCLR_min: CLE to RE# delay 444 * @tCLS_min: CLE setup time 445 * @tCOH_min: CE# high to output hold 446 * @tCS_min: CE# setup time 447 * @tDH_min: Data hold time 448 * @tDS_min: Data setup time 449 * @tFEAT_max: Busy time for Set Features and Get Features 450 * @tIR_min: Output hi-Z to RE# low 451 * @tITC_max: Interface and Timing Mode Change time 452 * @tRC_min: RE# cycle time 453 * @tREA_max: RE# access time 454 * @tREH_min: RE# high hold time 455 * @tRHOH_min: RE# high to output hold 456 * @tRHW_min: RE# high to WE# low 457 * @tRHZ_max: RE# high to output hi-Z 458 * @tRLOH_min: RE# low to output hold 459 * @tRP_min: RE# pulse width 460 * @tRR_min: Ready to RE# low (data only) 461 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 462 * rising edge of R/B#. 463 * @tWB_max: WE# high to SR[6] low 464 * @tWC_min: WE# cycle time 465 * @tWH_min: WE# high hold time 466 * @tWHR_min: WE# high to RE# low 467 * @tWP_min: WE# pulse width 468 * @tWW_min: WP# transition to WE# low 469 */ 470 struct nand_sdr_timings { 471 u64 tBERS_max; 472 u32 tCCS_min; 473 u64 tPROG_max; 474 u64 tR_max; 475 u32 tALH_min; 476 u32 tADL_min; 477 u32 tALS_min; 478 u32 tAR_min; 479 u32 tCEA_max; 480 u32 tCEH_min; 481 u32 tCH_min; 482 u32 tCHZ_max; 483 u32 tCLH_min; 484 u32 tCLR_min; 485 u32 tCLS_min; 486 u32 tCOH_min; 487 u32 tCS_min; 488 u32 tDH_min; 489 u32 tDS_min; 490 u32 tFEAT_max; 491 u32 tIR_min; 492 u32 tITC_max; 493 u32 tRC_min; 494 u32 tREA_max; 495 u32 tREH_min; 496 u32 tRHOH_min; 497 u32 tRHW_min; 498 u32 tRHZ_max; 499 u32 tRLOH_min; 500 u32 tRP_min; 501 u32 tRR_min; 502 u64 tRST_max; 503 u32 tWB_max; 504 u32 tWC_min; 505 u32 tWH_min; 506 u32 tWHR_min; 507 u32 tWP_min; 508 u32 tWW_min; 509 }; 510 511 /** 512 * enum nand_data_interface_type - NAND interface timing type 513 * @NAND_SDR_IFACE: Single Data Rate interface 514 */ 515 enum nand_data_interface_type { 516 NAND_SDR_IFACE, 517 }; 518 519 /** 520 * struct nand_data_interface - NAND interface timing 521 * @type: type of the timing 522 * @timings: The timing, type according to @type 523 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE. 524 */ 525 struct nand_data_interface { 526 enum nand_data_interface_type type; 527 union { 528 struct nand_sdr_timings sdr; 529 } timings; 530 }; 531 532 /** 533 * nand_get_sdr_timings - get SDR timing from data interface 534 * @conf: The data interface 535 */ 536 static inline const struct nand_sdr_timings * 537 nand_get_sdr_timings(const struct nand_data_interface *conf) 538 { 539 if (conf->type != NAND_SDR_IFACE) 540 return ERR_PTR(-EINVAL); 541 542 return &conf->timings.sdr; 543 } 544 545 /** 546 * struct nand_op_cmd_instr - Definition of a command instruction 547 * @opcode: the command to issue in one cycle 548 */ 549 struct nand_op_cmd_instr { 550 u8 opcode; 551 }; 552 553 /** 554 * struct nand_op_addr_instr - Definition of an address instruction 555 * @naddrs: length of the @addrs array 556 * @addrs: array containing the address cycles to issue 557 */ 558 struct nand_op_addr_instr { 559 unsigned int naddrs; 560 const u8 *addrs; 561 }; 562 563 /** 564 * struct nand_op_data_instr - Definition of a data instruction 565 * @len: number of data bytes to move 566 * @buf: buffer to fill 567 * @buf.in: buffer to fill when reading from the NAND chip 568 * @buf.out: buffer to read from when writing to the NAND chip 569 * @force_8bit: force 8-bit access 570 * 571 * Please note that "in" and "out" are inverted from the ONFI specification 572 * and are from the controller perspective, so a "in" is a read from the NAND 573 * chip while a "out" is a write to the NAND chip. 574 */ 575 struct nand_op_data_instr { 576 unsigned int len; 577 union { 578 void *in; 579 const void *out; 580 } buf; 581 bool force_8bit; 582 }; 583 584 /** 585 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction 586 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms 587 */ 588 struct nand_op_waitrdy_instr { 589 unsigned int timeout_ms; 590 }; 591 592 /** 593 * enum nand_op_instr_type - Definition of all instruction types 594 * @NAND_OP_CMD_INSTR: command instruction 595 * @NAND_OP_ADDR_INSTR: address instruction 596 * @NAND_OP_DATA_IN_INSTR: data in instruction 597 * @NAND_OP_DATA_OUT_INSTR: data out instruction 598 * @NAND_OP_WAITRDY_INSTR: wait ready instruction 599 */ 600 enum nand_op_instr_type { 601 NAND_OP_CMD_INSTR, 602 NAND_OP_ADDR_INSTR, 603 NAND_OP_DATA_IN_INSTR, 604 NAND_OP_DATA_OUT_INSTR, 605 NAND_OP_WAITRDY_INSTR, 606 }; 607 608 /** 609 * struct nand_op_instr - Instruction object 610 * @type: the instruction type 611 * @ctx: extra data associated to the instruction. You'll have to use the 612 * appropriate element depending on @type 613 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR 614 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR 615 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR 616 * or %NAND_OP_DATA_OUT_INSTR 617 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR 618 * @delay_ns: delay the controller should apply after the instruction has been 619 * issued on the bus. Most modern controllers have internal timings 620 * control logic, and in this case, the controller driver can ignore 621 * this field. 622 */ 623 struct nand_op_instr { 624 enum nand_op_instr_type type; 625 union { 626 struct nand_op_cmd_instr cmd; 627 struct nand_op_addr_instr addr; 628 struct nand_op_data_instr data; 629 struct nand_op_waitrdy_instr waitrdy; 630 } ctx; 631 unsigned int delay_ns; 632 }; 633 634 /* 635 * Special handling must be done for the WAITRDY timeout parameter as it usually 636 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or 637 * tBERS (during an erase) which all of them are u64 values that cannot be 638 * divided by usual kernel macros and must be handled with the special 639 * DIV_ROUND_UP_ULL() macro. 640 * 641 * Cast to type of dividend is needed here to guarantee that the result won't 642 * be an unsigned long long when the dividend is an unsigned long (or smaller), 643 * which is what the compiler does when it sees ternary operator with 2 644 * different return types (picks the largest type to make sure there's no 645 * loss). 646 */ 647 #define __DIVIDE(dividend, divisor) ({ \ 648 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \ 649 DIV_ROUND_UP(dividend, divisor) : \ 650 DIV_ROUND_UP_ULL(dividend, divisor)); \ 651 }) 652 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000) 653 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000) 654 655 #define NAND_OP_CMD(id, ns) \ 656 { \ 657 .type = NAND_OP_CMD_INSTR, \ 658 .ctx.cmd.opcode = id, \ 659 .delay_ns = ns, \ 660 } 661 662 #define NAND_OP_ADDR(ncycles, cycles, ns) \ 663 { \ 664 .type = NAND_OP_ADDR_INSTR, \ 665 .ctx.addr = { \ 666 .naddrs = ncycles, \ 667 .addrs = cycles, \ 668 }, \ 669 .delay_ns = ns, \ 670 } 671 672 #define NAND_OP_DATA_IN(l, b, ns) \ 673 { \ 674 .type = NAND_OP_DATA_IN_INSTR, \ 675 .ctx.data = { \ 676 .len = l, \ 677 .buf.in = b, \ 678 .force_8bit = false, \ 679 }, \ 680 .delay_ns = ns, \ 681 } 682 683 #define NAND_OP_DATA_OUT(l, b, ns) \ 684 { \ 685 .type = NAND_OP_DATA_OUT_INSTR, \ 686 .ctx.data = { \ 687 .len = l, \ 688 .buf.out = b, \ 689 .force_8bit = false, \ 690 }, \ 691 .delay_ns = ns, \ 692 } 693 694 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \ 695 { \ 696 .type = NAND_OP_DATA_IN_INSTR, \ 697 .ctx.data = { \ 698 .len = l, \ 699 .buf.in = b, \ 700 .force_8bit = true, \ 701 }, \ 702 .delay_ns = ns, \ 703 } 704 705 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \ 706 { \ 707 .type = NAND_OP_DATA_OUT_INSTR, \ 708 .ctx.data = { \ 709 .len = l, \ 710 .buf.out = b, \ 711 .force_8bit = true, \ 712 }, \ 713 .delay_ns = ns, \ 714 } 715 716 #define NAND_OP_WAIT_RDY(tout_ms, ns) \ 717 { \ 718 .type = NAND_OP_WAITRDY_INSTR, \ 719 .ctx.waitrdy.timeout_ms = tout_ms, \ 720 .delay_ns = ns, \ 721 } 722 723 /** 724 * struct nand_subop - a sub operation 725 * @instrs: array of instructions 726 * @ninstrs: length of the @instrs array 727 * @first_instr_start_off: offset to start from for the first instruction 728 * of the sub-operation 729 * @last_instr_end_off: offset to end at (excluded) for the last instruction 730 * of the sub-operation 731 * 732 * Both @first_instr_start_off and @last_instr_end_off only apply to data or 733 * address instructions. 734 * 735 * When an operation cannot be handled as is by the NAND controller, it will 736 * be split by the parser into sub-operations which will be passed to the 737 * controller driver. 738 */ 739 struct nand_subop { 740 const struct nand_op_instr *instrs; 741 unsigned int ninstrs; 742 unsigned int first_instr_start_off; 743 unsigned int last_instr_end_off; 744 }; 745 746 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop, 747 unsigned int op_id); 748 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop, 749 unsigned int op_id); 750 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop, 751 unsigned int op_id); 752 unsigned int nand_subop_get_data_len(const struct nand_subop *subop, 753 unsigned int op_id); 754 755 /** 756 * struct nand_op_parser_addr_constraints - Constraints for address instructions 757 * @maxcycles: maximum number of address cycles the controller can issue in a 758 * single step 759 */ 760 struct nand_op_parser_addr_constraints { 761 unsigned int maxcycles; 762 }; 763 764 /** 765 * struct nand_op_parser_data_constraints - Constraints for data instructions 766 * @maxlen: maximum data length that the controller can handle in a single step 767 */ 768 struct nand_op_parser_data_constraints { 769 unsigned int maxlen; 770 }; 771 772 /** 773 * struct nand_op_parser_pattern_elem - One element of a pattern 774 * @type: the instructuction type 775 * @optional: whether this element of the pattern is optional or mandatory 776 * @ctx: address or data constraint 777 * @ctx.addr: address constraint (number of cycles) 778 * @ctx.data: data constraint (data length) 779 */ 780 struct nand_op_parser_pattern_elem { 781 enum nand_op_instr_type type; 782 bool optional; 783 union { 784 struct nand_op_parser_addr_constraints addr; 785 struct nand_op_parser_data_constraints data; 786 } ctx; 787 }; 788 789 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \ 790 { \ 791 .type = NAND_OP_CMD_INSTR, \ 792 .optional = _opt, \ 793 } 794 795 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \ 796 { \ 797 .type = NAND_OP_ADDR_INSTR, \ 798 .optional = _opt, \ 799 .ctx.addr.maxcycles = _maxcycles, \ 800 } 801 802 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \ 803 { \ 804 .type = NAND_OP_DATA_IN_INSTR, \ 805 .optional = _opt, \ 806 .ctx.data.maxlen = _maxlen, \ 807 } 808 809 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \ 810 { \ 811 .type = NAND_OP_DATA_OUT_INSTR, \ 812 .optional = _opt, \ 813 .ctx.data.maxlen = _maxlen, \ 814 } 815 816 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \ 817 { \ 818 .type = NAND_OP_WAITRDY_INSTR, \ 819 .optional = _opt, \ 820 } 821 822 /** 823 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor 824 * @elems: array of pattern elements 825 * @nelems: number of pattern elements in @elems array 826 * @exec: the function that will issue a sub-operation 827 * 828 * A pattern is a list of elements, each element reprensenting one instruction 829 * with its constraints. The pattern itself is used by the core to match NAND 830 * chip operation with NAND controller operations. 831 * Once a match between a NAND controller operation pattern and a NAND chip 832 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec() 833 * hook is called so that the controller driver can issue the operation on the 834 * bus. 835 * 836 * Controller drivers should declare as many patterns as they support and pass 837 * this list of patterns (created with the help of the following macro) to 838 * the nand_op_parser_exec_op() helper. 839 */ 840 struct nand_op_parser_pattern { 841 const struct nand_op_parser_pattern_elem *elems; 842 unsigned int nelems; 843 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop); 844 }; 845 846 #define NAND_OP_PARSER_PATTERN(_exec, ...) \ 847 { \ 848 .exec = _exec, \ 849 .elems = (struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \ 850 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \ 851 sizeof(struct nand_op_parser_pattern_elem), \ 852 } 853 854 /** 855 * struct nand_op_parser - NAND controller operation parser descriptor 856 * @patterns: array of supported patterns 857 * @npatterns: length of the @patterns array 858 * 859 * The parser descriptor is just an array of supported patterns which will be 860 * iterated by nand_op_parser_exec_op() everytime it tries to execute an 861 * NAND operation (or tries to determine if a specific operation is supported). 862 * 863 * It is worth mentioning that patterns will be tested in their declaration 864 * order, and the first match will be taken, so it's important to order patterns 865 * appropriately so that simple/inefficient patterns are placed at the end of 866 * the list. Usually, this is where you put single instruction patterns. 867 */ 868 struct nand_op_parser { 869 const struct nand_op_parser_pattern *patterns; 870 unsigned int npatterns; 871 }; 872 873 #define NAND_OP_PARSER(...) \ 874 { \ 875 .patterns = (struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \ 876 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \ 877 sizeof(struct nand_op_parser_pattern), \ 878 } 879 880 /** 881 * struct nand_operation - NAND operation descriptor 882 * @instrs: array of instructions to execute 883 * @ninstrs: length of the @instrs array 884 * 885 * The actual operation structure that will be passed to chip->exec_op(). 886 */ 887 struct nand_operation { 888 const struct nand_op_instr *instrs; 889 unsigned int ninstrs; 890 }; 891 892 #define NAND_OPERATION(_instrs) \ 893 { \ 894 .instrs = _instrs, \ 895 .ninstrs = ARRAY_SIZE(_instrs), \ 896 } 897 898 int nand_op_parser_exec_op(struct nand_chip *chip, 899 const struct nand_op_parser *parser, 900 const struct nand_operation *op, bool check_only); 901 902 /** 903 * struct nand_legacy - NAND chip legacy fields/hooks 904 * @IO_ADDR_R: address to read the 8 I/O lines of the flash device 905 * @IO_ADDR_W: address to write the 8 I/O lines of the flash device 906 * @read_byte: read one byte from the chip 907 * @write_byte: write a single byte to the chip on the low 8 I/O lines 908 * @write_buf: write data from the buffer to the chip 909 * @read_buf: read data from the chip into the buffer 910 * @cmd_ctrl: hardware specific function for controlling ALE/CLE/nCE. Also used 911 * to write command and address 912 * @cmdfunc: hardware specific function for writing commands to the chip. 913 * @dev_ready: hardware specific function for accessing device ready/busy line. 914 * If set to NULL no access to ready/busy is available and the 915 * ready/busy information is read from the chip status register. 916 * @waitfunc: hardware specific function for wait on ready. 917 * @block_bad: check if a block is bad, using OOB markers 918 * @block_markbad: mark a block bad 919 * @erase: erase function 920 * @set_features: set the NAND chip features 921 * @get_features: get the NAND chip features 922 * @chip_delay: chip dependent delay for transferring data from array to read 923 * regs (tR). 924 * 925 * If you look at this structure you're already wrong. These fields/hooks are 926 * all deprecated. 927 */ 928 struct nand_legacy { 929 void __iomem *IO_ADDR_R; 930 void __iomem *IO_ADDR_W; 931 u8 (*read_byte)(struct nand_chip *chip); 932 void (*write_byte)(struct nand_chip *chip, u8 byte); 933 void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len); 934 void (*read_buf)(struct nand_chip *chip, u8 *buf, int len); 935 void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl); 936 void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column, 937 int page_addr); 938 int (*dev_ready)(struct nand_chip *chip); 939 int (*waitfunc)(struct nand_chip *chip); 940 int (*block_bad)(struct nand_chip *chip, loff_t ofs); 941 int (*block_markbad)(struct nand_chip *chip, loff_t ofs); 942 int (*erase)(struct nand_chip *chip, int page); 943 int (*set_features)(struct nand_chip *chip, int feature_addr, 944 u8 *subfeature_para); 945 int (*get_features)(struct nand_chip *chip, int feature_addr, 946 u8 *subfeature_para); 947 int chip_delay; 948 }; 949 950 /** 951 * struct nand_chip - NAND Private Flash Chip Data 952 * @mtd: MTD device registered to the MTD framework 953 * @legacy: All legacy fields/hooks. If you develop a new driver, 954 * don't even try to use any of these fields/hooks, and if 955 * you're modifying an existing driver that is using those 956 * fields/hooks, you should consider reworking the driver 957 * avoid using them. 958 * @select_chip: [REPLACEABLE] select chip nr 959 * @exec_op: controller specific method to execute NAND operations. 960 * This method replaces ->cmdfunc(), 961 * ->legacy.{read,write}_{buf,byte,word}(), 962 * ->legacy.dev_ready() and ->waifunc(). 963 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 964 * setting the read-retry mode. Mostly needed for MLC NAND. 965 * @ecc: [BOARDSPECIFIC] ECC control structure 966 * @buf_align: minimum buffer alignment required by a platform 967 * @dummy_controller: dummy controller implementation for drivers that can 968 * only control a single chip 969 * @state: [INTERN] the current state of the NAND device 970 * @oob_poi: "poison value buffer," used for laying out OOB data 971 * before writing 972 * @page_shift: [INTERN] number of address bits in a page (column 973 * address bits). 974 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 975 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 976 * @chip_shift: [INTERN] number of address bits in one chip 977 * @options: [BOARDSPECIFIC] various chip options. They can partly 978 * be set to inform nand_scan about special functionality. 979 * See the defines for further explanation. 980 * @bbt_options: [INTERN] bad block specific options. All options used 981 * here must come from bbm.h. By default, these options 982 * will be copied to the appropriate nand_bbt_descr's. 983 * @badblockpos: [INTERN] position of the bad block marker in the oob 984 * area. 985 * @badblockbits: [INTERN] minimum number of set bits in a good block's 986 * bad block marker position; i.e., BBM == 11110111b is 987 * not bad when badblockbits == 7 988 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 989 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 990 * Minimum amount of bit errors per @ecc_step_ds guaranteed 991 * to be correctable. If unknown, set to zero. 992 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 993 * also from the datasheet. It is the recommended ECC step 994 * size, if known; if unknown, set to zero. 995 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 996 * set to the actually used ONFI mode if the chip is 997 * ONFI compliant or deduced from the datasheet if 998 * the NAND chip is not ONFI compliant. 999 * @numchips: [INTERN] number of physical chips 1000 * @chipsize: [INTERN] the size of one chip for multichip arrays 1001 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 1002 * @data_buf: [INTERN] buffer for data, size is (page size + oobsize). 1003 * @pagebuf: [INTERN] holds the pagenumber which is currently in 1004 * data_buf. 1005 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 1006 * currently in data_buf. 1007 * @subpagesize: [INTERN] holds the subpagesize 1008 * @id: [INTERN] holds NAND ID 1009 * @parameters: [INTERN] holds generic parameters under an easily 1010 * readable form. 1011 * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a 1012 * this nand device will encounter their life times. 1013 * @blocks_per_die: [INTERN] The number of PEBs in a die 1014 * @data_interface: [INTERN] NAND interface timing information 1015 * @read_retries: [INTERN] the number of read retry modes supported 1016 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If 1017 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 1018 * means the configuration should not be applied but 1019 * only checked. 1020 * @bbt: [INTERN] bad block table pointer 1021 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 1022 * lookup. 1023 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 1024 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 1025 * bad block scan. 1026 * @controller: [REPLACEABLE] a pointer to a hardware controller 1027 * structure which is shared among multiple independent 1028 * devices. 1029 * @priv: [OPTIONAL] pointer to private chip data 1030 * @manufacturer: [INTERN] Contains manufacturer information 1031 * @manufacturer.desc: [INTERN] Contains manufacturer's description 1032 * @manufacturer.priv: [INTERN] Contains manufacturer private information 1033 */ 1034 1035 struct nand_chip { 1036 struct mtd_info mtd; 1037 1038 struct nand_legacy legacy; 1039 1040 void (*select_chip)(struct nand_chip *chip, int cs); 1041 int (*exec_op)(struct nand_chip *chip, 1042 const struct nand_operation *op, 1043 bool check_only); 1044 int (*setup_read_retry)(struct nand_chip *chip, int retry_mode); 1045 int (*setup_data_interface)(struct nand_chip *chip, int chipnr, 1046 const struct nand_data_interface *conf); 1047 1048 unsigned int options; 1049 unsigned int bbt_options; 1050 1051 int page_shift; 1052 int phys_erase_shift; 1053 int bbt_erase_shift; 1054 int chip_shift; 1055 int numchips; 1056 uint64_t chipsize; 1057 int pagemask; 1058 u8 *data_buf; 1059 int pagebuf; 1060 unsigned int pagebuf_bitflips; 1061 int subpagesize; 1062 uint8_t bits_per_cell; 1063 uint16_t ecc_strength_ds; 1064 uint16_t ecc_step_ds; 1065 int onfi_timing_mode_default; 1066 int badblockpos; 1067 int badblockbits; 1068 1069 struct nand_id id; 1070 struct nand_parameters parameters; 1071 u16 max_bb_per_die; 1072 u32 blocks_per_die; 1073 1074 struct nand_data_interface data_interface; 1075 1076 int read_retries; 1077 1078 flstate_t state; 1079 1080 uint8_t *oob_poi; 1081 struct nand_controller *controller; 1082 1083 struct nand_ecc_ctrl ecc; 1084 unsigned long buf_align; 1085 struct nand_controller dummy_controller; 1086 1087 uint8_t *bbt; 1088 struct nand_bbt_descr *bbt_td; 1089 struct nand_bbt_descr *bbt_md; 1090 1091 struct nand_bbt_descr *badblock_pattern; 1092 1093 void *priv; 1094 1095 struct { 1096 const struct nand_manufacturer *desc; 1097 void *priv; 1098 } manufacturer; 1099 }; 1100 1101 static inline int nand_exec_op(struct nand_chip *chip, 1102 const struct nand_operation *op) 1103 { 1104 if (!chip->exec_op) 1105 return -ENOTSUPP; 1106 1107 return chip->exec_op(chip, op, false); 1108 } 1109 1110 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; 1111 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops; 1112 1113 static inline void nand_set_flash_node(struct nand_chip *chip, 1114 struct device_node *np) 1115 { 1116 mtd_set_of_node(&chip->mtd, np); 1117 } 1118 1119 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) 1120 { 1121 return mtd_get_of_node(&chip->mtd); 1122 } 1123 1124 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 1125 { 1126 return container_of(mtd, struct nand_chip, mtd); 1127 } 1128 1129 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 1130 { 1131 return &chip->mtd; 1132 } 1133 1134 static inline void *nand_get_controller_data(struct nand_chip *chip) 1135 { 1136 return chip->priv; 1137 } 1138 1139 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 1140 { 1141 chip->priv = priv; 1142 } 1143 1144 static inline void nand_set_manufacturer_data(struct nand_chip *chip, 1145 void *priv) 1146 { 1147 chip->manufacturer.priv = priv; 1148 } 1149 1150 static inline void *nand_get_manufacturer_data(struct nand_chip *chip) 1151 { 1152 return chip->manufacturer.priv; 1153 } 1154 1155 /* 1156 * A helper for defining older NAND chips where the second ID byte fully 1157 * defined the chip, including the geometry (chip size, eraseblock size, page 1158 * size). All these chips have 512 bytes NAND page size. 1159 */ 1160 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 1161 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 1162 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 1163 1164 /* 1165 * A helper for defining newer chips which report their page size and 1166 * eraseblock size via the extended ID bytes. 1167 * 1168 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 1169 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 1170 * device ID now only represented a particular total chip size (and voltage, 1171 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1172 * using the same device ID. 1173 */ 1174 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1175 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1176 .options = (opts) } 1177 1178 #define NAND_ECC_INFO(_strength, _step) \ 1179 { .strength_ds = (_strength), .step_ds = (_step) } 1180 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1181 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1182 1183 /** 1184 * struct nand_flash_dev - NAND Flash Device ID Structure 1185 * @name: a human-readable name of the NAND chip 1186 * @dev_id: the device ID (the second byte of the full chip ID array) 1187 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1188 * memory address as @id[0]) 1189 * @dev_id: device ID part of the full chip ID array (refers the same memory 1190 * address as @id[1]) 1191 * @id: full device ID array 1192 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1193 * well as the eraseblock size) is determined from the extended NAND 1194 * chip ID array) 1195 * @chipsize: total chip size in MiB 1196 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1197 * @options: stores various chip bit options 1198 * @id_len: The valid length of the @id. 1199 * @oobsize: OOB size 1200 * @ecc: ECC correctability and step information from the datasheet. 1201 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1202 * @ecc_strength_ds in nand_chip{}. 1203 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1204 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1205 * For example, the "4bit ECC for each 512Byte" can be set with 1206 * NAND_ECC_INFO(4, 512). 1207 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1208 * reset. Should be deduced from timings described 1209 * in the datasheet. 1210 * 1211 */ 1212 struct nand_flash_dev { 1213 char *name; 1214 union { 1215 struct { 1216 uint8_t mfr_id; 1217 uint8_t dev_id; 1218 }; 1219 uint8_t id[NAND_MAX_ID_LEN]; 1220 }; 1221 unsigned int pagesize; 1222 unsigned int chipsize; 1223 unsigned int erasesize; 1224 unsigned int options; 1225 uint16_t id_len; 1226 uint16_t oobsize; 1227 struct { 1228 uint16_t strength_ds; 1229 uint16_t step_ds; 1230 } ecc; 1231 int onfi_timing_mode_default; 1232 }; 1233 1234 int nand_create_bbt(struct nand_chip *chip); 1235 1236 /* 1237 * Check if it is a SLC nand. 1238 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1239 * We do not distinguish the MLC and TLC now. 1240 */ 1241 static inline bool nand_is_slc(struct nand_chip *chip) 1242 { 1243 WARN(chip->bits_per_cell == 0, 1244 "chip->bits_per_cell is used uninitialized\n"); 1245 return chip->bits_per_cell == 1; 1246 } 1247 1248 /** 1249 * Check if the opcode's address should be sent only on the lower 8 bits 1250 * @command: opcode to check 1251 */ 1252 static inline int nand_opcode_8bits(unsigned int command) 1253 { 1254 switch (command) { 1255 case NAND_CMD_READID: 1256 case NAND_CMD_PARAM: 1257 case NAND_CMD_GET_FEATURES: 1258 case NAND_CMD_SET_FEATURES: 1259 return 1; 1260 default: 1261 break; 1262 } 1263 return 0; 1264 } 1265 1266 int nand_check_erased_ecc_chunk(void *data, int datalen, 1267 void *ecc, int ecclen, 1268 void *extraoob, int extraooblen, 1269 int threshold); 1270 1271 int nand_ecc_choose_conf(struct nand_chip *chip, 1272 const struct nand_ecc_caps *caps, int oobavail); 1273 1274 /* Default write_oob implementation */ 1275 int nand_write_oob_std(struct nand_chip *chip, int page); 1276 1277 /* Default read_oob implementation */ 1278 int nand_read_oob_std(struct nand_chip *chip, int page); 1279 1280 /* Stub used by drivers that do not support GET/SET FEATURES operations */ 1281 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr, 1282 u8 *subfeature_param); 1283 1284 /* Default read_page_raw implementation */ 1285 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required, 1286 int page); 1287 1288 /* Default write_page_raw implementation */ 1289 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 1290 int oob_required, int page); 1291 1292 /* Reset and initialize a NAND device */ 1293 int nand_reset(struct nand_chip *chip, int chipnr); 1294 1295 /* NAND operation helpers */ 1296 int nand_reset_op(struct nand_chip *chip); 1297 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, 1298 unsigned int len); 1299 int nand_status_op(struct nand_chip *chip, u8 *status); 1300 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock); 1301 int nand_read_page_op(struct nand_chip *chip, unsigned int page, 1302 unsigned int offset_in_page, void *buf, unsigned int len); 1303 int nand_change_read_column_op(struct nand_chip *chip, 1304 unsigned int offset_in_page, void *buf, 1305 unsigned int len, bool force_8bit); 1306 int nand_read_oob_op(struct nand_chip *chip, unsigned int page, 1307 unsigned int offset_in_page, void *buf, unsigned int len); 1308 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, 1309 unsigned int offset_in_page, const void *buf, 1310 unsigned int len); 1311 int nand_prog_page_end_op(struct nand_chip *chip); 1312 int nand_prog_page_op(struct nand_chip *chip, unsigned int page, 1313 unsigned int offset_in_page, const void *buf, 1314 unsigned int len); 1315 int nand_change_write_column_op(struct nand_chip *chip, 1316 unsigned int offset_in_page, const void *buf, 1317 unsigned int len, bool force_8bit); 1318 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, 1319 bool force_8bit); 1320 int nand_write_data_op(struct nand_chip *chip, const void *buf, 1321 unsigned int len, bool force_8bit); 1322 1323 /* Scan and identify a NAND device */ 1324 int nand_scan_with_ids(struct nand_chip *chip, unsigned int max_chips, 1325 struct nand_flash_dev *ids); 1326 1327 static inline int nand_scan(struct nand_chip *chip, unsigned int max_chips) 1328 { 1329 return nand_scan_with_ids(chip, max_chips, NULL); 1330 } 1331 1332 /* Internal helper for board drivers which need to override command function */ 1333 void nand_wait_ready(struct nand_chip *chip); 1334 1335 /* 1336 * Free resources held by the NAND device, must be called on error after a 1337 * sucessful nand_scan(). 1338 */ 1339 void nand_cleanup(struct nand_chip *chip); 1340 /* Unregister the MTD device and calls nand_cleanup() */ 1341 void nand_release(struct nand_chip *chip); 1342 1343 /* 1344 * External helper for controller drivers that have to implement the WAITRDY 1345 * instruction and have no physical pin to check it. 1346 */ 1347 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms); 1348 1349 #endif /* __LINUX_MTD_RAWNAND_H */ 1350