1 /* 2 * Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Info: 9 * Contains defines, datastructures for ndfc nand controller 10 * 11 */ 12 #ifndef __LINUX_MTD_NDFC_H 13 #define __LINUX_MTD_NDFC_H 14 15 /* NDFC Register definitions */ 16 #define NDFC_CMD 0x00 17 #define NDFC_ALE 0x04 18 #define NDFC_DATA 0x08 19 #define NDFC_ECC 0x10 20 #define NDFC_BCFG0 0x30 21 #define NDFC_BCFG1 0x34 22 #define NDFC_BCFG2 0x38 23 #define NDFC_BCFG3 0x3c 24 #define NDFC_CCR 0x40 25 #define NDFC_STAT 0x44 26 #define NDFC_HWCTL 0x48 27 #define NDFC_REVID 0x50 28 29 #define NDFC_STAT_IS_READY 0x01000000 30 31 #define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */ 32 #define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */ 33 #define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */ 34 #define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */ 35 #define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */ 36 #define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */ 37 #define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */ 38 #define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */ 39 #define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */ 40 #define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */ 41 #define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */ 42 #define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */ 43 #define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */ 44 #define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */ 45 #define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */ 46 #define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */ 47 48 #define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */ 49 #define NDFC_BxCFG_CED 0x40000000 /* nCE Style */ 50 #define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */ 51 #define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */ 52 #define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */ 53 54 #define NDFC_MAX_BANKS 4 55 56 struct ndfc_controller_settings { 57 uint32_t ccr_settings; 58 uint64_t ndfc_erpn; 59 }; 60 61 struct ndfc_chip_settings { 62 uint32_t bank_settings; 63 }; 64 65 #endif 66