1da7fbe58SPierre Ossman /* 2da7fbe58SPierre Ossman * Header for MultiMediaCard (MMC) 3da7fbe58SPierre Ossman * 4da7fbe58SPierre Ossman * Copyright 2002 Hewlett-Packard Company 5da7fbe58SPierre Ossman * 6da7fbe58SPierre Ossman * Use consistent with the GNU GPL is permitted, 7da7fbe58SPierre Ossman * provided that this copyright notice is 8da7fbe58SPierre Ossman * preserved in its entirety in all copies and derived works. 9da7fbe58SPierre Ossman * 10da7fbe58SPierre Ossman * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, 11da7fbe58SPierre Ossman * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS 12da7fbe58SPierre Ossman * FITNESS FOR ANY PARTICULAR PURPOSE. 13da7fbe58SPierre Ossman * 14da7fbe58SPierre Ossman * Many thanks to Alessandro Rubini and Jonathan Corbet! 15da7fbe58SPierre Ossman * 16da7fbe58SPierre Ossman * Based strongly on code by: 17da7fbe58SPierre Ossman * 18da7fbe58SPierre Ossman * Author: Yong-iL Joh <tolkien@mizi.com> 19da7fbe58SPierre Ossman * 20da7fbe58SPierre Ossman * Author: Andrew Christian 21da7fbe58SPierre Ossman * 15 May 2002 22da7fbe58SPierre Ossman */ 23da7fbe58SPierre Ossman 24100e9186SRobert P. J. Day #ifndef LINUX_MMC_MMC_H 25100e9186SRobert P. J. Day #define LINUX_MMC_MMC_H 26da7fbe58SPierre Ossman 27da7fbe58SPierre Ossman /* Standard MMC commands (4.1) type argument response */ 28da7fbe58SPierre Ossman /* class 1 */ 29da7fbe58SPierre Ossman #define MMC_GO_IDLE_STATE 0 /* bc */ 30da7fbe58SPierre Ossman #define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ 31da7fbe58SPierre Ossman #define MMC_ALL_SEND_CID 2 /* bcr R2 */ 32da7fbe58SPierre Ossman #define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ 33da7fbe58SPierre Ossman #define MMC_SET_DSR 4 /* bc [31:16] RCA */ 34b1ebe384SJarkko Lavinen #define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */ 35da7fbe58SPierre Ossman #define MMC_SWITCH 6 /* ac [31:0] See below R1b */ 36da7fbe58SPierre Ossman #define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ 37da7fbe58SPierre Ossman #define MMC_SEND_EXT_CSD 8 /* adtc R1 */ 38da7fbe58SPierre Ossman #define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */ 39da7fbe58SPierre Ossman #define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ 40da7fbe58SPierre Ossman #define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ 41da7fbe58SPierre Ossman #define MMC_STOP_TRANSMISSION 12 /* ac R1b */ 42da7fbe58SPierre Ossman #define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ 4322113efdSAries Lee #define MMC_BUS_TEST_R 14 /* adtc R1 */ 44da7fbe58SPierre Ossman #define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ 4522113efdSAries Lee #define MMC_BUS_TEST_W 19 /* adtc R1 */ 4697018580SDavid Brownell #define MMC_SPI_READ_OCR 58 /* spi spi_R3 */ 4797018580SDavid Brownell #define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */ 48da7fbe58SPierre Ossman 49da7fbe58SPierre Ossman /* class 2 */ 50da7fbe58SPierre Ossman #define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ 51da7fbe58SPierre Ossman #define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ 52da7fbe58SPierre Ossman #define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ 53b513ea25SArindam Nath #define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */ 54a4924c71SGirish K S #define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */ 55da7fbe58SPierre Ossman 56da7fbe58SPierre Ossman /* class 3 */ 57da7fbe58SPierre Ossman #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ 58da7fbe58SPierre Ossman 59da7fbe58SPierre Ossman /* class 4 */ 60da7fbe58SPierre Ossman #define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ 61da7fbe58SPierre Ossman #define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ 62da7fbe58SPierre Ossman #define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ 63da7fbe58SPierre Ossman #define MMC_PROGRAM_CID 26 /* adtc R1 */ 64da7fbe58SPierre Ossman #define MMC_PROGRAM_CSD 27 /* adtc R1 */ 65da7fbe58SPierre Ossman 66da7fbe58SPierre Ossman /* class 6 */ 67da7fbe58SPierre Ossman #define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ 68da7fbe58SPierre Ossman #define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ 69da7fbe58SPierre Ossman #define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ 70da7fbe58SPierre Ossman 71da7fbe58SPierre Ossman /* class 5 */ 72da7fbe58SPierre Ossman #define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ 73da7fbe58SPierre Ossman #define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ 74da7fbe58SPierre Ossman #define MMC_ERASE 38 /* ac R1b */ 75da7fbe58SPierre Ossman 76da7fbe58SPierre Ossman /* class 9 */ 77da7fbe58SPierre Ossman #define MMC_FAST_IO 39 /* ac <Complex> R4 */ 78da7fbe58SPierre Ossman #define MMC_GO_IRQ_STATE 40 /* bcr R5 */ 79da7fbe58SPierre Ossman 80da7fbe58SPierre Ossman /* class 7 */ 81da7fbe58SPierre Ossman #define MMC_LOCK_UNLOCK 42 /* adtc R1b */ 82da7fbe58SPierre Ossman 83da7fbe58SPierre Ossman /* class 8 */ 84da7fbe58SPierre Ossman #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ 85da7fbe58SPierre Ossman #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ 86da7fbe58SPierre Ossman 87d0c97cfbSAndrei Warkentin static inline bool mmc_op_multi(u32 opcode) 88d0c97cfbSAndrei Warkentin { 89d0c97cfbSAndrei Warkentin return opcode == MMC_WRITE_MULTIPLE_BLOCK || 90d0c97cfbSAndrei Warkentin opcode == MMC_READ_MULTIPLE_BLOCK; 91d0c97cfbSAndrei Warkentin } 92d0c97cfbSAndrei Warkentin 93da7fbe58SPierre Ossman /* 94da7fbe58SPierre Ossman * MMC_SWITCH argument format: 95da7fbe58SPierre Ossman * 96da7fbe58SPierre Ossman * [31:26] Always 0 97da7fbe58SPierre Ossman * [25:24] Access Mode 98da7fbe58SPierre Ossman * [23:16] Location of target Byte in EXT_CSD 99da7fbe58SPierre Ossman * [15:08] Value Byte 100da7fbe58SPierre Ossman * [07:03] Always 0 101da7fbe58SPierre Ossman * [02:00] Command Set 102da7fbe58SPierre Ossman */ 103da7fbe58SPierre Ossman 104da7fbe58SPierre Ossman /* 10597018580SDavid Brownell MMC status in R1, for native mode (SPI bits are different) 106da7fbe58SPierre Ossman Type 107da7fbe58SPierre Ossman e : error bit 108da7fbe58SPierre Ossman s : status bit 109da7fbe58SPierre Ossman r : detected and set for the actual command response 110da7fbe58SPierre Ossman x : detected and set during command execution. the host must poll 111da7fbe58SPierre Ossman the card by sending status command in order to read these bits. 112da7fbe58SPierre Ossman Clear condition 113da7fbe58SPierre Ossman a : according to the card state 114da7fbe58SPierre Ossman b : always related to the previous command. Reception of 115da7fbe58SPierre Ossman a valid command will clear it (with a delay of one command) 116da7fbe58SPierre Ossman c : clear by read 117da7fbe58SPierre Ossman */ 118da7fbe58SPierre Ossman 119da7fbe58SPierre Ossman #define R1_OUT_OF_RANGE (1 << 31) /* er, c */ 120da7fbe58SPierre Ossman #define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ 121da7fbe58SPierre Ossman #define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ 122da7fbe58SPierre Ossman #define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ 123da7fbe58SPierre Ossman #define R1_ERASE_PARAM (1 << 27) /* ex, c */ 124da7fbe58SPierre Ossman #define R1_WP_VIOLATION (1 << 26) /* erx, c */ 125da7fbe58SPierre Ossman #define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ 126da7fbe58SPierre Ossman #define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ 127da7fbe58SPierre Ossman #define R1_COM_CRC_ERROR (1 << 23) /* er, b */ 128da7fbe58SPierre Ossman #define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ 129da7fbe58SPierre Ossman #define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ 130da7fbe58SPierre Ossman #define R1_CC_ERROR (1 << 20) /* erx, c */ 131da7fbe58SPierre Ossman #define R1_ERROR (1 << 19) /* erx, c */ 132da7fbe58SPierre Ossman #define R1_UNDERRUN (1 << 18) /* ex, c */ 133da7fbe58SPierre Ossman #define R1_OVERRUN (1 << 17) /* ex, c */ 134da7fbe58SPierre Ossman #define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ 135da7fbe58SPierre Ossman #define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ 136da7fbe58SPierre Ossman #define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ 137da7fbe58SPierre Ossman #define R1_ERASE_RESET (1 << 13) /* sr, c */ 138da7fbe58SPierre Ossman #define R1_STATUS(x) (x & 0xFFFFE000) 139da7fbe58SPierre Ossman #define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ 140da7fbe58SPierre Ossman #define R1_READY_FOR_DATA (1 << 8) /* sx, a */ 141ef0b27d4SAdrian Hunter #define R1_SWITCH_ERROR (1 << 7) /* sx, c */ 142abd9ac14SSeungwon Jeon #define R1_EXCEPTION_EVENT (1 << 6) /* sr, a */ 143da7fbe58SPierre Ossman #define R1_APP_CMD (1 << 5) /* sr, c */ 144da7fbe58SPierre Ossman 1450a2d4048SRussell King - ARM Linux #define R1_STATE_IDLE 0 1460a2d4048SRussell King - ARM Linux #define R1_STATE_READY 1 1470a2d4048SRussell King - ARM Linux #define R1_STATE_IDENT 2 1480a2d4048SRussell King - ARM Linux #define R1_STATE_STBY 3 1490a2d4048SRussell King - ARM Linux #define R1_STATE_TRAN 4 1500a2d4048SRussell King - ARM Linux #define R1_STATE_DATA 5 1510a2d4048SRussell King - ARM Linux #define R1_STATE_RCV 6 1520a2d4048SRussell King - ARM Linux #define R1_STATE_PRG 7 1530a2d4048SRussell King - ARM Linux #define R1_STATE_DIS 8 1540a2d4048SRussell King - ARM Linux 15597018580SDavid Brownell /* 15697018580SDavid Brownell * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS 15797018580SDavid Brownell * R1 is the low order byte; R2 is the next highest byte, when present. 15897018580SDavid Brownell */ 15997018580SDavid Brownell #define R1_SPI_IDLE (1 << 0) 16097018580SDavid Brownell #define R1_SPI_ERASE_RESET (1 << 1) 16197018580SDavid Brownell #define R1_SPI_ILLEGAL_COMMAND (1 << 2) 16297018580SDavid Brownell #define R1_SPI_COM_CRC (1 << 3) 16397018580SDavid Brownell #define R1_SPI_ERASE_SEQ (1 << 4) 16497018580SDavid Brownell #define R1_SPI_ADDRESS (1 << 5) 16597018580SDavid Brownell #define R1_SPI_PARAMETER (1 << 6) 16697018580SDavid Brownell /* R1 bit 7 is always zero */ 16797018580SDavid Brownell #define R2_SPI_CARD_LOCKED (1 << 8) 16897018580SDavid Brownell #define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */ 16997018580SDavid Brownell #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP 17097018580SDavid Brownell #define R2_SPI_ERROR (1 << 10) 17197018580SDavid Brownell #define R2_SPI_CC_ERROR (1 << 11) 17297018580SDavid Brownell #define R2_SPI_CARD_ECC_ERROR (1 << 12) 17397018580SDavid Brownell #define R2_SPI_WP_VIOLATION (1 << 13) 17497018580SDavid Brownell #define R2_SPI_ERASE_PARAM (1 << 14) 17597018580SDavid Brownell #define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ 17697018580SDavid Brownell #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE 17797018580SDavid Brownell 178da7fbe58SPierre Ossman /* These are unpacked versions of the actual responses */ 179da7fbe58SPierre Ossman 180da7fbe58SPierre Ossman struct _mmc_csd { 181da7fbe58SPierre Ossman u8 csd_structure; 182da7fbe58SPierre Ossman u8 spec_vers; 183da7fbe58SPierre Ossman u8 taac; 184da7fbe58SPierre Ossman u8 nsac; 185da7fbe58SPierre Ossman u8 tran_speed; 186da7fbe58SPierre Ossman u16 ccc; 187da7fbe58SPierre Ossman u8 read_bl_len; 188da7fbe58SPierre Ossman u8 read_bl_partial; 189da7fbe58SPierre Ossman u8 write_blk_misalign; 190da7fbe58SPierre Ossman u8 read_blk_misalign; 191da7fbe58SPierre Ossman u8 dsr_imp; 192da7fbe58SPierre Ossman u16 c_size; 193da7fbe58SPierre Ossman u8 vdd_r_curr_min; 194da7fbe58SPierre Ossman u8 vdd_r_curr_max; 195da7fbe58SPierre Ossman u8 vdd_w_curr_min; 196da7fbe58SPierre Ossman u8 vdd_w_curr_max; 197da7fbe58SPierre Ossman u8 c_size_mult; 198da7fbe58SPierre Ossman union { 199da7fbe58SPierre Ossman struct { /* MMC system specification version 3.1 */ 200da7fbe58SPierre Ossman u8 erase_grp_size; 201da7fbe58SPierre Ossman u8 erase_grp_mult; 202da7fbe58SPierre Ossman } v31; 203da7fbe58SPierre Ossman struct { /* MMC system specification version 2.2 */ 204da7fbe58SPierre Ossman u8 sector_size; 205da7fbe58SPierre Ossman u8 erase_grp_size; 206da7fbe58SPierre Ossman } v22; 207da7fbe58SPierre Ossman } erase; 208da7fbe58SPierre Ossman u8 wp_grp_size; 209da7fbe58SPierre Ossman u8 wp_grp_enable; 210da7fbe58SPierre Ossman u8 default_ecc; 211da7fbe58SPierre Ossman u8 r2w_factor; 212da7fbe58SPierre Ossman u8 write_bl_len; 213da7fbe58SPierre Ossman u8 write_bl_partial; 214da7fbe58SPierre Ossman u8 file_format_grp; 215da7fbe58SPierre Ossman u8 copy; 216da7fbe58SPierre Ossman u8 perm_write_protect; 217da7fbe58SPierre Ossman u8 tmp_write_protect; 218da7fbe58SPierre Ossman u8 file_format; 219da7fbe58SPierre Ossman u8 ecc; 220da7fbe58SPierre Ossman }; 221da7fbe58SPierre Ossman 222da7fbe58SPierre Ossman /* 223da7fbe58SPierre Ossman * OCR bits are mostly in host.h 224da7fbe58SPierre Ossman */ 225da7fbe58SPierre Ossman #define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */ 226da7fbe58SPierre Ossman 227da7fbe58SPierre Ossman /* 228da7fbe58SPierre Ossman * Card Command Classes (CCC) 229da7fbe58SPierre Ossman */ 230da7fbe58SPierre Ossman #define CCC_BASIC (1<<0) /* (0) Basic protocol functions */ 231da7fbe58SPierre Ossman /* (CMD0,1,2,3,4,7,9,10,12,13,15) */ 23297018580SDavid Brownell /* (and for SPI, CMD58,59) */ 233da7fbe58SPierre Ossman #define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */ 234da7fbe58SPierre Ossman /* (CMD11) */ 235da7fbe58SPierre Ossman #define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */ 236da7fbe58SPierre Ossman /* (CMD16,17,18) */ 237da7fbe58SPierre Ossman #define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */ 238da7fbe58SPierre Ossman /* (CMD20) */ 239da7fbe58SPierre Ossman #define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */ 240da7fbe58SPierre Ossman /* (CMD16,24,25,26,27) */ 241da7fbe58SPierre Ossman #define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */ 242da7fbe58SPierre Ossman /* (CMD32,33,34,35,36,37,38,39) */ 243da7fbe58SPierre Ossman #define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */ 244da7fbe58SPierre Ossman /* (CMD28,29,30) */ 245da7fbe58SPierre Ossman #define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */ 246da7fbe58SPierre Ossman /* (CMD16,CMD42) */ 247da7fbe58SPierre Ossman #define CCC_APP_SPEC (1<<8) /* (8) Application specific */ 248da7fbe58SPierre Ossman /* (CMD55,56,57,ACMD*) */ 249da7fbe58SPierre Ossman #define CCC_IO_MODE (1<<9) /* (9) I/O mode */ 250da7fbe58SPierre Ossman /* (CMD5,39,40,52,53) */ 251da7fbe58SPierre Ossman #define CCC_SWITCH (1<<10) /* (10) High speed switch */ 252da7fbe58SPierre Ossman /* (CMD6,34,35,36,37,50) */ 253da7fbe58SPierre Ossman /* (11) Reserved */ 254da7fbe58SPierre Ossman /* (CMD?) */ 255da7fbe58SPierre Ossman 256da7fbe58SPierre Ossman /* 257da7fbe58SPierre Ossman * CSD field definitions 258da7fbe58SPierre Ossman */ 259da7fbe58SPierre Ossman 260da7fbe58SPierre Ossman #define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */ 261da7fbe58SPierre Ossman #define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */ 262da7fbe58SPierre Ossman #define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */ 263da7fbe58SPierre Ossman #define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */ 264da7fbe58SPierre Ossman 265da7fbe58SPierre Ossman #define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */ 266da7fbe58SPierre Ossman #define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */ 267da7fbe58SPierre Ossman #define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */ 268da7fbe58SPierre Ossman #define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */ 269da7fbe58SPierre Ossman #define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */ 270da7fbe58SPierre Ossman 271da7fbe58SPierre Ossman /* 272da7fbe58SPierre Ossman * EXT_CSD fields 273da7fbe58SPierre Ossman */ 274da7fbe58SPierre Ossman 275881d1c25SSeungwon Jeon #define EXT_CSD_FLUSH_CACHE 32 /* W */ 276881d1c25SSeungwon Jeon #define EXT_CSD_CACHE_CTRL 33 /* R/W */ 277bec8726aSGirish K S #define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */ 278abd9ac14SSeungwon Jeon #define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */ 279abd9ac14SSeungwon Jeon #define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */ 280abd9ac14SSeungwon Jeon #define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */ 281abd9ac14SSeungwon Jeon #define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */ 2824265900eSSaugata Das #define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */ 283e0c368d5SNamjae Jeon #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ 28469803d4fSGrégory Soutadé #define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */ 285709de99dSChuanxiao Dong #define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */ 286709de99dSChuanxiao Dong #define EXT_CSD_PARTITION_SUPPORT 160 /* RO */ 287eb0d8f13SJaehoon Chung #define EXT_CSD_HPI_MGMT 161 /* R/W */ 288b2499518SAdrian Hunter #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ 289950d56acSJaehoon Chung #define EXT_CSD_BKOPS_EN 163 /* R/W */ 290950d56acSJaehoon Chung #define EXT_CSD_BKOPS_START 164 /* W */ 291d9ddd629SKyungmin Park #define EXT_CSD_SANITIZE_START 165 /* W */ 292f4c5522bSAndrei Warkentin #define EXT_CSD_WR_REL_PARAM 166 /* RO */ 293090d25feSLoic Pallardy #define EXT_CSD_RPMB_MULT 168 /* RO */ 294add710eaSJohan Rudholm #define EXT_CSD_BOOT_WP 173 /* R/W */ 295dfe86cbaSAdrian Hunter #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ 296371a689fSAndrei Warkentin #define EXT_CSD_PART_CONFIG 179 /* R/W */ 297dfe86cbaSAdrian Hunter #define EXT_CSD_ERASED_MEM_CONT 181 /* RO */ 298da7fbe58SPierre Ossman #define EXT_CSD_BUS_WIDTH 183 /* R/W */ 299da7fbe58SPierre Ossman #define EXT_CSD_HS_TIMING 185 /* R/W */ 300b87d8dbfSGirish K S #define EXT_CSD_POWER_CLASS 187 /* R/W */ 301d7604d76SPierre Ossman #define EXT_CSD_REV 192 /* RO */ 302dfe86cbaSAdrian Hunter #define EXT_CSD_STRUCTURE 194 /* RO */ 303dfe86cbaSAdrian Hunter #define EXT_CSD_CARD_TYPE 196 /* RO */ 304eb0d8f13SJaehoon Chung #define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */ 305371a689fSAndrei Warkentin #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */ 306b87d8dbfSGirish K S #define EXT_CSD_PWR_CL_52_195 200 /* RO */ 307b87d8dbfSGirish K S #define EXT_CSD_PWR_CL_26_195 201 /* RO */ 308b87d8dbfSGirish K S #define EXT_CSD_PWR_CL_52_360 202 /* RO */ 309b87d8dbfSGirish K S #define EXT_CSD_PWR_CL_26_360 203 /* RO */ 310da7fbe58SPierre Ossman #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ 311dfe86cbaSAdrian Hunter #define EXT_CSD_S_A_TIMEOUT 217 /* RO */ 312f4c5522bSAndrei Warkentin #define EXT_CSD_REL_WR_SEC_C 222 /* RO */ 313709de99dSChuanxiao Dong #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ 314dfe86cbaSAdrian Hunter #define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */ 315dfe86cbaSAdrian Hunter #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ 316371a689fSAndrei Warkentin #define EXT_CSD_BOOT_MULT 226 /* RO */ 317dfe86cbaSAdrian Hunter #define EXT_CSD_SEC_TRIM_MULT 229 /* RO */ 318dfe86cbaSAdrian Hunter #define EXT_CSD_SEC_ERASE_MULT 230 /* RO */ 319dfe86cbaSAdrian Hunter #define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ 320dfe86cbaSAdrian Hunter #define EXT_CSD_TRIM_MULT 232 /* RO */ 321b87d8dbfSGirish K S #define EXT_CSD_PWR_CL_200_195 236 /* RO */ 322b87d8dbfSGirish K S #define EXT_CSD_PWR_CL_200_360 237 /* RO */ 323b87d8dbfSGirish K S #define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */ 324b87d8dbfSGirish K S #define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */ 325950d56acSJaehoon Chung #define EXT_CSD_BKOPS_STATUS 246 /* RO */ 326b87d8dbfSGirish K S #define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */ 327b23cf0bdSSeungwon Jeon #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ 328881d1c25SSeungwon Jeon #define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ 3290a5b6438SSeungwon Jeon #define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */ 3304265900eSSaugata Das #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ 3314265900eSSaugata Das #define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */ 332abd9ac14SSeungwon Jeon #define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */ 333abd9ac14SSeungwon Jeon #define EXT_CSD_MAX_PACKED_READS 501 /* RO */ 334950d56acSJaehoon Chung #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ 335eb0d8f13SJaehoon Chung #define EXT_CSD_HPI_FEATURES 503 /* RO */ 336da7fbe58SPierre Ossman 337da7fbe58SPierre Ossman /* 338da7fbe58SPierre Ossman * EXT_CSD field definitions 339da7fbe58SPierre Ossman */ 340da7fbe58SPierre Ossman 341f4c5522bSAndrei Warkentin #define EXT_CSD_WR_REL_PARAM_EN (1<<2) 342f4c5522bSAndrei Warkentin 343add710eaSJohan Rudholm #define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40) 344add710eaSJohan Rudholm #define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10) 345add710eaSJohan Rudholm #define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04) 346add710eaSJohan Rudholm #define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01) 347add710eaSJohan Rudholm 348371a689fSAndrei Warkentin #define EXT_CSD_PART_CONFIG_ACC_MASK (0x7) 349371a689fSAndrei Warkentin #define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1) 350090d25feSLoic Pallardy #define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3) 351e0c368d5SNamjae Jeon #define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4) 352e0c368d5SNamjae Jeon 35369803d4fSGrégory Soutadé #define EXT_CSD_PART_SETTING_COMPLETED (0x1) 354e0c368d5SNamjae Jeon #define EXT_CSD_PART_SUPPORT_PART_EN (0x1) 355371a689fSAndrei Warkentin 356da7fbe58SPierre Ossman #define EXT_CSD_CMD_SET_NORMAL (1<<0) 357da7fbe58SPierre Ossman #define EXT_CSD_CMD_SET_SECURE (1<<1) 358da7fbe58SPierre Ossman #define EXT_CSD_CMD_SET_CPSECURE (1<<2) 359da7fbe58SPierre Ossman 3602415c0efSSeungwon Jeon #define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */ 3612415c0efSSeungwon Jeon #define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */ 3622415c0efSSeungwon Jeon #define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \ 3632415c0efSSeungwon Jeon EXT_CSD_CARD_TYPE_HS_52) 364dfc13e84SHanumath Prasad #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */ 365dfc13e84SHanumath Prasad /* DDR mode @1.8V or 3V I/O */ 366dfc13e84SHanumath Prasad #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */ 367dfc13e84SHanumath Prasad /* DDR mode @1.2V I/O */ 368dfc13e84SHanumath Prasad #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ 369dfc13e84SHanumath Prasad | EXT_CSD_CARD_TYPE_DDR_1_2V) 3702415c0efSSeungwon Jeon #define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */ 3712415c0efSSeungwon Jeon #define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */ 372a4924c71SGirish K S /* SDR mode @1.2V I/O */ 3732415c0efSSeungwon Jeon #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ 3742415c0efSSeungwon Jeon EXT_CSD_CARD_TYPE_HS200_1_2V) 3750a5b6438SSeungwon Jeon #define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */ 3760a5b6438SSeungwon Jeon #define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */ 3770a5b6438SSeungwon Jeon #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ 3780a5b6438SSeungwon Jeon EXT_CSD_CARD_TYPE_HS400_1_2V) 379a4924c71SGirish K S 380da7fbe58SPierre Ossman #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 381da7fbe58SPierre Ossman #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 382da7fbe58SPierre Ossman #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 383dfc13e84SHanumath Prasad #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ 384dfc13e84SHanumath Prasad #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ 385da7fbe58SPierre Ossman 386577fb131SSeungwon Jeon #define EXT_CSD_TIMING_BC 0 /* Backwards compatility */ 387577fb131SSeungwon Jeon #define EXT_CSD_TIMING_HS 1 /* High speed */ 388577fb131SSeungwon Jeon #define EXT_CSD_TIMING_HS200 2 /* HS200 */ 3890a5b6438SSeungwon Jeon #define EXT_CSD_TIMING_HS400 3 /* HS400 */ 390577fb131SSeungwon Jeon 391dfe86cbaSAdrian Hunter #define EXT_CSD_SEC_ER_EN BIT(0) 392dfe86cbaSAdrian Hunter #define EXT_CSD_SEC_BD_BLK_EN BIT(2) 393dfe86cbaSAdrian Hunter #define EXT_CSD_SEC_GB_CL_EN BIT(4) 394d9ddd629SKyungmin Park #define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */ 395dfe86cbaSAdrian Hunter 396b2499518SAdrian Hunter #define EXT_CSD_RST_N_EN_MASK 0x3 397b2499518SAdrian Hunter #define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */ 398b2499518SAdrian Hunter 399bec8726aSGirish K S #define EXT_CSD_NO_POWER_NOTIFICATION 0 400bec8726aSGirish K S #define EXT_CSD_POWER_ON 1 401bec8726aSGirish K S #define EXT_CSD_POWER_OFF_SHORT 2 402bec8726aSGirish K S #define EXT_CSD_POWER_OFF_LONG 3 403bec8726aSGirish K S 404b87d8dbfSGirish K S #define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */ 405b87d8dbfSGirish K S #define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */ 406b87d8dbfSGirish K S #define EXT_CSD_PWR_CL_8BIT_SHIFT 4 407b87d8dbfSGirish K S #define EXT_CSD_PWR_CL_4BIT_SHIFT 0 408abd9ac14SSeungwon Jeon 409abd9ac14SSeungwon Jeon #define EXT_CSD_PACKED_EVENT_EN BIT(3) 410abd9ac14SSeungwon Jeon 411da7fbe58SPierre Ossman /* 412950d56acSJaehoon Chung * EXCEPTION_EVENT_STATUS field 413950d56acSJaehoon Chung */ 414950d56acSJaehoon Chung #define EXT_CSD_URGENT_BKOPS BIT(0) 415950d56acSJaehoon Chung #define EXT_CSD_DYNCAP_NEEDED BIT(1) 416950d56acSJaehoon Chung #define EXT_CSD_SYSPOOL_EXHAUSTED BIT(2) 417950d56acSJaehoon Chung #define EXT_CSD_PACKED_FAILURE BIT(3) 418950d56acSJaehoon Chung 419abd9ac14SSeungwon Jeon #define EXT_CSD_PACKED_GENERIC_ERROR BIT(0) 420abd9ac14SSeungwon Jeon #define EXT_CSD_PACKED_INDEXED_ERROR BIT(1) 421abd9ac14SSeungwon Jeon 422950d56acSJaehoon Chung /* 423950d56acSJaehoon Chung * BKOPS status level 424950d56acSJaehoon Chung */ 425950d56acSJaehoon Chung #define EXT_CSD_BKOPS_LEVEL_2 0x2 426950d56acSJaehoon Chung 427950d56acSJaehoon Chung /* 428da7fbe58SPierre Ossman * MMC_SWITCH access modes 429da7fbe58SPierre Ossman */ 430da7fbe58SPierre Ossman 431da7fbe58SPierre Ossman #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 432da7fbe58SPierre Ossman #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */ 433da7fbe58SPierre Ossman #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */ 434da7fbe58SPierre Ossman #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ 435da7fbe58SPierre Ossman 436100e9186SRobert P. J. Day #endif /* LINUX_MMC_MMC_H */ 437