1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_QP_H 34 #define MLX5_QP_H 35 36 #include <linux/mlx5/device.h> 37 #include <linux/mlx5/driver.h> 38 39 #define MLX5_INVALID_LKEY 0x100 40 /* UMR (3 WQE_BB's) + SIG (3 WQE_BB's) + PSV (mem) + PSV (wire) */ 41 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 8) 42 #define MLX5_DIF_SIZE 8 43 #define MLX5_STRIDE_BLOCK_OP 0x400 44 #define MLX5_CPY_GRD_MASK 0xc0 45 #define MLX5_CPY_APP_MASK 0x30 46 #define MLX5_CPY_REF_MASK 0x0f 47 #define MLX5_BSF_INC_REFTAG (1 << 6) 48 #define MLX5_BSF_INL_VALID (1 << 15) 49 #define MLX5_BSF_REFRESH_DIF (1 << 14) 50 #define MLX5_BSF_REPEAT_BLOCK (1 << 7) 51 #define MLX5_BSF_APPTAG_ESCAPE 0x1 52 #define MLX5_BSF_APPREF_ESCAPE 0x2 53 54 enum mlx5_qp_optpar { 55 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 56 MLX5_QP_OPTPAR_RRE = 1 << 1, 57 MLX5_QP_OPTPAR_RAE = 1 << 2, 58 MLX5_QP_OPTPAR_RWE = 1 << 3, 59 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 60 MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 61 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 62 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 63 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 64 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 65 MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 66 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 67 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 68 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 69 MLX5_QP_OPTPAR_LAG_TX_AFF = 1 << 15, 70 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 71 MLX5_QP_OPTPAR_SRQN = 1 << 18, 72 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 73 MLX5_QP_OPTPAR_DC_HS = 1 << 20, 74 MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 75 MLX5_QP_OPTPAR_COUNTER_SET_ID = 1 << 25, 76 }; 77 78 enum mlx5_qp_state { 79 MLX5_QP_STATE_RST = 0, 80 MLX5_QP_STATE_INIT = 1, 81 MLX5_QP_STATE_RTR = 2, 82 MLX5_QP_STATE_RTS = 3, 83 MLX5_QP_STATE_SQER = 4, 84 MLX5_QP_STATE_SQD = 5, 85 MLX5_QP_STATE_ERR = 6, 86 MLX5_QP_STATE_SQ_DRAINING = 7, 87 MLX5_QP_STATE_SUSPENDED = 9, 88 MLX5_QP_NUM_STATE, 89 MLX5_QP_STATE, 90 MLX5_QP_STATE_BAD, 91 }; 92 93 enum { 94 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1, 95 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1, 96 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1, 97 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1, 98 }; 99 100 enum { 101 MLX5_QP_ST_RC = 0x0, 102 MLX5_QP_ST_UC = 0x1, 103 MLX5_QP_ST_UD = 0x2, 104 MLX5_QP_ST_XRC = 0x3, 105 MLX5_QP_ST_MLX = 0x4, 106 MLX5_QP_ST_DCI = 0x5, 107 MLX5_QP_ST_DCT = 0x6, 108 MLX5_QP_ST_QP0 = 0x7, 109 MLX5_QP_ST_QP1 = 0x8, 110 MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 111 MLX5_QP_ST_RAW_IPV6 = 0xa, 112 MLX5_QP_ST_SNIFFER = 0xb, 113 MLX5_QP_ST_SYNC_UMR = 0xe, 114 MLX5_QP_ST_PTP_1588 = 0xd, 115 MLX5_QP_ST_REG_UMR = 0xc, 116 MLX5_QP_ST_MAX 117 }; 118 119 enum { 120 MLX5_QP_PM_MIGRATED = 0x3, 121 MLX5_QP_PM_ARMED = 0x0, 122 MLX5_QP_PM_REARM = 0x1 123 }; 124 125 enum { 126 MLX5_NON_ZERO_RQ = 0x0, 127 MLX5_SRQ_RQ = 0x1, 128 MLX5_CRQ_RQ = 0x2, 129 MLX5_ZERO_LEN_RQ = 0x3 130 }; 131 132 /* TODO REM */ 133 enum { 134 /* params1 */ 135 MLX5_QP_BIT_SRE = 1 << 15, 136 MLX5_QP_BIT_SWE = 1 << 14, 137 MLX5_QP_BIT_SAE = 1 << 13, 138 /* params2 */ 139 MLX5_QP_BIT_RRE = 1 << 15, 140 MLX5_QP_BIT_RWE = 1 << 14, 141 MLX5_QP_BIT_RAE = 1 << 13, 142 MLX5_QP_BIT_RIC = 1 << 4, 143 MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2, 144 MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1, 145 MLX5_QP_BIT_CC_MASTER = 1 << 0 146 }; 147 148 enum { 149 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 150 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2, 151 MLX5_WQE_CTRL_SOLICITED = 1 << 1, 152 }; 153 154 enum { 155 MLX5_SEND_WQE_DS = 16, 156 MLX5_SEND_WQE_BB = 64, 157 }; 158 159 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS) 160 161 enum { 162 MLX5_SEND_WQE_MAX_WQEBBS = 16, 163 }; 164 165 enum { 166 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 167 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 168 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 169 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 170 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 171 }; 172 173 enum { 174 MLX5_FENCE_MODE_NONE = 0 << 5, 175 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 176 MLX5_FENCE_MODE_FENCE = 2 << 5, 177 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 178 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 179 }; 180 181 enum { 182 MLX5_RCV_DBR = 0, 183 MLX5_SND_DBR = 1, 184 }; 185 186 enum { 187 MLX5_FLAGS_INLINE = 1<<7, 188 MLX5_FLAGS_CHECK_FREE = 1<<5, 189 }; 190 191 struct mlx5_wqe_fmr_seg { 192 __be32 flags; 193 __be32 mem_key; 194 __be64 buf_list; 195 __be64 start_addr; 196 __be64 reg_len; 197 __be32 offset; 198 __be32 page_size; 199 u32 reserved[2]; 200 }; 201 202 struct mlx5_wqe_ctrl_seg { 203 __be32 opmod_idx_opcode; 204 __be32 qpn_ds; 205 u8 signature; 206 u8 rsvd[2]; 207 u8 fm_ce_se; 208 union { 209 __be32 general_id; 210 __be32 imm; 211 __be32 umr_mkey; 212 __be32 tisn; 213 }; 214 }; 215 216 #define MLX5_WQE_CTRL_DS_MASK 0x3f 217 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00 218 #define MLX5_WQE_CTRL_QPN_SHIFT 8 219 #define MLX5_WQE_DS_UNITS 16 220 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff 221 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00 222 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8 223 224 enum { 225 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4, 226 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5, 227 MLX5_ETH_WQE_L3_CSUM = 1 << 6, 228 MLX5_ETH_WQE_L4_CSUM = 1 << 7, 229 }; 230 231 enum { 232 MLX5_ETH_WQE_SVLAN = 1 << 0, 233 MLX5_ETH_WQE_TRAILER_HDR_OUTER_IP_ASSOC = 1 << 26, 234 MLX5_ETH_WQE_TRAILER_HDR_OUTER_L4_ASSOC = 1 << 27, 235 MLX5_ETH_WQE_TRAILER_HDR_INNER_IP_ASSOC = 3 << 26, 236 MLX5_ETH_WQE_TRAILER_HDR_INNER_L4_ASSOC = 1 << 28, 237 MLX5_ETH_WQE_INSERT_TRAILER = 1 << 30, 238 MLX5_ETH_WQE_INSERT_VLAN = 1 << 15, 239 }; 240 241 enum { 242 MLX5_ETH_WQE_SWP_INNER_L3_IPV6 = 1 << 0, 243 MLX5_ETH_WQE_SWP_INNER_L4_UDP = 1 << 1, 244 MLX5_ETH_WQE_SWP_OUTER_L3_IPV6 = 1 << 4, 245 MLX5_ETH_WQE_SWP_OUTER_L4_UDP = 1 << 5, 246 }; 247 248 struct mlx5_wqe_eth_seg { 249 u8 swp_outer_l4_offset; 250 u8 swp_outer_l3_offset; 251 u8 swp_inner_l4_offset; 252 u8 swp_inner_l3_offset; 253 u8 cs_flags; 254 u8 swp_flags; 255 __be16 mss; 256 __be32 rsvd2; 257 union { 258 struct { 259 __be16 sz; 260 u8 start[2]; 261 } inline_hdr; 262 struct { 263 __be16 type; 264 __be16 vlan_tci; 265 } insert; 266 __be32 trailer; 267 }; 268 }; 269 270 struct mlx5_wqe_xrc_seg { 271 __be32 xrc_srqn; 272 u8 rsvd[12]; 273 }; 274 275 struct mlx5_wqe_masked_atomic_seg { 276 __be64 swap_add; 277 __be64 compare; 278 __be64 swap_add_mask; 279 __be64 compare_mask; 280 }; 281 282 struct mlx5_base_av { 283 union { 284 struct { 285 __be32 qkey; 286 __be32 reserved; 287 } qkey; 288 __be64 dc_key; 289 } key; 290 __be32 dqp_dct; 291 u8 stat_rate_sl; 292 u8 fl_mlid; 293 union { 294 __be16 rlid; 295 __be16 udp_sport; 296 }; 297 }; 298 299 struct mlx5_av { 300 union { 301 struct { 302 __be32 qkey; 303 __be32 reserved; 304 } qkey; 305 __be64 dc_key; 306 } key; 307 __be32 dqp_dct; 308 u8 stat_rate_sl; 309 u8 fl_mlid; 310 union { 311 __be16 rlid; 312 __be16 udp_sport; 313 }; 314 u8 reserved0[4]; 315 u8 rmac[6]; 316 u8 tclass; 317 u8 hop_limit; 318 __be32 grh_gid_fl; 319 u8 rgid[16]; 320 }; 321 322 struct mlx5_ib_ah { 323 struct ib_ah ibah; 324 struct mlx5_av av; 325 u8 xmit_port; 326 }; 327 328 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) 329 { 330 return container_of(ibah, struct mlx5_ib_ah, ibah); 331 } 332 333 struct mlx5_wqe_datagram_seg { 334 struct mlx5_av av; 335 }; 336 337 struct mlx5_wqe_raddr_seg { 338 __be64 raddr; 339 __be32 rkey; 340 u32 reserved; 341 }; 342 343 struct mlx5_wqe_atomic_seg { 344 __be64 swap_add; 345 __be64 compare; 346 }; 347 348 struct mlx5_wqe_data_seg { 349 __be32 byte_count; 350 __be32 lkey; 351 __be64 addr; 352 }; 353 354 struct mlx5_wqe_umr_ctrl_seg { 355 u8 flags; 356 u8 rsvd0[3]; 357 __be16 xlt_octowords; 358 union { 359 __be16 xlt_offset; 360 __be16 bsf_octowords; 361 }; 362 __be64 mkey_mask; 363 __be32 xlt_offset_47_16; 364 u8 rsvd1[28]; 365 }; 366 367 struct mlx5_seg_set_psv { 368 __be32 psv_num; 369 __be16 syndrome; 370 __be16 status; 371 __be32 transient_sig; 372 __be32 ref_tag; 373 }; 374 375 struct mlx5_seg_get_psv { 376 u8 rsvd[19]; 377 u8 num_psv; 378 __be32 l_key; 379 __be64 va; 380 __be32 psv_index[4]; 381 }; 382 383 struct mlx5_seg_check_psv { 384 u8 rsvd0[2]; 385 __be16 err_coalescing_op; 386 u8 rsvd1[2]; 387 __be16 xport_err_op; 388 u8 rsvd2[2]; 389 __be16 xport_err_mask; 390 u8 rsvd3[7]; 391 u8 num_psv; 392 __be32 l_key; 393 __be64 va; 394 __be32 psv_index[4]; 395 }; 396 397 struct mlx5_rwqe_sig { 398 u8 rsvd0[4]; 399 u8 signature; 400 u8 rsvd1[11]; 401 }; 402 403 struct mlx5_wqe_signature_seg { 404 u8 rsvd0[4]; 405 u8 signature; 406 u8 rsvd1[11]; 407 }; 408 409 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff 410 411 struct mlx5_wqe_inline_seg { 412 __be32 byte_count; 413 __be32 data[]; 414 }; 415 416 enum mlx5_sig_type { 417 MLX5_DIF_CRC = 0x1, 418 MLX5_DIF_IPCS = 0x2, 419 }; 420 421 struct mlx5_bsf_inl { 422 __be16 vld_refresh; 423 __be16 dif_apptag; 424 __be32 dif_reftag; 425 u8 sig_type; 426 u8 rp_inv_seed; 427 u8 rsvd[3]; 428 u8 dif_inc_ref_guard_check; 429 __be16 dif_app_bitmask_check; 430 }; 431 432 struct mlx5_bsf { 433 struct mlx5_bsf_basic { 434 u8 bsf_size_sbs; 435 u8 check_byte_mask; 436 union { 437 u8 copy_byte_mask; 438 u8 bs_selector; 439 u8 rsvd_wflags; 440 } wire; 441 union { 442 u8 bs_selector; 443 u8 rsvd_mflags; 444 } mem; 445 __be32 raw_data_size; 446 __be32 w_bfs_psv; 447 __be32 m_bfs_psv; 448 } basic; 449 struct mlx5_bsf_ext { 450 __be32 t_init_gen_pro_size; 451 __be32 rsvd_epi_size; 452 __be32 w_tfs_psv; 453 __be32 m_tfs_psv; 454 } ext; 455 struct mlx5_bsf_inl w_inl; 456 struct mlx5_bsf_inl m_inl; 457 }; 458 459 struct mlx5_mtt { 460 __be64 ptag; 461 }; 462 463 struct mlx5_klm { 464 __be32 bcount; 465 __be32 key; 466 __be64 va; 467 }; 468 469 struct mlx5_stride_block_entry { 470 __be16 stride; 471 __be16 bcount; 472 __be32 key; 473 __be64 va; 474 }; 475 476 struct mlx5_stride_block_ctrl_seg { 477 __be32 bcount_per_cycle; 478 __be32 op; 479 __be32 repeat_count; 480 u16 rsvd; 481 __be16 num_entries; 482 }; 483 484 struct mlx5_core_qp { 485 struct mlx5_core_rsc_common common; /* must be first */ 486 void (*event) (struct mlx5_core_qp *, int); 487 int qpn; 488 struct mlx5_rsc_debug *dbg; 489 int pid; 490 u16 uid; 491 }; 492 493 struct mlx5_core_dct { 494 struct mlx5_core_qp mqp; 495 struct completion drained; 496 }; 497 498 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 499 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 500 501 static inline const char *mlx5_qp_type_str(int type) 502 { 503 switch (type) { 504 case MLX5_QP_ST_RC: return "RC"; 505 case MLX5_QP_ST_UC: return "C"; 506 case MLX5_QP_ST_UD: return "UD"; 507 case MLX5_QP_ST_XRC: return "XRC"; 508 case MLX5_QP_ST_MLX: return "MLX"; 509 case MLX5_QP_ST_QP0: return "QP0"; 510 case MLX5_QP_ST_QP1: return "QP1"; 511 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 512 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 513 case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 514 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 515 case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 516 case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 517 default: return "Invalid transport type"; 518 } 519 } 520 521 static inline const char *mlx5_qp_state_str(int state) 522 { 523 switch (state) { 524 case MLX5_QP_STATE_RST: 525 return "RST"; 526 case MLX5_QP_STATE_INIT: 527 return "INIT"; 528 case MLX5_QP_STATE_RTR: 529 return "RTR"; 530 case MLX5_QP_STATE_RTS: 531 return "RTS"; 532 case MLX5_QP_STATE_SQER: 533 return "SQER"; 534 case MLX5_QP_STATE_SQD: 535 return "SQD"; 536 case MLX5_QP_STATE_ERR: 537 return "ERR"; 538 case MLX5_QP_STATE_SQ_DRAINING: 539 return "SQ_DRAINING"; 540 case MLX5_QP_STATE_SUSPENDED: 541 return "SUSPENDED"; 542 default: return "Invalid QP state"; 543 } 544 } 545 546 #endif /* MLX5_QP_H */ 547