xref: /openbmc/linux/include/linux/mlx5/mlx5_ifc.h (revision fa0a497b)
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34 
35 enum {
36 	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
37 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
38 	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
39 	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
40 	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
41 	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
42 	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
43 	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
44 	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
45 	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
46 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
47 	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
48 	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
49 	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
50 	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
51 	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
52 	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
53 	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
54 	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
57 	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
58 	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
59 	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
60 };
61 
62 enum {
63 	MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
64 	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
65 	MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
66 	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
67 };
68 
69 enum {
70 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
71 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
72 };
73 
74 enum {
75 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
76 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
77 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
78 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
79 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
80 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
81 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
82 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
83 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
84 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
85 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
86 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
87 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
88 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
89 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
90 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
91 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
92 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
93 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
94 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
95 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
96 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
97 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
98 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
99 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
100 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
101 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
102 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
103 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
104 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
105 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
106 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
107 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
108 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
109 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
110 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
111 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
112 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
113 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
114 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
115 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
116 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
117 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
118 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
119 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
120 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
121 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
122 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
123 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
124 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
125 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
126 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
127 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
128 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
129 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
130 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
131 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
132 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
133 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
134 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
135 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
136 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
137 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
138 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
139 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
140 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
141 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
142 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
143 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
144 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
145 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
146 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
147 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
148 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
149 	MLX5_CMD_OP_DETTACH_FROM_MCG              = 0x807,
150 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
151 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
152 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
153 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
154 	MLX5_CMD_OP_NOP                           = 0x80d,
155 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
156 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
157 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
158 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
159 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
160 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
161 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
162 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
163 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
164 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
165 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
166 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
167 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
168 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
169 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
170 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
171 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
172 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
173 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
174 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
175 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
176 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
177 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
178 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
179 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
180 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
181 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
182 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
183 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
184 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
185 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
186 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
187 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
188 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
189 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
190 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
191 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
192 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
193 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
194 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
195 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
196 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
197 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
198 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
199 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
200 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
201 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
202 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
203 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
204 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
205 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c
206 };
207 
208 struct mlx5_ifc_flow_table_fields_supported_bits {
209 	u8         outer_dmac[0x1];
210 	u8         outer_smac[0x1];
211 	u8         outer_ether_type[0x1];
212 	u8         reserved_at_3[0x1];
213 	u8         outer_first_prio[0x1];
214 	u8         outer_first_cfi[0x1];
215 	u8         outer_first_vid[0x1];
216 	u8         reserved_at_7[0x1];
217 	u8         outer_second_prio[0x1];
218 	u8         outer_second_cfi[0x1];
219 	u8         outer_second_vid[0x1];
220 	u8         reserved_at_b[0x1];
221 	u8         outer_sip[0x1];
222 	u8         outer_dip[0x1];
223 	u8         outer_frag[0x1];
224 	u8         outer_ip_protocol[0x1];
225 	u8         outer_ip_ecn[0x1];
226 	u8         outer_ip_dscp[0x1];
227 	u8         outer_udp_sport[0x1];
228 	u8         outer_udp_dport[0x1];
229 	u8         outer_tcp_sport[0x1];
230 	u8         outer_tcp_dport[0x1];
231 	u8         outer_tcp_flags[0x1];
232 	u8         outer_gre_protocol[0x1];
233 	u8         outer_gre_key[0x1];
234 	u8         outer_vxlan_vni[0x1];
235 	u8         reserved_at_1a[0x5];
236 	u8         source_eswitch_port[0x1];
237 
238 	u8         inner_dmac[0x1];
239 	u8         inner_smac[0x1];
240 	u8         inner_ether_type[0x1];
241 	u8         reserved_at_23[0x1];
242 	u8         inner_first_prio[0x1];
243 	u8         inner_first_cfi[0x1];
244 	u8         inner_first_vid[0x1];
245 	u8         reserved_at_27[0x1];
246 	u8         inner_second_prio[0x1];
247 	u8         inner_second_cfi[0x1];
248 	u8         inner_second_vid[0x1];
249 	u8         reserved_at_2b[0x1];
250 	u8         inner_sip[0x1];
251 	u8         inner_dip[0x1];
252 	u8         inner_frag[0x1];
253 	u8         inner_ip_protocol[0x1];
254 	u8         inner_ip_ecn[0x1];
255 	u8         inner_ip_dscp[0x1];
256 	u8         inner_udp_sport[0x1];
257 	u8         inner_udp_dport[0x1];
258 	u8         inner_tcp_sport[0x1];
259 	u8         inner_tcp_dport[0x1];
260 	u8         inner_tcp_flags[0x1];
261 	u8         reserved_at_37[0x9];
262 
263 	u8         reserved_at_40[0x40];
264 };
265 
266 struct mlx5_ifc_flow_table_prop_layout_bits {
267 	u8         ft_support[0x1];
268 	u8         reserved_at_1[0x2];
269 	u8	   flow_modify_en[0x1];
270 	u8         modify_root[0x1];
271 	u8         identified_miss_table_mode[0x1];
272 	u8         flow_table_modify[0x1];
273 	u8         reserved_at_7[0x19];
274 
275 	u8         reserved_at_20[0x2];
276 	u8         log_max_ft_size[0x6];
277 	u8         reserved_at_28[0x10];
278 	u8         max_ft_level[0x8];
279 
280 	u8         reserved_at_40[0x20];
281 
282 	u8         reserved_at_60[0x18];
283 	u8         log_max_ft_num[0x8];
284 
285 	u8         reserved_at_80[0x18];
286 	u8         log_max_destination[0x8];
287 
288 	u8         reserved_at_a0[0x18];
289 	u8         log_max_flow[0x8];
290 
291 	u8         reserved_at_c0[0x40];
292 
293 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
294 
295 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
296 };
297 
298 struct mlx5_ifc_odp_per_transport_service_cap_bits {
299 	u8         send[0x1];
300 	u8         receive[0x1];
301 	u8         write[0x1];
302 	u8         read[0x1];
303 	u8         reserved_at_4[0x1];
304 	u8         srq_receive[0x1];
305 	u8         reserved_at_6[0x1a];
306 };
307 
308 struct mlx5_ifc_ipv4_layout_bits {
309 	u8         reserved_at_0[0x60];
310 
311 	u8         ipv4[0x20];
312 };
313 
314 struct mlx5_ifc_ipv6_layout_bits {
315 	u8         ipv6[16][0x8];
316 };
317 
318 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
319 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
320 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
321 	u8         reserved_at_0[0x80];
322 };
323 
324 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
325 	u8         smac_47_16[0x20];
326 
327 	u8         smac_15_0[0x10];
328 	u8         ethertype[0x10];
329 
330 	u8         dmac_47_16[0x20];
331 
332 	u8         dmac_15_0[0x10];
333 	u8         first_prio[0x3];
334 	u8         first_cfi[0x1];
335 	u8         first_vid[0xc];
336 
337 	u8         ip_protocol[0x8];
338 	u8         ip_dscp[0x6];
339 	u8         ip_ecn[0x2];
340 	u8         vlan_tag[0x1];
341 	u8         reserved_at_91[0x1];
342 	u8         frag[0x1];
343 	u8         reserved_at_93[0x4];
344 	u8         tcp_flags[0x9];
345 
346 	u8         tcp_sport[0x10];
347 	u8         tcp_dport[0x10];
348 
349 	u8         reserved_at_c0[0x20];
350 
351 	u8         udp_sport[0x10];
352 	u8         udp_dport[0x10];
353 
354 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
355 
356 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
357 };
358 
359 struct mlx5_ifc_fte_match_set_misc_bits {
360 	u8         reserved_at_0[0x20];
361 
362 	u8         reserved_at_20[0x10];
363 	u8         source_port[0x10];
364 
365 	u8         outer_second_prio[0x3];
366 	u8         outer_second_cfi[0x1];
367 	u8         outer_second_vid[0xc];
368 	u8         inner_second_prio[0x3];
369 	u8         inner_second_cfi[0x1];
370 	u8         inner_second_vid[0xc];
371 
372 	u8         outer_second_vlan_tag[0x1];
373 	u8         inner_second_vlan_tag[0x1];
374 	u8         reserved_at_62[0xe];
375 	u8         gre_protocol[0x10];
376 
377 	u8         gre_key_h[0x18];
378 	u8         gre_key_l[0x8];
379 
380 	u8         vxlan_vni[0x18];
381 	u8         reserved_at_b8[0x8];
382 
383 	u8         reserved_at_c0[0x20];
384 
385 	u8         reserved_at_e0[0xc];
386 	u8         outer_ipv6_flow_label[0x14];
387 
388 	u8         reserved_at_100[0xc];
389 	u8         inner_ipv6_flow_label[0x14];
390 
391 	u8         reserved_at_120[0xe0];
392 };
393 
394 struct mlx5_ifc_cmd_pas_bits {
395 	u8         pa_h[0x20];
396 
397 	u8         pa_l[0x14];
398 	u8         reserved_at_34[0xc];
399 };
400 
401 struct mlx5_ifc_uint64_bits {
402 	u8         hi[0x20];
403 
404 	u8         lo[0x20];
405 };
406 
407 enum {
408 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
409 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
410 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
411 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
412 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
413 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
414 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
415 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
416 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
417 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
418 };
419 
420 struct mlx5_ifc_ads_bits {
421 	u8         fl[0x1];
422 	u8         free_ar[0x1];
423 	u8         reserved_at_2[0xe];
424 	u8         pkey_index[0x10];
425 
426 	u8         reserved_at_20[0x8];
427 	u8         grh[0x1];
428 	u8         mlid[0x7];
429 	u8         rlid[0x10];
430 
431 	u8         ack_timeout[0x5];
432 	u8         reserved_at_45[0x3];
433 	u8         src_addr_index[0x8];
434 	u8         reserved_at_50[0x4];
435 	u8         stat_rate[0x4];
436 	u8         hop_limit[0x8];
437 
438 	u8         reserved_at_60[0x4];
439 	u8         tclass[0x8];
440 	u8         flow_label[0x14];
441 
442 	u8         rgid_rip[16][0x8];
443 
444 	u8         reserved_at_100[0x4];
445 	u8         f_dscp[0x1];
446 	u8         f_ecn[0x1];
447 	u8         reserved_at_106[0x1];
448 	u8         f_eth_prio[0x1];
449 	u8         ecn[0x2];
450 	u8         dscp[0x6];
451 	u8         udp_sport[0x10];
452 
453 	u8         dei_cfi[0x1];
454 	u8         eth_prio[0x3];
455 	u8         sl[0x4];
456 	u8         port[0x8];
457 	u8         rmac_47_32[0x10];
458 
459 	u8         rmac_31_0[0x20];
460 };
461 
462 struct mlx5_ifc_flow_table_nic_cap_bits {
463 	u8         nic_rx_multi_path_tirs[0x1];
464 	u8         reserved_at_1[0x1ff];
465 
466 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
467 
468 	u8         reserved_at_400[0x200];
469 
470 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
471 
472 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
473 
474 	u8         reserved_at_a00[0x200];
475 
476 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
477 
478 	u8         reserved_at_e00[0x7200];
479 };
480 
481 struct mlx5_ifc_flow_table_eswitch_cap_bits {
482 	u8     reserved_at_0[0x200];
483 
484 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
485 
486 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
487 
488 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
489 
490 	u8      reserved_at_800[0x7800];
491 };
492 
493 struct mlx5_ifc_e_switch_cap_bits {
494 	u8         vport_svlan_strip[0x1];
495 	u8         vport_cvlan_strip[0x1];
496 	u8         vport_svlan_insert[0x1];
497 	u8         vport_cvlan_insert_if_not_exist[0x1];
498 	u8         vport_cvlan_insert_overwrite[0x1];
499 	u8         reserved_at_5[0x1b];
500 
501 	u8         reserved_at_20[0x7e0];
502 };
503 
504 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
505 	u8         csum_cap[0x1];
506 	u8         vlan_cap[0x1];
507 	u8         lro_cap[0x1];
508 	u8         lro_psh_flag[0x1];
509 	u8         lro_time_stamp[0x1];
510 	u8         reserved_at_5[0x3];
511 	u8         self_lb_en_modifiable[0x1];
512 	u8         reserved_at_9[0x2];
513 	u8         max_lso_cap[0x5];
514 	u8         reserved_at_10[0x4];
515 	u8         rss_ind_tbl_cap[0x4];
516 	u8         reserved_at_18[0x3];
517 	u8         tunnel_lso_const_out_ip_id[0x1];
518 	u8         reserved_at_1c[0x2];
519 	u8         tunnel_statless_gre[0x1];
520 	u8         tunnel_stateless_vxlan[0x1];
521 
522 	u8         reserved_at_20[0x20];
523 
524 	u8         reserved_at_40[0x10];
525 	u8         lro_min_mss_size[0x10];
526 
527 	u8         reserved_at_60[0x120];
528 
529 	u8         lro_timer_supported_periods[4][0x20];
530 
531 	u8         reserved_at_200[0x600];
532 };
533 
534 struct mlx5_ifc_roce_cap_bits {
535 	u8         roce_apm[0x1];
536 	u8         reserved_at_1[0x1f];
537 
538 	u8         reserved_at_20[0x60];
539 
540 	u8         reserved_at_80[0xc];
541 	u8         l3_type[0x4];
542 	u8         reserved_at_90[0x8];
543 	u8         roce_version[0x8];
544 
545 	u8         reserved_at_a0[0x10];
546 	u8         r_roce_dest_udp_port[0x10];
547 
548 	u8         r_roce_max_src_udp_port[0x10];
549 	u8         r_roce_min_src_udp_port[0x10];
550 
551 	u8         reserved_at_e0[0x10];
552 	u8         roce_address_table_size[0x10];
553 
554 	u8         reserved_at_100[0x700];
555 };
556 
557 enum {
558 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
559 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
560 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
561 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
562 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
563 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
564 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
565 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
566 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
567 };
568 
569 enum {
570 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
571 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
572 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
573 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
574 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
575 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
576 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
577 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
578 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
579 };
580 
581 struct mlx5_ifc_atomic_caps_bits {
582 	u8         reserved_at_0[0x40];
583 
584 	u8         atomic_req_8B_endianess_mode[0x2];
585 	u8         reserved_at_42[0x4];
586 	u8         supported_atomic_req_8B_endianess_mode_1[0x1];
587 
588 	u8         reserved_at_47[0x19];
589 
590 	u8         reserved_at_60[0x20];
591 
592 	u8         reserved_at_80[0x10];
593 	u8         atomic_operations[0x10];
594 
595 	u8         reserved_at_a0[0x10];
596 	u8         atomic_size_qp[0x10];
597 
598 	u8         reserved_at_c0[0x10];
599 	u8         atomic_size_dc[0x10];
600 
601 	u8         reserved_at_e0[0x720];
602 };
603 
604 struct mlx5_ifc_odp_cap_bits {
605 	u8         reserved_at_0[0x40];
606 
607 	u8         sig[0x1];
608 	u8         reserved_at_41[0x1f];
609 
610 	u8         reserved_at_60[0x20];
611 
612 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
613 
614 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
615 
616 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
617 
618 	u8         reserved_at_e0[0x720];
619 };
620 
621 struct mlx5_ifc_calc_op {
622 	u8        reserved_at_0[0x10];
623 	u8        reserved_at_10[0x9];
624 	u8        op_swap_endianness[0x1];
625 	u8        op_min[0x1];
626 	u8        op_xor[0x1];
627 	u8        op_or[0x1];
628 	u8        op_and[0x1];
629 	u8        op_max[0x1];
630 	u8        op_add[0x1];
631 };
632 
633 struct mlx5_ifc_vector_calc_cap_bits {
634 	u8         calc_matrix[0x1];
635 	u8         reserved_at_1[0x1f];
636 	u8         reserved_at_20[0x8];
637 	u8         max_vec_count[0x8];
638 	u8         reserved_at_30[0xd];
639 	u8         max_chunk_size[0x3];
640 	struct mlx5_ifc_calc_op calc0;
641 	struct mlx5_ifc_calc_op calc1;
642 	struct mlx5_ifc_calc_op calc2;
643 	struct mlx5_ifc_calc_op calc3;
644 
645 	u8         reserved_at_e0[0x720];
646 };
647 
648 enum {
649 	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
650 	MLX5_WQ_TYPE_CYCLIC       = 0x1,
651 	MLX5_WQ_TYPE_STRQ         = 0x2,
652 };
653 
654 enum {
655 	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
656 	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
657 };
658 
659 enum {
660 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
661 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
662 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
663 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
664 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
665 };
666 
667 enum {
668 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
669 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
670 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
671 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
672 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
673 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
674 };
675 
676 enum {
677 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
678 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
679 };
680 
681 enum {
682 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
683 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
684 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
685 };
686 
687 enum {
688 	MLX5_CAP_PORT_TYPE_IB  = 0x0,
689 	MLX5_CAP_PORT_TYPE_ETH = 0x1,
690 };
691 
692 struct mlx5_ifc_cmd_hca_cap_bits {
693 	u8         reserved_at_0[0x80];
694 
695 	u8         log_max_srq_sz[0x8];
696 	u8         log_max_qp_sz[0x8];
697 	u8         reserved_at_90[0xb];
698 	u8         log_max_qp[0x5];
699 
700 	u8         reserved_at_a0[0xb];
701 	u8         log_max_srq[0x5];
702 	u8         reserved_at_b0[0x10];
703 
704 	u8         reserved_at_c0[0x8];
705 	u8         log_max_cq_sz[0x8];
706 	u8         reserved_at_d0[0xb];
707 	u8         log_max_cq[0x5];
708 
709 	u8         log_max_eq_sz[0x8];
710 	u8         reserved_at_e8[0x2];
711 	u8         log_max_mkey[0x6];
712 	u8         reserved_at_f0[0xc];
713 	u8         log_max_eq[0x4];
714 
715 	u8         max_indirection[0x8];
716 	u8         reserved_at_108[0x1];
717 	u8         log_max_mrw_sz[0x7];
718 	u8         reserved_at_110[0x2];
719 	u8         log_max_bsf_list_size[0x6];
720 	u8         reserved_at_118[0x2];
721 	u8         log_max_klm_list_size[0x6];
722 
723 	u8         reserved_at_120[0xa];
724 	u8         log_max_ra_req_dc[0x6];
725 	u8         reserved_at_130[0xa];
726 	u8         log_max_ra_res_dc[0x6];
727 
728 	u8         reserved_at_140[0xa];
729 	u8         log_max_ra_req_qp[0x6];
730 	u8         reserved_at_150[0xa];
731 	u8         log_max_ra_res_qp[0x6];
732 
733 	u8         pad_cap[0x1];
734 	u8         cc_query_allowed[0x1];
735 	u8         cc_modify_allowed[0x1];
736 	u8         reserved_at_163[0xd];
737 	u8         gid_table_size[0x10];
738 
739 	u8         out_of_seq_cnt[0x1];
740 	u8         vport_counters[0x1];
741 	u8         reserved_at_182[0x4];
742 	u8         max_qp_cnt[0xa];
743 	u8         pkey_table_size[0x10];
744 
745 	u8         vport_group_manager[0x1];
746 	u8         vhca_group_manager[0x1];
747 	u8         ib_virt[0x1];
748 	u8         eth_virt[0x1];
749 	u8         reserved_at_1a4[0x1];
750 	u8         ets[0x1];
751 	u8         nic_flow_table[0x1];
752 	u8         eswitch_flow_table[0x1];
753 	u8	   early_vf_enable;
754 	u8         reserved_at_1a8[0x2];
755 	u8         local_ca_ack_delay[0x5];
756 	u8         reserved_at_1af[0x6];
757 	u8         port_type[0x2];
758 	u8         num_ports[0x8];
759 
760 	u8         reserved_at_1bf[0x3];
761 	u8         log_max_msg[0x5];
762 	u8         reserved_at_1c7[0x4];
763 	u8         max_tc[0x4];
764 	u8         reserved_at_1cf[0x6];
765 	u8         rol_s[0x1];
766 	u8         rol_g[0x1];
767 	u8         reserved_at_1d7[0x1];
768 	u8         wol_s[0x1];
769 	u8         wol_g[0x1];
770 	u8         wol_a[0x1];
771 	u8         wol_b[0x1];
772 	u8         wol_m[0x1];
773 	u8         wol_u[0x1];
774 	u8         wol_p[0x1];
775 
776 	u8         stat_rate_support[0x10];
777 	u8         reserved_at_1ef[0xc];
778 	u8         cqe_version[0x4];
779 
780 	u8         compact_address_vector[0x1];
781 	u8         reserved_at_200[0x3];
782 	u8         ipoib_basic_offloads[0x1];
783 	u8         reserved_at_204[0xa];
784 	u8         drain_sigerr[0x1];
785 	u8         cmdif_checksum[0x2];
786 	u8         sigerr_cqe[0x1];
787 	u8         reserved_at_212[0x1];
788 	u8         wq_signature[0x1];
789 	u8         sctr_data_cqe[0x1];
790 	u8         reserved_at_215[0x1];
791 	u8         sho[0x1];
792 	u8         tph[0x1];
793 	u8         rf[0x1];
794 	u8         dct[0x1];
795 	u8         reserved_at_21a[0x1];
796 	u8         eth_net_offloads[0x1];
797 	u8         roce[0x1];
798 	u8         atomic[0x1];
799 	u8         reserved_at_21e[0x1];
800 
801 	u8         cq_oi[0x1];
802 	u8         cq_resize[0x1];
803 	u8         cq_moderation[0x1];
804 	u8         reserved_at_222[0x3];
805 	u8         cq_eq_remap[0x1];
806 	u8         pg[0x1];
807 	u8         block_lb_mc[0x1];
808 	u8         reserved_at_228[0x1];
809 	u8         scqe_break_moderation[0x1];
810 	u8         reserved_at_22a[0x1];
811 	u8         cd[0x1];
812 	u8         reserved_at_22c[0x1];
813 	u8         apm[0x1];
814 	u8         vector_calc[0x1];
815 	u8         reserved_at_22f[0x1];
816 	u8	   imaicl[0x1];
817 	u8         reserved_at_231[0x4];
818 	u8         qkv[0x1];
819 	u8         pkv[0x1];
820 	u8         set_deth_sqpn[0x1];
821 	u8         reserved_at_239[0x3];
822 	u8         xrc[0x1];
823 	u8         ud[0x1];
824 	u8         uc[0x1];
825 	u8         rc[0x1];
826 
827 	u8         reserved_at_23f[0xa];
828 	u8         uar_sz[0x6];
829 	u8         reserved_at_24f[0x8];
830 	u8         log_pg_sz[0x8];
831 
832 	u8         bf[0x1];
833 	u8         reserved_at_260[0x1];
834 	u8         pad_tx_eth_packet[0x1];
835 	u8         reserved_at_262[0x8];
836 	u8         log_bf_reg_size[0x5];
837 	u8         reserved_at_26f[0x10];
838 
839 	u8         reserved_at_27f[0x10];
840 	u8         max_wqe_sz_sq[0x10];
841 
842 	u8         reserved_at_29f[0x10];
843 	u8         max_wqe_sz_rq[0x10];
844 
845 	u8         reserved_at_2bf[0x10];
846 	u8         max_wqe_sz_sq_dc[0x10];
847 
848 	u8         reserved_at_2df[0x7];
849 	u8         max_qp_mcg[0x19];
850 
851 	u8         reserved_at_2ff[0x18];
852 	u8         log_max_mcg[0x8];
853 
854 	u8         reserved_at_31f[0x3];
855 	u8         log_max_transport_domain[0x5];
856 	u8         reserved_at_327[0x3];
857 	u8         log_max_pd[0x5];
858 	u8         reserved_at_32f[0xb];
859 	u8         log_max_xrcd[0x5];
860 
861 	u8         reserved_at_33f[0x20];
862 
863 	u8         reserved_at_35f[0x3];
864 	u8         log_max_rq[0x5];
865 	u8         reserved_at_367[0x3];
866 	u8         log_max_sq[0x5];
867 	u8         reserved_at_36f[0x3];
868 	u8         log_max_tir[0x5];
869 	u8         reserved_at_377[0x3];
870 	u8         log_max_tis[0x5];
871 
872 	u8         basic_cyclic_rcv_wqe[0x1];
873 	u8         reserved_at_380[0x2];
874 	u8         log_max_rmp[0x5];
875 	u8         reserved_at_387[0x3];
876 	u8         log_max_rqt[0x5];
877 	u8         reserved_at_38f[0x3];
878 	u8         log_max_rqt_size[0x5];
879 	u8         reserved_at_397[0x3];
880 	u8         log_max_tis_per_sq[0x5];
881 
882 	u8         reserved_at_39f[0x3];
883 	u8         log_max_stride_sz_rq[0x5];
884 	u8         reserved_at_3a7[0x3];
885 	u8         log_min_stride_sz_rq[0x5];
886 	u8         reserved_at_3af[0x3];
887 	u8         log_max_stride_sz_sq[0x5];
888 	u8         reserved_at_3b7[0x3];
889 	u8         log_min_stride_sz_sq[0x5];
890 
891 	u8         reserved_at_3bf[0x1b];
892 	u8         log_max_wq_sz[0x5];
893 
894 	u8         nic_vport_change_event[0x1];
895 	u8         reserved_at_3e0[0xa];
896 	u8         log_max_vlan_list[0x5];
897 	u8         reserved_at_3ef[0x3];
898 	u8         log_max_current_mc_list[0x5];
899 	u8         reserved_at_3f7[0x3];
900 	u8         log_max_current_uc_list[0x5];
901 
902 	u8         reserved_at_3ff[0x80];
903 
904 	u8         reserved_at_47f[0x3];
905 	u8         log_max_l2_table[0x5];
906 	u8         reserved_at_487[0x8];
907 	u8         log_uar_page_sz[0x10];
908 
909 	u8         reserved_at_49f[0x20];
910 	u8         device_frequency_mhz[0x20];
911 	u8         device_frequency_khz[0x20];
912 	u8         reserved_at_4ff[0x5f];
913 	u8         cqe_zip[0x1];
914 
915 	u8         cqe_zip_timeout[0x10];
916 	u8         cqe_zip_max_num[0x10];
917 
918 	u8         reserved_at_57f[0x220];
919 };
920 
921 enum mlx5_flow_destination_type {
922 	MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
923 	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
924 	MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
925 };
926 
927 struct mlx5_ifc_dest_format_struct_bits {
928 	u8         destination_type[0x8];
929 	u8         destination_id[0x18];
930 
931 	u8         reserved_at_20[0x20];
932 };
933 
934 struct mlx5_ifc_fte_match_param_bits {
935 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
936 
937 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
938 
939 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
940 
941 	u8         reserved_at_600[0xa00];
942 };
943 
944 enum {
945 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
946 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
947 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
948 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
949 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
950 };
951 
952 struct mlx5_ifc_rx_hash_field_select_bits {
953 	u8         l3_prot_type[0x1];
954 	u8         l4_prot_type[0x1];
955 	u8         selected_fields[0x1e];
956 };
957 
958 enum {
959 	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
960 	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
961 };
962 
963 enum {
964 	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
965 	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
966 };
967 
968 struct mlx5_ifc_wq_bits {
969 	u8         wq_type[0x4];
970 	u8         wq_signature[0x1];
971 	u8         end_padding_mode[0x2];
972 	u8         cd_slave[0x1];
973 	u8         reserved_at_8[0x18];
974 
975 	u8         hds_skip_first_sge[0x1];
976 	u8         log2_hds_buf_size[0x3];
977 	u8         reserved_at_24[0x7];
978 	u8         page_offset[0x5];
979 	u8         lwm[0x10];
980 
981 	u8         reserved_at_40[0x8];
982 	u8         pd[0x18];
983 
984 	u8         reserved_at_60[0x8];
985 	u8         uar_page[0x18];
986 
987 	u8         dbr_addr[0x40];
988 
989 	u8         hw_counter[0x20];
990 
991 	u8         sw_counter[0x20];
992 
993 	u8         reserved_at_100[0xc];
994 	u8         log_wq_stride[0x4];
995 	u8         reserved_at_110[0x3];
996 	u8         log_wq_pg_sz[0x5];
997 	u8         reserved_at_118[0x3];
998 	u8         log_wq_sz[0x5];
999 
1000 	u8         reserved_at_120[0x4e0];
1001 
1002 	struct mlx5_ifc_cmd_pas_bits pas[0];
1003 };
1004 
1005 struct mlx5_ifc_rq_num_bits {
1006 	u8         reserved_at_0[0x8];
1007 	u8         rq_num[0x18];
1008 };
1009 
1010 struct mlx5_ifc_mac_address_layout_bits {
1011 	u8         reserved_at_0[0x10];
1012 	u8         mac_addr_47_32[0x10];
1013 
1014 	u8         mac_addr_31_0[0x20];
1015 };
1016 
1017 struct mlx5_ifc_vlan_layout_bits {
1018 	u8         reserved_at_0[0x14];
1019 	u8         vlan[0x0c];
1020 
1021 	u8         reserved_at_20[0x20];
1022 };
1023 
1024 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1025 	u8         reserved_at_0[0xa0];
1026 
1027 	u8         min_time_between_cnps[0x20];
1028 
1029 	u8         reserved_at_c0[0x12];
1030 	u8         cnp_dscp[0x6];
1031 	u8         reserved_at_d8[0x5];
1032 	u8         cnp_802p_prio[0x3];
1033 
1034 	u8         reserved_at_e0[0x720];
1035 };
1036 
1037 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1038 	u8         reserved_at_0[0x60];
1039 
1040 	u8         reserved_at_60[0x4];
1041 	u8         clamp_tgt_rate[0x1];
1042 	u8         reserved_at_65[0x3];
1043 	u8         clamp_tgt_rate_after_time_inc[0x1];
1044 	u8         reserved_at_69[0x17];
1045 
1046 	u8         reserved_at_80[0x20];
1047 
1048 	u8         rpg_time_reset[0x20];
1049 
1050 	u8         rpg_byte_reset[0x20];
1051 
1052 	u8         rpg_threshold[0x20];
1053 
1054 	u8         rpg_max_rate[0x20];
1055 
1056 	u8         rpg_ai_rate[0x20];
1057 
1058 	u8         rpg_hai_rate[0x20];
1059 
1060 	u8         rpg_gd[0x20];
1061 
1062 	u8         rpg_min_dec_fac[0x20];
1063 
1064 	u8         rpg_min_rate[0x20];
1065 
1066 	u8         reserved_at_1c0[0xe0];
1067 
1068 	u8         rate_to_set_on_first_cnp[0x20];
1069 
1070 	u8         dce_tcp_g[0x20];
1071 
1072 	u8         dce_tcp_rtt[0x20];
1073 
1074 	u8         rate_reduce_monitor_period[0x20];
1075 
1076 	u8         reserved_at_320[0x20];
1077 
1078 	u8         initial_alpha_value[0x20];
1079 
1080 	u8         reserved_at_360[0x4a0];
1081 };
1082 
1083 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1084 	u8         reserved_at_0[0x80];
1085 
1086 	u8         rppp_max_rps[0x20];
1087 
1088 	u8         rpg_time_reset[0x20];
1089 
1090 	u8         rpg_byte_reset[0x20];
1091 
1092 	u8         rpg_threshold[0x20];
1093 
1094 	u8         rpg_max_rate[0x20];
1095 
1096 	u8         rpg_ai_rate[0x20];
1097 
1098 	u8         rpg_hai_rate[0x20];
1099 
1100 	u8         rpg_gd[0x20];
1101 
1102 	u8         rpg_min_dec_fac[0x20];
1103 
1104 	u8         rpg_min_rate[0x20];
1105 
1106 	u8         reserved_at_1c0[0x640];
1107 };
1108 
1109 enum {
1110 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1111 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1112 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1113 };
1114 
1115 struct mlx5_ifc_resize_field_select_bits {
1116 	u8         resize_field_select[0x20];
1117 };
1118 
1119 enum {
1120 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1121 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1122 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1123 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1124 };
1125 
1126 struct mlx5_ifc_modify_field_select_bits {
1127 	u8         modify_field_select[0x20];
1128 };
1129 
1130 struct mlx5_ifc_field_select_r_roce_np_bits {
1131 	u8         field_select_r_roce_np[0x20];
1132 };
1133 
1134 struct mlx5_ifc_field_select_r_roce_rp_bits {
1135 	u8         field_select_r_roce_rp[0x20];
1136 };
1137 
1138 enum {
1139 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1140 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1141 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1142 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1143 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1144 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1145 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1146 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1147 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1148 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1149 };
1150 
1151 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1152 	u8         field_select_8021qaurp[0x20];
1153 };
1154 
1155 struct mlx5_ifc_phys_layer_cntrs_bits {
1156 	u8         time_since_last_clear_high[0x20];
1157 
1158 	u8         time_since_last_clear_low[0x20];
1159 
1160 	u8         symbol_errors_high[0x20];
1161 
1162 	u8         symbol_errors_low[0x20];
1163 
1164 	u8         sync_headers_errors_high[0x20];
1165 
1166 	u8         sync_headers_errors_low[0x20];
1167 
1168 	u8         edpl_bip_errors_lane0_high[0x20];
1169 
1170 	u8         edpl_bip_errors_lane0_low[0x20];
1171 
1172 	u8         edpl_bip_errors_lane1_high[0x20];
1173 
1174 	u8         edpl_bip_errors_lane1_low[0x20];
1175 
1176 	u8         edpl_bip_errors_lane2_high[0x20];
1177 
1178 	u8         edpl_bip_errors_lane2_low[0x20];
1179 
1180 	u8         edpl_bip_errors_lane3_high[0x20];
1181 
1182 	u8         edpl_bip_errors_lane3_low[0x20];
1183 
1184 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
1185 
1186 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
1187 
1188 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
1189 
1190 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
1191 
1192 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
1193 
1194 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
1195 
1196 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
1197 
1198 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
1199 
1200 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1201 
1202 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1203 
1204 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1205 
1206 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1207 
1208 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1209 
1210 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1211 
1212 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1213 
1214 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1215 
1216 	u8         rs_fec_corrected_blocks_high[0x20];
1217 
1218 	u8         rs_fec_corrected_blocks_low[0x20];
1219 
1220 	u8         rs_fec_uncorrectable_blocks_high[0x20];
1221 
1222 	u8         rs_fec_uncorrectable_blocks_low[0x20];
1223 
1224 	u8         rs_fec_no_errors_blocks_high[0x20];
1225 
1226 	u8         rs_fec_no_errors_blocks_low[0x20];
1227 
1228 	u8         rs_fec_single_error_blocks_high[0x20];
1229 
1230 	u8         rs_fec_single_error_blocks_low[0x20];
1231 
1232 	u8         rs_fec_corrected_symbols_total_high[0x20];
1233 
1234 	u8         rs_fec_corrected_symbols_total_low[0x20];
1235 
1236 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
1237 
1238 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
1239 
1240 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
1241 
1242 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
1243 
1244 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
1245 
1246 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
1247 
1248 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
1249 
1250 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
1251 
1252 	u8         link_down_events[0x20];
1253 
1254 	u8         successful_recovery_events[0x20];
1255 
1256 	u8         reserved_at_640[0x180];
1257 };
1258 
1259 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1260 	u8	   symbol_error_counter[0x10];
1261 
1262 	u8         link_error_recovery_counter[0x8];
1263 
1264 	u8         link_downed_counter[0x8];
1265 
1266 	u8         port_rcv_errors[0x10];
1267 
1268 	u8         port_rcv_remote_physical_errors[0x10];
1269 
1270 	u8         port_rcv_switch_relay_errors[0x10];
1271 
1272 	u8         port_xmit_discards[0x10];
1273 
1274 	u8         port_xmit_constraint_errors[0x8];
1275 
1276 	u8         port_rcv_constraint_errors[0x8];
1277 
1278 	u8         reserved_at_70[0x8];
1279 
1280 	u8         link_overrun_errors[0x8];
1281 
1282 	u8	   reserved_at_80[0x10];
1283 
1284 	u8         vl_15_dropped[0x10];
1285 
1286 	u8	   reserved_at_a0[0xa0];
1287 };
1288 
1289 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1290 	u8         transmit_queue_high[0x20];
1291 
1292 	u8         transmit_queue_low[0x20];
1293 
1294 	u8         reserved_at_40[0x780];
1295 };
1296 
1297 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1298 	u8         rx_octets_high[0x20];
1299 
1300 	u8         rx_octets_low[0x20];
1301 
1302 	u8         reserved_at_40[0xc0];
1303 
1304 	u8         rx_frames_high[0x20];
1305 
1306 	u8         rx_frames_low[0x20];
1307 
1308 	u8         tx_octets_high[0x20];
1309 
1310 	u8         tx_octets_low[0x20];
1311 
1312 	u8         reserved_at_180[0xc0];
1313 
1314 	u8         tx_frames_high[0x20];
1315 
1316 	u8         tx_frames_low[0x20];
1317 
1318 	u8         rx_pause_high[0x20];
1319 
1320 	u8         rx_pause_low[0x20];
1321 
1322 	u8         rx_pause_duration_high[0x20];
1323 
1324 	u8         rx_pause_duration_low[0x20];
1325 
1326 	u8         tx_pause_high[0x20];
1327 
1328 	u8         tx_pause_low[0x20];
1329 
1330 	u8         tx_pause_duration_high[0x20];
1331 
1332 	u8         tx_pause_duration_low[0x20];
1333 
1334 	u8         rx_pause_transition_high[0x20];
1335 
1336 	u8         rx_pause_transition_low[0x20];
1337 
1338 	u8         reserved_at_3c0[0x400];
1339 };
1340 
1341 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1342 	u8         port_transmit_wait_high[0x20];
1343 
1344 	u8         port_transmit_wait_low[0x20];
1345 
1346 	u8         reserved_at_40[0x780];
1347 };
1348 
1349 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1350 	u8         dot3stats_alignment_errors_high[0x20];
1351 
1352 	u8         dot3stats_alignment_errors_low[0x20];
1353 
1354 	u8         dot3stats_fcs_errors_high[0x20];
1355 
1356 	u8         dot3stats_fcs_errors_low[0x20];
1357 
1358 	u8         dot3stats_single_collision_frames_high[0x20];
1359 
1360 	u8         dot3stats_single_collision_frames_low[0x20];
1361 
1362 	u8         dot3stats_multiple_collision_frames_high[0x20];
1363 
1364 	u8         dot3stats_multiple_collision_frames_low[0x20];
1365 
1366 	u8         dot3stats_sqe_test_errors_high[0x20];
1367 
1368 	u8         dot3stats_sqe_test_errors_low[0x20];
1369 
1370 	u8         dot3stats_deferred_transmissions_high[0x20];
1371 
1372 	u8         dot3stats_deferred_transmissions_low[0x20];
1373 
1374 	u8         dot3stats_late_collisions_high[0x20];
1375 
1376 	u8         dot3stats_late_collisions_low[0x20];
1377 
1378 	u8         dot3stats_excessive_collisions_high[0x20];
1379 
1380 	u8         dot3stats_excessive_collisions_low[0x20];
1381 
1382 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1383 
1384 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1385 
1386 	u8         dot3stats_carrier_sense_errors_high[0x20];
1387 
1388 	u8         dot3stats_carrier_sense_errors_low[0x20];
1389 
1390 	u8         dot3stats_frame_too_longs_high[0x20];
1391 
1392 	u8         dot3stats_frame_too_longs_low[0x20];
1393 
1394 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
1395 
1396 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
1397 
1398 	u8         dot3stats_symbol_errors_high[0x20];
1399 
1400 	u8         dot3stats_symbol_errors_low[0x20];
1401 
1402 	u8         dot3control_in_unknown_opcodes_high[0x20];
1403 
1404 	u8         dot3control_in_unknown_opcodes_low[0x20];
1405 
1406 	u8         dot3in_pause_frames_high[0x20];
1407 
1408 	u8         dot3in_pause_frames_low[0x20];
1409 
1410 	u8         dot3out_pause_frames_high[0x20];
1411 
1412 	u8         dot3out_pause_frames_low[0x20];
1413 
1414 	u8         reserved_at_400[0x3c0];
1415 };
1416 
1417 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1418 	u8         ether_stats_drop_events_high[0x20];
1419 
1420 	u8         ether_stats_drop_events_low[0x20];
1421 
1422 	u8         ether_stats_octets_high[0x20];
1423 
1424 	u8         ether_stats_octets_low[0x20];
1425 
1426 	u8         ether_stats_pkts_high[0x20];
1427 
1428 	u8         ether_stats_pkts_low[0x20];
1429 
1430 	u8         ether_stats_broadcast_pkts_high[0x20];
1431 
1432 	u8         ether_stats_broadcast_pkts_low[0x20];
1433 
1434 	u8         ether_stats_multicast_pkts_high[0x20];
1435 
1436 	u8         ether_stats_multicast_pkts_low[0x20];
1437 
1438 	u8         ether_stats_crc_align_errors_high[0x20];
1439 
1440 	u8         ether_stats_crc_align_errors_low[0x20];
1441 
1442 	u8         ether_stats_undersize_pkts_high[0x20];
1443 
1444 	u8         ether_stats_undersize_pkts_low[0x20];
1445 
1446 	u8         ether_stats_oversize_pkts_high[0x20];
1447 
1448 	u8         ether_stats_oversize_pkts_low[0x20];
1449 
1450 	u8         ether_stats_fragments_high[0x20];
1451 
1452 	u8         ether_stats_fragments_low[0x20];
1453 
1454 	u8         ether_stats_jabbers_high[0x20];
1455 
1456 	u8         ether_stats_jabbers_low[0x20];
1457 
1458 	u8         ether_stats_collisions_high[0x20];
1459 
1460 	u8         ether_stats_collisions_low[0x20];
1461 
1462 	u8         ether_stats_pkts64octets_high[0x20];
1463 
1464 	u8         ether_stats_pkts64octets_low[0x20];
1465 
1466 	u8         ether_stats_pkts65to127octets_high[0x20];
1467 
1468 	u8         ether_stats_pkts65to127octets_low[0x20];
1469 
1470 	u8         ether_stats_pkts128to255octets_high[0x20];
1471 
1472 	u8         ether_stats_pkts128to255octets_low[0x20];
1473 
1474 	u8         ether_stats_pkts256to511octets_high[0x20];
1475 
1476 	u8         ether_stats_pkts256to511octets_low[0x20];
1477 
1478 	u8         ether_stats_pkts512to1023octets_high[0x20];
1479 
1480 	u8         ether_stats_pkts512to1023octets_low[0x20];
1481 
1482 	u8         ether_stats_pkts1024to1518octets_high[0x20];
1483 
1484 	u8         ether_stats_pkts1024to1518octets_low[0x20];
1485 
1486 	u8         ether_stats_pkts1519to2047octets_high[0x20];
1487 
1488 	u8         ether_stats_pkts1519to2047octets_low[0x20];
1489 
1490 	u8         ether_stats_pkts2048to4095octets_high[0x20];
1491 
1492 	u8         ether_stats_pkts2048to4095octets_low[0x20];
1493 
1494 	u8         ether_stats_pkts4096to8191octets_high[0x20];
1495 
1496 	u8         ether_stats_pkts4096to8191octets_low[0x20];
1497 
1498 	u8         ether_stats_pkts8192to10239octets_high[0x20];
1499 
1500 	u8         ether_stats_pkts8192to10239octets_low[0x20];
1501 
1502 	u8         reserved_at_540[0x280];
1503 };
1504 
1505 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1506 	u8         if_in_octets_high[0x20];
1507 
1508 	u8         if_in_octets_low[0x20];
1509 
1510 	u8         if_in_ucast_pkts_high[0x20];
1511 
1512 	u8         if_in_ucast_pkts_low[0x20];
1513 
1514 	u8         if_in_discards_high[0x20];
1515 
1516 	u8         if_in_discards_low[0x20];
1517 
1518 	u8         if_in_errors_high[0x20];
1519 
1520 	u8         if_in_errors_low[0x20];
1521 
1522 	u8         if_in_unknown_protos_high[0x20];
1523 
1524 	u8         if_in_unknown_protos_low[0x20];
1525 
1526 	u8         if_out_octets_high[0x20];
1527 
1528 	u8         if_out_octets_low[0x20];
1529 
1530 	u8         if_out_ucast_pkts_high[0x20];
1531 
1532 	u8         if_out_ucast_pkts_low[0x20];
1533 
1534 	u8         if_out_discards_high[0x20];
1535 
1536 	u8         if_out_discards_low[0x20];
1537 
1538 	u8         if_out_errors_high[0x20];
1539 
1540 	u8         if_out_errors_low[0x20];
1541 
1542 	u8         if_in_multicast_pkts_high[0x20];
1543 
1544 	u8         if_in_multicast_pkts_low[0x20];
1545 
1546 	u8         if_in_broadcast_pkts_high[0x20];
1547 
1548 	u8         if_in_broadcast_pkts_low[0x20];
1549 
1550 	u8         if_out_multicast_pkts_high[0x20];
1551 
1552 	u8         if_out_multicast_pkts_low[0x20];
1553 
1554 	u8         if_out_broadcast_pkts_high[0x20];
1555 
1556 	u8         if_out_broadcast_pkts_low[0x20];
1557 
1558 	u8         reserved_at_340[0x480];
1559 };
1560 
1561 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1562 	u8         a_frames_transmitted_ok_high[0x20];
1563 
1564 	u8         a_frames_transmitted_ok_low[0x20];
1565 
1566 	u8         a_frames_received_ok_high[0x20];
1567 
1568 	u8         a_frames_received_ok_low[0x20];
1569 
1570 	u8         a_frame_check_sequence_errors_high[0x20];
1571 
1572 	u8         a_frame_check_sequence_errors_low[0x20];
1573 
1574 	u8         a_alignment_errors_high[0x20];
1575 
1576 	u8         a_alignment_errors_low[0x20];
1577 
1578 	u8         a_octets_transmitted_ok_high[0x20];
1579 
1580 	u8         a_octets_transmitted_ok_low[0x20];
1581 
1582 	u8         a_octets_received_ok_high[0x20];
1583 
1584 	u8         a_octets_received_ok_low[0x20];
1585 
1586 	u8         a_multicast_frames_xmitted_ok_high[0x20];
1587 
1588 	u8         a_multicast_frames_xmitted_ok_low[0x20];
1589 
1590 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
1591 
1592 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
1593 
1594 	u8         a_multicast_frames_received_ok_high[0x20];
1595 
1596 	u8         a_multicast_frames_received_ok_low[0x20];
1597 
1598 	u8         a_broadcast_frames_received_ok_high[0x20];
1599 
1600 	u8         a_broadcast_frames_received_ok_low[0x20];
1601 
1602 	u8         a_in_range_length_errors_high[0x20];
1603 
1604 	u8         a_in_range_length_errors_low[0x20];
1605 
1606 	u8         a_out_of_range_length_field_high[0x20];
1607 
1608 	u8         a_out_of_range_length_field_low[0x20];
1609 
1610 	u8         a_frame_too_long_errors_high[0x20];
1611 
1612 	u8         a_frame_too_long_errors_low[0x20];
1613 
1614 	u8         a_symbol_error_during_carrier_high[0x20];
1615 
1616 	u8         a_symbol_error_during_carrier_low[0x20];
1617 
1618 	u8         a_mac_control_frames_transmitted_high[0x20];
1619 
1620 	u8         a_mac_control_frames_transmitted_low[0x20];
1621 
1622 	u8         a_mac_control_frames_received_high[0x20];
1623 
1624 	u8         a_mac_control_frames_received_low[0x20];
1625 
1626 	u8         a_unsupported_opcodes_received_high[0x20];
1627 
1628 	u8         a_unsupported_opcodes_received_low[0x20];
1629 
1630 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
1631 
1632 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
1633 
1634 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1635 
1636 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1637 
1638 	u8         reserved_at_4c0[0x300];
1639 };
1640 
1641 struct mlx5_ifc_cmd_inter_comp_event_bits {
1642 	u8         command_completion_vector[0x20];
1643 
1644 	u8         reserved_at_20[0xc0];
1645 };
1646 
1647 struct mlx5_ifc_stall_vl_event_bits {
1648 	u8         reserved_at_0[0x18];
1649 	u8         port_num[0x1];
1650 	u8         reserved_at_19[0x3];
1651 	u8         vl[0x4];
1652 
1653 	u8         reserved_at_20[0xa0];
1654 };
1655 
1656 struct mlx5_ifc_db_bf_congestion_event_bits {
1657 	u8         event_subtype[0x8];
1658 	u8         reserved_at_8[0x8];
1659 	u8         congestion_level[0x8];
1660 	u8         reserved_at_18[0x8];
1661 
1662 	u8         reserved_at_20[0xa0];
1663 };
1664 
1665 struct mlx5_ifc_gpio_event_bits {
1666 	u8         reserved_at_0[0x60];
1667 
1668 	u8         gpio_event_hi[0x20];
1669 
1670 	u8         gpio_event_lo[0x20];
1671 
1672 	u8         reserved_at_a0[0x40];
1673 };
1674 
1675 struct mlx5_ifc_port_state_change_event_bits {
1676 	u8         reserved_at_0[0x40];
1677 
1678 	u8         port_num[0x4];
1679 	u8         reserved_at_44[0x1c];
1680 
1681 	u8         reserved_at_60[0x80];
1682 };
1683 
1684 struct mlx5_ifc_dropped_packet_logged_bits {
1685 	u8         reserved_at_0[0xe0];
1686 };
1687 
1688 enum {
1689 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1690 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1691 };
1692 
1693 struct mlx5_ifc_cq_error_bits {
1694 	u8         reserved_at_0[0x8];
1695 	u8         cqn[0x18];
1696 
1697 	u8         reserved_at_20[0x20];
1698 
1699 	u8         reserved_at_40[0x18];
1700 	u8         syndrome[0x8];
1701 
1702 	u8         reserved_at_60[0x80];
1703 };
1704 
1705 struct mlx5_ifc_rdma_page_fault_event_bits {
1706 	u8         bytes_committed[0x20];
1707 
1708 	u8         r_key[0x20];
1709 
1710 	u8         reserved_at_40[0x10];
1711 	u8         packet_len[0x10];
1712 
1713 	u8         rdma_op_len[0x20];
1714 
1715 	u8         rdma_va[0x40];
1716 
1717 	u8         reserved_at_c0[0x5];
1718 	u8         rdma[0x1];
1719 	u8         write[0x1];
1720 	u8         requestor[0x1];
1721 	u8         qp_number[0x18];
1722 };
1723 
1724 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1725 	u8         bytes_committed[0x20];
1726 
1727 	u8         reserved_at_20[0x10];
1728 	u8         wqe_index[0x10];
1729 
1730 	u8         reserved_at_40[0x10];
1731 	u8         len[0x10];
1732 
1733 	u8         reserved_at_60[0x60];
1734 
1735 	u8         reserved_at_c0[0x5];
1736 	u8         rdma[0x1];
1737 	u8         write_read[0x1];
1738 	u8         requestor[0x1];
1739 	u8         qpn[0x18];
1740 };
1741 
1742 struct mlx5_ifc_qp_events_bits {
1743 	u8         reserved_at_0[0xa0];
1744 
1745 	u8         type[0x8];
1746 	u8         reserved_at_a8[0x18];
1747 
1748 	u8         reserved_at_c0[0x8];
1749 	u8         qpn_rqn_sqn[0x18];
1750 };
1751 
1752 struct mlx5_ifc_dct_events_bits {
1753 	u8         reserved_at_0[0xc0];
1754 
1755 	u8         reserved_at_c0[0x8];
1756 	u8         dct_number[0x18];
1757 };
1758 
1759 struct mlx5_ifc_comp_event_bits {
1760 	u8         reserved_at_0[0xc0];
1761 
1762 	u8         reserved_at_c0[0x8];
1763 	u8         cq_number[0x18];
1764 };
1765 
1766 enum {
1767 	MLX5_QPC_STATE_RST        = 0x0,
1768 	MLX5_QPC_STATE_INIT       = 0x1,
1769 	MLX5_QPC_STATE_RTR        = 0x2,
1770 	MLX5_QPC_STATE_RTS        = 0x3,
1771 	MLX5_QPC_STATE_SQER       = 0x4,
1772 	MLX5_QPC_STATE_ERR        = 0x6,
1773 	MLX5_QPC_STATE_SQD        = 0x7,
1774 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
1775 };
1776 
1777 enum {
1778 	MLX5_QPC_ST_RC            = 0x0,
1779 	MLX5_QPC_ST_UC            = 0x1,
1780 	MLX5_QPC_ST_UD            = 0x2,
1781 	MLX5_QPC_ST_XRC           = 0x3,
1782 	MLX5_QPC_ST_DCI           = 0x5,
1783 	MLX5_QPC_ST_QP0           = 0x7,
1784 	MLX5_QPC_ST_QP1           = 0x8,
1785 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1786 	MLX5_QPC_ST_REG_UMR       = 0xc,
1787 };
1788 
1789 enum {
1790 	MLX5_QPC_PM_STATE_ARMED     = 0x0,
1791 	MLX5_QPC_PM_STATE_REARM     = 0x1,
1792 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1793 	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1794 };
1795 
1796 enum {
1797 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1798 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1799 };
1800 
1801 enum {
1802 	MLX5_QPC_MTU_256_BYTES        = 0x1,
1803 	MLX5_QPC_MTU_512_BYTES        = 0x2,
1804 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
1805 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
1806 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
1807 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1808 };
1809 
1810 enum {
1811 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1812 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1813 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1814 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1815 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1816 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1817 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1818 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1819 };
1820 
1821 enum {
1822 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1823 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1824 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1825 };
1826 
1827 enum {
1828 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
1829 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1830 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1831 };
1832 
1833 struct mlx5_ifc_qpc_bits {
1834 	u8         state[0x4];
1835 	u8         reserved_at_4[0x4];
1836 	u8         st[0x8];
1837 	u8         reserved_at_10[0x3];
1838 	u8         pm_state[0x2];
1839 	u8         reserved_at_15[0x7];
1840 	u8         end_padding_mode[0x2];
1841 	u8         reserved_at_1e[0x2];
1842 
1843 	u8         wq_signature[0x1];
1844 	u8         block_lb_mc[0x1];
1845 	u8         atomic_like_write_en[0x1];
1846 	u8         latency_sensitive[0x1];
1847 	u8         reserved_at_24[0x1];
1848 	u8         drain_sigerr[0x1];
1849 	u8         reserved_at_26[0x2];
1850 	u8         pd[0x18];
1851 
1852 	u8         mtu[0x3];
1853 	u8         log_msg_max[0x5];
1854 	u8         reserved_at_48[0x1];
1855 	u8         log_rq_size[0x4];
1856 	u8         log_rq_stride[0x3];
1857 	u8         no_sq[0x1];
1858 	u8         log_sq_size[0x4];
1859 	u8         reserved_at_55[0x6];
1860 	u8         rlky[0x1];
1861 	u8         ulp_stateless_offload_mode[0x4];
1862 
1863 	u8         counter_set_id[0x8];
1864 	u8         uar_page[0x18];
1865 
1866 	u8         reserved_at_80[0x8];
1867 	u8         user_index[0x18];
1868 
1869 	u8         reserved_at_a0[0x3];
1870 	u8         log_page_size[0x5];
1871 	u8         remote_qpn[0x18];
1872 
1873 	struct mlx5_ifc_ads_bits primary_address_path;
1874 
1875 	struct mlx5_ifc_ads_bits secondary_address_path;
1876 
1877 	u8         log_ack_req_freq[0x4];
1878 	u8         reserved_at_384[0x4];
1879 	u8         log_sra_max[0x3];
1880 	u8         reserved_at_38b[0x2];
1881 	u8         retry_count[0x3];
1882 	u8         rnr_retry[0x3];
1883 	u8         reserved_at_393[0x1];
1884 	u8         fre[0x1];
1885 	u8         cur_rnr_retry[0x3];
1886 	u8         cur_retry_count[0x3];
1887 	u8         reserved_at_39b[0x5];
1888 
1889 	u8         reserved_at_3a0[0x20];
1890 
1891 	u8         reserved_at_3c0[0x8];
1892 	u8         next_send_psn[0x18];
1893 
1894 	u8         reserved_at_3e0[0x8];
1895 	u8         cqn_snd[0x18];
1896 
1897 	u8         reserved_at_400[0x40];
1898 
1899 	u8         reserved_at_440[0x8];
1900 	u8         last_acked_psn[0x18];
1901 
1902 	u8         reserved_at_460[0x8];
1903 	u8         ssn[0x18];
1904 
1905 	u8         reserved_at_480[0x8];
1906 	u8         log_rra_max[0x3];
1907 	u8         reserved_at_48b[0x1];
1908 	u8         atomic_mode[0x4];
1909 	u8         rre[0x1];
1910 	u8         rwe[0x1];
1911 	u8         rae[0x1];
1912 	u8         reserved_at_493[0x1];
1913 	u8         page_offset[0x6];
1914 	u8         reserved_at_49a[0x3];
1915 	u8         cd_slave_receive[0x1];
1916 	u8         cd_slave_send[0x1];
1917 	u8         cd_master[0x1];
1918 
1919 	u8         reserved_at_4a0[0x3];
1920 	u8         min_rnr_nak[0x5];
1921 	u8         next_rcv_psn[0x18];
1922 
1923 	u8         reserved_at_4c0[0x8];
1924 	u8         xrcd[0x18];
1925 
1926 	u8         reserved_at_4e0[0x8];
1927 	u8         cqn_rcv[0x18];
1928 
1929 	u8         dbr_addr[0x40];
1930 
1931 	u8         q_key[0x20];
1932 
1933 	u8         reserved_at_560[0x5];
1934 	u8         rq_type[0x3];
1935 	u8         srqn_rmpn[0x18];
1936 
1937 	u8         reserved_at_580[0x8];
1938 	u8         rmsn[0x18];
1939 
1940 	u8         hw_sq_wqebb_counter[0x10];
1941 	u8         sw_sq_wqebb_counter[0x10];
1942 
1943 	u8         hw_rq_counter[0x20];
1944 
1945 	u8         sw_rq_counter[0x20];
1946 
1947 	u8         reserved_at_600[0x20];
1948 
1949 	u8         reserved_at_620[0xf];
1950 	u8         cgs[0x1];
1951 	u8         cs_req[0x8];
1952 	u8         cs_res[0x8];
1953 
1954 	u8         dc_access_key[0x40];
1955 
1956 	u8         reserved_at_680[0xc0];
1957 };
1958 
1959 struct mlx5_ifc_roce_addr_layout_bits {
1960 	u8         source_l3_address[16][0x8];
1961 
1962 	u8         reserved_at_80[0x3];
1963 	u8         vlan_valid[0x1];
1964 	u8         vlan_id[0xc];
1965 	u8         source_mac_47_32[0x10];
1966 
1967 	u8         source_mac_31_0[0x20];
1968 
1969 	u8         reserved_at_c0[0x14];
1970 	u8         roce_l3_type[0x4];
1971 	u8         roce_version[0x8];
1972 
1973 	u8         reserved_at_e0[0x20];
1974 };
1975 
1976 union mlx5_ifc_hca_cap_union_bits {
1977 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1978 	struct mlx5_ifc_odp_cap_bits odp_cap;
1979 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
1980 	struct mlx5_ifc_roce_cap_bits roce_cap;
1981 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1982 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1983 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
1984 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
1985 	struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
1986 	u8         reserved_at_0[0x8000];
1987 };
1988 
1989 enum {
1990 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1991 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1992 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1993 };
1994 
1995 struct mlx5_ifc_flow_context_bits {
1996 	u8         reserved_at_0[0x20];
1997 
1998 	u8         group_id[0x20];
1999 
2000 	u8         reserved_at_40[0x8];
2001 	u8         flow_tag[0x18];
2002 
2003 	u8         reserved_at_60[0x10];
2004 	u8         action[0x10];
2005 
2006 	u8         reserved_at_80[0x8];
2007 	u8         destination_list_size[0x18];
2008 
2009 	u8         reserved_at_a0[0x160];
2010 
2011 	struct mlx5_ifc_fte_match_param_bits match_value;
2012 
2013 	u8         reserved_at_1200[0x600];
2014 
2015 	struct mlx5_ifc_dest_format_struct_bits destination[0];
2016 };
2017 
2018 enum {
2019 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2020 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2021 };
2022 
2023 struct mlx5_ifc_xrc_srqc_bits {
2024 	u8         state[0x4];
2025 	u8         log_xrc_srq_size[0x4];
2026 	u8         reserved_at_8[0x18];
2027 
2028 	u8         wq_signature[0x1];
2029 	u8         cont_srq[0x1];
2030 	u8         reserved_at_22[0x1];
2031 	u8         rlky[0x1];
2032 	u8         basic_cyclic_rcv_wqe[0x1];
2033 	u8         log_rq_stride[0x3];
2034 	u8         xrcd[0x18];
2035 
2036 	u8         page_offset[0x6];
2037 	u8         reserved_at_46[0x2];
2038 	u8         cqn[0x18];
2039 
2040 	u8         reserved_at_60[0x20];
2041 
2042 	u8         user_index_equal_xrc_srqn[0x1];
2043 	u8         reserved_at_81[0x1];
2044 	u8         log_page_size[0x6];
2045 	u8         user_index[0x18];
2046 
2047 	u8         reserved_at_a0[0x20];
2048 
2049 	u8         reserved_at_c0[0x8];
2050 	u8         pd[0x18];
2051 
2052 	u8         lwm[0x10];
2053 	u8         wqe_cnt[0x10];
2054 
2055 	u8         reserved_at_100[0x40];
2056 
2057 	u8         db_record_addr_h[0x20];
2058 
2059 	u8         db_record_addr_l[0x1e];
2060 	u8         reserved_at_17e[0x2];
2061 
2062 	u8         reserved_at_180[0x80];
2063 };
2064 
2065 struct mlx5_ifc_traffic_counter_bits {
2066 	u8         packets[0x40];
2067 
2068 	u8         octets[0x40];
2069 };
2070 
2071 struct mlx5_ifc_tisc_bits {
2072 	u8         reserved_at_0[0xc];
2073 	u8         prio[0x4];
2074 	u8         reserved_at_10[0x10];
2075 
2076 	u8         reserved_at_20[0x100];
2077 
2078 	u8         reserved_at_120[0x8];
2079 	u8         transport_domain[0x18];
2080 
2081 	u8         reserved_at_140[0x3c0];
2082 };
2083 
2084 enum {
2085 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2086 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2087 };
2088 
2089 enum {
2090 	MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2091 	MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2092 };
2093 
2094 enum {
2095 	MLX5_RX_HASH_FN_NONE           = 0x0,
2096 	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2097 	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2098 };
2099 
2100 enum {
2101 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2102 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2103 };
2104 
2105 struct mlx5_ifc_tirc_bits {
2106 	u8         reserved_at_0[0x20];
2107 
2108 	u8         disp_type[0x4];
2109 	u8         reserved_at_24[0x1c];
2110 
2111 	u8         reserved_at_40[0x40];
2112 
2113 	u8         reserved_at_80[0x4];
2114 	u8         lro_timeout_period_usecs[0x10];
2115 	u8         lro_enable_mask[0x4];
2116 	u8         lro_max_ip_payload_size[0x8];
2117 
2118 	u8         reserved_at_a0[0x40];
2119 
2120 	u8         reserved_at_e0[0x8];
2121 	u8         inline_rqn[0x18];
2122 
2123 	u8         rx_hash_symmetric[0x1];
2124 	u8         reserved_at_101[0x1];
2125 	u8         tunneled_offload_en[0x1];
2126 	u8         reserved_at_103[0x5];
2127 	u8         indirect_table[0x18];
2128 
2129 	u8         rx_hash_fn[0x4];
2130 	u8         reserved_at_124[0x2];
2131 	u8         self_lb_block[0x2];
2132 	u8         transport_domain[0x18];
2133 
2134 	u8         rx_hash_toeplitz_key[10][0x20];
2135 
2136 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2137 
2138 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2139 
2140 	u8         reserved_at_2c0[0x4c0];
2141 };
2142 
2143 enum {
2144 	MLX5_SRQC_STATE_GOOD   = 0x0,
2145 	MLX5_SRQC_STATE_ERROR  = 0x1,
2146 };
2147 
2148 struct mlx5_ifc_srqc_bits {
2149 	u8         state[0x4];
2150 	u8         log_srq_size[0x4];
2151 	u8         reserved_at_8[0x18];
2152 
2153 	u8         wq_signature[0x1];
2154 	u8         cont_srq[0x1];
2155 	u8         reserved_at_22[0x1];
2156 	u8         rlky[0x1];
2157 	u8         reserved_at_24[0x1];
2158 	u8         log_rq_stride[0x3];
2159 	u8         xrcd[0x18];
2160 
2161 	u8         page_offset[0x6];
2162 	u8         reserved_at_46[0x2];
2163 	u8         cqn[0x18];
2164 
2165 	u8         reserved_at_60[0x20];
2166 
2167 	u8         reserved_at_80[0x2];
2168 	u8         log_page_size[0x6];
2169 	u8         reserved_at_88[0x18];
2170 
2171 	u8         reserved_at_a0[0x20];
2172 
2173 	u8         reserved_at_c0[0x8];
2174 	u8         pd[0x18];
2175 
2176 	u8         lwm[0x10];
2177 	u8         wqe_cnt[0x10];
2178 
2179 	u8         reserved_at_100[0x40];
2180 
2181 	u8         dbr_addr[0x40];
2182 
2183 	u8         reserved_at_180[0x80];
2184 };
2185 
2186 enum {
2187 	MLX5_SQC_STATE_RST  = 0x0,
2188 	MLX5_SQC_STATE_RDY  = 0x1,
2189 	MLX5_SQC_STATE_ERR  = 0x3,
2190 };
2191 
2192 struct mlx5_ifc_sqc_bits {
2193 	u8         rlky[0x1];
2194 	u8         cd_master[0x1];
2195 	u8         fre[0x1];
2196 	u8         flush_in_error_en[0x1];
2197 	u8         reserved_at_4[0x4];
2198 	u8         state[0x4];
2199 	u8         reserved_at_c[0x14];
2200 
2201 	u8         reserved_at_20[0x8];
2202 	u8         user_index[0x18];
2203 
2204 	u8         reserved_at_40[0x8];
2205 	u8         cqn[0x18];
2206 
2207 	u8         reserved_at_60[0xa0];
2208 
2209 	u8         tis_lst_sz[0x10];
2210 	u8         reserved_at_110[0x10];
2211 
2212 	u8         reserved_at_120[0x40];
2213 
2214 	u8         reserved_at_160[0x8];
2215 	u8         tis_num_0[0x18];
2216 
2217 	struct mlx5_ifc_wq_bits wq;
2218 };
2219 
2220 struct mlx5_ifc_rqtc_bits {
2221 	u8         reserved_at_0[0xa0];
2222 
2223 	u8         reserved_at_a0[0x10];
2224 	u8         rqt_max_size[0x10];
2225 
2226 	u8         reserved_at_c0[0x10];
2227 	u8         rqt_actual_size[0x10];
2228 
2229 	u8         reserved_at_e0[0x6a0];
2230 
2231 	struct mlx5_ifc_rq_num_bits rq_num[0];
2232 };
2233 
2234 enum {
2235 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2236 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2237 };
2238 
2239 enum {
2240 	MLX5_RQC_STATE_RST  = 0x0,
2241 	MLX5_RQC_STATE_RDY  = 0x1,
2242 	MLX5_RQC_STATE_ERR  = 0x3,
2243 };
2244 
2245 struct mlx5_ifc_rqc_bits {
2246 	u8         rlky[0x1];
2247 	u8         reserved_at_1[0x2];
2248 	u8         vsd[0x1];
2249 	u8         mem_rq_type[0x4];
2250 	u8         state[0x4];
2251 	u8         reserved_at_c[0x1];
2252 	u8         flush_in_error_en[0x1];
2253 	u8         reserved_at_e[0x12];
2254 
2255 	u8         reserved_at_20[0x8];
2256 	u8         user_index[0x18];
2257 
2258 	u8         reserved_at_40[0x8];
2259 	u8         cqn[0x18];
2260 
2261 	u8         counter_set_id[0x8];
2262 	u8         reserved_at_68[0x18];
2263 
2264 	u8         reserved_at_80[0x8];
2265 	u8         rmpn[0x18];
2266 
2267 	u8         reserved_at_a0[0xe0];
2268 
2269 	struct mlx5_ifc_wq_bits wq;
2270 };
2271 
2272 enum {
2273 	MLX5_RMPC_STATE_RDY  = 0x1,
2274 	MLX5_RMPC_STATE_ERR  = 0x3,
2275 };
2276 
2277 struct mlx5_ifc_rmpc_bits {
2278 	u8         reserved_at_0[0x8];
2279 	u8         state[0x4];
2280 	u8         reserved_at_c[0x14];
2281 
2282 	u8         basic_cyclic_rcv_wqe[0x1];
2283 	u8         reserved_at_21[0x1f];
2284 
2285 	u8         reserved_at_40[0x140];
2286 
2287 	struct mlx5_ifc_wq_bits wq;
2288 };
2289 
2290 struct mlx5_ifc_nic_vport_context_bits {
2291 	u8         reserved_at_0[0x1f];
2292 	u8         roce_en[0x1];
2293 
2294 	u8         arm_change_event[0x1];
2295 	u8         reserved_at_21[0x1a];
2296 	u8         event_on_mtu[0x1];
2297 	u8         event_on_promisc_change[0x1];
2298 	u8         event_on_vlan_change[0x1];
2299 	u8         event_on_mc_address_change[0x1];
2300 	u8         event_on_uc_address_change[0x1];
2301 
2302 	u8         reserved_at_40[0xf0];
2303 
2304 	u8         mtu[0x10];
2305 
2306 	u8         system_image_guid[0x40];
2307 	u8         port_guid[0x40];
2308 	u8         node_guid[0x40];
2309 
2310 	u8         reserved_at_200[0x140];
2311 	u8         qkey_violation_counter[0x10];
2312 	u8         reserved_at_350[0x430];
2313 
2314 	u8         promisc_uc[0x1];
2315 	u8         promisc_mc[0x1];
2316 	u8         promisc_all[0x1];
2317 	u8         reserved_at_783[0x2];
2318 	u8         allowed_list_type[0x3];
2319 	u8         reserved_at_788[0xc];
2320 	u8         allowed_list_size[0xc];
2321 
2322 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
2323 
2324 	u8         reserved_at_7e0[0x20];
2325 
2326 	u8         current_uc_mac_address[0][0x40];
2327 };
2328 
2329 enum {
2330 	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2331 	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2332 	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2333 };
2334 
2335 struct mlx5_ifc_mkc_bits {
2336 	u8         reserved_at_0[0x1];
2337 	u8         free[0x1];
2338 	u8         reserved_at_2[0xd];
2339 	u8         small_fence_on_rdma_read_response[0x1];
2340 	u8         umr_en[0x1];
2341 	u8         a[0x1];
2342 	u8         rw[0x1];
2343 	u8         rr[0x1];
2344 	u8         lw[0x1];
2345 	u8         lr[0x1];
2346 	u8         access_mode[0x2];
2347 	u8         reserved_at_18[0x8];
2348 
2349 	u8         qpn[0x18];
2350 	u8         mkey_7_0[0x8];
2351 
2352 	u8         reserved_at_40[0x20];
2353 
2354 	u8         length64[0x1];
2355 	u8         bsf_en[0x1];
2356 	u8         sync_umr[0x1];
2357 	u8         reserved_at_63[0x2];
2358 	u8         expected_sigerr_count[0x1];
2359 	u8         reserved_at_66[0x1];
2360 	u8         en_rinval[0x1];
2361 	u8         pd[0x18];
2362 
2363 	u8         start_addr[0x40];
2364 
2365 	u8         len[0x40];
2366 
2367 	u8         bsf_octword_size[0x20];
2368 
2369 	u8         reserved_at_120[0x80];
2370 
2371 	u8         translations_octword_size[0x20];
2372 
2373 	u8         reserved_at_1c0[0x1b];
2374 	u8         log_page_size[0x5];
2375 
2376 	u8         reserved_at_1e0[0x20];
2377 };
2378 
2379 struct mlx5_ifc_pkey_bits {
2380 	u8         reserved_at_0[0x10];
2381 	u8         pkey[0x10];
2382 };
2383 
2384 struct mlx5_ifc_array128_auto_bits {
2385 	u8         array128_auto[16][0x8];
2386 };
2387 
2388 struct mlx5_ifc_hca_vport_context_bits {
2389 	u8         field_select[0x20];
2390 
2391 	u8         reserved_at_20[0xe0];
2392 
2393 	u8         sm_virt_aware[0x1];
2394 	u8         has_smi[0x1];
2395 	u8         has_raw[0x1];
2396 	u8         grh_required[0x1];
2397 	u8         reserved_at_104[0xc];
2398 	u8         port_physical_state[0x4];
2399 	u8         vport_state_policy[0x4];
2400 	u8         port_state[0x4];
2401 	u8         vport_state[0x4];
2402 
2403 	u8         reserved_at_120[0x20];
2404 
2405 	u8         system_image_guid[0x40];
2406 
2407 	u8         port_guid[0x40];
2408 
2409 	u8         node_guid[0x40];
2410 
2411 	u8         cap_mask1[0x20];
2412 
2413 	u8         cap_mask1_field_select[0x20];
2414 
2415 	u8         cap_mask2[0x20];
2416 
2417 	u8         cap_mask2_field_select[0x20];
2418 
2419 	u8         reserved_at_280[0x80];
2420 
2421 	u8         lid[0x10];
2422 	u8         reserved_at_310[0x4];
2423 	u8         init_type_reply[0x4];
2424 	u8         lmc[0x3];
2425 	u8         subnet_timeout[0x5];
2426 
2427 	u8         sm_lid[0x10];
2428 	u8         sm_sl[0x4];
2429 	u8         reserved_at_334[0xc];
2430 
2431 	u8         qkey_violation_counter[0x10];
2432 	u8         pkey_violation_counter[0x10];
2433 
2434 	u8         reserved_at_360[0xca0];
2435 };
2436 
2437 struct mlx5_ifc_esw_vport_context_bits {
2438 	u8         reserved_at_0[0x3];
2439 	u8         vport_svlan_strip[0x1];
2440 	u8         vport_cvlan_strip[0x1];
2441 	u8         vport_svlan_insert[0x1];
2442 	u8         vport_cvlan_insert[0x2];
2443 	u8         reserved_at_8[0x18];
2444 
2445 	u8         reserved_at_20[0x20];
2446 
2447 	u8         svlan_cfi[0x1];
2448 	u8         svlan_pcp[0x3];
2449 	u8         svlan_id[0xc];
2450 	u8         cvlan_cfi[0x1];
2451 	u8         cvlan_pcp[0x3];
2452 	u8         cvlan_id[0xc];
2453 
2454 	u8         reserved_at_60[0x7a0];
2455 };
2456 
2457 enum {
2458 	MLX5_EQC_STATUS_OK                = 0x0,
2459 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2460 };
2461 
2462 enum {
2463 	MLX5_EQC_ST_ARMED  = 0x9,
2464 	MLX5_EQC_ST_FIRED  = 0xa,
2465 };
2466 
2467 struct mlx5_ifc_eqc_bits {
2468 	u8         status[0x4];
2469 	u8         reserved_at_4[0x9];
2470 	u8         ec[0x1];
2471 	u8         oi[0x1];
2472 	u8         reserved_at_f[0x5];
2473 	u8         st[0x4];
2474 	u8         reserved_at_18[0x8];
2475 
2476 	u8         reserved_at_20[0x20];
2477 
2478 	u8         reserved_at_40[0x14];
2479 	u8         page_offset[0x6];
2480 	u8         reserved_at_5a[0x6];
2481 
2482 	u8         reserved_at_60[0x3];
2483 	u8         log_eq_size[0x5];
2484 	u8         uar_page[0x18];
2485 
2486 	u8         reserved_at_80[0x20];
2487 
2488 	u8         reserved_at_a0[0x18];
2489 	u8         intr[0x8];
2490 
2491 	u8         reserved_at_c0[0x3];
2492 	u8         log_page_size[0x5];
2493 	u8         reserved_at_c8[0x18];
2494 
2495 	u8         reserved_at_e0[0x60];
2496 
2497 	u8         reserved_at_140[0x8];
2498 	u8         consumer_counter[0x18];
2499 
2500 	u8         reserved_at_160[0x8];
2501 	u8         producer_counter[0x18];
2502 
2503 	u8         reserved_at_180[0x80];
2504 };
2505 
2506 enum {
2507 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
2508 	MLX5_DCTC_STATE_DRAINING  = 0x1,
2509 	MLX5_DCTC_STATE_DRAINED   = 0x2,
2510 };
2511 
2512 enum {
2513 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2514 	MLX5_DCTC_CS_RES_NA         = 0x1,
2515 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2516 };
2517 
2518 enum {
2519 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
2520 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
2521 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2522 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2523 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2524 };
2525 
2526 struct mlx5_ifc_dctc_bits {
2527 	u8         reserved_at_0[0x4];
2528 	u8         state[0x4];
2529 	u8         reserved_at_8[0x18];
2530 
2531 	u8         reserved_at_20[0x8];
2532 	u8         user_index[0x18];
2533 
2534 	u8         reserved_at_40[0x8];
2535 	u8         cqn[0x18];
2536 
2537 	u8         counter_set_id[0x8];
2538 	u8         atomic_mode[0x4];
2539 	u8         rre[0x1];
2540 	u8         rwe[0x1];
2541 	u8         rae[0x1];
2542 	u8         atomic_like_write_en[0x1];
2543 	u8         latency_sensitive[0x1];
2544 	u8         rlky[0x1];
2545 	u8         free_ar[0x1];
2546 	u8         reserved_at_73[0xd];
2547 
2548 	u8         reserved_at_80[0x8];
2549 	u8         cs_res[0x8];
2550 	u8         reserved_at_90[0x3];
2551 	u8         min_rnr_nak[0x5];
2552 	u8         reserved_at_98[0x8];
2553 
2554 	u8         reserved_at_a0[0x8];
2555 	u8         srqn[0x18];
2556 
2557 	u8         reserved_at_c0[0x8];
2558 	u8         pd[0x18];
2559 
2560 	u8         tclass[0x8];
2561 	u8         reserved_at_e8[0x4];
2562 	u8         flow_label[0x14];
2563 
2564 	u8         dc_access_key[0x40];
2565 
2566 	u8         reserved_at_140[0x5];
2567 	u8         mtu[0x3];
2568 	u8         port[0x8];
2569 	u8         pkey_index[0x10];
2570 
2571 	u8         reserved_at_160[0x8];
2572 	u8         my_addr_index[0x8];
2573 	u8         reserved_at_170[0x8];
2574 	u8         hop_limit[0x8];
2575 
2576 	u8         dc_access_key_violation_count[0x20];
2577 
2578 	u8         reserved_at_1a0[0x14];
2579 	u8         dei_cfi[0x1];
2580 	u8         eth_prio[0x3];
2581 	u8         ecn[0x2];
2582 	u8         dscp[0x6];
2583 
2584 	u8         reserved_at_1c0[0x40];
2585 };
2586 
2587 enum {
2588 	MLX5_CQC_STATUS_OK             = 0x0,
2589 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2590 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2591 };
2592 
2593 enum {
2594 	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2595 	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2596 };
2597 
2598 enum {
2599 	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2600 	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2601 	MLX5_CQC_ST_FIRED                                 = 0xa,
2602 };
2603 
2604 struct mlx5_ifc_cqc_bits {
2605 	u8         status[0x4];
2606 	u8         reserved_at_4[0x4];
2607 	u8         cqe_sz[0x3];
2608 	u8         cc[0x1];
2609 	u8         reserved_at_c[0x1];
2610 	u8         scqe_break_moderation_en[0x1];
2611 	u8         oi[0x1];
2612 	u8         reserved_at_f[0x2];
2613 	u8         cqe_zip_en[0x1];
2614 	u8         mini_cqe_res_format[0x2];
2615 	u8         st[0x4];
2616 	u8         reserved_at_18[0x8];
2617 
2618 	u8         reserved_at_20[0x20];
2619 
2620 	u8         reserved_at_40[0x14];
2621 	u8         page_offset[0x6];
2622 	u8         reserved_at_5a[0x6];
2623 
2624 	u8         reserved_at_60[0x3];
2625 	u8         log_cq_size[0x5];
2626 	u8         uar_page[0x18];
2627 
2628 	u8         reserved_at_80[0x4];
2629 	u8         cq_period[0xc];
2630 	u8         cq_max_count[0x10];
2631 
2632 	u8         reserved_at_a0[0x18];
2633 	u8         c_eqn[0x8];
2634 
2635 	u8         reserved_at_c0[0x3];
2636 	u8         log_page_size[0x5];
2637 	u8         reserved_at_c8[0x18];
2638 
2639 	u8         reserved_at_e0[0x20];
2640 
2641 	u8         reserved_at_100[0x8];
2642 	u8         last_notified_index[0x18];
2643 
2644 	u8         reserved_at_120[0x8];
2645 	u8         last_solicit_index[0x18];
2646 
2647 	u8         reserved_at_140[0x8];
2648 	u8         consumer_counter[0x18];
2649 
2650 	u8         reserved_at_160[0x8];
2651 	u8         producer_counter[0x18];
2652 
2653 	u8         reserved_at_180[0x40];
2654 
2655 	u8         dbr_addr[0x40];
2656 };
2657 
2658 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2659 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2660 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2661 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2662 	u8         reserved_at_0[0x800];
2663 };
2664 
2665 struct mlx5_ifc_query_adapter_param_block_bits {
2666 	u8         reserved_at_0[0xc0];
2667 
2668 	u8         reserved_at_c0[0x8];
2669 	u8         ieee_vendor_id[0x18];
2670 
2671 	u8         reserved_at_e0[0x10];
2672 	u8         vsd_vendor_id[0x10];
2673 
2674 	u8         vsd[208][0x8];
2675 
2676 	u8         vsd_contd_psid[16][0x8];
2677 };
2678 
2679 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2680 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
2681 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
2682 	u8         reserved_at_0[0x20];
2683 };
2684 
2685 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2686 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2687 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2688 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2689 	u8         reserved_at_0[0x20];
2690 };
2691 
2692 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2693 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2694 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2695 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2696 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2697 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2698 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2699 	struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2700 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2701 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2702 	u8         reserved_at_0[0x7c0];
2703 };
2704 
2705 union mlx5_ifc_event_auto_bits {
2706 	struct mlx5_ifc_comp_event_bits comp_event;
2707 	struct mlx5_ifc_dct_events_bits dct_events;
2708 	struct mlx5_ifc_qp_events_bits qp_events;
2709 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2710 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2711 	struct mlx5_ifc_cq_error_bits cq_error;
2712 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2713 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2714 	struct mlx5_ifc_gpio_event_bits gpio_event;
2715 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2716 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2717 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2718 	u8         reserved_at_0[0xe0];
2719 };
2720 
2721 struct mlx5_ifc_health_buffer_bits {
2722 	u8         reserved_at_0[0x100];
2723 
2724 	u8         assert_existptr[0x20];
2725 
2726 	u8         assert_callra[0x20];
2727 
2728 	u8         reserved_at_140[0x40];
2729 
2730 	u8         fw_version[0x20];
2731 
2732 	u8         hw_id[0x20];
2733 
2734 	u8         reserved_at_1c0[0x20];
2735 
2736 	u8         irisc_index[0x8];
2737 	u8         synd[0x8];
2738 	u8         ext_synd[0x10];
2739 };
2740 
2741 struct mlx5_ifc_register_loopback_control_bits {
2742 	u8         no_lb[0x1];
2743 	u8         reserved_at_1[0x7];
2744 	u8         port[0x8];
2745 	u8         reserved_at_10[0x10];
2746 
2747 	u8         reserved_at_20[0x60];
2748 };
2749 
2750 struct mlx5_ifc_teardown_hca_out_bits {
2751 	u8         status[0x8];
2752 	u8         reserved_at_8[0x18];
2753 
2754 	u8         syndrome[0x20];
2755 
2756 	u8         reserved_at_40[0x40];
2757 };
2758 
2759 enum {
2760 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2761 	MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2762 };
2763 
2764 struct mlx5_ifc_teardown_hca_in_bits {
2765 	u8         opcode[0x10];
2766 	u8         reserved_at_10[0x10];
2767 
2768 	u8         reserved_at_20[0x10];
2769 	u8         op_mod[0x10];
2770 
2771 	u8         reserved_at_40[0x10];
2772 	u8         profile[0x10];
2773 
2774 	u8         reserved_at_60[0x20];
2775 };
2776 
2777 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2778 	u8         status[0x8];
2779 	u8         reserved_at_8[0x18];
2780 
2781 	u8         syndrome[0x20];
2782 
2783 	u8         reserved_at_40[0x40];
2784 };
2785 
2786 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2787 	u8         opcode[0x10];
2788 	u8         reserved_at_10[0x10];
2789 
2790 	u8         reserved_at_20[0x10];
2791 	u8         op_mod[0x10];
2792 
2793 	u8         reserved_at_40[0x8];
2794 	u8         qpn[0x18];
2795 
2796 	u8         reserved_at_60[0x20];
2797 
2798 	u8         opt_param_mask[0x20];
2799 
2800 	u8         reserved_at_a0[0x20];
2801 
2802 	struct mlx5_ifc_qpc_bits qpc;
2803 
2804 	u8         reserved_at_800[0x80];
2805 };
2806 
2807 struct mlx5_ifc_sqd2rts_qp_out_bits {
2808 	u8         status[0x8];
2809 	u8         reserved_at_8[0x18];
2810 
2811 	u8         syndrome[0x20];
2812 
2813 	u8         reserved_at_40[0x40];
2814 };
2815 
2816 struct mlx5_ifc_sqd2rts_qp_in_bits {
2817 	u8         opcode[0x10];
2818 	u8         reserved_at_10[0x10];
2819 
2820 	u8         reserved_at_20[0x10];
2821 	u8         op_mod[0x10];
2822 
2823 	u8         reserved_at_40[0x8];
2824 	u8         qpn[0x18];
2825 
2826 	u8         reserved_at_60[0x20];
2827 
2828 	u8         opt_param_mask[0x20];
2829 
2830 	u8         reserved_at_a0[0x20];
2831 
2832 	struct mlx5_ifc_qpc_bits qpc;
2833 
2834 	u8         reserved_at_800[0x80];
2835 };
2836 
2837 struct mlx5_ifc_set_roce_address_out_bits {
2838 	u8         status[0x8];
2839 	u8         reserved_at_8[0x18];
2840 
2841 	u8         syndrome[0x20];
2842 
2843 	u8         reserved_at_40[0x40];
2844 };
2845 
2846 struct mlx5_ifc_set_roce_address_in_bits {
2847 	u8         opcode[0x10];
2848 	u8         reserved_at_10[0x10];
2849 
2850 	u8         reserved_at_20[0x10];
2851 	u8         op_mod[0x10];
2852 
2853 	u8         roce_address_index[0x10];
2854 	u8         reserved_at_50[0x10];
2855 
2856 	u8         reserved_at_60[0x20];
2857 
2858 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
2859 };
2860 
2861 struct mlx5_ifc_set_mad_demux_out_bits {
2862 	u8         status[0x8];
2863 	u8         reserved_at_8[0x18];
2864 
2865 	u8         syndrome[0x20];
2866 
2867 	u8         reserved_at_40[0x40];
2868 };
2869 
2870 enum {
2871 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
2872 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
2873 };
2874 
2875 struct mlx5_ifc_set_mad_demux_in_bits {
2876 	u8         opcode[0x10];
2877 	u8         reserved_at_10[0x10];
2878 
2879 	u8         reserved_at_20[0x10];
2880 	u8         op_mod[0x10];
2881 
2882 	u8         reserved_at_40[0x20];
2883 
2884 	u8         reserved_at_60[0x6];
2885 	u8         demux_mode[0x2];
2886 	u8         reserved_at_68[0x18];
2887 };
2888 
2889 struct mlx5_ifc_set_l2_table_entry_out_bits {
2890 	u8         status[0x8];
2891 	u8         reserved_at_8[0x18];
2892 
2893 	u8         syndrome[0x20];
2894 
2895 	u8         reserved_at_40[0x40];
2896 };
2897 
2898 struct mlx5_ifc_set_l2_table_entry_in_bits {
2899 	u8         opcode[0x10];
2900 	u8         reserved_at_10[0x10];
2901 
2902 	u8         reserved_at_20[0x10];
2903 	u8         op_mod[0x10];
2904 
2905 	u8         reserved_at_40[0x60];
2906 
2907 	u8         reserved_at_a0[0x8];
2908 	u8         table_index[0x18];
2909 
2910 	u8         reserved_at_c0[0x20];
2911 
2912 	u8         reserved_at_e0[0x13];
2913 	u8         vlan_valid[0x1];
2914 	u8         vlan[0xc];
2915 
2916 	struct mlx5_ifc_mac_address_layout_bits mac_address;
2917 
2918 	u8         reserved_at_140[0xc0];
2919 };
2920 
2921 struct mlx5_ifc_set_issi_out_bits {
2922 	u8         status[0x8];
2923 	u8         reserved_at_8[0x18];
2924 
2925 	u8         syndrome[0x20];
2926 
2927 	u8         reserved_at_40[0x40];
2928 };
2929 
2930 struct mlx5_ifc_set_issi_in_bits {
2931 	u8         opcode[0x10];
2932 	u8         reserved_at_10[0x10];
2933 
2934 	u8         reserved_at_20[0x10];
2935 	u8         op_mod[0x10];
2936 
2937 	u8         reserved_at_40[0x10];
2938 	u8         current_issi[0x10];
2939 
2940 	u8         reserved_at_60[0x20];
2941 };
2942 
2943 struct mlx5_ifc_set_hca_cap_out_bits {
2944 	u8         status[0x8];
2945 	u8         reserved_at_8[0x18];
2946 
2947 	u8         syndrome[0x20];
2948 
2949 	u8         reserved_at_40[0x40];
2950 };
2951 
2952 struct mlx5_ifc_set_hca_cap_in_bits {
2953 	u8         opcode[0x10];
2954 	u8         reserved_at_10[0x10];
2955 
2956 	u8         reserved_at_20[0x10];
2957 	u8         op_mod[0x10];
2958 
2959 	u8         reserved_at_40[0x40];
2960 
2961 	union mlx5_ifc_hca_cap_union_bits capability;
2962 };
2963 
2964 enum {
2965 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
2966 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
2967 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
2968 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
2969 };
2970 
2971 struct mlx5_ifc_set_fte_out_bits {
2972 	u8         status[0x8];
2973 	u8         reserved_at_8[0x18];
2974 
2975 	u8         syndrome[0x20];
2976 
2977 	u8         reserved_at_40[0x40];
2978 };
2979 
2980 struct mlx5_ifc_set_fte_in_bits {
2981 	u8         opcode[0x10];
2982 	u8         reserved_at_10[0x10];
2983 
2984 	u8         reserved_at_20[0x10];
2985 	u8         op_mod[0x10];
2986 
2987 	u8         reserved_at_40[0x40];
2988 
2989 	u8         table_type[0x8];
2990 	u8         reserved_at_88[0x18];
2991 
2992 	u8         reserved_at_a0[0x8];
2993 	u8         table_id[0x18];
2994 
2995 	u8         reserved_at_c0[0x18];
2996 	u8         modify_enable_mask[0x8];
2997 
2998 	u8         reserved_at_e0[0x20];
2999 
3000 	u8         flow_index[0x20];
3001 
3002 	u8         reserved_at_120[0xe0];
3003 
3004 	struct mlx5_ifc_flow_context_bits flow_context;
3005 };
3006 
3007 struct mlx5_ifc_rts2rts_qp_out_bits {
3008 	u8         status[0x8];
3009 	u8         reserved_at_8[0x18];
3010 
3011 	u8         syndrome[0x20];
3012 
3013 	u8         reserved_at_40[0x40];
3014 };
3015 
3016 struct mlx5_ifc_rts2rts_qp_in_bits {
3017 	u8         opcode[0x10];
3018 	u8         reserved_at_10[0x10];
3019 
3020 	u8         reserved_at_20[0x10];
3021 	u8         op_mod[0x10];
3022 
3023 	u8         reserved_at_40[0x8];
3024 	u8         qpn[0x18];
3025 
3026 	u8         reserved_at_60[0x20];
3027 
3028 	u8         opt_param_mask[0x20];
3029 
3030 	u8         reserved_at_a0[0x20];
3031 
3032 	struct mlx5_ifc_qpc_bits qpc;
3033 
3034 	u8         reserved_at_800[0x80];
3035 };
3036 
3037 struct mlx5_ifc_rtr2rts_qp_out_bits {
3038 	u8         status[0x8];
3039 	u8         reserved_at_8[0x18];
3040 
3041 	u8         syndrome[0x20];
3042 
3043 	u8         reserved_at_40[0x40];
3044 };
3045 
3046 struct mlx5_ifc_rtr2rts_qp_in_bits {
3047 	u8         opcode[0x10];
3048 	u8         reserved_at_10[0x10];
3049 
3050 	u8         reserved_at_20[0x10];
3051 	u8         op_mod[0x10];
3052 
3053 	u8         reserved_at_40[0x8];
3054 	u8         qpn[0x18];
3055 
3056 	u8         reserved_at_60[0x20];
3057 
3058 	u8         opt_param_mask[0x20];
3059 
3060 	u8         reserved_at_a0[0x20];
3061 
3062 	struct mlx5_ifc_qpc_bits qpc;
3063 
3064 	u8         reserved_at_800[0x80];
3065 };
3066 
3067 struct mlx5_ifc_rst2init_qp_out_bits {
3068 	u8         status[0x8];
3069 	u8         reserved_at_8[0x18];
3070 
3071 	u8         syndrome[0x20];
3072 
3073 	u8         reserved_at_40[0x40];
3074 };
3075 
3076 struct mlx5_ifc_rst2init_qp_in_bits {
3077 	u8         opcode[0x10];
3078 	u8         reserved_at_10[0x10];
3079 
3080 	u8         reserved_at_20[0x10];
3081 	u8         op_mod[0x10];
3082 
3083 	u8         reserved_at_40[0x8];
3084 	u8         qpn[0x18];
3085 
3086 	u8         reserved_at_60[0x20];
3087 
3088 	u8         opt_param_mask[0x20];
3089 
3090 	u8         reserved_at_a0[0x20];
3091 
3092 	struct mlx5_ifc_qpc_bits qpc;
3093 
3094 	u8         reserved_at_800[0x80];
3095 };
3096 
3097 struct mlx5_ifc_query_xrc_srq_out_bits {
3098 	u8         status[0x8];
3099 	u8         reserved_at_8[0x18];
3100 
3101 	u8         syndrome[0x20];
3102 
3103 	u8         reserved_at_40[0x40];
3104 
3105 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3106 
3107 	u8         reserved_at_280[0x600];
3108 
3109 	u8         pas[0][0x40];
3110 };
3111 
3112 struct mlx5_ifc_query_xrc_srq_in_bits {
3113 	u8         opcode[0x10];
3114 	u8         reserved_at_10[0x10];
3115 
3116 	u8         reserved_at_20[0x10];
3117 	u8         op_mod[0x10];
3118 
3119 	u8         reserved_at_40[0x8];
3120 	u8         xrc_srqn[0x18];
3121 
3122 	u8         reserved_at_60[0x20];
3123 };
3124 
3125 enum {
3126 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3127 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3128 };
3129 
3130 struct mlx5_ifc_query_vport_state_out_bits {
3131 	u8         status[0x8];
3132 	u8         reserved_at_8[0x18];
3133 
3134 	u8         syndrome[0x20];
3135 
3136 	u8         reserved_at_40[0x20];
3137 
3138 	u8         reserved_at_60[0x18];
3139 	u8         admin_state[0x4];
3140 	u8         state[0x4];
3141 };
3142 
3143 enum {
3144 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3145 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3146 };
3147 
3148 struct mlx5_ifc_query_vport_state_in_bits {
3149 	u8         opcode[0x10];
3150 	u8         reserved_at_10[0x10];
3151 
3152 	u8         reserved_at_20[0x10];
3153 	u8         op_mod[0x10];
3154 
3155 	u8         other_vport[0x1];
3156 	u8         reserved_at_41[0xf];
3157 	u8         vport_number[0x10];
3158 
3159 	u8         reserved_at_60[0x20];
3160 };
3161 
3162 struct mlx5_ifc_query_vport_counter_out_bits {
3163 	u8         status[0x8];
3164 	u8         reserved_at_8[0x18];
3165 
3166 	u8         syndrome[0x20];
3167 
3168 	u8         reserved_at_40[0x40];
3169 
3170 	struct mlx5_ifc_traffic_counter_bits received_errors;
3171 
3172 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
3173 
3174 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3175 
3176 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3177 
3178 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3179 
3180 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3181 
3182 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3183 
3184 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3185 
3186 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3187 
3188 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3189 
3190 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3191 
3192 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3193 
3194 	u8         reserved_at_680[0xa00];
3195 };
3196 
3197 enum {
3198 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3199 };
3200 
3201 struct mlx5_ifc_query_vport_counter_in_bits {
3202 	u8         opcode[0x10];
3203 	u8         reserved_at_10[0x10];
3204 
3205 	u8         reserved_at_20[0x10];
3206 	u8         op_mod[0x10];
3207 
3208 	u8         other_vport[0x1];
3209 	u8         reserved_at_41[0xb];
3210 	u8	   port_num[0x4];
3211 	u8         vport_number[0x10];
3212 
3213 	u8         reserved_at_60[0x60];
3214 
3215 	u8         clear[0x1];
3216 	u8         reserved_at_c1[0x1f];
3217 
3218 	u8         reserved_at_e0[0x20];
3219 };
3220 
3221 struct mlx5_ifc_query_tis_out_bits {
3222 	u8         status[0x8];
3223 	u8         reserved_at_8[0x18];
3224 
3225 	u8         syndrome[0x20];
3226 
3227 	u8         reserved_at_40[0x40];
3228 
3229 	struct mlx5_ifc_tisc_bits tis_context;
3230 };
3231 
3232 struct mlx5_ifc_query_tis_in_bits {
3233 	u8         opcode[0x10];
3234 	u8         reserved_at_10[0x10];
3235 
3236 	u8         reserved_at_20[0x10];
3237 	u8         op_mod[0x10];
3238 
3239 	u8         reserved_at_40[0x8];
3240 	u8         tisn[0x18];
3241 
3242 	u8         reserved_at_60[0x20];
3243 };
3244 
3245 struct mlx5_ifc_query_tir_out_bits {
3246 	u8         status[0x8];
3247 	u8         reserved_at_8[0x18];
3248 
3249 	u8         syndrome[0x20];
3250 
3251 	u8         reserved_at_40[0xc0];
3252 
3253 	struct mlx5_ifc_tirc_bits tir_context;
3254 };
3255 
3256 struct mlx5_ifc_query_tir_in_bits {
3257 	u8         opcode[0x10];
3258 	u8         reserved_at_10[0x10];
3259 
3260 	u8         reserved_at_20[0x10];
3261 	u8         op_mod[0x10];
3262 
3263 	u8         reserved_at_40[0x8];
3264 	u8         tirn[0x18];
3265 
3266 	u8         reserved_at_60[0x20];
3267 };
3268 
3269 struct mlx5_ifc_query_srq_out_bits {
3270 	u8         status[0x8];
3271 	u8         reserved_at_8[0x18];
3272 
3273 	u8         syndrome[0x20];
3274 
3275 	u8         reserved_at_40[0x40];
3276 
3277 	struct mlx5_ifc_srqc_bits srq_context_entry;
3278 
3279 	u8         reserved_at_280[0x600];
3280 
3281 	u8         pas[0][0x40];
3282 };
3283 
3284 struct mlx5_ifc_query_srq_in_bits {
3285 	u8         opcode[0x10];
3286 	u8         reserved_at_10[0x10];
3287 
3288 	u8         reserved_at_20[0x10];
3289 	u8         op_mod[0x10];
3290 
3291 	u8         reserved_at_40[0x8];
3292 	u8         srqn[0x18];
3293 
3294 	u8         reserved_at_60[0x20];
3295 };
3296 
3297 struct mlx5_ifc_query_sq_out_bits {
3298 	u8         status[0x8];
3299 	u8         reserved_at_8[0x18];
3300 
3301 	u8         syndrome[0x20];
3302 
3303 	u8         reserved_at_40[0xc0];
3304 
3305 	struct mlx5_ifc_sqc_bits sq_context;
3306 };
3307 
3308 struct mlx5_ifc_query_sq_in_bits {
3309 	u8         opcode[0x10];
3310 	u8         reserved_at_10[0x10];
3311 
3312 	u8         reserved_at_20[0x10];
3313 	u8         op_mod[0x10];
3314 
3315 	u8         reserved_at_40[0x8];
3316 	u8         sqn[0x18];
3317 
3318 	u8         reserved_at_60[0x20];
3319 };
3320 
3321 struct mlx5_ifc_query_special_contexts_out_bits {
3322 	u8         status[0x8];
3323 	u8         reserved_at_8[0x18];
3324 
3325 	u8         syndrome[0x20];
3326 
3327 	u8         reserved_at_40[0x20];
3328 
3329 	u8         resd_lkey[0x20];
3330 };
3331 
3332 struct mlx5_ifc_query_special_contexts_in_bits {
3333 	u8         opcode[0x10];
3334 	u8         reserved_at_10[0x10];
3335 
3336 	u8         reserved_at_20[0x10];
3337 	u8         op_mod[0x10];
3338 
3339 	u8         reserved_at_40[0x40];
3340 };
3341 
3342 struct mlx5_ifc_query_rqt_out_bits {
3343 	u8         status[0x8];
3344 	u8         reserved_at_8[0x18];
3345 
3346 	u8         syndrome[0x20];
3347 
3348 	u8         reserved_at_40[0xc0];
3349 
3350 	struct mlx5_ifc_rqtc_bits rqt_context;
3351 };
3352 
3353 struct mlx5_ifc_query_rqt_in_bits {
3354 	u8         opcode[0x10];
3355 	u8         reserved_at_10[0x10];
3356 
3357 	u8         reserved_at_20[0x10];
3358 	u8         op_mod[0x10];
3359 
3360 	u8         reserved_at_40[0x8];
3361 	u8         rqtn[0x18];
3362 
3363 	u8         reserved_at_60[0x20];
3364 };
3365 
3366 struct mlx5_ifc_query_rq_out_bits {
3367 	u8         status[0x8];
3368 	u8         reserved_at_8[0x18];
3369 
3370 	u8         syndrome[0x20];
3371 
3372 	u8         reserved_at_40[0xc0];
3373 
3374 	struct mlx5_ifc_rqc_bits rq_context;
3375 };
3376 
3377 struct mlx5_ifc_query_rq_in_bits {
3378 	u8         opcode[0x10];
3379 	u8         reserved_at_10[0x10];
3380 
3381 	u8         reserved_at_20[0x10];
3382 	u8         op_mod[0x10];
3383 
3384 	u8         reserved_at_40[0x8];
3385 	u8         rqn[0x18];
3386 
3387 	u8         reserved_at_60[0x20];
3388 };
3389 
3390 struct mlx5_ifc_query_roce_address_out_bits {
3391 	u8         status[0x8];
3392 	u8         reserved_at_8[0x18];
3393 
3394 	u8         syndrome[0x20];
3395 
3396 	u8         reserved_at_40[0x40];
3397 
3398 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
3399 };
3400 
3401 struct mlx5_ifc_query_roce_address_in_bits {
3402 	u8         opcode[0x10];
3403 	u8         reserved_at_10[0x10];
3404 
3405 	u8         reserved_at_20[0x10];
3406 	u8         op_mod[0x10];
3407 
3408 	u8         roce_address_index[0x10];
3409 	u8         reserved_at_50[0x10];
3410 
3411 	u8         reserved_at_60[0x20];
3412 };
3413 
3414 struct mlx5_ifc_query_rmp_out_bits {
3415 	u8         status[0x8];
3416 	u8         reserved_at_8[0x18];
3417 
3418 	u8         syndrome[0x20];
3419 
3420 	u8         reserved_at_40[0xc0];
3421 
3422 	struct mlx5_ifc_rmpc_bits rmp_context;
3423 };
3424 
3425 struct mlx5_ifc_query_rmp_in_bits {
3426 	u8         opcode[0x10];
3427 	u8         reserved_at_10[0x10];
3428 
3429 	u8         reserved_at_20[0x10];
3430 	u8         op_mod[0x10];
3431 
3432 	u8         reserved_at_40[0x8];
3433 	u8         rmpn[0x18];
3434 
3435 	u8         reserved_at_60[0x20];
3436 };
3437 
3438 struct mlx5_ifc_query_qp_out_bits {
3439 	u8         status[0x8];
3440 	u8         reserved_at_8[0x18];
3441 
3442 	u8         syndrome[0x20];
3443 
3444 	u8         reserved_at_40[0x40];
3445 
3446 	u8         opt_param_mask[0x20];
3447 
3448 	u8         reserved_at_a0[0x20];
3449 
3450 	struct mlx5_ifc_qpc_bits qpc;
3451 
3452 	u8         reserved_at_800[0x80];
3453 
3454 	u8         pas[0][0x40];
3455 };
3456 
3457 struct mlx5_ifc_query_qp_in_bits {
3458 	u8         opcode[0x10];
3459 	u8         reserved_at_10[0x10];
3460 
3461 	u8         reserved_at_20[0x10];
3462 	u8         op_mod[0x10];
3463 
3464 	u8         reserved_at_40[0x8];
3465 	u8         qpn[0x18];
3466 
3467 	u8         reserved_at_60[0x20];
3468 };
3469 
3470 struct mlx5_ifc_query_q_counter_out_bits {
3471 	u8         status[0x8];
3472 	u8         reserved_at_8[0x18];
3473 
3474 	u8         syndrome[0x20];
3475 
3476 	u8         reserved_at_40[0x40];
3477 
3478 	u8         rx_write_requests[0x20];
3479 
3480 	u8         reserved_at_a0[0x20];
3481 
3482 	u8         rx_read_requests[0x20];
3483 
3484 	u8         reserved_at_e0[0x20];
3485 
3486 	u8         rx_atomic_requests[0x20];
3487 
3488 	u8         reserved_at_120[0x20];
3489 
3490 	u8         rx_dct_connect[0x20];
3491 
3492 	u8         reserved_at_160[0x20];
3493 
3494 	u8         out_of_buffer[0x20];
3495 
3496 	u8         reserved_at_1a0[0x20];
3497 
3498 	u8         out_of_sequence[0x20];
3499 
3500 	u8         reserved_at_1e0[0x620];
3501 };
3502 
3503 struct mlx5_ifc_query_q_counter_in_bits {
3504 	u8         opcode[0x10];
3505 	u8         reserved_at_10[0x10];
3506 
3507 	u8         reserved_at_20[0x10];
3508 	u8         op_mod[0x10];
3509 
3510 	u8         reserved_at_40[0x80];
3511 
3512 	u8         clear[0x1];
3513 	u8         reserved_at_c1[0x1f];
3514 
3515 	u8         reserved_at_e0[0x18];
3516 	u8         counter_set_id[0x8];
3517 };
3518 
3519 struct mlx5_ifc_query_pages_out_bits {
3520 	u8         status[0x8];
3521 	u8         reserved_at_8[0x18];
3522 
3523 	u8         syndrome[0x20];
3524 
3525 	u8         reserved_at_40[0x10];
3526 	u8         function_id[0x10];
3527 
3528 	u8         num_pages[0x20];
3529 };
3530 
3531 enum {
3532 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3533 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3534 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3535 };
3536 
3537 struct mlx5_ifc_query_pages_in_bits {
3538 	u8         opcode[0x10];
3539 	u8         reserved_at_10[0x10];
3540 
3541 	u8         reserved_at_20[0x10];
3542 	u8         op_mod[0x10];
3543 
3544 	u8         reserved_at_40[0x10];
3545 	u8         function_id[0x10];
3546 
3547 	u8         reserved_at_60[0x20];
3548 };
3549 
3550 struct mlx5_ifc_query_nic_vport_context_out_bits {
3551 	u8         status[0x8];
3552 	u8         reserved_at_8[0x18];
3553 
3554 	u8         syndrome[0x20];
3555 
3556 	u8         reserved_at_40[0x40];
3557 
3558 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3559 };
3560 
3561 struct mlx5_ifc_query_nic_vport_context_in_bits {
3562 	u8         opcode[0x10];
3563 	u8         reserved_at_10[0x10];
3564 
3565 	u8         reserved_at_20[0x10];
3566 	u8         op_mod[0x10];
3567 
3568 	u8         other_vport[0x1];
3569 	u8         reserved_at_41[0xf];
3570 	u8         vport_number[0x10];
3571 
3572 	u8         reserved_at_60[0x5];
3573 	u8         allowed_list_type[0x3];
3574 	u8         reserved_at_68[0x18];
3575 };
3576 
3577 struct mlx5_ifc_query_mkey_out_bits {
3578 	u8         status[0x8];
3579 	u8         reserved_at_8[0x18];
3580 
3581 	u8         syndrome[0x20];
3582 
3583 	u8         reserved_at_40[0x40];
3584 
3585 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3586 
3587 	u8         reserved_at_280[0x600];
3588 
3589 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3590 
3591 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3592 };
3593 
3594 struct mlx5_ifc_query_mkey_in_bits {
3595 	u8         opcode[0x10];
3596 	u8         reserved_at_10[0x10];
3597 
3598 	u8         reserved_at_20[0x10];
3599 	u8         op_mod[0x10];
3600 
3601 	u8         reserved_at_40[0x8];
3602 	u8         mkey_index[0x18];
3603 
3604 	u8         pg_access[0x1];
3605 	u8         reserved_at_61[0x1f];
3606 };
3607 
3608 struct mlx5_ifc_query_mad_demux_out_bits {
3609 	u8         status[0x8];
3610 	u8         reserved_at_8[0x18];
3611 
3612 	u8         syndrome[0x20];
3613 
3614 	u8         reserved_at_40[0x40];
3615 
3616 	u8         mad_dumux_parameters_block[0x20];
3617 };
3618 
3619 struct mlx5_ifc_query_mad_demux_in_bits {
3620 	u8         opcode[0x10];
3621 	u8         reserved_at_10[0x10];
3622 
3623 	u8         reserved_at_20[0x10];
3624 	u8         op_mod[0x10];
3625 
3626 	u8         reserved_at_40[0x40];
3627 };
3628 
3629 struct mlx5_ifc_query_l2_table_entry_out_bits {
3630 	u8         status[0x8];
3631 	u8         reserved_at_8[0x18];
3632 
3633 	u8         syndrome[0x20];
3634 
3635 	u8         reserved_at_40[0xa0];
3636 
3637 	u8         reserved_at_e0[0x13];
3638 	u8         vlan_valid[0x1];
3639 	u8         vlan[0xc];
3640 
3641 	struct mlx5_ifc_mac_address_layout_bits mac_address;
3642 
3643 	u8         reserved_at_140[0xc0];
3644 };
3645 
3646 struct mlx5_ifc_query_l2_table_entry_in_bits {
3647 	u8         opcode[0x10];
3648 	u8         reserved_at_10[0x10];
3649 
3650 	u8         reserved_at_20[0x10];
3651 	u8         op_mod[0x10];
3652 
3653 	u8         reserved_at_40[0x60];
3654 
3655 	u8         reserved_at_a0[0x8];
3656 	u8         table_index[0x18];
3657 
3658 	u8         reserved_at_c0[0x140];
3659 };
3660 
3661 struct mlx5_ifc_query_issi_out_bits {
3662 	u8         status[0x8];
3663 	u8         reserved_at_8[0x18];
3664 
3665 	u8         syndrome[0x20];
3666 
3667 	u8         reserved_at_40[0x10];
3668 	u8         current_issi[0x10];
3669 
3670 	u8         reserved_at_60[0xa0];
3671 
3672 	u8         reserved_at_100[76][0x8];
3673 	u8         supported_issi_dw0[0x20];
3674 };
3675 
3676 struct mlx5_ifc_query_issi_in_bits {
3677 	u8         opcode[0x10];
3678 	u8         reserved_at_10[0x10];
3679 
3680 	u8         reserved_at_20[0x10];
3681 	u8         op_mod[0x10];
3682 
3683 	u8         reserved_at_40[0x40];
3684 };
3685 
3686 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3687 	u8         status[0x8];
3688 	u8         reserved_at_8[0x18];
3689 
3690 	u8         syndrome[0x20];
3691 
3692 	u8         reserved_at_40[0x40];
3693 
3694 	struct mlx5_ifc_pkey_bits pkey[0];
3695 };
3696 
3697 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3698 	u8         opcode[0x10];
3699 	u8         reserved_at_10[0x10];
3700 
3701 	u8         reserved_at_20[0x10];
3702 	u8         op_mod[0x10];
3703 
3704 	u8         other_vport[0x1];
3705 	u8         reserved_at_41[0xb];
3706 	u8         port_num[0x4];
3707 	u8         vport_number[0x10];
3708 
3709 	u8         reserved_at_60[0x10];
3710 	u8         pkey_index[0x10];
3711 };
3712 
3713 enum {
3714 	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
3715 	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
3716 	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
3717 };
3718 
3719 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3720 	u8         status[0x8];
3721 	u8         reserved_at_8[0x18];
3722 
3723 	u8         syndrome[0x20];
3724 
3725 	u8         reserved_at_40[0x20];
3726 
3727 	u8         gids_num[0x10];
3728 	u8         reserved_at_70[0x10];
3729 
3730 	struct mlx5_ifc_array128_auto_bits gid[0];
3731 };
3732 
3733 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3734 	u8         opcode[0x10];
3735 	u8         reserved_at_10[0x10];
3736 
3737 	u8         reserved_at_20[0x10];
3738 	u8         op_mod[0x10];
3739 
3740 	u8         other_vport[0x1];
3741 	u8         reserved_at_41[0xb];
3742 	u8         port_num[0x4];
3743 	u8         vport_number[0x10];
3744 
3745 	u8         reserved_at_60[0x10];
3746 	u8         gid_index[0x10];
3747 };
3748 
3749 struct mlx5_ifc_query_hca_vport_context_out_bits {
3750 	u8         status[0x8];
3751 	u8         reserved_at_8[0x18];
3752 
3753 	u8         syndrome[0x20];
3754 
3755 	u8         reserved_at_40[0x40];
3756 
3757 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3758 };
3759 
3760 struct mlx5_ifc_query_hca_vport_context_in_bits {
3761 	u8         opcode[0x10];
3762 	u8         reserved_at_10[0x10];
3763 
3764 	u8         reserved_at_20[0x10];
3765 	u8         op_mod[0x10];
3766 
3767 	u8         other_vport[0x1];
3768 	u8         reserved_at_41[0xb];
3769 	u8         port_num[0x4];
3770 	u8         vport_number[0x10];
3771 
3772 	u8         reserved_at_60[0x20];
3773 };
3774 
3775 struct mlx5_ifc_query_hca_cap_out_bits {
3776 	u8         status[0x8];
3777 	u8         reserved_at_8[0x18];
3778 
3779 	u8         syndrome[0x20];
3780 
3781 	u8         reserved_at_40[0x40];
3782 
3783 	union mlx5_ifc_hca_cap_union_bits capability;
3784 };
3785 
3786 struct mlx5_ifc_query_hca_cap_in_bits {
3787 	u8         opcode[0x10];
3788 	u8         reserved_at_10[0x10];
3789 
3790 	u8         reserved_at_20[0x10];
3791 	u8         op_mod[0x10];
3792 
3793 	u8         reserved_at_40[0x40];
3794 };
3795 
3796 struct mlx5_ifc_query_flow_table_out_bits {
3797 	u8         status[0x8];
3798 	u8         reserved_at_8[0x18];
3799 
3800 	u8         syndrome[0x20];
3801 
3802 	u8         reserved_at_40[0x80];
3803 
3804 	u8         reserved_at_c0[0x8];
3805 	u8         level[0x8];
3806 	u8         reserved_at_d0[0x8];
3807 	u8         log_size[0x8];
3808 
3809 	u8         reserved_at_e0[0x120];
3810 };
3811 
3812 struct mlx5_ifc_query_flow_table_in_bits {
3813 	u8         opcode[0x10];
3814 	u8         reserved_at_10[0x10];
3815 
3816 	u8         reserved_at_20[0x10];
3817 	u8         op_mod[0x10];
3818 
3819 	u8         reserved_at_40[0x40];
3820 
3821 	u8         table_type[0x8];
3822 	u8         reserved_at_88[0x18];
3823 
3824 	u8         reserved_at_a0[0x8];
3825 	u8         table_id[0x18];
3826 
3827 	u8         reserved_at_c0[0x140];
3828 };
3829 
3830 struct mlx5_ifc_query_fte_out_bits {
3831 	u8         status[0x8];
3832 	u8         reserved_at_8[0x18];
3833 
3834 	u8         syndrome[0x20];
3835 
3836 	u8         reserved_at_40[0x1c0];
3837 
3838 	struct mlx5_ifc_flow_context_bits flow_context;
3839 };
3840 
3841 struct mlx5_ifc_query_fte_in_bits {
3842 	u8         opcode[0x10];
3843 	u8         reserved_at_10[0x10];
3844 
3845 	u8         reserved_at_20[0x10];
3846 	u8         op_mod[0x10];
3847 
3848 	u8         reserved_at_40[0x40];
3849 
3850 	u8         table_type[0x8];
3851 	u8         reserved_at_88[0x18];
3852 
3853 	u8         reserved_at_a0[0x8];
3854 	u8         table_id[0x18];
3855 
3856 	u8         reserved_at_c0[0x40];
3857 
3858 	u8         flow_index[0x20];
3859 
3860 	u8         reserved_at_120[0xe0];
3861 };
3862 
3863 enum {
3864 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
3865 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
3866 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
3867 };
3868 
3869 struct mlx5_ifc_query_flow_group_out_bits {
3870 	u8         status[0x8];
3871 	u8         reserved_at_8[0x18];
3872 
3873 	u8         syndrome[0x20];
3874 
3875 	u8         reserved_at_40[0xa0];
3876 
3877 	u8         start_flow_index[0x20];
3878 
3879 	u8         reserved_at_100[0x20];
3880 
3881 	u8         end_flow_index[0x20];
3882 
3883 	u8         reserved_at_140[0xa0];
3884 
3885 	u8         reserved_at_1e0[0x18];
3886 	u8         match_criteria_enable[0x8];
3887 
3888 	struct mlx5_ifc_fte_match_param_bits match_criteria;
3889 
3890 	u8         reserved_at_1200[0xe00];
3891 };
3892 
3893 struct mlx5_ifc_query_flow_group_in_bits {
3894 	u8         opcode[0x10];
3895 	u8         reserved_at_10[0x10];
3896 
3897 	u8         reserved_at_20[0x10];
3898 	u8         op_mod[0x10];
3899 
3900 	u8         reserved_at_40[0x40];
3901 
3902 	u8         table_type[0x8];
3903 	u8         reserved_at_88[0x18];
3904 
3905 	u8         reserved_at_a0[0x8];
3906 	u8         table_id[0x18];
3907 
3908 	u8         group_id[0x20];
3909 
3910 	u8         reserved_at_e0[0x120];
3911 };
3912 
3913 struct mlx5_ifc_query_esw_vport_context_out_bits {
3914 	u8         status[0x8];
3915 	u8         reserved_at_8[0x18];
3916 
3917 	u8         syndrome[0x20];
3918 
3919 	u8         reserved_at_40[0x40];
3920 
3921 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3922 };
3923 
3924 struct mlx5_ifc_query_esw_vport_context_in_bits {
3925 	u8         opcode[0x10];
3926 	u8         reserved_at_10[0x10];
3927 
3928 	u8         reserved_at_20[0x10];
3929 	u8         op_mod[0x10];
3930 
3931 	u8         other_vport[0x1];
3932 	u8         reserved_at_41[0xf];
3933 	u8         vport_number[0x10];
3934 
3935 	u8         reserved_at_60[0x20];
3936 };
3937 
3938 struct mlx5_ifc_modify_esw_vport_context_out_bits {
3939 	u8         status[0x8];
3940 	u8         reserved_at_8[0x18];
3941 
3942 	u8         syndrome[0x20];
3943 
3944 	u8         reserved_at_40[0x40];
3945 };
3946 
3947 struct mlx5_ifc_esw_vport_context_fields_select_bits {
3948 	u8         reserved_at_0[0x1c];
3949 	u8         vport_cvlan_insert[0x1];
3950 	u8         vport_svlan_insert[0x1];
3951 	u8         vport_cvlan_strip[0x1];
3952 	u8         vport_svlan_strip[0x1];
3953 };
3954 
3955 struct mlx5_ifc_modify_esw_vport_context_in_bits {
3956 	u8         opcode[0x10];
3957 	u8         reserved_at_10[0x10];
3958 
3959 	u8         reserved_at_20[0x10];
3960 	u8         op_mod[0x10];
3961 
3962 	u8         other_vport[0x1];
3963 	u8         reserved_at_41[0xf];
3964 	u8         vport_number[0x10];
3965 
3966 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3967 
3968 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3969 };
3970 
3971 struct mlx5_ifc_query_eq_out_bits {
3972 	u8         status[0x8];
3973 	u8         reserved_at_8[0x18];
3974 
3975 	u8         syndrome[0x20];
3976 
3977 	u8         reserved_at_40[0x40];
3978 
3979 	struct mlx5_ifc_eqc_bits eq_context_entry;
3980 
3981 	u8         reserved_at_280[0x40];
3982 
3983 	u8         event_bitmask[0x40];
3984 
3985 	u8         reserved_at_300[0x580];
3986 
3987 	u8         pas[0][0x40];
3988 };
3989 
3990 struct mlx5_ifc_query_eq_in_bits {
3991 	u8         opcode[0x10];
3992 	u8         reserved_at_10[0x10];
3993 
3994 	u8         reserved_at_20[0x10];
3995 	u8         op_mod[0x10];
3996 
3997 	u8         reserved_at_40[0x18];
3998 	u8         eq_number[0x8];
3999 
4000 	u8         reserved_at_60[0x20];
4001 };
4002 
4003 struct mlx5_ifc_query_dct_out_bits {
4004 	u8         status[0x8];
4005 	u8         reserved_at_8[0x18];
4006 
4007 	u8         syndrome[0x20];
4008 
4009 	u8         reserved_at_40[0x40];
4010 
4011 	struct mlx5_ifc_dctc_bits dct_context_entry;
4012 
4013 	u8         reserved_at_280[0x180];
4014 };
4015 
4016 struct mlx5_ifc_query_dct_in_bits {
4017 	u8         opcode[0x10];
4018 	u8         reserved_at_10[0x10];
4019 
4020 	u8         reserved_at_20[0x10];
4021 	u8         op_mod[0x10];
4022 
4023 	u8         reserved_at_40[0x8];
4024 	u8         dctn[0x18];
4025 
4026 	u8         reserved_at_60[0x20];
4027 };
4028 
4029 struct mlx5_ifc_query_cq_out_bits {
4030 	u8         status[0x8];
4031 	u8         reserved_at_8[0x18];
4032 
4033 	u8         syndrome[0x20];
4034 
4035 	u8         reserved_at_40[0x40];
4036 
4037 	struct mlx5_ifc_cqc_bits cq_context;
4038 
4039 	u8         reserved_at_280[0x600];
4040 
4041 	u8         pas[0][0x40];
4042 };
4043 
4044 struct mlx5_ifc_query_cq_in_bits {
4045 	u8         opcode[0x10];
4046 	u8         reserved_at_10[0x10];
4047 
4048 	u8         reserved_at_20[0x10];
4049 	u8         op_mod[0x10];
4050 
4051 	u8         reserved_at_40[0x8];
4052 	u8         cqn[0x18];
4053 
4054 	u8         reserved_at_60[0x20];
4055 };
4056 
4057 struct mlx5_ifc_query_cong_status_out_bits {
4058 	u8         status[0x8];
4059 	u8         reserved_at_8[0x18];
4060 
4061 	u8         syndrome[0x20];
4062 
4063 	u8         reserved_at_40[0x20];
4064 
4065 	u8         enable[0x1];
4066 	u8         tag_enable[0x1];
4067 	u8         reserved_at_62[0x1e];
4068 };
4069 
4070 struct mlx5_ifc_query_cong_status_in_bits {
4071 	u8         opcode[0x10];
4072 	u8         reserved_at_10[0x10];
4073 
4074 	u8         reserved_at_20[0x10];
4075 	u8         op_mod[0x10];
4076 
4077 	u8         reserved_at_40[0x18];
4078 	u8         priority[0x4];
4079 	u8         cong_protocol[0x4];
4080 
4081 	u8         reserved_at_60[0x20];
4082 };
4083 
4084 struct mlx5_ifc_query_cong_statistics_out_bits {
4085 	u8         status[0x8];
4086 	u8         reserved_at_8[0x18];
4087 
4088 	u8         syndrome[0x20];
4089 
4090 	u8         reserved_at_40[0x40];
4091 
4092 	u8         cur_flows[0x20];
4093 
4094 	u8         sum_flows[0x20];
4095 
4096 	u8         cnp_ignored_high[0x20];
4097 
4098 	u8         cnp_ignored_low[0x20];
4099 
4100 	u8         cnp_handled_high[0x20];
4101 
4102 	u8         cnp_handled_low[0x20];
4103 
4104 	u8         reserved_at_140[0x100];
4105 
4106 	u8         time_stamp_high[0x20];
4107 
4108 	u8         time_stamp_low[0x20];
4109 
4110 	u8         accumulators_period[0x20];
4111 
4112 	u8         ecn_marked_roce_packets_high[0x20];
4113 
4114 	u8         ecn_marked_roce_packets_low[0x20];
4115 
4116 	u8         cnps_sent_high[0x20];
4117 
4118 	u8         cnps_sent_low[0x20];
4119 
4120 	u8         reserved_at_320[0x560];
4121 };
4122 
4123 struct mlx5_ifc_query_cong_statistics_in_bits {
4124 	u8         opcode[0x10];
4125 	u8         reserved_at_10[0x10];
4126 
4127 	u8         reserved_at_20[0x10];
4128 	u8         op_mod[0x10];
4129 
4130 	u8         clear[0x1];
4131 	u8         reserved_at_41[0x1f];
4132 
4133 	u8         reserved_at_60[0x20];
4134 };
4135 
4136 struct mlx5_ifc_query_cong_params_out_bits {
4137 	u8         status[0x8];
4138 	u8         reserved_at_8[0x18];
4139 
4140 	u8         syndrome[0x20];
4141 
4142 	u8         reserved_at_40[0x40];
4143 
4144 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4145 };
4146 
4147 struct mlx5_ifc_query_cong_params_in_bits {
4148 	u8         opcode[0x10];
4149 	u8         reserved_at_10[0x10];
4150 
4151 	u8         reserved_at_20[0x10];
4152 	u8         op_mod[0x10];
4153 
4154 	u8         reserved_at_40[0x1c];
4155 	u8         cong_protocol[0x4];
4156 
4157 	u8         reserved_at_60[0x20];
4158 };
4159 
4160 struct mlx5_ifc_query_adapter_out_bits {
4161 	u8         status[0x8];
4162 	u8         reserved_at_8[0x18];
4163 
4164 	u8         syndrome[0x20];
4165 
4166 	u8         reserved_at_40[0x40];
4167 
4168 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4169 };
4170 
4171 struct mlx5_ifc_query_adapter_in_bits {
4172 	u8         opcode[0x10];
4173 	u8         reserved_at_10[0x10];
4174 
4175 	u8         reserved_at_20[0x10];
4176 	u8         op_mod[0x10];
4177 
4178 	u8         reserved_at_40[0x40];
4179 };
4180 
4181 struct mlx5_ifc_qp_2rst_out_bits {
4182 	u8         status[0x8];
4183 	u8         reserved_at_8[0x18];
4184 
4185 	u8         syndrome[0x20];
4186 
4187 	u8         reserved_at_40[0x40];
4188 };
4189 
4190 struct mlx5_ifc_qp_2rst_in_bits {
4191 	u8         opcode[0x10];
4192 	u8         reserved_at_10[0x10];
4193 
4194 	u8         reserved_at_20[0x10];
4195 	u8         op_mod[0x10];
4196 
4197 	u8         reserved_at_40[0x8];
4198 	u8         qpn[0x18];
4199 
4200 	u8         reserved_at_60[0x20];
4201 };
4202 
4203 struct mlx5_ifc_qp_2err_out_bits {
4204 	u8         status[0x8];
4205 	u8         reserved_at_8[0x18];
4206 
4207 	u8         syndrome[0x20];
4208 
4209 	u8         reserved_at_40[0x40];
4210 };
4211 
4212 struct mlx5_ifc_qp_2err_in_bits {
4213 	u8         opcode[0x10];
4214 	u8         reserved_at_10[0x10];
4215 
4216 	u8         reserved_at_20[0x10];
4217 	u8         op_mod[0x10];
4218 
4219 	u8         reserved_at_40[0x8];
4220 	u8         qpn[0x18];
4221 
4222 	u8         reserved_at_60[0x20];
4223 };
4224 
4225 struct mlx5_ifc_page_fault_resume_out_bits {
4226 	u8         status[0x8];
4227 	u8         reserved_at_8[0x18];
4228 
4229 	u8         syndrome[0x20];
4230 
4231 	u8         reserved_at_40[0x40];
4232 };
4233 
4234 struct mlx5_ifc_page_fault_resume_in_bits {
4235 	u8         opcode[0x10];
4236 	u8         reserved_at_10[0x10];
4237 
4238 	u8         reserved_at_20[0x10];
4239 	u8         op_mod[0x10];
4240 
4241 	u8         error[0x1];
4242 	u8         reserved_at_41[0x4];
4243 	u8         rdma[0x1];
4244 	u8         read_write[0x1];
4245 	u8         req_res[0x1];
4246 	u8         qpn[0x18];
4247 
4248 	u8         reserved_at_60[0x20];
4249 };
4250 
4251 struct mlx5_ifc_nop_out_bits {
4252 	u8         status[0x8];
4253 	u8         reserved_at_8[0x18];
4254 
4255 	u8         syndrome[0x20];
4256 
4257 	u8         reserved_at_40[0x40];
4258 };
4259 
4260 struct mlx5_ifc_nop_in_bits {
4261 	u8         opcode[0x10];
4262 	u8         reserved_at_10[0x10];
4263 
4264 	u8         reserved_at_20[0x10];
4265 	u8         op_mod[0x10];
4266 
4267 	u8         reserved_at_40[0x40];
4268 };
4269 
4270 struct mlx5_ifc_modify_vport_state_out_bits {
4271 	u8         status[0x8];
4272 	u8         reserved_at_8[0x18];
4273 
4274 	u8         syndrome[0x20];
4275 
4276 	u8         reserved_at_40[0x40];
4277 };
4278 
4279 struct mlx5_ifc_modify_vport_state_in_bits {
4280 	u8         opcode[0x10];
4281 	u8         reserved_at_10[0x10];
4282 
4283 	u8         reserved_at_20[0x10];
4284 	u8         op_mod[0x10];
4285 
4286 	u8         other_vport[0x1];
4287 	u8         reserved_at_41[0xf];
4288 	u8         vport_number[0x10];
4289 
4290 	u8         reserved_at_60[0x18];
4291 	u8         admin_state[0x4];
4292 	u8         reserved_at_7c[0x4];
4293 };
4294 
4295 struct mlx5_ifc_modify_tis_out_bits {
4296 	u8         status[0x8];
4297 	u8         reserved_at_8[0x18];
4298 
4299 	u8         syndrome[0x20];
4300 
4301 	u8         reserved_at_40[0x40];
4302 };
4303 
4304 struct mlx5_ifc_modify_tis_bitmask_bits {
4305 	u8         reserved_at_0[0x20];
4306 
4307 	u8         reserved_at_20[0x1f];
4308 	u8         prio[0x1];
4309 };
4310 
4311 struct mlx5_ifc_modify_tis_in_bits {
4312 	u8         opcode[0x10];
4313 	u8         reserved_at_10[0x10];
4314 
4315 	u8         reserved_at_20[0x10];
4316 	u8         op_mod[0x10];
4317 
4318 	u8         reserved_at_40[0x8];
4319 	u8         tisn[0x18];
4320 
4321 	u8         reserved_at_60[0x20];
4322 
4323 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4324 
4325 	u8         reserved_at_c0[0x40];
4326 
4327 	struct mlx5_ifc_tisc_bits ctx;
4328 };
4329 
4330 struct mlx5_ifc_modify_tir_bitmask_bits {
4331 	u8	   reserved_at_0[0x20];
4332 
4333 	u8         reserved_at_20[0x1b];
4334 	u8         self_lb_en[0x1];
4335 	u8         reserved_at_3c[0x1];
4336 	u8         hash[0x1];
4337 	u8         reserved_at_3e[0x1];
4338 	u8         lro[0x1];
4339 };
4340 
4341 struct mlx5_ifc_modify_tir_out_bits {
4342 	u8         status[0x8];
4343 	u8         reserved_at_8[0x18];
4344 
4345 	u8         syndrome[0x20];
4346 
4347 	u8         reserved_at_40[0x40];
4348 };
4349 
4350 struct mlx5_ifc_modify_tir_in_bits {
4351 	u8         opcode[0x10];
4352 	u8         reserved_at_10[0x10];
4353 
4354 	u8         reserved_at_20[0x10];
4355 	u8         op_mod[0x10];
4356 
4357 	u8         reserved_at_40[0x8];
4358 	u8         tirn[0x18];
4359 
4360 	u8         reserved_at_60[0x20];
4361 
4362 	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4363 
4364 	u8         reserved_at_c0[0x40];
4365 
4366 	struct mlx5_ifc_tirc_bits ctx;
4367 };
4368 
4369 struct mlx5_ifc_modify_sq_out_bits {
4370 	u8         status[0x8];
4371 	u8         reserved_at_8[0x18];
4372 
4373 	u8         syndrome[0x20];
4374 
4375 	u8         reserved_at_40[0x40];
4376 };
4377 
4378 struct mlx5_ifc_modify_sq_in_bits {
4379 	u8         opcode[0x10];
4380 	u8         reserved_at_10[0x10];
4381 
4382 	u8         reserved_at_20[0x10];
4383 	u8         op_mod[0x10];
4384 
4385 	u8         sq_state[0x4];
4386 	u8         reserved_at_44[0x4];
4387 	u8         sqn[0x18];
4388 
4389 	u8         reserved_at_60[0x20];
4390 
4391 	u8         modify_bitmask[0x40];
4392 
4393 	u8         reserved_at_c0[0x40];
4394 
4395 	struct mlx5_ifc_sqc_bits ctx;
4396 };
4397 
4398 struct mlx5_ifc_modify_rqt_out_bits {
4399 	u8         status[0x8];
4400 	u8         reserved_at_8[0x18];
4401 
4402 	u8         syndrome[0x20];
4403 
4404 	u8         reserved_at_40[0x40];
4405 };
4406 
4407 struct mlx5_ifc_rqt_bitmask_bits {
4408 	u8	   reserved_at_0[0x20];
4409 
4410 	u8         reserved_at_20[0x1f];
4411 	u8         rqn_list[0x1];
4412 };
4413 
4414 struct mlx5_ifc_modify_rqt_in_bits {
4415 	u8         opcode[0x10];
4416 	u8         reserved_at_10[0x10];
4417 
4418 	u8         reserved_at_20[0x10];
4419 	u8         op_mod[0x10];
4420 
4421 	u8         reserved_at_40[0x8];
4422 	u8         rqtn[0x18];
4423 
4424 	u8         reserved_at_60[0x20];
4425 
4426 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
4427 
4428 	u8         reserved_at_c0[0x40];
4429 
4430 	struct mlx5_ifc_rqtc_bits ctx;
4431 };
4432 
4433 struct mlx5_ifc_modify_rq_out_bits {
4434 	u8         status[0x8];
4435 	u8         reserved_at_8[0x18];
4436 
4437 	u8         syndrome[0x20];
4438 
4439 	u8         reserved_at_40[0x40];
4440 };
4441 
4442 struct mlx5_ifc_modify_rq_in_bits {
4443 	u8         opcode[0x10];
4444 	u8         reserved_at_10[0x10];
4445 
4446 	u8         reserved_at_20[0x10];
4447 	u8         op_mod[0x10];
4448 
4449 	u8         rq_state[0x4];
4450 	u8         reserved_at_44[0x4];
4451 	u8         rqn[0x18];
4452 
4453 	u8         reserved_at_60[0x20];
4454 
4455 	u8         modify_bitmask[0x40];
4456 
4457 	u8         reserved_at_c0[0x40];
4458 
4459 	struct mlx5_ifc_rqc_bits ctx;
4460 };
4461 
4462 struct mlx5_ifc_modify_rmp_out_bits {
4463 	u8         status[0x8];
4464 	u8         reserved_at_8[0x18];
4465 
4466 	u8         syndrome[0x20];
4467 
4468 	u8         reserved_at_40[0x40];
4469 };
4470 
4471 struct mlx5_ifc_rmp_bitmask_bits {
4472 	u8	   reserved_at_0[0x20];
4473 
4474 	u8         reserved_at_20[0x1f];
4475 	u8         lwm[0x1];
4476 };
4477 
4478 struct mlx5_ifc_modify_rmp_in_bits {
4479 	u8         opcode[0x10];
4480 	u8         reserved_at_10[0x10];
4481 
4482 	u8         reserved_at_20[0x10];
4483 	u8         op_mod[0x10];
4484 
4485 	u8         rmp_state[0x4];
4486 	u8         reserved_at_44[0x4];
4487 	u8         rmpn[0x18];
4488 
4489 	u8         reserved_at_60[0x20];
4490 
4491 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
4492 
4493 	u8         reserved_at_c0[0x40];
4494 
4495 	struct mlx5_ifc_rmpc_bits ctx;
4496 };
4497 
4498 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4499 	u8         status[0x8];
4500 	u8         reserved_at_8[0x18];
4501 
4502 	u8         syndrome[0x20];
4503 
4504 	u8         reserved_at_40[0x40];
4505 };
4506 
4507 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4508 	u8         reserved_at_0[0x19];
4509 	u8         mtu[0x1];
4510 	u8         change_event[0x1];
4511 	u8         promisc[0x1];
4512 	u8         permanent_address[0x1];
4513 	u8         addresses_list[0x1];
4514 	u8         roce_en[0x1];
4515 	u8         reserved_at_1f[0x1];
4516 };
4517 
4518 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4519 	u8         opcode[0x10];
4520 	u8         reserved_at_10[0x10];
4521 
4522 	u8         reserved_at_20[0x10];
4523 	u8         op_mod[0x10];
4524 
4525 	u8         other_vport[0x1];
4526 	u8         reserved_at_41[0xf];
4527 	u8         vport_number[0x10];
4528 
4529 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4530 
4531 	u8         reserved_at_80[0x780];
4532 
4533 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4534 };
4535 
4536 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4537 	u8         status[0x8];
4538 	u8         reserved_at_8[0x18];
4539 
4540 	u8         syndrome[0x20];
4541 
4542 	u8         reserved_at_40[0x40];
4543 };
4544 
4545 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4546 	u8         opcode[0x10];
4547 	u8         reserved_at_10[0x10];
4548 
4549 	u8         reserved_at_20[0x10];
4550 	u8         op_mod[0x10];
4551 
4552 	u8         other_vport[0x1];
4553 	u8         reserved_at_41[0xb];
4554 	u8         port_num[0x4];
4555 	u8         vport_number[0x10];
4556 
4557 	u8         reserved_at_60[0x20];
4558 
4559 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4560 };
4561 
4562 struct mlx5_ifc_modify_cq_out_bits {
4563 	u8         status[0x8];
4564 	u8         reserved_at_8[0x18];
4565 
4566 	u8         syndrome[0x20];
4567 
4568 	u8         reserved_at_40[0x40];
4569 };
4570 
4571 enum {
4572 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4573 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4574 };
4575 
4576 struct mlx5_ifc_modify_cq_in_bits {
4577 	u8         opcode[0x10];
4578 	u8         reserved_at_10[0x10];
4579 
4580 	u8         reserved_at_20[0x10];
4581 	u8         op_mod[0x10];
4582 
4583 	u8         reserved_at_40[0x8];
4584 	u8         cqn[0x18];
4585 
4586 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4587 
4588 	struct mlx5_ifc_cqc_bits cq_context;
4589 
4590 	u8         reserved_at_280[0x600];
4591 
4592 	u8         pas[0][0x40];
4593 };
4594 
4595 struct mlx5_ifc_modify_cong_status_out_bits {
4596 	u8         status[0x8];
4597 	u8         reserved_at_8[0x18];
4598 
4599 	u8         syndrome[0x20];
4600 
4601 	u8         reserved_at_40[0x40];
4602 };
4603 
4604 struct mlx5_ifc_modify_cong_status_in_bits {
4605 	u8         opcode[0x10];
4606 	u8         reserved_at_10[0x10];
4607 
4608 	u8         reserved_at_20[0x10];
4609 	u8         op_mod[0x10];
4610 
4611 	u8         reserved_at_40[0x18];
4612 	u8         priority[0x4];
4613 	u8         cong_protocol[0x4];
4614 
4615 	u8         enable[0x1];
4616 	u8         tag_enable[0x1];
4617 	u8         reserved_at_62[0x1e];
4618 };
4619 
4620 struct mlx5_ifc_modify_cong_params_out_bits {
4621 	u8         status[0x8];
4622 	u8         reserved_at_8[0x18];
4623 
4624 	u8         syndrome[0x20];
4625 
4626 	u8         reserved_at_40[0x40];
4627 };
4628 
4629 struct mlx5_ifc_modify_cong_params_in_bits {
4630 	u8         opcode[0x10];
4631 	u8         reserved_at_10[0x10];
4632 
4633 	u8         reserved_at_20[0x10];
4634 	u8         op_mod[0x10];
4635 
4636 	u8         reserved_at_40[0x1c];
4637 	u8         cong_protocol[0x4];
4638 
4639 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4640 
4641 	u8         reserved_at_80[0x80];
4642 
4643 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4644 };
4645 
4646 struct mlx5_ifc_manage_pages_out_bits {
4647 	u8         status[0x8];
4648 	u8         reserved_at_8[0x18];
4649 
4650 	u8         syndrome[0x20];
4651 
4652 	u8         output_num_entries[0x20];
4653 
4654 	u8         reserved_at_60[0x20];
4655 
4656 	u8         pas[0][0x40];
4657 };
4658 
4659 enum {
4660 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
4661 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
4662 	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
4663 };
4664 
4665 struct mlx5_ifc_manage_pages_in_bits {
4666 	u8         opcode[0x10];
4667 	u8         reserved_at_10[0x10];
4668 
4669 	u8         reserved_at_20[0x10];
4670 	u8         op_mod[0x10];
4671 
4672 	u8         reserved_at_40[0x10];
4673 	u8         function_id[0x10];
4674 
4675 	u8         input_num_entries[0x20];
4676 
4677 	u8         pas[0][0x40];
4678 };
4679 
4680 struct mlx5_ifc_mad_ifc_out_bits {
4681 	u8         status[0x8];
4682 	u8         reserved_at_8[0x18];
4683 
4684 	u8         syndrome[0x20];
4685 
4686 	u8         reserved_at_40[0x40];
4687 
4688 	u8         response_mad_packet[256][0x8];
4689 };
4690 
4691 struct mlx5_ifc_mad_ifc_in_bits {
4692 	u8         opcode[0x10];
4693 	u8         reserved_at_10[0x10];
4694 
4695 	u8         reserved_at_20[0x10];
4696 	u8         op_mod[0x10];
4697 
4698 	u8         remote_lid[0x10];
4699 	u8         reserved_at_50[0x8];
4700 	u8         port[0x8];
4701 
4702 	u8         reserved_at_60[0x20];
4703 
4704 	u8         mad[256][0x8];
4705 };
4706 
4707 struct mlx5_ifc_init_hca_out_bits {
4708 	u8         status[0x8];
4709 	u8         reserved_at_8[0x18];
4710 
4711 	u8         syndrome[0x20];
4712 
4713 	u8         reserved_at_40[0x40];
4714 };
4715 
4716 struct mlx5_ifc_init_hca_in_bits {
4717 	u8         opcode[0x10];
4718 	u8         reserved_at_10[0x10];
4719 
4720 	u8         reserved_at_20[0x10];
4721 	u8         op_mod[0x10];
4722 
4723 	u8         reserved_at_40[0x40];
4724 };
4725 
4726 struct mlx5_ifc_init2rtr_qp_out_bits {
4727 	u8         status[0x8];
4728 	u8         reserved_at_8[0x18];
4729 
4730 	u8         syndrome[0x20];
4731 
4732 	u8         reserved_at_40[0x40];
4733 };
4734 
4735 struct mlx5_ifc_init2rtr_qp_in_bits {
4736 	u8         opcode[0x10];
4737 	u8         reserved_at_10[0x10];
4738 
4739 	u8         reserved_at_20[0x10];
4740 	u8         op_mod[0x10];
4741 
4742 	u8         reserved_at_40[0x8];
4743 	u8         qpn[0x18];
4744 
4745 	u8         reserved_at_60[0x20];
4746 
4747 	u8         opt_param_mask[0x20];
4748 
4749 	u8         reserved_at_a0[0x20];
4750 
4751 	struct mlx5_ifc_qpc_bits qpc;
4752 
4753 	u8         reserved_at_800[0x80];
4754 };
4755 
4756 struct mlx5_ifc_init2init_qp_out_bits {
4757 	u8         status[0x8];
4758 	u8         reserved_at_8[0x18];
4759 
4760 	u8         syndrome[0x20];
4761 
4762 	u8         reserved_at_40[0x40];
4763 };
4764 
4765 struct mlx5_ifc_init2init_qp_in_bits {
4766 	u8         opcode[0x10];
4767 	u8         reserved_at_10[0x10];
4768 
4769 	u8         reserved_at_20[0x10];
4770 	u8         op_mod[0x10];
4771 
4772 	u8         reserved_at_40[0x8];
4773 	u8         qpn[0x18];
4774 
4775 	u8         reserved_at_60[0x20];
4776 
4777 	u8         opt_param_mask[0x20];
4778 
4779 	u8         reserved_at_a0[0x20];
4780 
4781 	struct mlx5_ifc_qpc_bits qpc;
4782 
4783 	u8         reserved_at_800[0x80];
4784 };
4785 
4786 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4787 	u8         status[0x8];
4788 	u8         reserved_at_8[0x18];
4789 
4790 	u8         syndrome[0x20];
4791 
4792 	u8         reserved_at_40[0x40];
4793 
4794 	u8         packet_headers_log[128][0x8];
4795 
4796 	u8         packet_syndrome[64][0x8];
4797 };
4798 
4799 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4800 	u8         opcode[0x10];
4801 	u8         reserved_at_10[0x10];
4802 
4803 	u8         reserved_at_20[0x10];
4804 	u8         op_mod[0x10];
4805 
4806 	u8         reserved_at_40[0x40];
4807 };
4808 
4809 struct mlx5_ifc_gen_eqe_in_bits {
4810 	u8         opcode[0x10];
4811 	u8         reserved_at_10[0x10];
4812 
4813 	u8         reserved_at_20[0x10];
4814 	u8         op_mod[0x10];
4815 
4816 	u8         reserved_at_40[0x18];
4817 	u8         eq_number[0x8];
4818 
4819 	u8         reserved_at_60[0x20];
4820 
4821 	u8         eqe[64][0x8];
4822 };
4823 
4824 struct mlx5_ifc_gen_eq_out_bits {
4825 	u8         status[0x8];
4826 	u8         reserved_at_8[0x18];
4827 
4828 	u8         syndrome[0x20];
4829 
4830 	u8         reserved_at_40[0x40];
4831 };
4832 
4833 struct mlx5_ifc_enable_hca_out_bits {
4834 	u8         status[0x8];
4835 	u8         reserved_at_8[0x18];
4836 
4837 	u8         syndrome[0x20];
4838 
4839 	u8         reserved_at_40[0x20];
4840 };
4841 
4842 struct mlx5_ifc_enable_hca_in_bits {
4843 	u8         opcode[0x10];
4844 	u8         reserved_at_10[0x10];
4845 
4846 	u8         reserved_at_20[0x10];
4847 	u8         op_mod[0x10];
4848 
4849 	u8         reserved_at_40[0x10];
4850 	u8         function_id[0x10];
4851 
4852 	u8         reserved_at_60[0x20];
4853 };
4854 
4855 struct mlx5_ifc_drain_dct_out_bits {
4856 	u8         status[0x8];
4857 	u8         reserved_at_8[0x18];
4858 
4859 	u8         syndrome[0x20];
4860 
4861 	u8         reserved_at_40[0x40];
4862 };
4863 
4864 struct mlx5_ifc_drain_dct_in_bits {
4865 	u8         opcode[0x10];
4866 	u8         reserved_at_10[0x10];
4867 
4868 	u8         reserved_at_20[0x10];
4869 	u8         op_mod[0x10];
4870 
4871 	u8         reserved_at_40[0x8];
4872 	u8         dctn[0x18];
4873 
4874 	u8         reserved_at_60[0x20];
4875 };
4876 
4877 struct mlx5_ifc_disable_hca_out_bits {
4878 	u8         status[0x8];
4879 	u8         reserved_at_8[0x18];
4880 
4881 	u8         syndrome[0x20];
4882 
4883 	u8         reserved_at_40[0x20];
4884 };
4885 
4886 struct mlx5_ifc_disable_hca_in_bits {
4887 	u8         opcode[0x10];
4888 	u8         reserved_at_10[0x10];
4889 
4890 	u8         reserved_at_20[0x10];
4891 	u8         op_mod[0x10];
4892 
4893 	u8         reserved_at_40[0x10];
4894 	u8         function_id[0x10];
4895 
4896 	u8         reserved_at_60[0x20];
4897 };
4898 
4899 struct mlx5_ifc_detach_from_mcg_out_bits {
4900 	u8         status[0x8];
4901 	u8         reserved_at_8[0x18];
4902 
4903 	u8         syndrome[0x20];
4904 
4905 	u8         reserved_at_40[0x40];
4906 };
4907 
4908 struct mlx5_ifc_detach_from_mcg_in_bits {
4909 	u8         opcode[0x10];
4910 	u8         reserved_at_10[0x10];
4911 
4912 	u8         reserved_at_20[0x10];
4913 	u8         op_mod[0x10];
4914 
4915 	u8         reserved_at_40[0x8];
4916 	u8         qpn[0x18];
4917 
4918 	u8         reserved_at_60[0x20];
4919 
4920 	u8         multicast_gid[16][0x8];
4921 };
4922 
4923 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4924 	u8         status[0x8];
4925 	u8         reserved_at_8[0x18];
4926 
4927 	u8         syndrome[0x20];
4928 
4929 	u8         reserved_at_40[0x40];
4930 };
4931 
4932 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4933 	u8         opcode[0x10];
4934 	u8         reserved_at_10[0x10];
4935 
4936 	u8         reserved_at_20[0x10];
4937 	u8         op_mod[0x10];
4938 
4939 	u8         reserved_at_40[0x8];
4940 	u8         xrc_srqn[0x18];
4941 
4942 	u8         reserved_at_60[0x20];
4943 };
4944 
4945 struct mlx5_ifc_destroy_tis_out_bits {
4946 	u8         status[0x8];
4947 	u8         reserved_at_8[0x18];
4948 
4949 	u8         syndrome[0x20];
4950 
4951 	u8         reserved_at_40[0x40];
4952 };
4953 
4954 struct mlx5_ifc_destroy_tis_in_bits {
4955 	u8         opcode[0x10];
4956 	u8         reserved_at_10[0x10];
4957 
4958 	u8         reserved_at_20[0x10];
4959 	u8         op_mod[0x10];
4960 
4961 	u8         reserved_at_40[0x8];
4962 	u8         tisn[0x18];
4963 
4964 	u8         reserved_at_60[0x20];
4965 };
4966 
4967 struct mlx5_ifc_destroy_tir_out_bits {
4968 	u8         status[0x8];
4969 	u8         reserved_at_8[0x18];
4970 
4971 	u8         syndrome[0x20];
4972 
4973 	u8         reserved_at_40[0x40];
4974 };
4975 
4976 struct mlx5_ifc_destroy_tir_in_bits {
4977 	u8         opcode[0x10];
4978 	u8         reserved_at_10[0x10];
4979 
4980 	u8         reserved_at_20[0x10];
4981 	u8         op_mod[0x10];
4982 
4983 	u8         reserved_at_40[0x8];
4984 	u8         tirn[0x18];
4985 
4986 	u8         reserved_at_60[0x20];
4987 };
4988 
4989 struct mlx5_ifc_destroy_srq_out_bits {
4990 	u8         status[0x8];
4991 	u8         reserved_at_8[0x18];
4992 
4993 	u8         syndrome[0x20];
4994 
4995 	u8         reserved_at_40[0x40];
4996 };
4997 
4998 struct mlx5_ifc_destroy_srq_in_bits {
4999 	u8         opcode[0x10];
5000 	u8         reserved_at_10[0x10];
5001 
5002 	u8         reserved_at_20[0x10];
5003 	u8         op_mod[0x10];
5004 
5005 	u8         reserved_at_40[0x8];
5006 	u8         srqn[0x18];
5007 
5008 	u8         reserved_at_60[0x20];
5009 };
5010 
5011 struct mlx5_ifc_destroy_sq_out_bits {
5012 	u8         status[0x8];
5013 	u8         reserved_at_8[0x18];
5014 
5015 	u8         syndrome[0x20];
5016 
5017 	u8         reserved_at_40[0x40];
5018 };
5019 
5020 struct mlx5_ifc_destroy_sq_in_bits {
5021 	u8         opcode[0x10];
5022 	u8         reserved_at_10[0x10];
5023 
5024 	u8         reserved_at_20[0x10];
5025 	u8         op_mod[0x10];
5026 
5027 	u8         reserved_at_40[0x8];
5028 	u8         sqn[0x18];
5029 
5030 	u8         reserved_at_60[0x20];
5031 };
5032 
5033 struct mlx5_ifc_destroy_rqt_out_bits {
5034 	u8         status[0x8];
5035 	u8         reserved_at_8[0x18];
5036 
5037 	u8         syndrome[0x20];
5038 
5039 	u8         reserved_at_40[0x40];
5040 };
5041 
5042 struct mlx5_ifc_destroy_rqt_in_bits {
5043 	u8         opcode[0x10];
5044 	u8         reserved_at_10[0x10];
5045 
5046 	u8         reserved_at_20[0x10];
5047 	u8         op_mod[0x10];
5048 
5049 	u8         reserved_at_40[0x8];
5050 	u8         rqtn[0x18];
5051 
5052 	u8         reserved_at_60[0x20];
5053 };
5054 
5055 struct mlx5_ifc_destroy_rq_out_bits {
5056 	u8         status[0x8];
5057 	u8         reserved_at_8[0x18];
5058 
5059 	u8         syndrome[0x20];
5060 
5061 	u8         reserved_at_40[0x40];
5062 };
5063 
5064 struct mlx5_ifc_destroy_rq_in_bits {
5065 	u8         opcode[0x10];
5066 	u8         reserved_at_10[0x10];
5067 
5068 	u8         reserved_at_20[0x10];
5069 	u8         op_mod[0x10];
5070 
5071 	u8         reserved_at_40[0x8];
5072 	u8         rqn[0x18];
5073 
5074 	u8         reserved_at_60[0x20];
5075 };
5076 
5077 struct mlx5_ifc_destroy_rmp_out_bits {
5078 	u8         status[0x8];
5079 	u8         reserved_at_8[0x18];
5080 
5081 	u8         syndrome[0x20];
5082 
5083 	u8         reserved_at_40[0x40];
5084 };
5085 
5086 struct mlx5_ifc_destroy_rmp_in_bits {
5087 	u8         opcode[0x10];
5088 	u8         reserved_at_10[0x10];
5089 
5090 	u8         reserved_at_20[0x10];
5091 	u8         op_mod[0x10];
5092 
5093 	u8         reserved_at_40[0x8];
5094 	u8         rmpn[0x18];
5095 
5096 	u8         reserved_at_60[0x20];
5097 };
5098 
5099 struct mlx5_ifc_destroy_qp_out_bits {
5100 	u8         status[0x8];
5101 	u8         reserved_at_8[0x18];
5102 
5103 	u8         syndrome[0x20];
5104 
5105 	u8         reserved_at_40[0x40];
5106 };
5107 
5108 struct mlx5_ifc_destroy_qp_in_bits {
5109 	u8         opcode[0x10];
5110 	u8         reserved_at_10[0x10];
5111 
5112 	u8         reserved_at_20[0x10];
5113 	u8         op_mod[0x10];
5114 
5115 	u8         reserved_at_40[0x8];
5116 	u8         qpn[0x18];
5117 
5118 	u8         reserved_at_60[0x20];
5119 };
5120 
5121 struct mlx5_ifc_destroy_psv_out_bits {
5122 	u8         status[0x8];
5123 	u8         reserved_at_8[0x18];
5124 
5125 	u8         syndrome[0x20];
5126 
5127 	u8         reserved_at_40[0x40];
5128 };
5129 
5130 struct mlx5_ifc_destroy_psv_in_bits {
5131 	u8         opcode[0x10];
5132 	u8         reserved_at_10[0x10];
5133 
5134 	u8         reserved_at_20[0x10];
5135 	u8         op_mod[0x10];
5136 
5137 	u8         reserved_at_40[0x8];
5138 	u8         psvn[0x18];
5139 
5140 	u8         reserved_at_60[0x20];
5141 };
5142 
5143 struct mlx5_ifc_destroy_mkey_out_bits {
5144 	u8         status[0x8];
5145 	u8         reserved_at_8[0x18];
5146 
5147 	u8         syndrome[0x20];
5148 
5149 	u8         reserved_at_40[0x40];
5150 };
5151 
5152 struct mlx5_ifc_destroy_mkey_in_bits {
5153 	u8         opcode[0x10];
5154 	u8         reserved_at_10[0x10];
5155 
5156 	u8         reserved_at_20[0x10];
5157 	u8         op_mod[0x10];
5158 
5159 	u8         reserved_at_40[0x8];
5160 	u8         mkey_index[0x18];
5161 
5162 	u8         reserved_at_60[0x20];
5163 };
5164 
5165 struct mlx5_ifc_destroy_flow_table_out_bits {
5166 	u8         status[0x8];
5167 	u8         reserved_at_8[0x18];
5168 
5169 	u8         syndrome[0x20];
5170 
5171 	u8         reserved_at_40[0x40];
5172 };
5173 
5174 struct mlx5_ifc_destroy_flow_table_in_bits {
5175 	u8         opcode[0x10];
5176 	u8         reserved_at_10[0x10];
5177 
5178 	u8         reserved_at_20[0x10];
5179 	u8         op_mod[0x10];
5180 
5181 	u8         reserved_at_40[0x40];
5182 
5183 	u8         table_type[0x8];
5184 	u8         reserved_at_88[0x18];
5185 
5186 	u8         reserved_at_a0[0x8];
5187 	u8         table_id[0x18];
5188 
5189 	u8         reserved_at_c0[0x140];
5190 };
5191 
5192 struct mlx5_ifc_destroy_flow_group_out_bits {
5193 	u8         status[0x8];
5194 	u8         reserved_at_8[0x18];
5195 
5196 	u8         syndrome[0x20];
5197 
5198 	u8         reserved_at_40[0x40];
5199 };
5200 
5201 struct mlx5_ifc_destroy_flow_group_in_bits {
5202 	u8         opcode[0x10];
5203 	u8         reserved_at_10[0x10];
5204 
5205 	u8         reserved_at_20[0x10];
5206 	u8         op_mod[0x10];
5207 
5208 	u8         reserved_at_40[0x40];
5209 
5210 	u8         table_type[0x8];
5211 	u8         reserved_at_88[0x18];
5212 
5213 	u8         reserved_at_a0[0x8];
5214 	u8         table_id[0x18];
5215 
5216 	u8         group_id[0x20];
5217 
5218 	u8         reserved_at_e0[0x120];
5219 };
5220 
5221 struct mlx5_ifc_destroy_eq_out_bits {
5222 	u8         status[0x8];
5223 	u8         reserved_at_8[0x18];
5224 
5225 	u8         syndrome[0x20];
5226 
5227 	u8         reserved_at_40[0x40];
5228 };
5229 
5230 struct mlx5_ifc_destroy_eq_in_bits {
5231 	u8         opcode[0x10];
5232 	u8         reserved_at_10[0x10];
5233 
5234 	u8         reserved_at_20[0x10];
5235 	u8         op_mod[0x10];
5236 
5237 	u8         reserved_at_40[0x18];
5238 	u8         eq_number[0x8];
5239 
5240 	u8         reserved_at_60[0x20];
5241 };
5242 
5243 struct mlx5_ifc_destroy_dct_out_bits {
5244 	u8         status[0x8];
5245 	u8         reserved_at_8[0x18];
5246 
5247 	u8         syndrome[0x20];
5248 
5249 	u8         reserved_at_40[0x40];
5250 };
5251 
5252 struct mlx5_ifc_destroy_dct_in_bits {
5253 	u8         opcode[0x10];
5254 	u8         reserved_at_10[0x10];
5255 
5256 	u8         reserved_at_20[0x10];
5257 	u8         op_mod[0x10];
5258 
5259 	u8         reserved_at_40[0x8];
5260 	u8         dctn[0x18];
5261 
5262 	u8         reserved_at_60[0x20];
5263 };
5264 
5265 struct mlx5_ifc_destroy_cq_out_bits {
5266 	u8         status[0x8];
5267 	u8         reserved_at_8[0x18];
5268 
5269 	u8         syndrome[0x20];
5270 
5271 	u8         reserved_at_40[0x40];
5272 };
5273 
5274 struct mlx5_ifc_destroy_cq_in_bits {
5275 	u8         opcode[0x10];
5276 	u8         reserved_at_10[0x10];
5277 
5278 	u8         reserved_at_20[0x10];
5279 	u8         op_mod[0x10];
5280 
5281 	u8         reserved_at_40[0x8];
5282 	u8         cqn[0x18];
5283 
5284 	u8         reserved_at_60[0x20];
5285 };
5286 
5287 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5288 	u8         status[0x8];
5289 	u8         reserved_at_8[0x18];
5290 
5291 	u8         syndrome[0x20];
5292 
5293 	u8         reserved_at_40[0x40];
5294 };
5295 
5296 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5297 	u8         opcode[0x10];
5298 	u8         reserved_at_10[0x10];
5299 
5300 	u8         reserved_at_20[0x10];
5301 	u8         op_mod[0x10];
5302 
5303 	u8         reserved_at_40[0x20];
5304 
5305 	u8         reserved_at_60[0x10];
5306 	u8         vxlan_udp_port[0x10];
5307 };
5308 
5309 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5310 	u8         status[0x8];
5311 	u8         reserved_at_8[0x18];
5312 
5313 	u8         syndrome[0x20];
5314 
5315 	u8         reserved_at_40[0x40];
5316 };
5317 
5318 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5319 	u8         opcode[0x10];
5320 	u8         reserved_at_10[0x10];
5321 
5322 	u8         reserved_at_20[0x10];
5323 	u8         op_mod[0x10];
5324 
5325 	u8         reserved_at_40[0x60];
5326 
5327 	u8         reserved_at_a0[0x8];
5328 	u8         table_index[0x18];
5329 
5330 	u8         reserved_at_c0[0x140];
5331 };
5332 
5333 struct mlx5_ifc_delete_fte_out_bits {
5334 	u8         status[0x8];
5335 	u8         reserved_at_8[0x18];
5336 
5337 	u8         syndrome[0x20];
5338 
5339 	u8         reserved_at_40[0x40];
5340 };
5341 
5342 struct mlx5_ifc_delete_fte_in_bits {
5343 	u8         opcode[0x10];
5344 	u8         reserved_at_10[0x10];
5345 
5346 	u8         reserved_at_20[0x10];
5347 	u8         op_mod[0x10];
5348 
5349 	u8         reserved_at_40[0x40];
5350 
5351 	u8         table_type[0x8];
5352 	u8         reserved_at_88[0x18];
5353 
5354 	u8         reserved_at_a0[0x8];
5355 	u8         table_id[0x18];
5356 
5357 	u8         reserved_at_c0[0x40];
5358 
5359 	u8         flow_index[0x20];
5360 
5361 	u8         reserved_at_120[0xe0];
5362 };
5363 
5364 struct mlx5_ifc_dealloc_xrcd_out_bits {
5365 	u8         status[0x8];
5366 	u8         reserved_at_8[0x18];
5367 
5368 	u8         syndrome[0x20];
5369 
5370 	u8         reserved_at_40[0x40];
5371 };
5372 
5373 struct mlx5_ifc_dealloc_xrcd_in_bits {
5374 	u8         opcode[0x10];
5375 	u8         reserved_at_10[0x10];
5376 
5377 	u8         reserved_at_20[0x10];
5378 	u8         op_mod[0x10];
5379 
5380 	u8         reserved_at_40[0x8];
5381 	u8         xrcd[0x18];
5382 
5383 	u8         reserved_at_60[0x20];
5384 };
5385 
5386 struct mlx5_ifc_dealloc_uar_out_bits {
5387 	u8         status[0x8];
5388 	u8         reserved_at_8[0x18];
5389 
5390 	u8         syndrome[0x20];
5391 
5392 	u8         reserved_at_40[0x40];
5393 };
5394 
5395 struct mlx5_ifc_dealloc_uar_in_bits {
5396 	u8         opcode[0x10];
5397 	u8         reserved_at_10[0x10];
5398 
5399 	u8         reserved_at_20[0x10];
5400 	u8         op_mod[0x10];
5401 
5402 	u8         reserved_at_40[0x8];
5403 	u8         uar[0x18];
5404 
5405 	u8         reserved_at_60[0x20];
5406 };
5407 
5408 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5409 	u8         status[0x8];
5410 	u8         reserved_at_8[0x18];
5411 
5412 	u8         syndrome[0x20];
5413 
5414 	u8         reserved_at_40[0x40];
5415 };
5416 
5417 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5418 	u8         opcode[0x10];
5419 	u8         reserved_at_10[0x10];
5420 
5421 	u8         reserved_at_20[0x10];
5422 	u8         op_mod[0x10];
5423 
5424 	u8         reserved_at_40[0x8];
5425 	u8         transport_domain[0x18];
5426 
5427 	u8         reserved_at_60[0x20];
5428 };
5429 
5430 struct mlx5_ifc_dealloc_q_counter_out_bits {
5431 	u8         status[0x8];
5432 	u8         reserved_at_8[0x18];
5433 
5434 	u8         syndrome[0x20];
5435 
5436 	u8         reserved_at_40[0x40];
5437 };
5438 
5439 struct mlx5_ifc_dealloc_q_counter_in_bits {
5440 	u8         opcode[0x10];
5441 	u8         reserved_at_10[0x10];
5442 
5443 	u8         reserved_at_20[0x10];
5444 	u8         op_mod[0x10];
5445 
5446 	u8         reserved_at_40[0x18];
5447 	u8         counter_set_id[0x8];
5448 
5449 	u8         reserved_at_60[0x20];
5450 };
5451 
5452 struct mlx5_ifc_dealloc_pd_out_bits {
5453 	u8         status[0x8];
5454 	u8         reserved_at_8[0x18];
5455 
5456 	u8         syndrome[0x20];
5457 
5458 	u8         reserved_at_40[0x40];
5459 };
5460 
5461 struct mlx5_ifc_dealloc_pd_in_bits {
5462 	u8         opcode[0x10];
5463 	u8         reserved_at_10[0x10];
5464 
5465 	u8         reserved_at_20[0x10];
5466 	u8         op_mod[0x10];
5467 
5468 	u8         reserved_at_40[0x8];
5469 	u8         pd[0x18];
5470 
5471 	u8         reserved_at_60[0x20];
5472 };
5473 
5474 struct mlx5_ifc_create_xrc_srq_out_bits {
5475 	u8         status[0x8];
5476 	u8         reserved_at_8[0x18];
5477 
5478 	u8         syndrome[0x20];
5479 
5480 	u8         reserved_at_40[0x8];
5481 	u8         xrc_srqn[0x18];
5482 
5483 	u8         reserved_at_60[0x20];
5484 };
5485 
5486 struct mlx5_ifc_create_xrc_srq_in_bits {
5487 	u8         opcode[0x10];
5488 	u8         reserved_at_10[0x10];
5489 
5490 	u8         reserved_at_20[0x10];
5491 	u8         op_mod[0x10];
5492 
5493 	u8         reserved_at_40[0x40];
5494 
5495 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5496 
5497 	u8         reserved_at_280[0x600];
5498 
5499 	u8         pas[0][0x40];
5500 };
5501 
5502 struct mlx5_ifc_create_tis_out_bits {
5503 	u8         status[0x8];
5504 	u8         reserved_at_8[0x18];
5505 
5506 	u8         syndrome[0x20];
5507 
5508 	u8         reserved_at_40[0x8];
5509 	u8         tisn[0x18];
5510 
5511 	u8         reserved_at_60[0x20];
5512 };
5513 
5514 struct mlx5_ifc_create_tis_in_bits {
5515 	u8         opcode[0x10];
5516 	u8         reserved_at_10[0x10];
5517 
5518 	u8         reserved_at_20[0x10];
5519 	u8         op_mod[0x10];
5520 
5521 	u8         reserved_at_40[0xc0];
5522 
5523 	struct mlx5_ifc_tisc_bits ctx;
5524 };
5525 
5526 struct mlx5_ifc_create_tir_out_bits {
5527 	u8         status[0x8];
5528 	u8         reserved_at_8[0x18];
5529 
5530 	u8         syndrome[0x20];
5531 
5532 	u8         reserved_at_40[0x8];
5533 	u8         tirn[0x18];
5534 
5535 	u8         reserved_at_60[0x20];
5536 };
5537 
5538 struct mlx5_ifc_create_tir_in_bits {
5539 	u8         opcode[0x10];
5540 	u8         reserved_at_10[0x10];
5541 
5542 	u8         reserved_at_20[0x10];
5543 	u8         op_mod[0x10];
5544 
5545 	u8         reserved_at_40[0xc0];
5546 
5547 	struct mlx5_ifc_tirc_bits ctx;
5548 };
5549 
5550 struct mlx5_ifc_create_srq_out_bits {
5551 	u8         status[0x8];
5552 	u8         reserved_at_8[0x18];
5553 
5554 	u8         syndrome[0x20];
5555 
5556 	u8         reserved_at_40[0x8];
5557 	u8         srqn[0x18];
5558 
5559 	u8         reserved_at_60[0x20];
5560 };
5561 
5562 struct mlx5_ifc_create_srq_in_bits {
5563 	u8         opcode[0x10];
5564 	u8         reserved_at_10[0x10];
5565 
5566 	u8         reserved_at_20[0x10];
5567 	u8         op_mod[0x10];
5568 
5569 	u8         reserved_at_40[0x40];
5570 
5571 	struct mlx5_ifc_srqc_bits srq_context_entry;
5572 
5573 	u8         reserved_at_280[0x600];
5574 
5575 	u8         pas[0][0x40];
5576 };
5577 
5578 struct mlx5_ifc_create_sq_out_bits {
5579 	u8         status[0x8];
5580 	u8         reserved_at_8[0x18];
5581 
5582 	u8         syndrome[0x20];
5583 
5584 	u8         reserved_at_40[0x8];
5585 	u8         sqn[0x18];
5586 
5587 	u8         reserved_at_60[0x20];
5588 };
5589 
5590 struct mlx5_ifc_create_sq_in_bits {
5591 	u8         opcode[0x10];
5592 	u8         reserved_at_10[0x10];
5593 
5594 	u8         reserved_at_20[0x10];
5595 	u8         op_mod[0x10];
5596 
5597 	u8         reserved_at_40[0xc0];
5598 
5599 	struct mlx5_ifc_sqc_bits ctx;
5600 };
5601 
5602 struct mlx5_ifc_create_rqt_out_bits {
5603 	u8         status[0x8];
5604 	u8         reserved_at_8[0x18];
5605 
5606 	u8         syndrome[0x20];
5607 
5608 	u8         reserved_at_40[0x8];
5609 	u8         rqtn[0x18];
5610 
5611 	u8         reserved_at_60[0x20];
5612 };
5613 
5614 struct mlx5_ifc_create_rqt_in_bits {
5615 	u8         opcode[0x10];
5616 	u8         reserved_at_10[0x10];
5617 
5618 	u8         reserved_at_20[0x10];
5619 	u8         op_mod[0x10];
5620 
5621 	u8         reserved_at_40[0xc0];
5622 
5623 	struct mlx5_ifc_rqtc_bits rqt_context;
5624 };
5625 
5626 struct mlx5_ifc_create_rq_out_bits {
5627 	u8         status[0x8];
5628 	u8         reserved_at_8[0x18];
5629 
5630 	u8         syndrome[0x20];
5631 
5632 	u8         reserved_at_40[0x8];
5633 	u8         rqn[0x18];
5634 
5635 	u8         reserved_at_60[0x20];
5636 };
5637 
5638 struct mlx5_ifc_create_rq_in_bits {
5639 	u8         opcode[0x10];
5640 	u8         reserved_at_10[0x10];
5641 
5642 	u8         reserved_at_20[0x10];
5643 	u8         op_mod[0x10];
5644 
5645 	u8         reserved_at_40[0xc0];
5646 
5647 	struct mlx5_ifc_rqc_bits ctx;
5648 };
5649 
5650 struct mlx5_ifc_create_rmp_out_bits {
5651 	u8         status[0x8];
5652 	u8         reserved_at_8[0x18];
5653 
5654 	u8         syndrome[0x20];
5655 
5656 	u8         reserved_at_40[0x8];
5657 	u8         rmpn[0x18];
5658 
5659 	u8         reserved_at_60[0x20];
5660 };
5661 
5662 struct mlx5_ifc_create_rmp_in_bits {
5663 	u8         opcode[0x10];
5664 	u8         reserved_at_10[0x10];
5665 
5666 	u8         reserved_at_20[0x10];
5667 	u8         op_mod[0x10];
5668 
5669 	u8         reserved_at_40[0xc0];
5670 
5671 	struct mlx5_ifc_rmpc_bits ctx;
5672 };
5673 
5674 struct mlx5_ifc_create_qp_out_bits {
5675 	u8         status[0x8];
5676 	u8         reserved_at_8[0x18];
5677 
5678 	u8         syndrome[0x20];
5679 
5680 	u8         reserved_at_40[0x8];
5681 	u8         qpn[0x18];
5682 
5683 	u8         reserved_at_60[0x20];
5684 };
5685 
5686 struct mlx5_ifc_create_qp_in_bits {
5687 	u8         opcode[0x10];
5688 	u8         reserved_at_10[0x10];
5689 
5690 	u8         reserved_at_20[0x10];
5691 	u8         op_mod[0x10];
5692 
5693 	u8         reserved_at_40[0x40];
5694 
5695 	u8         opt_param_mask[0x20];
5696 
5697 	u8         reserved_at_a0[0x20];
5698 
5699 	struct mlx5_ifc_qpc_bits qpc;
5700 
5701 	u8         reserved_at_800[0x80];
5702 
5703 	u8         pas[0][0x40];
5704 };
5705 
5706 struct mlx5_ifc_create_psv_out_bits {
5707 	u8         status[0x8];
5708 	u8         reserved_at_8[0x18];
5709 
5710 	u8         syndrome[0x20];
5711 
5712 	u8         reserved_at_40[0x40];
5713 
5714 	u8         reserved_at_80[0x8];
5715 	u8         psv0_index[0x18];
5716 
5717 	u8         reserved_at_a0[0x8];
5718 	u8         psv1_index[0x18];
5719 
5720 	u8         reserved_at_c0[0x8];
5721 	u8         psv2_index[0x18];
5722 
5723 	u8         reserved_at_e0[0x8];
5724 	u8         psv3_index[0x18];
5725 };
5726 
5727 struct mlx5_ifc_create_psv_in_bits {
5728 	u8         opcode[0x10];
5729 	u8         reserved_at_10[0x10];
5730 
5731 	u8         reserved_at_20[0x10];
5732 	u8         op_mod[0x10];
5733 
5734 	u8         num_psv[0x4];
5735 	u8         reserved_at_44[0x4];
5736 	u8         pd[0x18];
5737 
5738 	u8         reserved_at_60[0x20];
5739 };
5740 
5741 struct mlx5_ifc_create_mkey_out_bits {
5742 	u8         status[0x8];
5743 	u8         reserved_at_8[0x18];
5744 
5745 	u8         syndrome[0x20];
5746 
5747 	u8         reserved_at_40[0x8];
5748 	u8         mkey_index[0x18];
5749 
5750 	u8         reserved_at_60[0x20];
5751 };
5752 
5753 struct mlx5_ifc_create_mkey_in_bits {
5754 	u8         opcode[0x10];
5755 	u8         reserved_at_10[0x10];
5756 
5757 	u8         reserved_at_20[0x10];
5758 	u8         op_mod[0x10];
5759 
5760 	u8         reserved_at_40[0x20];
5761 
5762 	u8         pg_access[0x1];
5763 	u8         reserved_at_61[0x1f];
5764 
5765 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5766 
5767 	u8         reserved_at_280[0x80];
5768 
5769 	u8         translations_octword_actual_size[0x20];
5770 
5771 	u8         reserved_at_320[0x560];
5772 
5773 	u8         klm_pas_mtt[0][0x20];
5774 };
5775 
5776 struct mlx5_ifc_create_flow_table_out_bits {
5777 	u8         status[0x8];
5778 	u8         reserved_at_8[0x18];
5779 
5780 	u8         syndrome[0x20];
5781 
5782 	u8         reserved_at_40[0x8];
5783 	u8         table_id[0x18];
5784 
5785 	u8         reserved_at_60[0x20];
5786 };
5787 
5788 struct mlx5_ifc_create_flow_table_in_bits {
5789 	u8         opcode[0x10];
5790 	u8         reserved_at_10[0x10];
5791 
5792 	u8         reserved_at_20[0x10];
5793 	u8         op_mod[0x10];
5794 
5795 	u8         reserved_at_40[0x40];
5796 
5797 	u8         table_type[0x8];
5798 	u8         reserved_at_88[0x18];
5799 
5800 	u8         reserved_at_a0[0x20];
5801 
5802 	u8         reserved_at_c0[0x4];
5803 	u8         table_miss_mode[0x4];
5804 	u8         level[0x8];
5805 	u8         reserved_at_d0[0x8];
5806 	u8         log_size[0x8];
5807 
5808 	u8         reserved_at_e0[0x8];
5809 	u8         table_miss_id[0x18];
5810 
5811 	u8         reserved_at_100[0x100];
5812 };
5813 
5814 struct mlx5_ifc_create_flow_group_out_bits {
5815 	u8         status[0x8];
5816 	u8         reserved_at_8[0x18];
5817 
5818 	u8         syndrome[0x20];
5819 
5820 	u8         reserved_at_40[0x8];
5821 	u8         group_id[0x18];
5822 
5823 	u8         reserved_at_60[0x20];
5824 };
5825 
5826 enum {
5827 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5828 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5829 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5830 };
5831 
5832 struct mlx5_ifc_create_flow_group_in_bits {
5833 	u8         opcode[0x10];
5834 	u8         reserved_at_10[0x10];
5835 
5836 	u8         reserved_at_20[0x10];
5837 	u8         op_mod[0x10];
5838 
5839 	u8         reserved_at_40[0x40];
5840 
5841 	u8         table_type[0x8];
5842 	u8         reserved_at_88[0x18];
5843 
5844 	u8         reserved_at_a0[0x8];
5845 	u8         table_id[0x18];
5846 
5847 	u8         reserved_at_c0[0x20];
5848 
5849 	u8         start_flow_index[0x20];
5850 
5851 	u8         reserved_at_100[0x20];
5852 
5853 	u8         end_flow_index[0x20];
5854 
5855 	u8         reserved_at_140[0xa0];
5856 
5857 	u8         reserved_at_1e0[0x18];
5858 	u8         match_criteria_enable[0x8];
5859 
5860 	struct mlx5_ifc_fte_match_param_bits match_criteria;
5861 
5862 	u8         reserved_at_1200[0xe00];
5863 };
5864 
5865 struct mlx5_ifc_create_eq_out_bits {
5866 	u8         status[0x8];
5867 	u8         reserved_at_8[0x18];
5868 
5869 	u8         syndrome[0x20];
5870 
5871 	u8         reserved_at_40[0x18];
5872 	u8         eq_number[0x8];
5873 
5874 	u8         reserved_at_60[0x20];
5875 };
5876 
5877 struct mlx5_ifc_create_eq_in_bits {
5878 	u8         opcode[0x10];
5879 	u8         reserved_at_10[0x10];
5880 
5881 	u8         reserved_at_20[0x10];
5882 	u8         op_mod[0x10];
5883 
5884 	u8         reserved_at_40[0x40];
5885 
5886 	struct mlx5_ifc_eqc_bits eq_context_entry;
5887 
5888 	u8         reserved_at_280[0x40];
5889 
5890 	u8         event_bitmask[0x40];
5891 
5892 	u8         reserved_at_300[0x580];
5893 
5894 	u8         pas[0][0x40];
5895 };
5896 
5897 struct mlx5_ifc_create_dct_out_bits {
5898 	u8         status[0x8];
5899 	u8         reserved_at_8[0x18];
5900 
5901 	u8         syndrome[0x20];
5902 
5903 	u8         reserved_at_40[0x8];
5904 	u8         dctn[0x18];
5905 
5906 	u8         reserved_at_60[0x20];
5907 };
5908 
5909 struct mlx5_ifc_create_dct_in_bits {
5910 	u8         opcode[0x10];
5911 	u8         reserved_at_10[0x10];
5912 
5913 	u8         reserved_at_20[0x10];
5914 	u8         op_mod[0x10];
5915 
5916 	u8         reserved_at_40[0x40];
5917 
5918 	struct mlx5_ifc_dctc_bits dct_context_entry;
5919 
5920 	u8         reserved_at_280[0x180];
5921 };
5922 
5923 struct mlx5_ifc_create_cq_out_bits {
5924 	u8         status[0x8];
5925 	u8         reserved_at_8[0x18];
5926 
5927 	u8         syndrome[0x20];
5928 
5929 	u8         reserved_at_40[0x8];
5930 	u8         cqn[0x18];
5931 
5932 	u8         reserved_at_60[0x20];
5933 };
5934 
5935 struct mlx5_ifc_create_cq_in_bits {
5936 	u8         opcode[0x10];
5937 	u8         reserved_at_10[0x10];
5938 
5939 	u8         reserved_at_20[0x10];
5940 	u8         op_mod[0x10];
5941 
5942 	u8         reserved_at_40[0x40];
5943 
5944 	struct mlx5_ifc_cqc_bits cq_context;
5945 
5946 	u8         reserved_at_280[0x600];
5947 
5948 	u8         pas[0][0x40];
5949 };
5950 
5951 struct mlx5_ifc_config_int_moderation_out_bits {
5952 	u8         status[0x8];
5953 	u8         reserved_at_8[0x18];
5954 
5955 	u8         syndrome[0x20];
5956 
5957 	u8         reserved_at_40[0x4];
5958 	u8         min_delay[0xc];
5959 	u8         int_vector[0x10];
5960 
5961 	u8         reserved_at_60[0x20];
5962 };
5963 
5964 enum {
5965 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
5966 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
5967 };
5968 
5969 struct mlx5_ifc_config_int_moderation_in_bits {
5970 	u8         opcode[0x10];
5971 	u8         reserved_at_10[0x10];
5972 
5973 	u8         reserved_at_20[0x10];
5974 	u8         op_mod[0x10];
5975 
5976 	u8         reserved_at_40[0x4];
5977 	u8         min_delay[0xc];
5978 	u8         int_vector[0x10];
5979 
5980 	u8         reserved_at_60[0x20];
5981 };
5982 
5983 struct mlx5_ifc_attach_to_mcg_out_bits {
5984 	u8         status[0x8];
5985 	u8         reserved_at_8[0x18];
5986 
5987 	u8         syndrome[0x20];
5988 
5989 	u8         reserved_at_40[0x40];
5990 };
5991 
5992 struct mlx5_ifc_attach_to_mcg_in_bits {
5993 	u8         opcode[0x10];
5994 	u8         reserved_at_10[0x10];
5995 
5996 	u8         reserved_at_20[0x10];
5997 	u8         op_mod[0x10];
5998 
5999 	u8         reserved_at_40[0x8];
6000 	u8         qpn[0x18];
6001 
6002 	u8         reserved_at_60[0x20];
6003 
6004 	u8         multicast_gid[16][0x8];
6005 };
6006 
6007 struct mlx5_ifc_arm_xrc_srq_out_bits {
6008 	u8         status[0x8];
6009 	u8         reserved_at_8[0x18];
6010 
6011 	u8         syndrome[0x20];
6012 
6013 	u8         reserved_at_40[0x40];
6014 };
6015 
6016 enum {
6017 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6018 };
6019 
6020 struct mlx5_ifc_arm_xrc_srq_in_bits {
6021 	u8         opcode[0x10];
6022 	u8         reserved_at_10[0x10];
6023 
6024 	u8         reserved_at_20[0x10];
6025 	u8         op_mod[0x10];
6026 
6027 	u8         reserved_at_40[0x8];
6028 	u8         xrc_srqn[0x18];
6029 
6030 	u8         reserved_at_60[0x10];
6031 	u8         lwm[0x10];
6032 };
6033 
6034 struct mlx5_ifc_arm_rq_out_bits {
6035 	u8         status[0x8];
6036 	u8         reserved_at_8[0x18];
6037 
6038 	u8         syndrome[0x20];
6039 
6040 	u8         reserved_at_40[0x40];
6041 };
6042 
6043 enum {
6044 	MLX5_ARM_RQ_IN_OP_MOD_SRQ_  = 0x1,
6045 };
6046 
6047 struct mlx5_ifc_arm_rq_in_bits {
6048 	u8         opcode[0x10];
6049 	u8         reserved_at_10[0x10];
6050 
6051 	u8         reserved_at_20[0x10];
6052 	u8         op_mod[0x10];
6053 
6054 	u8         reserved_at_40[0x8];
6055 	u8         srq_number[0x18];
6056 
6057 	u8         reserved_at_60[0x10];
6058 	u8         lwm[0x10];
6059 };
6060 
6061 struct mlx5_ifc_arm_dct_out_bits {
6062 	u8         status[0x8];
6063 	u8         reserved_at_8[0x18];
6064 
6065 	u8         syndrome[0x20];
6066 
6067 	u8         reserved_at_40[0x40];
6068 };
6069 
6070 struct mlx5_ifc_arm_dct_in_bits {
6071 	u8         opcode[0x10];
6072 	u8         reserved_at_10[0x10];
6073 
6074 	u8         reserved_at_20[0x10];
6075 	u8         op_mod[0x10];
6076 
6077 	u8         reserved_at_40[0x8];
6078 	u8         dct_number[0x18];
6079 
6080 	u8         reserved_at_60[0x20];
6081 };
6082 
6083 struct mlx5_ifc_alloc_xrcd_out_bits {
6084 	u8         status[0x8];
6085 	u8         reserved_at_8[0x18];
6086 
6087 	u8         syndrome[0x20];
6088 
6089 	u8         reserved_at_40[0x8];
6090 	u8         xrcd[0x18];
6091 
6092 	u8         reserved_at_60[0x20];
6093 };
6094 
6095 struct mlx5_ifc_alloc_xrcd_in_bits {
6096 	u8         opcode[0x10];
6097 	u8         reserved_at_10[0x10];
6098 
6099 	u8         reserved_at_20[0x10];
6100 	u8         op_mod[0x10];
6101 
6102 	u8         reserved_at_40[0x40];
6103 };
6104 
6105 struct mlx5_ifc_alloc_uar_out_bits {
6106 	u8         status[0x8];
6107 	u8         reserved_at_8[0x18];
6108 
6109 	u8         syndrome[0x20];
6110 
6111 	u8         reserved_at_40[0x8];
6112 	u8         uar[0x18];
6113 
6114 	u8         reserved_at_60[0x20];
6115 };
6116 
6117 struct mlx5_ifc_alloc_uar_in_bits {
6118 	u8         opcode[0x10];
6119 	u8         reserved_at_10[0x10];
6120 
6121 	u8         reserved_at_20[0x10];
6122 	u8         op_mod[0x10];
6123 
6124 	u8         reserved_at_40[0x40];
6125 };
6126 
6127 struct mlx5_ifc_alloc_transport_domain_out_bits {
6128 	u8         status[0x8];
6129 	u8         reserved_at_8[0x18];
6130 
6131 	u8         syndrome[0x20];
6132 
6133 	u8         reserved_at_40[0x8];
6134 	u8         transport_domain[0x18];
6135 
6136 	u8         reserved_at_60[0x20];
6137 };
6138 
6139 struct mlx5_ifc_alloc_transport_domain_in_bits {
6140 	u8         opcode[0x10];
6141 	u8         reserved_at_10[0x10];
6142 
6143 	u8         reserved_at_20[0x10];
6144 	u8         op_mod[0x10];
6145 
6146 	u8         reserved_at_40[0x40];
6147 };
6148 
6149 struct mlx5_ifc_alloc_q_counter_out_bits {
6150 	u8         status[0x8];
6151 	u8         reserved_at_8[0x18];
6152 
6153 	u8         syndrome[0x20];
6154 
6155 	u8         reserved_at_40[0x18];
6156 	u8         counter_set_id[0x8];
6157 
6158 	u8         reserved_at_60[0x20];
6159 };
6160 
6161 struct mlx5_ifc_alloc_q_counter_in_bits {
6162 	u8         opcode[0x10];
6163 	u8         reserved_at_10[0x10];
6164 
6165 	u8         reserved_at_20[0x10];
6166 	u8         op_mod[0x10];
6167 
6168 	u8         reserved_at_40[0x40];
6169 };
6170 
6171 struct mlx5_ifc_alloc_pd_out_bits {
6172 	u8         status[0x8];
6173 	u8         reserved_at_8[0x18];
6174 
6175 	u8         syndrome[0x20];
6176 
6177 	u8         reserved_at_40[0x8];
6178 	u8         pd[0x18];
6179 
6180 	u8         reserved_at_60[0x20];
6181 };
6182 
6183 struct mlx5_ifc_alloc_pd_in_bits {
6184 	u8         opcode[0x10];
6185 	u8         reserved_at_10[0x10];
6186 
6187 	u8         reserved_at_20[0x10];
6188 	u8         op_mod[0x10];
6189 
6190 	u8         reserved_at_40[0x40];
6191 };
6192 
6193 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6194 	u8         status[0x8];
6195 	u8         reserved_at_8[0x18];
6196 
6197 	u8         syndrome[0x20];
6198 
6199 	u8         reserved_at_40[0x40];
6200 };
6201 
6202 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6203 	u8         opcode[0x10];
6204 	u8         reserved_at_10[0x10];
6205 
6206 	u8         reserved_at_20[0x10];
6207 	u8         op_mod[0x10];
6208 
6209 	u8         reserved_at_40[0x20];
6210 
6211 	u8         reserved_at_60[0x10];
6212 	u8         vxlan_udp_port[0x10];
6213 };
6214 
6215 struct mlx5_ifc_access_register_out_bits {
6216 	u8         status[0x8];
6217 	u8         reserved_at_8[0x18];
6218 
6219 	u8         syndrome[0x20];
6220 
6221 	u8         reserved_at_40[0x40];
6222 
6223 	u8         register_data[0][0x20];
6224 };
6225 
6226 enum {
6227 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6228 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6229 };
6230 
6231 struct mlx5_ifc_access_register_in_bits {
6232 	u8         opcode[0x10];
6233 	u8         reserved_at_10[0x10];
6234 
6235 	u8         reserved_at_20[0x10];
6236 	u8         op_mod[0x10];
6237 
6238 	u8         reserved_at_40[0x10];
6239 	u8         register_id[0x10];
6240 
6241 	u8         argument[0x20];
6242 
6243 	u8         register_data[0][0x20];
6244 };
6245 
6246 struct mlx5_ifc_sltp_reg_bits {
6247 	u8         status[0x4];
6248 	u8         version[0x4];
6249 	u8         local_port[0x8];
6250 	u8         pnat[0x2];
6251 	u8         reserved_at_12[0x2];
6252 	u8         lane[0x4];
6253 	u8         reserved_at_18[0x8];
6254 
6255 	u8         reserved_at_20[0x20];
6256 
6257 	u8         reserved_at_40[0x7];
6258 	u8         polarity[0x1];
6259 	u8         ob_tap0[0x8];
6260 	u8         ob_tap1[0x8];
6261 	u8         ob_tap2[0x8];
6262 
6263 	u8         reserved_at_60[0xc];
6264 	u8         ob_preemp_mode[0x4];
6265 	u8         ob_reg[0x8];
6266 	u8         ob_bias[0x8];
6267 
6268 	u8         reserved_at_80[0x20];
6269 };
6270 
6271 struct mlx5_ifc_slrg_reg_bits {
6272 	u8         status[0x4];
6273 	u8         version[0x4];
6274 	u8         local_port[0x8];
6275 	u8         pnat[0x2];
6276 	u8         reserved_at_12[0x2];
6277 	u8         lane[0x4];
6278 	u8         reserved_at_18[0x8];
6279 
6280 	u8         time_to_link_up[0x10];
6281 	u8         reserved_at_30[0xc];
6282 	u8         grade_lane_speed[0x4];
6283 
6284 	u8         grade_version[0x8];
6285 	u8         grade[0x18];
6286 
6287 	u8         reserved_at_60[0x4];
6288 	u8         height_grade_type[0x4];
6289 	u8         height_grade[0x18];
6290 
6291 	u8         height_dz[0x10];
6292 	u8         height_dv[0x10];
6293 
6294 	u8         reserved_at_a0[0x10];
6295 	u8         height_sigma[0x10];
6296 
6297 	u8         reserved_at_c0[0x20];
6298 
6299 	u8         reserved_at_e0[0x4];
6300 	u8         phase_grade_type[0x4];
6301 	u8         phase_grade[0x18];
6302 
6303 	u8         reserved_at_100[0x8];
6304 	u8         phase_eo_pos[0x8];
6305 	u8         reserved_at_110[0x8];
6306 	u8         phase_eo_neg[0x8];
6307 
6308 	u8         ffe_set_tested[0x10];
6309 	u8         test_errors_per_lane[0x10];
6310 };
6311 
6312 struct mlx5_ifc_pvlc_reg_bits {
6313 	u8         reserved_at_0[0x8];
6314 	u8         local_port[0x8];
6315 	u8         reserved_at_10[0x10];
6316 
6317 	u8         reserved_at_20[0x1c];
6318 	u8         vl_hw_cap[0x4];
6319 
6320 	u8         reserved_at_40[0x1c];
6321 	u8         vl_admin[0x4];
6322 
6323 	u8         reserved_at_60[0x1c];
6324 	u8         vl_operational[0x4];
6325 };
6326 
6327 struct mlx5_ifc_pude_reg_bits {
6328 	u8         swid[0x8];
6329 	u8         local_port[0x8];
6330 	u8         reserved_at_10[0x4];
6331 	u8         admin_status[0x4];
6332 	u8         reserved_at_18[0x4];
6333 	u8         oper_status[0x4];
6334 
6335 	u8         reserved_at_20[0x60];
6336 };
6337 
6338 struct mlx5_ifc_ptys_reg_bits {
6339 	u8         reserved_at_0[0x8];
6340 	u8         local_port[0x8];
6341 	u8         reserved_at_10[0xd];
6342 	u8         proto_mask[0x3];
6343 
6344 	u8         reserved_at_20[0x40];
6345 
6346 	u8         eth_proto_capability[0x20];
6347 
6348 	u8         ib_link_width_capability[0x10];
6349 	u8         ib_proto_capability[0x10];
6350 
6351 	u8         reserved_at_a0[0x20];
6352 
6353 	u8         eth_proto_admin[0x20];
6354 
6355 	u8         ib_link_width_admin[0x10];
6356 	u8         ib_proto_admin[0x10];
6357 
6358 	u8         reserved_at_100[0x20];
6359 
6360 	u8         eth_proto_oper[0x20];
6361 
6362 	u8         ib_link_width_oper[0x10];
6363 	u8         ib_proto_oper[0x10];
6364 
6365 	u8         reserved_at_160[0x20];
6366 
6367 	u8         eth_proto_lp_advertise[0x20];
6368 
6369 	u8         reserved_at_1a0[0x60];
6370 };
6371 
6372 struct mlx5_ifc_ptas_reg_bits {
6373 	u8         reserved_at_0[0x20];
6374 
6375 	u8         algorithm_options[0x10];
6376 	u8         reserved_at_30[0x4];
6377 	u8         repetitions_mode[0x4];
6378 	u8         num_of_repetitions[0x8];
6379 
6380 	u8         grade_version[0x8];
6381 	u8         height_grade_type[0x4];
6382 	u8         phase_grade_type[0x4];
6383 	u8         height_grade_weight[0x8];
6384 	u8         phase_grade_weight[0x8];
6385 
6386 	u8         gisim_measure_bits[0x10];
6387 	u8         adaptive_tap_measure_bits[0x10];
6388 
6389 	u8         ber_bath_high_error_threshold[0x10];
6390 	u8         ber_bath_mid_error_threshold[0x10];
6391 
6392 	u8         ber_bath_low_error_threshold[0x10];
6393 	u8         one_ratio_high_threshold[0x10];
6394 
6395 	u8         one_ratio_high_mid_threshold[0x10];
6396 	u8         one_ratio_low_mid_threshold[0x10];
6397 
6398 	u8         one_ratio_low_threshold[0x10];
6399 	u8         ndeo_error_threshold[0x10];
6400 
6401 	u8         mixer_offset_step_size[0x10];
6402 	u8         reserved_at_110[0x8];
6403 	u8         mix90_phase_for_voltage_bath[0x8];
6404 
6405 	u8         mixer_offset_start[0x10];
6406 	u8         mixer_offset_end[0x10];
6407 
6408 	u8         reserved_at_140[0x15];
6409 	u8         ber_test_time[0xb];
6410 };
6411 
6412 struct mlx5_ifc_pspa_reg_bits {
6413 	u8         swid[0x8];
6414 	u8         local_port[0x8];
6415 	u8         sub_port[0x8];
6416 	u8         reserved_at_18[0x8];
6417 
6418 	u8         reserved_at_20[0x20];
6419 };
6420 
6421 struct mlx5_ifc_pqdr_reg_bits {
6422 	u8         reserved_at_0[0x8];
6423 	u8         local_port[0x8];
6424 	u8         reserved_at_10[0x5];
6425 	u8         prio[0x3];
6426 	u8         reserved_at_18[0x6];
6427 	u8         mode[0x2];
6428 
6429 	u8         reserved_at_20[0x20];
6430 
6431 	u8         reserved_at_40[0x10];
6432 	u8         min_threshold[0x10];
6433 
6434 	u8         reserved_at_60[0x10];
6435 	u8         max_threshold[0x10];
6436 
6437 	u8         reserved_at_80[0x10];
6438 	u8         mark_probability_denominator[0x10];
6439 
6440 	u8         reserved_at_a0[0x60];
6441 };
6442 
6443 struct mlx5_ifc_ppsc_reg_bits {
6444 	u8         reserved_at_0[0x8];
6445 	u8         local_port[0x8];
6446 	u8         reserved_at_10[0x10];
6447 
6448 	u8         reserved_at_20[0x60];
6449 
6450 	u8         reserved_at_80[0x1c];
6451 	u8         wrps_admin[0x4];
6452 
6453 	u8         reserved_at_a0[0x1c];
6454 	u8         wrps_status[0x4];
6455 
6456 	u8         reserved_at_c0[0x8];
6457 	u8         up_threshold[0x8];
6458 	u8         reserved_at_d0[0x8];
6459 	u8         down_threshold[0x8];
6460 
6461 	u8         reserved_at_e0[0x20];
6462 
6463 	u8         reserved_at_100[0x1c];
6464 	u8         srps_admin[0x4];
6465 
6466 	u8         reserved_at_120[0x1c];
6467 	u8         srps_status[0x4];
6468 
6469 	u8         reserved_at_140[0x40];
6470 };
6471 
6472 struct mlx5_ifc_pplr_reg_bits {
6473 	u8         reserved_at_0[0x8];
6474 	u8         local_port[0x8];
6475 	u8         reserved_at_10[0x10];
6476 
6477 	u8         reserved_at_20[0x8];
6478 	u8         lb_cap[0x8];
6479 	u8         reserved_at_30[0x8];
6480 	u8         lb_en[0x8];
6481 };
6482 
6483 struct mlx5_ifc_pplm_reg_bits {
6484 	u8         reserved_at_0[0x8];
6485 	u8         local_port[0x8];
6486 	u8         reserved_at_10[0x10];
6487 
6488 	u8         reserved_at_20[0x20];
6489 
6490 	u8         port_profile_mode[0x8];
6491 	u8         static_port_profile[0x8];
6492 	u8         active_port_profile[0x8];
6493 	u8         reserved_at_58[0x8];
6494 
6495 	u8         retransmission_active[0x8];
6496 	u8         fec_mode_active[0x18];
6497 
6498 	u8         reserved_at_80[0x20];
6499 };
6500 
6501 struct mlx5_ifc_ppcnt_reg_bits {
6502 	u8         swid[0x8];
6503 	u8         local_port[0x8];
6504 	u8         pnat[0x2];
6505 	u8         reserved_at_12[0x8];
6506 	u8         grp[0x6];
6507 
6508 	u8         clr[0x1];
6509 	u8         reserved_at_21[0x1c];
6510 	u8         prio_tc[0x3];
6511 
6512 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6513 };
6514 
6515 struct mlx5_ifc_ppad_reg_bits {
6516 	u8         reserved_at_0[0x3];
6517 	u8         single_mac[0x1];
6518 	u8         reserved_at_4[0x4];
6519 	u8         local_port[0x8];
6520 	u8         mac_47_32[0x10];
6521 
6522 	u8         mac_31_0[0x20];
6523 
6524 	u8         reserved_at_40[0x40];
6525 };
6526 
6527 struct mlx5_ifc_pmtu_reg_bits {
6528 	u8         reserved_at_0[0x8];
6529 	u8         local_port[0x8];
6530 	u8         reserved_at_10[0x10];
6531 
6532 	u8         max_mtu[0x10];
6533 	u8         reserved_at_30[0x10];
6534 
6535 	u8         admin_mtu[0x10];
6536 	u8         reserved_at_50[0x10];
6537 
6538 	u8         oper_mtu[0x10];
6539 	u8         reserved_at_70[0x10];
6540 };
6541 
6542 struct mlx5_ifc_pmpr_reg_bits {
6543 	u8         reserved_at_0[0x8];
6544 	u8         module[0x8];
6545 	u8         reserved_at_10[0x10];
6546 
6547 	u8         reserved_at_20[0x18];
6548 	u8         attenuation_5g[0x8];
6549 
6550 	u8         reserved_at_40[0x18];
6551 	u8         attenuation_7g[0x8];
6552 
6553 	u8         reserved_at_60[0x18];
6554 	u8         attenuation_12g[0x8];
6555 };
6556 
6557 struct mlx5_ifc_pmpe_reg_bits {
6558 	u8         reserved_at_0[0x8];
6559 	u8         module[0x8];
6560 	u8         reserved_at_10[0xc];
6561 	u8         module_status[0x4];
6562 
6563 	u8         reserved_at_20[0x60];
6564 };
6565 
6566 struct mlx5_ifc_pmpc_reg_bits {
6567 	u8         module_state_updated[32][0x8];
6568 };
6569 
6570 struct mlx5_ifc_pmlpn_reg_bits {
6571 	u8         reserved_at_0[0x4];
6572 	u8         mlpn_status[0x4];
6573 	u8         local_port[0x8];
6574 	u8         reserved_at_10[0x10];
6575 
6576 	u8         e[0x1];
6577 	u8         reserved_at_21[0x1f];
6578 };
6579 
6580 struct mlx5_ifc_pmlp_reg_bits {
6581 	u8         rxtx[0x1];
6582 	u8         reserved_at_1[0x7];
6583 	u8         local_port[0x8];
6584 	u8         reserved_at_10[0x8];
6585 	u8         width[0x8];
6586 
6587 	u8         lane0_module_mapping[0x20];
6588 
6589 	u8         lane1_module_mapping[0x20];
6590 
6591 	u8         lane2_module_mapping[0x20];
6592 
6593 	u8         lane3_module_mapping[0x20];
6594 
6595 	u8         reserved_at_a0[0x160];
6596 };
6597 
6598 struct mlx5_ifc_pmaos_reg_bits {
6599 	u8         reserved_at_0[0x8];
6600 	u8         module[0x8];
6601 	u8         reserved_at_10[0x4];
6602 	u8         admin_status[0x4];
6603 	u8         reserved_at_18[0x4];
6604 	u8         oper_status[0x4];
6605 
6606 	u8         ase[0x1];
6607 	u8         ee[0x1];
6608 	u8         reserved_at_22[0x1c];
6609 	u8         e[0x2];
6610 
6611 	u8         reserved_at_40[0x40];
6612 };
6613 
6614 struct mlx5_ifc_plpc_reg_bits {
6615 	u8         reserved_at_0[0x4];
6616 	u8         profile_id[0xc];
6617 	u8         reserved_at_10[0x4];
6618 	u8         proto_mask[0x4];
6619 	u8         reserved_at_18[0x8];
6620 
6621 	u8         reserved_at_20[0x10];
6622 	u8         lane_speed[0x10];
6623 
6624 	u8         reserved_at_40[0x17];
6625 	u8         lpbf[0x1];
6626 	u8         fec_mode_policy[0x8];
6627 
6628 	u8         retransmission_capability[0x8];
6629 	u8         fec_mode_capability[0x18];
6630 
6631 	u8         retransmission_support_admin[0x8];
6632 	u8         fec_mode_support_admin[0x18];
6633 
6634 	u8         retransmission_request_admin[0x8];
6635 	u8         fec_mode_request_admin[0x18];
6636 
6637 	u8         reserved_at_c0[0x80];
6638 };
6639 
6640 struct mlx5_ifc_plib_reg_bits {
6641 	u8         reserved_at_0[0x8];
6642 	u8         local_port[0x8];
6643 	u8         reserved_at_10[0x8];
6644 	u8         ib_port[0x8];
6645 
6646 	u8         reserved_at_20[0x60];
6647 };
6648 
6649 struct mlx5_ifc_plbf_reg_bits {
6650 	u8         reserved_at_0[0x8];
6651 	u8         local_port[0x8];
6652 	u8         reserved_at_10[0xd];
6653 	u8         lbf_mode[0x3];
6654 
6655 	u8         reserved_at_20[0x20];
6656 };
6657 
6658 struct mlx5_ifc_pipg_reg_bits {
6659 	u8         reserved_at_0[0x8];
6660 	u8         local_port[0x8];
6661 	u8         reserved_at_10[0x10];
6662 
6663 	u8         dic[0x1];
6664 	u8         reserved_at_21[0x19];
6665 	u8         ipg[0x4];
6666 	u8         reserved_at_3e[0x2];
6667 };
6668 
6669 struct mlx5_ifc_pifr_reg_bits {
6670 	u8         reserved_at_0[0x8];
6671 	u8         local_port[0x8];
6672 	u8         reserved_at_10[0x10];
6673 
6674 	u8         reserved_at_20[0xe0];
6675 
6676 	u8         port_filter[8][0x20];
6677 
6678 	u8         port_filter_update_en[8][0x20];
6679 };
6680 
6681 struct mlx5_ifc_pfcc_reg_bits {
6682 	u8         reserved_at_0[0x8];
6683 	u8         local_port[0x8];
6684 	u8         reserved_at_10[0x10];
6685 
6686 	u8         ppan[0x4];
6687 	u8         reserved_at_24[0x4];
6688 	u8         prio_mask_tx[0x8];
6689 	u8         reserved_at_30[0x8];
6690 	u8         prio_mask_rx[0x8];
6691 
6692 	u8         pptx[0x1];
6693 	u8         aptx[0x1];
6694 	u8         reserved_at_42[0x6];
6695 	u8         pfctx[0x8];
6696 	u8         reserved_at_50[0x10];
6697 
6698 	u8         pprx[0x1];
6699 	u8         aprx[0x1];
6700 	u8         reserved_at_62[0x6];
6701 	u8         pfcrx[0x8];
6702 	u8         reserved_at_70[0x10];
6703 
6704 	u8         reserved_at_80[0x80];
6705 };
6706 
6707 struct mlx5_ifc_pelc_reg_bits {
6708 	u8         op[0x4];
6709 	u8         reserved_at_4[0x4];
6710 	u8         local_port[0x8];
6711 	u8         reserved_at_10[0x10];
6712 
6713 	u8         op_admin[0x8];
6714 	u8         op_capability[0x8];
6715 	u8         op_request[0x8];
6716 	u8         op_active[0x8];
6717 
6718 	u8         admin[0x40];
6719 
6720 	u8         capability[0x40];
6721 
6722 	u8         request[0x40];
6723 
6724 	u8         active[0x40];
6725 
6726 	u8         reserved_at_140[0x80];
6727 };
6728 
6729 struct mlx5_ifc_peir_reg_bits {
6730 	u8         reserved_at_0[0x8];
6731 	u8         local_port[0x8];
6732 	u8         reserved_at_10[0x10];
6733 
6734 	u8         reserved_at_20[0xc];
6735 	u8         error_count[0x4];
6736 	u8         reserved_at_30[0x10];
6737 
6738 	u8         reserved_at_40[0xc];
6739 	u8         lane[0x4];
6740 	u8         reserved_at_50[0x8];
6741 	u8         error_type[0x8];
6742 };
6743 
6744 struct mlx5_ifc_pcap_reg_bits {
6745 	u8         reserved_at_0[0x8];
6746 	u8         local_port[0x8];
6747 	u8         reserved_at_10[0x10];
6748 
6749 	u8         port_capability_mask[4][0x20];
6750 };
6751 
6752 struct mlx5_ifc_paos_reg_bits {
6753 	u8         swid[0x8];
6754 	u8         local_port[0x8];
6755 	u8         reserved_at_10[0x4];
6756 	u8         admin_status[0x4];
6757 	u8         reserved_at_18[0x4];
6758 	u8         oper_status[0x4];
6759 
6760 	u8         ase[0x1];
6761 	u8         ee[0x1];
6762 	u8         reserved_at_22[0x1c];
6763 	u8         e[0x2];
6764 
6765 	u8         reserved_at_40[0x40];
6766 };
6767 
6768 struct mlx5_ifc_pamp_reg_bits {
6769 	u8         reserved_at_0[0x8];
6770 	u8         opamp_group[0x8];
6771 	u8         reserved_at_10[0xc];
6772 	u8         opamp_group_type[0x4];
6773 
6774 	u8         start_index[0x10];
6775 	u8         reserved_at_30[0x4];
6776 	u8         num_of_indices[0xc];
6777 
6778 	u8         index_data[18][0x10];
6779 };
6780 
6781 struct mlx5_ifc_lane_2_module_mapping_bits {
6782 	u8         reserved_at_0[0x6];
6783 	u8         rx_lane[0x2];
6784 	u8         reserved_at_8[0x6];
6785 	u8         tx_lane[0x2];
6786 	u8         reserved_at_10[0x8];
6787 	u8         module[0x8];
6788 };
6789 
6790 struct mlx5_ifc_bufferx_reg_bits {
6791 	u8         reserved_at_0[0x6];
6792 	u8         lossy[0x1];
6793 	u8         epsb[0x1];
6794 	u8         reserved_at_8[0xc];
6795 	u8         size[0xc];
6796 
6797 	u8         xoff_threshold[0x10];
6798 	u8         xon_threshold[0x10];
6799 };
6800 
6801 struct mlx5_ifc_set_node_in_bits {
6802 	u8         node_description[64][0x8];
6803 };
6804 
6805 struct mlx5_ifc_register_power_settings_bits {
6806 	u8         reserved_at_0[0x18];
6807 	u8         power_settings_level[0x8];
6808 
6809 	u8         reserved_at_20[0x60];
6810 };
6811 
6812 struct mlx5_ifc_register_host_endianness_bits {
6813 	u8         he[0x1];
6814 	u8         reserved_at_1[0x1f];
6815 
6816 	u8         reserved_at_20[0x60];
6817 };
6818 
6819 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6820 	u8         reserved_at_0[0x20];
6821 
6822 	u8         mkey[0x20];
6823 
6824 	u8         addressh_63_32[0x20];
6825 
6826 	u8         addressl_31_0[0x20];
6827 };
6828 
6829 struct mlx5_ifc_ud_adrs_vector_bits {
6830 	u8         dc_key[0x40];
6831 
6832 	u8         ext[0x1];
6833 	u8         reserved_at_41[0x7];
6834 	u8         destination_qp_dct[0x18];
6835 
6836 	u8         static_rate[0x4];
6837 	u8         sl_eth_prio[0x4];
6838 	u8         fl[0x1];
6839 	u8         mlid[0x7];
6840 	u8         rlid_udp_sport[0x10];
6841 
6842 	u8         reserved_at_80[0x20];
6843 
6844 	u8         rmac_47_16[0x20];
6845 
6846 	u8         rmac_15_0[0x10];
6847 	u8         tclass[0x8];
6848 	u8         hop_limit[0x8];
6849 
6850 	u8         reserved_at_e0[0x1];
6851 	u8         grh[0x1];
6852 	u8         reserved_at_e2[0x2];
6853 	u8         src_addr_index[0x8];
6854 	u8         flow_label[0x14];
6855 
6856 	u8         rgid_rip[16][0x8];
6857 };
6858 
6859 struct mlx5_ifc_pages_req_event_bits {
6860 	u8         reserved_at_0[0x10];
6861 	u8         function_id[0x10];
6862 
6863 	u8         num_pages[0x20];
6864 
6865 	u8         reserved_at_40[0xa0];
6866 };
6867 
6868 struct mlx5_ifc_eqe_bits {
6869 	u8         reserved_at_0[0x8];
6870 	u8         event_type[0x8];
6871 	u8         reserved_at_10[0x8];
6872 	u8         event_sub_type[0x8];
6873 
6874 	u8         reserved_at_20[0xe0];
6875 
6876 	union mlx5_ifc_event_auto_bits event_data;
6877 
6878 	u8         reserved_at_1e0[0x10];
6879 	u8         signature[0x8];
6880 	u8         reserved_at_1f8[0x7];
6881 	u8         owner[0x1];
6882 };
6883 
6884 enum {
6885 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
6886 };
6887 
6888 struct mlx5_ifc_cmd_queue_entry_bits {
6889 	u8         type[0x8];
6890 	u8         reserved_at_8[0x18];
6891 
6892 	u8         input_length[0x20];
6893 
6894 	u8         input_mailbox_pointer_63_32[0x20];
6895 
6896 	u8         input_mailbox_pointer_31_9[0x17];
6897 	u8         reserved_at_77[0x9];
6898 
6899 	u8         command_input_inline_data[16][0x8];
6900 
6901 	u8         command_output_inline_data[16][0x8];
6902 
6903 	u8         output_mailbox_pointer_63_32[0x20];
6904 
6905 	u8         output_mailbox_pointer_31_9[0x17];
6906 	u8         reserved_at_1b7[0x9];
6907 
6908 	u8         output_length[0x20];
6909 
6910 	u8         token[0x8];
6911 	u8         signature[0x8];
6912 	u8         reserved_at_1f0[0x8];
6913 	u8         status[0x7];
6914 	u8         ownership[0x1];
6915 };
6916 
6917 struct mlx5_ifc_cmd_out_bits {
6918 	u8         status[0x8];
6919 	u8         reserved_at_8[0x18];
6920 
6921 	u8         syndrome[0x20];
6922 
6923 	u8         command_output[0x20];
6924 };
6925 
6926 struct mlx5_ifc_cmd_in_bits {
6927 	u8         opcode[0x10];
6928 	u8         reserved_at_10[0x10];
6929 
6930 	u8         reserved_at_20[0x10];
6931 	u8         op_mod[0x10];
6932 
6933 	u8         command[0][0x20];
6934 };
6935 
6936 struct mlx5_ifc_cmd_if_box_bits {
6937 	u8         mailbox_data[512][0x8];
6938 
6939 	u8         reserved_at_1000[0x180];
6940 
6941 	u8         next_pointer_63_32[0x20];
6942 
6943 	u8         next_pointer_31_10[0x16];
6944 	u8         reserved_at_11b6[0xa];
6945 
6946 	u8         block_number[0x20];
6947 
6948 	u8         reserved_at_11e0[0x8];
6949 	u8         token[0x8];
6950 	u8         ctrl_signature[0x8];
6951 	u8         signature[0x8];
6952 };
6953 
6954 struct mlx5_ifc_mtt_bits {
6955 	u8         ptag_63_32[0x20];
6956 
6957 	u8         ptag_31_8[0x18];
6958 	u8         reserved_at_38[0x6];
6959 	u8         wr_en[0x1];
6960 	u8         rd_en[0x1];
6961 };
6962 
6963 struct mlx5_ifc_query_wol_rol_out_bits {
6964 	u8         status[0x8];
6965 	u8         reserved_at_8[0x18];
6966 
6967 	u8         syndrome[0x20];
6968 
6969 	u8         reserved_at_40[0x10];
6970 	u8         rol_mode[0x8];
6971 	u8         wol_mode[0x8];
6972 
6973 	u8         reserved_at_60[0x20];
6974 };
6975 
6976 struct mlx5_ifc_query_wol_rol_in_bits {
6977 	u8         opcode[0x10];
6978 	u8         reserved_at_10[0x10];
6979 
6980 	u8         reserved_at_20[0x10];
6981 	u8         op_mod[0x10];
6982 
6983 	u8         reserved_at_40[0x40];
6984 };
6985 
6986 struct mlx5_ifc_set_wol_rol_out_bits {
6987 	u8         status[0x8];
6988 	u8         reserved_at_8[0x18];
6989 
6990 	u8         syndrome[0x20];
6991 
6992 	u8         reserved_at_40[0x40];
6993 };
6994 
6995 struct mlx5_ifc_set_wol_rol_in_bits {
6996 	u8         opcode[0x10];
6997 	u8         reserved_at_10[0x10];
6998 
6999 	u8         reserved_at_20[0x10];
7000 	u8         op_mod[0x10];
7001 
7002 	u8         rol_mode_valid[0x1];
7003 	u8         wol_mode_valid[0x1];
7004 	u8         reserved_at_42[0xe];
7005 	u8         rol_mode[0x8];
7006 	u8         wol_mode[0x8];
7007 
7008 	u8         reserved_at_60[0x20];
7009 };
7010 
7011 enum {
7012 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
7013 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
7014 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
7015 };
7016 
7017 enum {
7018 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
7019 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
7020 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
7021 };
7022 
7023 enum {
7024 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
7025 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
7026 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
7027 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
7028 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
7029 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
7030 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
7031 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
7032 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
7033 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
7034 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
7035 };
7036 
7037 struct mlx5_ifc_initial_seg_bits {
7038 	u8         fw_rev_minor[0x10];
7039 	u8         fw_rev_major[0x10];
7040 
7041 	u8         cmd_interface_rev[0x10];
7042 	u8         fw_rev_subminor[0x10];
7043 
7044 	u8         reserved_at_40[0x40];
7045 
7046 	u8         cmdq_phy_addr_63_32[0x20];
7047 
7048 	u8         cmdq_phy_addr_31_12[0x14];
7049 	u8         reserved_at_b4[0x2];
7050 	u8         nic_interface[0x2];
7051 	u8         log_cmdq_size[0x4];
7052 	u8         log_cmdq_stride[0x4];
7053 
7054 	u8         command_doorbell_vector[0x20];
7055 
7056 	u8         reserved_at_e0[0xf00];
7057 
7058 	u8         initializing[0x1];
7059 	u8         reserved_at_fe1[0x4];
7060 	u8         nic_interface_supported[0x3];
7061 	u8         reserved_at_fe8[0x18];
7062 
7063 	struct mlx5_ifc_health_buffer_bits health_buffer;
7064 
7065 	u8         no_dram_nic_offset[0x20];
7066 
7067 	u8         reserved_at_1220[0x6e40];
7068 
7069 	u8         reserved_at_8060[0x1f];
7070 	u8         clear_int[0x1];
7071 
7072 	u8         health_syndrome[0x8];
7073 	u8         health_counter[0x18];
7074 
7075 	u8         reserved_at_80a0[0x17fc0];
7076 };
7077 
7078 union mlx5_ifc_ports_control_registers_document_bits {
7079 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7080 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7081 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7082 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7083 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7084 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7085 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7086 	struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7087 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7088 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
7089 	struct mlx5_ifc_paos_reg_bits paos_reg;
7090 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
7091 	struct mlx5_ifc_peir_reg_bits peir_reg;
7092 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
7093 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7094 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7095 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7096 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
7097 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
7098 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
7099 	struct mlx5_ifc_plib_reg_bits plib_reg;
7100 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
7101 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7102 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7103 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7104 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7105 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7106 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7107 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7108 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
7109 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7110 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
7111 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
7112 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7113 	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7114 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
7115 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
7116 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
7117 	struct mlx5_ifc_pude_reg_bits pude_reg;
7118 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7119 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
7120 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
7121 	u8         reserved_at_0[0x60e0];
7122 };
7123 
7124 union mlx5_ifc_debug_enhancements_document_bits {
7125 	struct mlx5_ifc_health_buffer_bits health_buffer;
7126 	u8         reserved_at_0[0x200];
7127 };
7128 
7129 union mlx5_ifc_uplink_pci_interface_document_bits {
7130 	struct mlx5_ifc_initial_seg_bits initial_seg;
7131 	u8         reserved_at_0[0x20060];
7132 };
7133 
7134 struct mlx5_ifc_set_flow_table_root_out_bits {
7135 	u8         status[0x8];
7136 	u8         reserved_at_8[0x18];
7137 
7138 	u8         syndrome[0x20];
7139 
7140 	u8         reserved_at_40[0x40];
7141 };
7142 
7143 struct mlx5_ifc_set_flow_table_root_in_bits {
7144 	u8         opcode[0x10];
7145 	u8         reserved_at_10[0x10];
7146 
7147 	u8         reserved_at_20[0x10];
7148 	u8         op_mod[0x10];
7149 
7150 	u8         reserved_at_40[0x40];
7151 
7152 	u8         table_type[0x8];
7153 	u8         reserved_at_88[0x18];
7154 
7155 	u8         reserved_at_a0[0x8];
7156 	u8         table_id[0x18];
7157 
7158 	u8         reserved_at_c0[0x140];
7159 };
7160 
7161 enum {
7162 	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7163 };
7164 
7165 struct mlx5_ifc_modify_flow_table_out_bits {
7166 	u8         status[0x8];
7167 	u8         reserved_at_8[0x18];
7168 
7169 	u8         syndrome[0x20];
7170 
7171 	u8         reserved_at_40[0x40];
7172 };
7173 
7174 struct mlx5_ifc_modify_flow_table_in_bits {
7175 	u8         opcode[0x10];
7176 	u8         reserved_at_10[0x10];
7177 
7178 	u8         reserved_at_20[0x10];
7179 	u8         op_mod[0x10];
7180 
7181 	u8         reserved_at_40[0x20];
7182 
7183 	u8         reserved_at_60[0x10];
7184 	u8         modify_field_select[0x10];
7185 
7186 	u8         table_type[0x8];
7187 	u8         reserved_at_88[0x18];
7188 
7189 	u8         reserved_at_a0[0x8];
7190 	u8         table_id[0x18];
7191 
7192 	u8         reserved_at_c0[0x4];
7193 	u8         table_miss_mode[0x4];
7194 	u8         reserved_at_c8[0x18];
7195 
7196 	u8         reserved_at_e0[0x8];
7197 	u8         table_miss_id[0x18];
7198 
7199 	u8         reserved_at_100[0x100];
7200 };
7201 
7202 struct mlx5_ifc_ets_tcn_config_reg_bits {
7203 	u8         g[0x1];
7204 	u8         b[0x1];
7205 	u8         r[0x1];
7206 	u8         reserved_at_3[0x9];
7207 	u8         group[0x4];
7208 	u8         reserved_at_10[0x9];
7209 	u8         bw_allocation[0x7];
7210 
7211 	u8         reserved_at_20[0xc];
7212 	u8         max_bw_units[0x4];
7213 	u8         reserved_at_30[0x8];
7214 	u8         max_bw_value[0x8];
7215 };
7216 
7217 struct mlx5_ifc_ets_global_config_reg_bits {
7218 	u8         reserved_at_0[0x2];
7219 	u8         r[0x1];
7220 	u8         reserved_at_3[0x1d];
7221 
7222 	u8         reserved_at_20[0xc];
7223 	u8         max_bw_units[0x4];
7224 	u8         reserved_at_30[0x8];
7225 	u8         max_bw_value[0x8];
7226 };
7227 
7228 struct mlx5_ifc_qetc_reg_bits {
7229 	u8                                         reserved_at_0[0x8];
7230 	u8                                         port_number[0x8];
7231 	u8                                         reserved_at_10[0x30];
7232 
7233 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
7234 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7235 };
7236 
7237 struct mlx5_ifc_qtct_reg_bits {
7238 	u8         reserved_at_0[0x8];
7239 	u8         port_number[0x8];
7240 	u8         reserved_at_10[0xd];
7241 	u8         prio[0x3];
7242 
7243 	u8         reserved_at_20[0x1d];
7244 	u8         tclass[0x3];
7245 };
7246 
7247 #endif /* MLX5_IFC_H */
7248