1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 }; 72 73 enum { 74 MLX5_SHARED_RESOURCE_UID = 0xffff, 75 }; 76 77 enum { 78 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 79 }; 80 81 enum { 82 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 83 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 84 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 85 }; 86 87 enum { 88 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 89 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 90 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 91 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 92 MLX5_OBJ_TYPE_MKEY = 0xff01, 93 MLX5_OBJ_TYPE_QP = 0xff02, 94 MLX5_OBJ_TYPE_PSV = 0xff03, 95 MLX5_OBJ_TYPE_RMP = 0xff04, 96 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 97 MLX5_OBJ_TYPE_RQ = 0xff06, 98 MLX5_OBJ_TYPE_SQ = 0xff07, 99 MLX5_OBJ_TYPE_TIR = 0xff08, 100 MLX5_OBJ_TYPE_TIS = 0xff09, 101 MLX5_OBJ_TYPE_DCT = 0xff0a, 102 MLX5_OBJ_TYPE_XRQ = 0xff0b, 103 MLX5_OBJ_TYPE_RQT = 0xff0e, 104 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 105 MLX5_OBJ_TYPE_CQ = 0xff10, 106 }; 107 108 enum { 109 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 110 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 111 MLX5_CMD_OP_INIT_HCA = 0x102, 112 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 113 MLX5_CMD_OP_ENABLE_HCA = 0x104, 114 MLX5_CMD_OP_DISABLE_HCA = 0x105, 115 MLX5_CMD_OP_QUERY_PAGES = 0x107, 116 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 117 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 118 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 119 MLX5_CMD_OP_SET_ISSI = 0x10b, 120 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 121 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 122 MLX5_CMD_OP_ALLOC_SF = 0x113, 123 MLX5_CMD_OP_DEALLOC_SF = 0x114, 124 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 125 MLX5_CMD_OP_RESUME_VHCA = 0x116, 126 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 127 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 128 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 137 MLX5_CMD_OP_CREATE_EQ = 0x301, 138 MLX5_CMD_OP_DESTROY_EQ = 0x302, 139 MLX5_CMD_OP_QUERY_EQ = 0x303, 140 MLX5_CMD_OP_GEN_EQE = 0x304, 141 MLX5_CMD_OP_CREATE_CQ = 0x400, 142 MLX5_CMD_OP_DESTROY_CQ = 0x401, 143 MLX5_CMD_OP_QUERY_CQ = 0x402, 144 MLX5_CMD_OP_MODIFY_CQ = 0x403, 145 MLX5_CMD_OP_CREATE_QP = 0x500, 146 MLX5_CMD_OP_DESTROY_QP = 0x501, 147 MLX5_CMD_OP_RST2INIT_QP = 0x502, 148 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 149 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 150 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 151 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 152 MLX5_CMD_OP_2ERR_QP = 0x507, 153 MLX5_CMD_OP_2RST_QP = 0x50a, 154 MLX5_CMD_OP_QUERY_QP = 0x50b, 155 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 156 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 157 MLX5_CMD_OP_CREATE_PSV = 0x600, 158 MLX5_CMD_OP_DESTROY_PSV = 0x601, 159 MLX5_CMD_OP_CREATE_SRQ = 0x700, 160 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 161 MLX5_CMD_OP_QUERY_SRQ = 0x702, 162 MLX5_CMD_OP_ARM_RQ = 0x703, 163 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 164 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 165 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 166 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 167 MLX5_CMD_OP_CREATE_DCT = 0x710, 168 MLX5_CMD_OP_DESTROY_DCT = 0x711, 169 MLX5_CMD_OP_DRAIN_DCT = 0x712, 170 MLX5_CMD_OP_QUERY_DCT = 0x713, 171 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 172 MLX5_CMD_OP_CREATE_XRQ = 0x717, 173 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 174 MLX5_CMD_OP_QUERY_XRQ = 0x719, 175 MLX5_CMD_OP_ARM_XRQ = 0x71a, 176 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 177 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 178 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 179 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 180 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 181 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 182 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 183 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 184 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 185 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 186 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 187 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 188 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 189 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 190 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 191 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 194 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 195 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 196 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 197 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 198 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 199 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 200 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 201 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 202 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 203 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 204 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 205 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 206 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 207 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 208 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 209 MLX5_CMD_OP_ALLOC_PD = 0x800, 210 MLX5_CMD_OP_DEALLOC_PD = 0x801, 211 MLX5_CMD_OP_ALLOC_UAR = 0x802, 212 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 213 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 214 MLX5_CMD_OP_ACCESS_REG = 0x805, 215 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 216 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 217 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 218 MLX5_CMD_OP_MAD_IFC = 0x50d, 219 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 220 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 221 MLX5_CMD_OP_NOP = 0x80d, 222 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 223 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 224 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 225 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 226 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 227 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 228 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 229 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 230 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 231 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 232 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 233 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 234 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 235 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 236 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 237 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 238 MLX5_CMD_OP_CREATE_LAG = 0x840, 239 MLX5_CMD_OP_MODIFY_LAG = 0x841, 240 MLX5_CMD_OP_QUERY_LAG = 0x842, 241 MLX5_CMD_OP_DESTROY_LAG = 0x843, 242 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 243 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 244 MLX5_CMD_OP_CREATE_TIR = 0x900, 245 MLX5_CMD_OP_MODIFY_TIR = 0x901, 246 MLX5_CMD_OP_DESTROY_TIR = 0x902, 247 MLX5_CMD_OP_QUERY_TIR = 0x903, 248 MLX5_CMD_OP_CREATE_SQ = 0x904, 249 MLX5_CMD_OP_MODIFY_SQ = 0x905, 250 MLX5_CMD_OP_DESTROY_SQ = 0x906, 251 MLX5_CMD_OP_QUERY_SQ = 0x907, 252 MLX5_CMD_OP_CREATE_RQ = 0x908, 253 MLX5_CMD_OP_MODIFY_RQ = 0x909, 254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 255 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 256 MLX5_CMD_OP_QUERY_RQ = 0x90b, 257 MLX5_CMD_OP_CREATE_RMP = 0x90c, 258 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 259 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 260 MLX5_CMD_OP_QUERY_RMP = 0x90f, 261 MLX5_CMD_OP_CREATE_TIS = 0x912, 262 MLX5_CMD_OP_MODIFY_TIS = 0x913, 263 MLX5_CMD_OP_DESTROY_TIS = 0x914, 264 MLX5_CMD_OP_QUERY_TIS = 0x915, 265 MLX5_CMD_OP_CREATE_RQT = 0x916, 266 MLX5_CMD_OP_MODIFY_RQT = 0x917, 267 MLX5_CMD_OP_DESTROY_RQT = 0x918, 268 MLX5_CMD_OP_QUERY_RQT = 0x919, 269 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 270 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 271 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 272 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 273 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 274 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 275 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 277 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 278 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 279 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 280 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 281 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 282 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 283 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 284 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 285 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 286 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 287 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 288 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 289 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 290 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 291 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 292 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 293 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 294 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 295 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 296 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 297 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 298 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 299 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 300 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 301 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 302 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 303 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 304 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 305 MLX5_CMD_OP_MAX 306 }; 307 308 /* Valid range for general commands that don't work over an object */ 309 enum { 310 MLX5_CMD_OP_GENERAL_START = 0xb00, 311 MLX5_CMD_OP_GENERAL_END = 0xd00, 312 }; 313 314 struct mlx5_ifc_flow_table_fields_supported_bits { 315 u8 outer_dmac[0x1]; 316 u8 outer_smac[0x1]; 317 u8 outer_ether_type[0x1]; 318 u8 outer_ip_version[0x1]; 319 u8 outer_first_prio[0x1]; 320 u8 outer_first_cfi[0x1]; 321 u8 outer_first_vid[0x1]; 322 u8 outer_ipv4_ttl[0x1]; 323 u8 outer_second_prio[0x1]; 324 u8 outer_second_cfi[0x1]; 325 u8 outer_second_vid[0x1]; 326 u8 reserved_at_b[0x1]; 327 u8 outer_sip[0x1]; 328 u8 outer_dip[0x1]; 329 u8 outer_frag[0x1]; 330 u8 outer_ip_protocol[0x1]; 331 u8 outer_ip_ecn[0x1]; 332 u8 outer_ip_dscp[0x1]; 333 u8 outer_udp_sport[0x1]; 334 u8 outer_udp_dport[0x1]; 335 u8 outer_tcp_sport[0x1]; 336 u8 outer_tcp_dport[0x1]; 337 u8 outer_tcp_flags[0x1]; 338 u8 outer_gre_protocol[0x1]; 339 u8 outer_gre_key[0x1]; 340 u8 outer_vxlan_vni[0x1]; 341 u8 outer_geneve_vni[0x1]; 342 u8 outer_geneve_oam[0x1]; 343 u8 outer_geneve_protocol_type[0x1]; 344 u8 outer_geneve_opt_len[0x1]; 345 u8 source_vhca_port[0x1]; 346 u8 source_eswitch_port[0x1]; 347 348 u8 inner_dmac[0x1]; 349 u8 inner_smac[0x1]; 350 u8 inner_ether_type[0x1]; 351 u8 inner_ip_version[0x1]; 352 u8 inner_first_prio[0x1]; 353 u8 inner_first_cfi[0x1]; 354 u8 inner_first_vid[0x1]; 355 u8 reserved_at_27[0x1]; 356 u8 inner_second_prio[0x1]; 357 u8 inner_second_cfi[0x1]; 358 u8 inner_second_vid[0x1]; 359 u8 reserved_at_2b[0x1]; 360 u8 inner_sip[0x1]; 361 u8 inner_dip[0x1]; 362 u8 inner_frag[0x1]; 363 u8 inner_ip_protocol[0x1]; 364 u8 inner_ip_ecn[0x1]; 365 u8 inner_ip_dscp[0x1]; 366 u8 inner_udp_sport[0x1]; 367 u8 inner_udp_dport[0x1]; 368 u8 inner_tcp_sport[0x1]; 369 u8 inner_tcp_dport[0x1]; 370 u8 inner_tcp_flags[0x1]; 371 u8 reserved_at_37[0x9]; 372 373 u8 geneve_tlv_option_0_data[0x1]; 374 u8 geneve_tlv_option_0_exist[0x1]; 375 u8 reserved_at_42[0x3]; 376 u8 outer_first_mpls_over_udp[0x4]; 377 u8 outer_first_mpls_over_gre[0x4]; 378 u8 inner_first_mpls[0x4]; 379 u8 outer_first_mpls[0x4]; 380 u8 reserved_at_55[0x2]; 381 u8 outer_esp_spi[0x1]; 382 u8 reserved_at_58[0x2]; 383 u8 bth_dst_qp[0x1]; 384 u8 reserved_at_5b[0x5]; 385 386 u8 reserved_at_60[0x18]; 387 u8 metadata_reg_c_7[0x1]; 388 u8 metadata_reg_c_6[0x1]; 389 u8 metadata_reg_c_5[0x1]; 390 u8 metadata_reg_c_4[0x1]; 391 u8 metadata_reg_c_3[0x1]; 392 u8 metadata_reg_c_2[0x1]; 393 u8 metadata_reg_c_1[0x1]; 394 u8 metadata_reg_c_0[0x1]; 395 }; 396 397 struct mlx5_ifc_flow_table_fields_supported_2_bits { 398 u8 reserved_at_0[0xe]; 399 u8 bth_opcode[0x1]; 400 u8 reserved_at_f[0x11]; 401 402 u8 reserved_at_20[0x60]; 403 }; 404 405 struct mlx5_ifc_flow_table_prop_layout_bits { 406 u8 ft_support[0x1]; 407 u8 reserved_at_1[0x1]; 408 u8 flow_counter[0x1]; 409 u8 flow_modify_en[0x1]; 410 u8 modify_root[0x1]; 411 u8 identified_miss_table_mode[0x1]; 412 u8 flow_table_modify[0x1]; 413 u8 reformat[0x1]; 414 u8 decap[0x1]; 415 u8 reserved_at_9[0x1]; 416 u8 pop_vlan[0x1]; 417 u8 push_vlan[0x1]; 418 u8 reserved_at_c[0x1]; 419 u8 pop_vlan_2[0x1]; 420 u8 push_vlan_2[0x1]; 421 u8 reformat_and_vlan_action[0x1]; 422 u8 reserved_at_10[0x1]; 423 u8 sw_owner[0x1]; 424 u8 reformat_l3_tunnel_to_l2[0x1]; 425 u8 reformat_l2_to_l3_tunnel[0x1]; 426 u8 reformat_and_modify_action[0x1]; 427 u8 ignore_flow_level[0x1]; 428 u8 reserved_at_16[0x1]; 429 u8 table_miss_action_domain[0x1]; 430 u8 termination_table[0x1]; 431 u8 reformat_and_fwd_to_table[0x1]; 432 u8 reserved_at_1a[0x2]; 433 u8 ipsec_encrypt[0x1]; 434 u8 ipsec_decrypt[0x1]; 435 u8 sw_owner_v2[0x1]; 436 u8 reserved_at_1f[0x1]; 437 438 u8 termination_table_raw_traffic[0x1]; 439 u8 reserved_at_21[0x1]; 440 u8 log_max_ft_size[0x6]; 441 u8 log_max_modify_header_context[0x8]; 442 u8 max_modify_header_actions[0x8]; 443 u8 max_ft_level[0x8]; 444 445 u8 reserved_at_40[0x6]; 446 u8 execute_aso[0x1]; 447 u8 reserved_at_47[0x19]; 448 449 u8 reserved_at_60[0x2]; 450 u8 reformat_insert[0x1]; 451 u8 reformat_remove[0x1]; 452 u8 reserver_at_64[0x14]; 453 u8 log_max_ft_num[0x8]; 454 455 u8 reserved_at_80[0x10]; 456 u8 log_max_flow_counter[0x8]; 457 u8 log_max_destination[0x8]; 458 459 u8 reserved_at_a0[0x18]; 460 u8 log_max_flow[0x8]; 461 462 u8 reserved_at_c0[0x40]; 463 464 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 465 466 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 467 }; 468 469 struct mlx5_ifc_odp_per_transport_service_cap_bits { 470 u8 send[0x1]; 471 u8 receive[0x1]; 472 u8 write[0x1]; 473 u8 read[0x1]; 474 u8 atomic[0x1]; 475 u8 srq_receive[0x1]; 476 u8 reserved_at_6[0x1a]; 477 }; 478 479 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 480 u8 smac_47_16[0x20]; 481 482 u8 smac_15_0[0x10]; 483 u8 ethertype[0x10]; 484 485 u8 dmac_47_16[0x20]; 486 487 u8 dmac_15_0[0x10]; 488 u8 first_prio[0x3]; 489 u8 first_cfi[0x1]; 490 u8 first_vid[0xc]; 491 492 u8 ip_protocol[0x8]; 493 u8 ip_dscp[0x6]; 494 u8 ip_ecn[0x2]; 495 u8 cvlan_tag[0x1]; 496 u8 svlan_tag[0x1]; 497 u8 frag[0x1]; 498 u8 ip_version[0x4]; 499 u8 tcp_flags[0x9]; 500 501 u8 tcp_sport[0x10]; 502 u8 tcp_dport[0x10]; 503 504 u8 reserved_at_c0[0x10]; 505 u8 ipv4_ihl[0x4]; 506 u8 reserved_at_c4[0x4]; 507 508 u8 ttl_hoplimit[0x8]; 509 510 u8 udp_sport[0x10]; 511 u8 udp_dport[0x10]; 512 513 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 514 515 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 516 }; 517 518 struct mlx5_ifc_nvgre_key_bits { 519 u8 hi[0x18]; 520 u8 lo[0x8]; 521 }; 522 523 union mlx5_ifc_gre_key_bits { 524 struct mlx5_ifc_nvgre_key_bits nvgre; 525 u8 key[0x20]; 526 }; 527 528 struct mlx5_ifc_fte_match_set_misc_bits { 529 u8 gre_c_present[0x1]; 530 u8 reserved_at_1[0x1]; 531 u8 gre_k_present[0x1]; 532 u8 gre_s_present[0x1]; 533 u8 source_vhca_port[0x4]; 534 u8 source_sqn[0x18]; 535 536 u8 source_eswitch_owner_vhca_id[0x10]; 537 u8 source_port[0x10]; 538 539 u8 outer_second_prio[0x3]; 540 u8 outer_second_cfi[0x1]; 541 u8 outer_second_vid[0xc]; 542 u8 inner_second_prio[0x3]; 543 u8 inner_second_cfi[0x1]; 544 u8 inner_second_vid[0xc]; 545 546 u8 outer_second_cvlan_tag[0x1]; 547 u8 inner_second_cvlan_tag[0x1]; 548 u8 outer_second_svlan_tag[0x1]; 549 u8 inner_second_svlan_tag[0x1]; 550 u8 reserved_at_64[0xc]; 551 u8 gre_protocol[0x10]; 552 553 union mlx5_ifc_gre_key_bits gre_key; 554 555 u8 vxlan_vni[0x18]; 556 u8 bth_opcode[0x8]; 557 558 u8 geneve_vni[0x18]; 559 u8 reserved_at_d8[0x6]; 560 u8 geneve_tlv_option_0_exist[0x1]; 561 u8 geneve_oam[0x1]; 562 563 u8 reserved_at_e0[0xc]; 564 u8 outer_ipv6_flow_label[0x14]; 565 566 u8 reserved_at_100[0xc]; 567 u8 inner_ipv6_flow_label[0x14]; 568 569 u8 reserved_at_120[0xa]; 570 u8 geneve_opt_len[0x6]; 571 u8 geneve_protocol_type[0x10]; 572 573 u8 reserved_at_140[0x8]; 574 u8 bth_dst_qp[0x18]; 575 u8 reserved_at_160[0x20]; 576 u8 outer_esp_spi[0x20]; 577 u8 reserved_at_1a0[0x60]; 578 }; 579 580 struct mlx5_ifc_fte_match_mpls_bits { 581 u8 mpls_label[0x14]; 582 u8 mpls_exp[0x3]; 583 u8 mpls_s_bos[0x1]; 584 u8 mpls_ttl[0x8]; 585 }; 586 587 struct mlx5_ifc_fte_match_set_misc2_bits { 588 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 589 590 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 591 592 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 593 594 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 595 596 u8 metadata_reg_c_7[0x20]; 597 598 u8 metadata_reg_c_6[0x20]; 599 600 u8 metadata_reg_c_5[0x20]; 601 602 u8 metadata_reg_c_4[0x20]; 603 604 u8 metadata_reg_c_3[0x20]; 605 606 u8 metadata_reg_c_2[0x20]; 607 608 u8 metadata_reg_c_1[0x20]; 609 610 u8 metadata_reg_c_0[0x20]; 611 612 u8 metadata_reg_a[0x20]; 613 614 u8 reserved_at_1a0[0x60]; 615 }; 616 617 struct mlx5_ifc_fte_match_set_misc3_bits { 618 u8 inner_tcp_seq_num[0x20]; 619 620 u8 outer_tcp_seq_num[0x20]; 621 622 u8 inner_tcp_ack_num[0x20]; 623 624 u8 outer_tcp_ack_num[0x20]; 625 626 u8 reserved_at_80[0x8]; 627 u8 outer_vxlan_gpe_vni[0x18]; 628 629 u8 outer_vxlan_gpe_next_protocol[0x8]; 630 u8 outer_vxlan_gpe_flags[0x8]; 631 u8 reserved_at_b0[0x10]; 632 633 u8 icmp_header_data[0x20]; 634 635 u8 icmpv6_header_data[0x20]; 636 637 u8 icmp_type[0x8]; 638 u8 icmp_code[0x8]; 639 u8 icmpv6_type[0x8]; 640 u8 icmpv6_code[0x8]; 641 642 u8 geneve_tlv_option_0_data[0x20]; 643 644 u8 gtpu_teid[0x20]; 645 646 u8 gtpu_msg_type[0x8]; 647 u8 gtpu_msg_flags[0x8]; 648 u8 reserved_at_170[0x10]; 649 650 u8 gtpu_dw_2[0x20]; 651 652 u8 gtpu_first_ext_dw_0[0x20]; 653 654 u8 gtpu_dw_0[0x20]; 655 656 u8 reserved_at_1e0[0x20]; 657 }; 658 659 struct mlx5_ifc_fte_match_set_misc4_bits { 660 u8 prog_sample_field_value_0[0x20]; 661 662 u8 prog_sample_field_id_0[0x20]; 663 664 u8 prog_sample_field_value_1[0x20]; 665 666 u8 prog_sample_field_id_1[0x20]; 667 668 u8 prog_sample_field_value_2[0x20]; 669 670 u8 prog_sample_field_id_2[0x20]; 671 672 u8 prog_sample_field_value_3[0x20]; 673 674 u8 prog_sample_field_id_3[0x20]; 675 676 u8 reserved_at_100[0x100]; 677 }; 678 679 struct mlx5_ifc_fte_match_set_misc5_bits { 680 u8 macsec_tag_0[0x20]; 681 682 u8 macsec_tag_1[0x20]; 683 684 u8 macsec_tag_2[0x20]; 685 686 u8 macsec_tag_3[0x20]; 687 688 u8 tunnel_header_0[0x20]; 689 690 u8 tunnel_header_1[0x20]; 691 692 u8 tunnel_header_2[0x20]; 693 694 u8 tunnel_header_3[0x20]; 695 696 u8 reserved_at_100[0x100]; 697 }; 698 699 struct mlx5_ifc_cmd_pas_bits { 700 u8 pa_h[0x20]; 701 702 u8 pa_l[0x14]; 703 u8 reserved_at_34[0xc]; 704 }; 705 706 struct mlx5_ifc_uint64_bits { 707 u8 hi[0x20]; 708 709 u8 lo[0x20]; 710 }; 711 712 enum { 713 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 714 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 715 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 716 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 717 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 718 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 719 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 720 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 721 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 722 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 723 }; 724 725 struct mlx5_ifc_ads_bits { 726 u8 fl[0x1]; 727 u8 free_ar[0x1]; 728 u8 reserved_at_2[0xe]; 729 u8 pkey_index[0x10]; 730 731 u8 reserved_at_20[0x8]; 732 u8 grh[0x1]; 733 u8 mlid[0x7]; 734 u8 rlid[0x10]; 735 736 u8 ack_timeout[0x5]; 737 u8 reserved_at_45[0x3]; 738 u8 src_addr_index[0x8]; 739 u8 reserved_at_50[0x4]; 740 u8 stat_rate[0x4]; 741 u8 hop_limit[0x8]; 742 743 u8 reserved_at_60[0x4]; 744 u8 tclass[0x8]; 745 u8 flow_label[0x14]; 746 747 u8 rgid_rip[16][0x8]; 748 749 u8 reserved_at_100[0x4]; 750 u8 f_dscp[0x1]; 751 u8 f_ecn[0x1]; 752 u8 reserved_at_106[0x1]; 753 u8 f_eth_prio[0x1]; 754 u8 ecn[0x2]; 755 u8 dscp[0x6]; 756 u8 udp_sport[0x10]; 757 758 u8 dei_cfi[0x1]; 759 u8 eth_prio[0x3]; 760 u8 sl[0x4]; 761 u8 vhca_port_num[0x8]; 762 u8 rmac_47_32[0x10]; 763 764 u8 rmac_31_0[0x20]; 765 }; 766 767 struct mlx5_ifc_flow_table_nic_cap_bits { 768 u8 nic_rx_multi_path_tirs[0x1]; 769 u8 nic_rx_multi_path_tirs_fts[0x1]; 770 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 771 u8 reserved_at_3[0x4]; 772 u8 sw_owner_reformat_supported[0x1]; 773 u8 reserved_at_8[0x18]; 774 775 u8 encap_general_header[0x1]; 776 u8 reserved_at_21[0xa]; 777 u8 log_max_packet_reformat_context[0x5]; 778 u8 reserved_at_30[0x6]; 779 u8 max_encap_header_size[0xa]; 780 u8 reserved_at_40[0x1c0]; 781 782 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 783 784 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 785 786 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 787 788 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 789 790 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 791 792 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 793 794 u8 reserved_at_e00[0x700]; 795 796 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 797 798 u8 reserved_at_1580[0x280]; 799 800 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 801 802 u8 reserved_at_1880[0x780]; 803 804 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 805 806 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 807 808 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 809 810 u8 reserved_at_20c0[0x5f40]; 811 }; 812 813 struct mlx5_ifc_port_selection_cap_bits { 814 u8 reserved_at_0[0x10]; 815 u8 port_select_flow_table[0x1]; 816 u8 reserved_at_11[0xf]; 817 818 u8 reserved_at_20[0x1e0]; 819 820 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 821 822 u8 reserved_at_400[0x7c00]; 823 }; 824 825 enum { 826 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 827 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 828 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 829 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 830 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 831 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 832 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 833 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 834 }; 835 836 struct mlx5_ifc_flow_table_eswitch_cap_bits { 837 u8 fdb_to_vport_reg_c_id[0x8]; 838 u8 reserved_at_8[0xd]; 839 u8 fdb_modify_header_fwd_to_table[0x1]; 840 u8 fdb_ipv4_ttl_modify[0x1]; 841 u8 flow_source[0x1]; 842 u8 reserved_at_18[0x2]; 843 u8 multi_fdb_encap[0x1]; 844 u8 egress_acl_forward_to_vport[0x1]; 845 u8 fdb_multi_path_to_table[0x1]; 846 u8 reserved_at_1d[0x3]; 847 848 u8 reserved_at_20[0x1e0]; 849 850 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 851 852 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 853 854 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 855 856 u8 reserved_at_800[0x1000]; 857 858 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 859 860 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 861 862 u8 sw_steering_uplink_icm_address_rx[0x40]; 863 864 u8 sw_steering_uplink_icm_address_tx[0x40]; 865 866 u8 reserved_at_1900[0x6700]; 867 }; 868 869 enum { 870 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 871 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 872 }; 873 874 struct mlx5_ifc_e_switch_cap_bits { 875 u8 vport_svlan_strip[0x1]; 876 u8 vport_cvlan_strip[0x1]; 877 u8 vport_svlan_insert[0x1]; 878 u8 vport_cvlan_insert_if_not_exist[0x1]; 879 u8 vport_cvlan_insert_overwrite[0x1]; 880 u8 reserved_at_5[0x2]; 881 u8 esw_shared_ingress_acl[0x1]; 882 u8 esw_uplink_ingress_acl[0x1]; 883 u8 root_ft_on_other_esw[0x1]; 884 u8 reserved_at_a[0xf]; 885 u8 esw_functions_changed[0x1]; 886 u8 reserved_at_1a[0x1]; 887 u8 ecpf_vport_exists[0x1]; 888 u8 counter_eswitch_affinity[0x1]; 889 u8 merged_eswitch[0x1]; 890 u8 nic_vport_node_guid_modify[0x1]; 891 u8 nic_vport_port_guid_modify[0x1]; 892 893 u8 vxlan_encap_decap[0x1]; 894 u8 nvgre_encap_decap[0x1]; 895 u8 reserved_at_22[0x1]; 896 u8 log_max_fdb_encap_uplink[0x5]; 897 u8 reserved_at_21[0x3]; 898 u8 log_max_packet_reformat_context[0x5]; 899 u8 reserved_2b[0x6]; 900 u8 max_encap_header_size[0xa]; 901 902 u8 reserved_at_40[0xb]; 903 u8 log_max_esw_sf[0x5]; 904 u8 esw_sf_base_id[0x10]; 905 906 u8 reserved_at_60[0x7a0]; 907 908 }; 909 910 struct mlx5_ifc_qos_cap_bits { 911 u8 packet_pacing[0x1]; 912 u8 esw_scheduling[0x1]; 913 u8 esw_bw_share[0x1]; 914 u8 esw_rate_limit[0x1]; 915 u8 reserved_at_4[0x1]; 916 u8 packet_pacing_burst_bound[0x1]; 917 u8 packet_pacing_typical_size[0x1]; 918 u8 reserved_at_7[0x1]; 919 u8 nic_sq_scheduling[0x1]; 920 u8 nic_bw_share[0x1]; 921 u8 nic_rate_limit[0x1]; 922 u8 packet_pacing_uid[0x1]; 923 u8 log_esw_max_sched_depth[0x4]; 924 u8 reserved_at_10[0x10]; 925 926 u8 reserved_at_20[0xb]; 927 u8 log_max_qos_nic_queue_group[0x5]; 928 u8 reserved_at_30[0x10]; 929 930 u8 packet_pacing_max_rate[0x20]; 931 932 u8 packet_pacing_min_rate[0x20]; 933 934 u8 reserved_at_80[0x10]; 935 u8 packet_pacing_rate_table_size[0x10]; 936 937 u8 esw_element_type[0x10]; 938 u8 esw_tsar_type[0x10]; 939 940 u8 reserved_at_c0[0x10]; 941 u8 max_qos_para_vport[0x10]; 942 943 u8 max_tsar_bw_share[0x20]; 944 945 u8 reserved_at_100[0x20]; 946 947 u8 reserved_at_120[0x3]; 948 u8 log_meter_aso_granularity[0x5]; 949 u8 reserved_at_128[0x3]; 950 u8 log_meter_aso_max_alloc[0x5]; 951 u8 reserved_at_130[0x3]; 952 u8 log_max_num_meter_aso[0x5]; 953 u8 reserved_at_138[0x8]; 954 955 u8 reserved_at_140[0x6c0]; 956 }; 957 958 struct mlx5_ifc_debug_cap_bits { 959 u8 core_dump_general[0x1]; 960 u8 core_dump_qp[0x1]; 961 u8 reserved_at_2[0x7]; 962 u8 resource_dump[0x1]; 963 u8 reserved_at_a[0x16]; 964 965 u8 reserved_at_20[0x2]; 966 u8 stall_detect[0x1]; 967 u8 reserved_at_23[0x1d]; 968 969 u8 reserved_at_40[0x7c0]; 970 }; 971 972 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 973 u8 csum_cap[0x1]; 974 u8 vlan_cap[0x1]; 975 u8 lro_cap[0x1]; 976 u8 lro_psh_flag[0x1]; 977 u8 lro_time_stamp[0x1]; 978 u8 reserved_at_5[0x2]; 979 u8 wqe_vlan_insert[0x1]; 980 u8 self_lb_en_modifiable[0x1]; 981 u8 reserved_at_9[0x2]; 982 u8 max_lso_cap[0x5]; 983 u8 multi_pkt_send_wqe[0x2]; 984 u8 wqe_inline_mode[0x2]; 985 u8 rss_ind_tbl_cap[0x4]; 986 u8 reg_umr_sq[0x1]; 987 u8 scatter_fcs[0x1]; 988 u8 enhanced_multi_pkt_send_wqe[0x1]; 989 u8 tunnel_lso_const_out_ip_id[0x1]; 990 u8 tunnel_lro_gre[0x1]; 991 u8 tunnel_lro_vxlan[0x1]; 992 u8 tunnel_stateless_gre[0x1]; 993 u8 tunnel_stateless_vxlan[0x1]; 994 995 u8 swp[0x1]; 996 u8 swp_csum[0x1]; 997 u8 swp_lso[0x1]; 998 u8 cqe_checksum_full[0x1]; 999 u8 tunnel_stateless_geneve_tx[0x1]; 1000 u8 tunnel_stateless_mpls_over_udp[0x1]; 1001 u8 tunnel_stateless_mpls_over_gre[0x1]; 1002 u8 tunnel_stateless_vxlan_gpe[0x1]; 1003 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1004 u8 tunnel_stateless_ip_over_ip[0x1]; 1005 u8 insert_trailer[0x1]; 1006 u8 reserved_at_2b[0x1]; 1007 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1008 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1009 u8 reserved_at_2e[0x2]; 1010 u8 max_vxlan_udp_ports[0x8]; 1011 u8 reserved_at_38[0x6]; 1012 u8 max_geneve_opt_len[0x1]; 1013 u8 tunnel_stateless_geneve_rx[0x1]; 1014 1015 u8 reserved_at_40[0x10]; 1016 u8 lro_min_mss_size[0x10]; 1017 1018 u8 reserved_at_60[0x120]; 1019 1020 u8 lro_timer_supported_periods[4][0x20]; 1021 1022 u8 reserved_at_200[0x600]; 1023 }; 1024 1025 enum { 1026 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1027 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1028 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1029 }; 1030 1031 struct mlx5_ifc_roce_cap_bits { 1032 u8 roce_apm[0x1]; 1033 u8 reserved_at_1[0x3]; 1034 u8 sw_r_roce_src_udp_port[0x1]; 1035 u8 fl_rc_qp_when_roce_disabled[0x1]; 1036 u8 fl_rc_qp_when_roce_enabled[0x1]; 1037 u8 reserved_at_7[0x17]; 1038 u8 qp_ts_format[0x2]; 1039 1040 u8 reserved_at_20[0x60]; 1041 1042 u8 reserved_at_80[0xc]; 1043 u8 l3_type[0x4]; 1044 u8 reserved_at_90[0x8]; 1045 u8 roce_version[0x8]; 1046 1047 u8 reserved_at_a0[0x10]; 1048 u8 r_roce_dest_udp_port[0x10]; 1049 1050 u8 r_roce_max_src_udp_port[0x10]; 1051 u8 r_roce_min_src_udp_port[0x10]; 1052 1053 u8 reserved_at_e0[0x10]; 1054 u8 roce_address_table_size[0x10]; 1055 1056 u8 reserved_at_100[0x700]; 1057 }; 1058 1059 struct mlx5_ifc_sync_steering_in_bits { 1060 u8 opcode[0x10]; 1061 u8 uid[0x10]; 1062 1063 u8 reserved_at_20[0x10]; 1064 u8 op_mod[0x10]; 1065 1066 u8 reserved_at_40[0xc0]; 1067 }; 1068 1069 struct mlx5_ifc_sync_steering_out_bits { 1070 u8 status[0x8]; 1071 u8 reserved_at_8[0x18]; 1072 1073 u8 syndrome[0x20]; 1074 1075 u8 reserved_at_40[0x40]; 1076 }; 1077 1078 struct mlx5_ifc_device_mem_cap_bits { 1079 u8 memic[0x1]; 1080 u8 reserved_at_1[0x1f]; 1081 1082 u8 reserved_at_20[0xb]; 1083 u8 log_min_memic_alloc_size[0x5]; 1084 u8 reserved_at_30[0x8]; 1085 u8 log_max_memic_addr_alignment[0x8]; 1086 1087 u8 memic_bar_start_addr[0x40]; 1088 1089 u8 memic_bar_size[0x20]; 1090 1091 u8 max_memic_size[0x20]; 1092 1093 u8 steering_sw_icm_start_address[0x40]; 1094 1095 u8 reserved_at_100[0x8]; 1096 u8 log_header_modify_sw_icm_size[0x8]; 1097 u8 reserved_at_110[0x2]; 1098 u8 log_sw_icm_alloc_granularity[0x6]; 1099 u8 log_steering_sw_icm_size[0x8]; 1100 1101 u8 reserved_at_120[0x18]; 1102 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1103 1104 u8 header_modify_sw_icm_start_address[0x40]; 1105 1106 u8 reserved_at_180[0x40]; 1107 1108 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1109 1110 u8 memic_operations[0x20]; 1111 1112 u8 reserved_at_220[0x5e0]; 1113 }; 1114 1115 struct mlx5_ifc_device_event_cap_bits { 1116 u8 user_affiliated_events[4][0x40]; 1117 1118 u8 user_unaffiliated_events[4][0x40]; 1119 }; 1120 1121 struct mlx5_ifc_virtio_emulation_cap_bits { 1122 u8 desc_tunnel_offload_type[0x1]; 1123 u8 eth_frame_offload_type[0x1]; 1124 u8 virtio_version_1_0[0x1]; 1125 u8 device_features_bits_mask[0xd]; 1126 u8 event_mode[0x8]; 1127 u8 virtio_queue_type[0x8]; 1128 1129 u8 max_tunnel_desc[0x10]; 1130 u8 reserved_at_30[0x3]; 1131 u8 log_doorbell_stride[0x5]; 1132 u8 reserved_at_38[0x3]; 1133 u8 log_doorbell_bar_size[0x5]; 1134 1135 u8 doorbell_bar_offset[0x40]; 1136 1137 u8 max_emulated_devices[0x8]; 1138 u8 max_num_virtio_queues[0x18]; 1139 1140 u8 reserved_at_a0[0x60]; 1141 1142 u8 umem_1_buffer_param_a[0x20]; 1143 1144 u8 umem_1_buffer_param_b[0x20]; 1145 1146 u8 umem_2_buffer_param_a[0x20]; 1147 1148 u8 umem_2_buffer_param_b[0x20]; 1149 1150 u8 umem_3_buffer_param_a[0x20]; 1151 1152 u8 umem_3_buffer_param_b[0x20]; 1153 1154 u8 reserved_at_1c0[0x640]; 1155 }; 1156 1157 enum { 1158 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1159 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1160 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1161 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1162 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1163 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1164 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1165 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1166 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1167 }; 1168 1169 enum { 1170 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1171 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1172 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1173 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1174 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1175 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1176 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1177 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1178 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1179 }; 1180 1181 struct mlx5_ifc_atomic_caps_bits { 1182 u8 reserved_at_0[0x40]; 1183 1184 u8 atomic_req_8B_endianness_mode[0x2]; 1185 u8 reserved_at_42[0x4]; 1186 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1187 1188 u8 reserved_at_47[0x19]; 1189 1190 u8 reserved_at_60[0x20]; 1191 1192 u8 reserved_at_80[0x10]; 1193 u8 atomic_operations[0x10]; 1194 1195 u8 reserved_at_a0[0x10]; 1196 u8 atomic_size_qp[0x10]; 1197 1198 u8 reserved_at_c0[0x10]; 1199 u8 atomic_size_dc[0x10]; 1200 1201 u8 reserved_at_e0[0x720]; 1202 }; 1203 1204 struct mlx5_ifc_odp_cap_bits { 1205 u8 reserved_at_0[0x40]; 1206 1207 u8 sig[0x1]; 1208 u8 reserved_at_41[0x1f]; 1209 1210 u8 reserved_at_60[0x20]; 1211 1212 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1213 1214 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1215 1216 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1217 1218 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1219 1220 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1221 1222 u8 reserved_at_120[0x6E0]; 1223 }; 1224 1225 struct mlx5_ifc_calc_op { 1226 u8 reserved_at_0[0x10]; 1227 u8 reserved_at_10[0x9]; 1228 u8 op_swap_endianness[0x1]; 1229 u8 op_min[0x1]; 1230 u8 op_xor[0x1]; 1231 u8 op_or[0x1]; 1232 u8 op_and[0x1]; 1233 u8 op_max[0x1]; 1234 u8 op_add[0x1]; 1235 }; 1236 1237 struct mlx5_ifc_vector_calc_cap_bits { 1238 u8 calc_matrix[0x1]; 1239 u8 reserved_at_1[0x1f]; 1240 u8 reserved_at_20[0x8]; 1241 u8 max_vec_count[0x8]; 1242 u8 reserved_at_30[0xd]; 1243 u8 max_chunk_size[0x3]; 1244 struct mlx5_ifc_calc_op calc0; 1245 struct mlx5_ifc_calc_op calc1; 1246 struct mlx5_ifc_calc_op calc2; 1247 struct mlx5_ifc_calc_op calc3; 1248 1249 u8 reserved_at_c0[0x720]; 1250 }; 1251 1252 struct mlx5_ifc_tls_cap_bits { 1253 u8 tls_1_2_aes_gcm_128[0x1]; 1254 u8 tls_1_3_aes_gcm_128[0x1]; 1255 u8 tls_1_2_aes_gcm_256[0x1]; 1256 u8 tls_1_3_aes_gcm_256[0x1]; 1257 u8 reserved_at_4[0x1c]; 1258 1259 u8 reserved_at_20[0x7e0]; 1260 }; 1261 1262 struct mlx5_ifc_ipsec_cap_bits { 1263 u8 ipsec_full_offload[0x1]; 1264 u8 ipsec_crypto_offload[0x1]; 1265 u8 ipsec_esn[0x1]; 1266 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1267 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1268 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1269 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1270 u8 reserved_at_7[0x4]; 1271 u8 log_max_ipsec_offload[0x5]; 1272 u8 reserved_at_10[0x10]; 1273 1274 u8 min_log_ipsec_full_replay_window[0x8]; 1275 u8 max_log_ipsec_full_replay_window[0x8]; 1276 u8 reserved_at_30[0x7d0]; 1277 }; 1278 1279 enum { 1280 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1281 MLX5_WQ_TYPE_CYCLIC = 0x1, 1282 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1283 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1284 }; 1285 1286 enum { 1287 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1288 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1289 }; 1290 1291 enum { 1292 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1293 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1294 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1295 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1296 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1297 }; 1298 1299 enum { 1300 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1301 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1302 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1303 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1304 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1305 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1306 }; 1307 1308 enum { 1309 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1310 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1311 }; 1312 1313 enum { 1314 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1315 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1316 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1317 }; 1318 1319 enum { 1320 MLX5_CAP_PORT_TYPE_IB = 0x0, 1321 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1322 }; 1323 1324 enum { 1325 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1326 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1327 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1328 }; 1329 1330 enum { 1331 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1332 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1333 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1334 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1335 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1336 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1337 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1338 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1339 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1340 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1341 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1342 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1343 }; 1344 1345 enum { 1346 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1347 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1348 }; 1349 1350 #define MLX5_FC_BULK_SIZE_FACTOR 128 1351 1352 enum mlx5_fc_bulk_alloc_bitmask { 1353 MLX5_FC_BULK_128 = (1 << 0), 1354 MLX5_FC_BULK_256 = (1 << 1), 1355 MLX5_FC_BULK_512 = (1 << 2), 1356 MLX5_FC_BULK_1024 = (1 << 3), 1357 MLX5_FC_BULK_2048 = (1 << 4), 1358 MLX5_FC_BULK_4096 = (1 << 5), 1359 MLX5_FC_BULK_8192 = (1 << 6), 1360 MLX5_FC_BULK_16384 = (1 << 7), 1361 }; 1362 1363 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1364 1365 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1366 1367 enum { 1368 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1369 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1370 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1371 }; 1372 1373 struct mlx5_ifc_cmd_hca_cap_bits { 1374 u8 reserved_at_0[0x1f]; 1375 u8 vhca_resource_manager[0x1]; 1376 1377 u8 hca_cap_2[0x1]; 1378 u8 create_lag_when_not_master_up[0x1]; 1379 u8 dtor[0x1]; 1380 u8 event_on_vhca_state_teardown_request[0x1]; 1381 u8 event_on_vhca_state_in_use[0x1]; 1382 u8 event_on_vhca_state_active[0x1]; 1383 u8 event_on_vhca_state_allocated[0x1]; 1384 u8 event_on_vhca_state_invalid[0x1]; 1385 u8 reserved_at_28[0x8]; 1386 u8 vhca_id[0x10]; 1387 1388 u8 reserved_at_40[0x40]; 1389 1390 u8 log_max_srq_sz[0x8]; 1391 u8 log_max_qp_sz[0x8]; 1392 u8 event_cap[0x1]; 1393 u8 reserved_at_91[0x2]; 1394 u8 isolate_vl_tc_new[0x1]; 1395 u8 reserved_at_94[0x4]; 1396 u8 prio_tag_required[0x1]; 1397 u8 reserved_at_99[0x2]; 1398 u8 log_max_qp[0x5]; 1399 1400 u8 reserved_at_a0[0x3]; 1401 u8 ece_support[0x1]; 1402 u8 reserved_at_a4[0x5]; 1403 u8 reg_c_preserve[0x1]; 1404 u8 reserved_at_aa[0x1]; 1405 u8 log_max_srq[0x5]; 1406 u8 reserved_at_b0[0x1]; 1407 u8 uplink_follow[0x1]; 1408 u8 ts_cqe_to_dest_cqn[0x1]; 1409 u8 reserved_at_b3[0x7]; 1410 u8 shampo[0x1]; 1411 u8 reserved_at_bb[0x5]; 1412 1413 u8 max_sgl_for_optimized_performance[0x8]; 1414 u8 log_max_cq_sz[0x8]; 1415 u8 relaxed_ordering_write_umr[0x1]; 1416 u8 relaxed_ordering_read_umr[0x1]; 1417 u8 reserved_at_d2[0x7]; 1418 u8 virtio_net_device_emualtion_manager[0x1]; 1419 u8 virtio_blk_device_emualtion_manager[0x1]; 1420 u8 log_max_cq[0x5]; 1421 1422 u8 log_max_eq_sz[0x8]; 1423 u8 relaxed_ordering_write[0x1]; 1424 u8 relaxed_ordering_read[0x1]; 1425 u8 log_max_mkey[0x6]; 1426 u8 reserved_at_f0[0x8]; 1427 u8 dump_fill_mkey[0x1]; 1428 u8 reserved_at_f9[0x2]; 1429 u8 fast_teardown[0x1]; 1430 u8 log_max_eq[0x4]; 1431 1432 u8 max_indirection[0x8]; 1433 u8 fixed_buffer_size[0x1]; 1434 u8 log_max_mrw_sz[0x7]; 1435 u8 force_teardown[0x1]; 1436 u8 reserved_at_111[0x1]; 1437 u8 log_max_bsf_list_size[0x6]; 1438 u8 umr_extended_translation_offset[0x1]; 1439 u8 null_mkey[0x1]; 1440 u8 log_max_klm_list_size[0x6]; 1441 1442 u8 reserved_at_120[0xa]; 1443 u8 log_max_ra_req_dc[0x6]; 1444 u8 reserved_at_130[0x9]; 1445 u8 vnic_env_cq_overrun[0x1]; 1446 u8 log_max_ra_res_dc[0x6]; 1447 1448 u8 reserved_at_140[0x5]; 1449 u8 release_all_pages[0x1]; 1450 u8 must_not_use[0x1]; 1451 u8 reserved_at_147[0x2]; 1452 u8 roce_accl[0x1]; 1453 u8 log_max_ra_req_qp[0x6]; 1454 u8 reserved_at_150[0xa]; 1455 u8 log_max_ra_res_qp[0x6]; 1456 1457 u8 end_pad[0x1]; 1458 u8 cc_query_allowed[0x1]; 1459 u8 cc_modify_allowed[0x1]; 1460 u8 start_pad[0x1]; 1461 u8 cache_line_128byte[0x1]; 1462 u8 reserved_at_165[0x4]; 1463 u8 rts2rts_qp_counters_set_id[0x1]; 1464 u8 reserved_at_16a[0x2]; 1465 u8 vnic_env_int_rq_oob[0x1]; 1466 u8 sbcam_reg[0x1]; 1467 u8 reserved_at_16e[0x1]; 1468 u8 qcam_reg[0x1]; 1469 u8 gid_table_size[0x10]; 1470 1471 u8 out_of_seq_cnt[0x1]; 1472 u8 vport_counters[0x1]; 1473 u8 retransmission_q_counters[0x1]; 1474 u8 debug[0x1]; 1475 u8 modify_rq_counter_set_id[0x1]; 1476 u8 rq_delay_drop[0x1]; 1477 u8 max_qp_cnt[0xa]; 1478 u8 pkey_table_size[0x10]; 1479 1480 u8 vport_group_manager[0x1]; 1481 u8 vhca_group_manager[0x1]; 1482 u8 ib_virt[0x1]; 1483 u8 eth_virt[0x1]; 1484 u8 vnic_env_queue_counters[0x1]; 1485 u8 ets[0x1]; 1486 u8 nic_flow_table[0x1]; 1487 u8 eswitch_manager[0x1]; 1488 u8 device_memory[0x1]; 1489 u8 mcam_reg[0x1]; 1490 u8 pcam_reg[0x1]; 1491 u8 local_ca_ack_delay[0x5]; 1492 u8 port_module_event[0x1]; 1493 u8 enhanced_error_q_counters[0x1]; 1494 u8 ports_check[0x1]; 1495 u8 reserved_at_1b3[0x1]; 1496 u8 disable_link_up[0x1]; 1497 u8 beacon_led[0x1]; 1498 u8 port_type[0x2]; 1499 u8 num_ports[0x8]; 1500 1501 u8 reserved_at_1c0[0x1]; 1502 u8 pps[0x1]; 1503 u8 pps_modify[0x1]; 1504 u8 log_max_msg[0x5]; 1505 u8 reserved_at_1c8[0x4]; 1506 u8 max_tc[0x4]; 1507 u8 temp_warn_event[0x1]; 1508 u8 dcbx[0x1]; 1509 u8 general_notification_event[0x1]; 1510 u8 reserved_at_1d3[0x2]; 1511 u8 fpga[0x1]; 1512 u8 rol_s[0x1]; 1513 u8 rol_g[0x1]; 1514 u8 reserved_at_1d8[0x1]; 1515 u8 wol_s[0x1]; 1516 u8 wol_g[0x1]; 1517 u8 wol_a[0x1]; 1518 u8 wol_b[0x1]; 1519 u8 wol_m[0x1]; 1520 u8 wol_u[0x1]; 1521 u8 wol_p[0x1]; 1522 1523 u8 stat_rate_support[0x10]; 1524 u8 reserved_at_1f0[0x1]; 1525 u8 pci_sync_for_fw_update_event[0x1]; 1526 u8 reserved_at_1f2[0x6]; 1527 u8 init2_lag_tx_port_affinity[0x1]; 1528 u8 reserved_at_1fa[0x3]; 1529 u8 cqe_version[0x4]; 1530 1531 u8 compact_address_vector[0x1]; 1532 u8 striding_rq[0x1]; 1533 u8 reserved_at_202[0x1]; 1534 u8 ipoib_enhanced_offloads[0x1]; 1535 u8 ipoib_basic_offloads[0x1]; 1536 u8 reserved_at_205[0x1]; 1537 u8 repeated_block_disabled[0x1]; 1538 u8 umr_modify_entity_size_disabled[0x1]; 1539 u8 umr_modify_atomic_disabled[0x1]; 1540 u8 umr_indirect_mkey_disabled[0x1]; 1541 u8 umr_fence[0x2]; 1542 u8 dc_req_scat_data_cqe[0x1]; 1543 u8 reserved_at_20d[0x2]; 1544 u8 drain_sigerr[0x1]; 1545 u8 cmdif_checksum[0x2]; 1546 u8 sigerr_cqe[0x1]; 1547 u8 reserved_at_213[0x1]; 1548 u8 wq_signature[0x1]; 1549 u8 sctr_data_cqe[0x1]; 1550 u8 reserved_at_216[0x1]; 1551 u8 sho[0x1]; 1552 u8 tph[0x1]; 1553 u8 rf[0x1]; 1554 u8 dct[0x1]; 1555 u8 qos[0x1]; 1556 u8 eth_net_offloads[0x1]; 1557 u8 roce[0x1]; 1558 u8 atomic[0x1]; 1559 u8 reserved_at_21f[0x1]; 1560 1561 u8 cq_oi[0x1]; 1562 u8 cq_resize[0x1]; 1563 u8 cq_moderation[0x1]; 1564 u8 reserved_at_223[0x3]; 1565 u8 cq_eq_remap[0x1]; 1566 u8 pg[0x1]; 1567 u8 block_lb_mc[0x1]; 1568 u8 reserved_at_229[0x1]; 1569 u8 scqe_break_moderation[0x1]; 1570 u8 cq_period_start_from_cqe[0x1]; 1571 u8 cd[0x1]; 1572 u8 reserved_at_22d[0x1]; 1573 u8 apm[0x1]; 1574 u8 vector_calc[0x1]; 1575 u8 umr_ptr_rlky[0x1]; 1576 u8 imaicl[0x1]; 1577 u8 qp_packet_based[0x1]; 1578 u8 reserved_at_233[0x3]; 1579 u8 qkv[0x1]; 1580 u8 pkv[0x1]; 1581 u8 set_deth_sqpn[0x1]; 1582 u8 reserved_at_239[0x3]; 1583 u8 xrc[0x1]; 1584 u8 ud[0x1]; 1585 u8 uc[0x1]; 1586 u8 rc[0x1]; 1587 1588 u8 uar_4k[0x1]; 1589 u8 reserved_at_241[0x9]; 1590 u8 uar_sz[0x6]; 1591 u8 port_selection_cap[0x1]; 1592 u8 reserved_at_248[0x1]; 1593 u8 umem_uid_0[0x1]; 1594 u8 reserved_at_250[0x5]; 1595 u8 log_pg_sz[0x8]; 1596 1597 u8 bf[0x1]; 1598 u8 driver_version[0x1]; 1599 u8 pad_tx_eth_packet[0x1]; 1600 u8 reserved_at_263[0x3]; 1601 u8 mkey_by_name[0x1]; 1602 u8 reserved_at_267[0x4]; 1603 1604 u8 log_bf_reg_size[0x5]; 1605 1606 u8 reserved_at_270[0x6]; 1607 u8 lag_dct[0x2]; 1608 u8 lag_tx_port_affinity[0x1]; 1609 u8 lag_native_fdb_selection[0x1]; 1610 u8 reserved_at_27a[0x1]; 1611 u8 lag_master[0x1]; 1612 u8 num_lag_ports[0x4]; 1613 1614 u8 reserved_at_280[0x10]; 1615 u8 max_wqe_sz_sq[0x10]; 1616 1617 u8 reserved_at_2a0[0x10]; 1618 u8 max_wqe_sz_rq[0x10]; 1619 1620 u8 max_flow_counter_31_16[0x10]; 1621 u8 max_wqe_sz_sq_dc[0x10]; 1622 1623 u8 reserved_at_2e0[0x7]; 1624 u8 max_qp_mcg[0x19]; 1625 1626 u8 reserved_at_300[0x10]; 1627 u8 flow_counter_bulk_alloc[0x8]; 1628 u8 log_max_mcg[0x8]; 1629 1630 u8 reserved_at_320[0x3]; 1631 u8 log_max_transport_domain[0x5]; 1632 u8 reserved_at_328[0x3]; 1633 u8 log_max_pd[0x5]; 1634 u8 reserved_at_330[0xb]; 1635 u8 log_max_xrcd[0x5]; 1636 1637 u8 nic_receive_steering_discard[0x1]; 1638 u8 receive_discard_vport_down[0x1]; 1639 u8 transmit_discard_vport_down[0x1]; 1640 u8 eq_overrun_count[0x1]; 1641 u8 reserved_at_344[0x1]; 1642 u8 invalid_command_count[0x1]; 1643 u8 quota_exceeded_count[0x1]; 1644 u8 reserved_at_347[0x1]; 1645 u8 log_max_flow_counter_bulk[0x8]; 1646 u8 max_flow_counter_15_0[0x10]; 1647 1648 1649 u8 reserved_at_360[0x3]; 1650 u8 log_max_rq[0x5]; 1651 u8 reserved_at_368[0x3]; 1652 u8 log_max_sq[0x5]; 1653 u8 reserved_at_370[0x3]; 1654 u8 log_max_tir[0x5]; 1655 u8 reserved_at_378[0x3]; 1656 u8 log_max_tis[0x5]; 1657 1658 u8 basic_cyclic_rcv_wqe[0x1]; 1659 u8 reserved_at_381[0x2]; 1660 u8 log_max_rmp[0x5]; 1661 u8 reserved_at_388[0x3]; 1662 u8 log_max_rqt[0x5]; 1663 u8 reserved_at_390[0x3]; 1664 u8 log_max_rqt_size[0x5]; 1665 u8 reserved_at_398[0x3]; 1666 u8 log_max_tis_per_sq[0x5]; 1667 1668 u8 ext_stride_num_range[0x1]; 1669 u8 roce_rw_supported[0x1]; 1670 u8 log_max_current_uc_list_wr_supported[0x1]; 1671 u8 log_max_stride_sz_rq[0x5]; 1672 u8 reserved_at_3a8[0x3]; 1673 u8 log_min_stride_sz_rq[0x5]; 1674 u8 reserved_at_3b0[0x3]; 1675 u8 log_max_stride_sz_sq[0x5]; 1676 u8 reserved_at_3b8[0x3]; 1677 u8 log_min_stride_sz_sq[0x5]; 1678 1679 u8 hairpin[0x1]; 1680 u8 reserved_at_3c1[0x2]; 1681 u8 log_max_hairpin_queues[0x5]; 1682 u8 reserved_at_3c8[0x3]; 1683 u8 log_max_hairpin_wq_data_sz[0x5]; 1684 u8 reserved_at_3d0[0x3]; 1685 u8 log_max_hairpin_num_packets[0x5]; 1686 u8 reserved_at_3d8[0x3]; 1687 u8 log_max_wq_sz[0x5]; 1688 1689 u8 nic_vport_change_event[0x1]; 1690 u8 disable_local_lb_uc[0x1]; 1691 u8 disable_local_lb_mc[0x1]; 1692 u8 log_min_hairpin_wq_data_sz[0x5]; 1693 u8 reserved_at_3e8[0x2]; 1694 u8 vhca_state[0x1]; 1695 u8 log_max_vlan_list[0x5]; 1696 u8 reserved_at_3f0[0x3]; 1697 u8 log_max_current_mc_list[0x5]; 1698 u8 reserved_at_3f8[0x3]; 1699 u8 log_max_current_uc_list[0x5]; 1700 1701 u8 general_obj_types[0x40]; 1702 1703 u8 sq_ts_format[0x2]; 1704 u8 rq_ts_format[0x2]; 1705 u8 steering_format_version[0x4]; 1706 u8 create_qp_start_hint[0x18]; 1707 1708 u8 reserved_at_460[0x3]; 1709 u8 log_max_uctx[0x5]; 1710 u8 reserved_at_468[0x2]; 1711 u8 ipsec_offload[0x1]; 1712 u8 log_max_umem[0x5]; 1713 u8 max_num_eqs[0x10]; 1714 1715 u8 reserved_at_480[0x1]; 1716 u8 tls_tx[0x1]; 1717 u8 tls_rx[0x1]; 1718 u8 log_max_l2_table[0x5]; 1719 u8 reserved_at_488[0x8]; 1720 u8 log_uar_page_sz[0x10]; 1721 1722 u8 reserved_at_4a0[0x20]; 1723 u8 device_frequency_mhz[0x20]; 1724 u8 device_frequency_khz[0x20]; 1725 1726 u8 reserved_at_500[0x20]; 1727 u8 num_of_uars_per_page[0x20]; 1728 1729 u8 flex_parser_protocols[0x20]; 1730 1731 u8 max_geneve_tlv_options[0x8]; 1732 u8 reserved_at_568[0x3]; 1733 u8 max_geneve_tlv_option_data_len[0x5]; 1734 u8 reserved_at_570[0x10]; 1735 1736 u8 reserved_at_580[0xb]; 1737 u8 log_max_dci_stream_channels[0x5]; 1738 u8 reserved_at_590[0x3]; 1739 u8 log_max_dci_errored_streams[0x5]; 1740 u8 reserved_at_598[0x8]; 1741 1742 u8 reserved_at_5a0[0x10]; 1743 u8 enhanced_cqe_compression[0x1]; 1744 u8 reserved_at_5b1[0x2]; 1745 u8 log_max_dek[0x5]; 1746 u8 reserved_at_5b8[0x4]; 1747 u8 mini_cqe_resp_stride_index[0x1]; 1748 u8 cqe_128_always[0x1]; 1749 u8 cqe_compression_128[0x1]; 1750 u8 cqe_compression[0x1]; 1751 1752 u8 cqe_compression_timeout[0x10]; 1753 u8 cqe_compression_max_num[0x10]; 1754 1755 u8 reserved_at_5e0[0x8]; 1756 u8 flex_parser_id_gtpu_dw_0[0x4]; 1757 u8 reserved_at_5ec[0x4]; 1758 u8 tag_matching[0x1]; 1759 u8 rndv_offload_rc[0x1]; 1760 u8 rndv_offload_dc[0x1]; 1761 u8 log_tag_matching_list_sz[0x5]; 1762 u8 reserved_at_5f8[0x3]; 1763 u8 log_max_xrq[0x5]; 1764 1765 u8 affiliate_nic_vport_criteria[0x8]; 1766 u8 native_port_num[0x8]; 1767 u8 num_vhca_ports[0x8]; 1768 u8 flex_parser_id_gtpu_teid[0x4]; 1769 u8 reserved_at_61c[0x2]; 1770 u8 sw_owner_id[0x1]; 1771 u8 reserved_at_61f[0x1]; 1772 1773 u8 max_num_of_monitor_counters[0x10]; 1774 u8 num_ppcnt_monitor_counters[0x10]; 1775 1776 u8 max_num_sf[0x10]; 1777 u8 num_q_monitor_counters[0x10]; 1778 1779 u8 reserved_at_660[0x20]; 1780 1781 u8 sf[0x1]; 1782 u8 sf_set_partition[0x1]; 1783 u8 reserved_at_682[0x1]; 1784 u8 log_max_sf[0x5]; 1785 u8 apu[0x1]; 1786 u8 reserved_at_689[0x4]; 1787 u8 migration[0x1]; 1788 u8 reserved_at_68e[0x2]; 1789 u8 log_min_sf_size[0x8]; 1790 u8 max_num_sf_partitions[0x8]; 1791 1792 u8 uctx_cap[0x20]; 1793 1794 u8 reserved_at_6c0[0x4]; 1795 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1796 u8 flex_parser_id_icmp_dw1[0x4]; 1797 u8 flex_parser_id_icmp_dw0[0x4]; 1798 u8 flex_parser_id_icmpv6_dw1[0x4]; 1799 u8 flex_parser_id_icmpv6_dw0[0x4]; 1800 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1801 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1802 1803 u8 max_num_match_definer[0x10]; 1804 u8 sf_base_id[0x10]; 1805 1806 u8 flex_parser_id_gtpu_dw_2[0x4]; 1807 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1808 u8 num_total_dynamic_vf_msix[0x18]; 1809 u8 reserved_at_720[0x14]; 1810 u8 dynamic_msix_table_size[0xc]; 1811 u8 reserved_at_740[0xc]; 1812 u8 min_dynamic_vf_msix_table_size[0x4]; 1813 u8 reserved_at_750[0x4]; 1814 u8 max_dynamic_vf_msix_table_size[0xc]; 1815 1816 u8 reserved_at_760[0x20]; 1817 u8 vhca_tunnel_commands[0x40]; 1818 u8 match_definer_format_supported[0x40]; 1819 }; 1820 1821 struct mlx5_ifc_cmd_hca_cap_2_bits { 1822 u8 reserved_at_0[0xa0]; 1823 1824 u8 max_reformat_insert_size[0x8]; 1825 u8 max_reformat_insert_offset[0x8]; 1826 u8 max_reformat_remove_size[0x8]; 1827 u8 max_reformat_remove_offset[0x8]; 1828 1829 u8 reserved_at_c0[0x740]; 1830 }; 1831 1832 enum mlx5_ifc_flow_destination_type { 1833 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1834 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1835 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1836 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1837 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1838 }; 1839 1840 enum mlx5_flow_table_miss_action { 1841 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1842 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1843 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1844 }; 1845 1846 struct mlx5_ifc_dest_format_struct_bits { 1847 u8 destination_type[0x8]; 1848 u8 destination_id[0x18]; 1849 1850 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1851 u8 packet_reformat[0x1]; 1852 u8 reserved_at_22[0xe]; 1853 u8 destination_eswitch_owner_vhca_id[0x10]; 1854 }; 1855 1856 struct mlx5_ifc_flow_counter_list_bits { 1857 u8 flow_counter_id[0x20]; 1858 1859 u8 reserved_at_20[0x20]; 1860 }; 1861 1862 struct mlx5_ifc_extended_dest_format_bits { 1863 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1864 1865 u8 packet_reformat_id[0x20]; 1866 1867 u8 reserved_at_60[0x20]; 1868 }; 1869 1870 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1871 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1872 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1873 }; 1874 1875 struct mlx5_ifc_fte_match_param_bits { 1876 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1877 1878 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1879 1880 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1881 1882 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1883 1884 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1885 1886 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1887 1888 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1889 1890 u8 reserved_at_e00[0x200]; 1891 }; 1892 1893 enum { 1894 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1895 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1896 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1897 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1898 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1899 }; 1900 1901 struct mlx5_ifc_rx_hash_field_select_bits { 1902 u8 l3_prot_type[0x1]; 1903 u8 l4_prot_type[0x1]; 1904 u8 selected_fields[0x1e]; 1905 }; 1906 1907 enum { 1908 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1909 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1910 }; 1911 1912 enum { 1913 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1914 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1915 }; 1916 1917 struct mlx5_ifc_wq_bits { 1918 u8 wq_type[0x4]; 1919 u8 wq_signature[0x1]; 1920 u8 end_padding_mode[0x2]; 1921 u8 cd_slave[0x1]; 1922 u8 reserved_at_8[0x18]; 1923 1924 u8 hds_skip_first_sge[0x1]; 1925 u8 log2_hds_buf_size[0x3]; 1926 u8 reserved_at_24[0x7]; 1927 u8 page_offset[0x5]; 1928 u8 lwm[0x10]; 1929 1930 u8 reserved_at_40[0x8]; 1931 u8 pd[0x18]; 1932 1933 u8 reserved_at_60[0x8]; 1934 u8 uar_page[0x18]; 1935 1936 u8 dbr_addr[0x40]; 1937 1938 u8 hw_counter[0x20]; 1939 1940 u8 sw_counter[0x20]; 1941 1942 u8 reserved_at_100[0xc]; 1943 u8 log_wq_stride[0x4]; 1944 u8 reserved_at_110[0x3]; 1945 u8 log_wq_pg_sz[0x5]; 1946 u8 reserved_at_118[0x3]; 1947 u8 log_wq_sz[0x5]; 1948 1949 u8 dbr_umem_valid[0x1]; 1950 u8 wq_umem_valid[0x1]; 1951 u8 reserved_at_122[0x1]; 1952 u8 log_hairpin_num_packets[0x5]; 1953 u8 reserved_at_128[0x3]; 1954 u8 log_hairpin_data_sz[0x5]; 1955 1956 u8 reserved_at_130[0x4]; 1957 u8 log_wqe_num_of_strides[0x4]; 1958 u8 two_byte_shift_en[0x1]; 1959 u8 reserved_at_139[0x4]; 1960 u8 log_wqe_stride_size[0x3]; 1961 1962 u8 reserved_at_140[0x80]; 1963 1964 u8 headers_mkey[0x20]; 1965 1966 u8 shampo_enable[0x1]; 1967 u8 reserved_at_1e1[0x4]; 1968 u8 log_reservation_size[0x3]; 1969 u8 reserved_at_1e8[0x5]; 1970 u8 log_max_num_of_packets_per_reservation[0x3]; 1971 u8 reserved_at_1f0[0x6]; 1972 u8 log_headers_entry_size[0x2]; 1973 u8 reserved_at_1f8[0x4]; 1974 u8 log_headers_buffer_entry_num[0x4]; 1975 1976 u8 reserved_at_200[0x400]; 1977 1978 struct mlx5_ifc_cmd_pas_bits pas[]; 1979 }; 1980 1981 struct mlx5_ifc_rq_num_bits { 1982 u8 reserved_at_0[0x8]; 1983 u8 rq_num[0x18]; 1984 }; 1985 1986 struct mlx5_ifc_mac_address_layout_bits { 1987 u8 reserved_at_0[0x10]; 1988 u8 mac_addr_47_32[0x10]; 1989 1990 u8 mac_addr_31_0[0x20]; 1991 }; 1992 1993 struct mlx5_ifc_vlan_layout_bits { 1994 u8 reserved_at_0[0x14]; 1995 u8 vlan[0x0c]; 1996 1997 u8 reserved_at_20[0x20]; 1998 }; 1999 2000 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2001 u8 reserved_at_0[0xa0]; 2002 2003 u8 min_time_between_cnps[0x20]; 2004 2005 u8 reserved_at_c0[0x12]; 2006 u8 cnp_dscp[0x6]; 2007 u8 reserved_at_d8[0x4]; 2008 u8 cnp_prio_mode[0x1]; 2009 u8 cnp_802p_prio[0x3]; 2010 2011 u8 reserved_at_e0[0x720]; 2012 }; 2013 2014 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2015 u8 reserved_at_0[0x60]; 2016 2017 u8 reserved_at_60[0x4]; 2018 u8 clamp_tgt_rate[0x1]; 2019 u8 reserved_at_65[0x3]; 2020 u8 clamp_tgt_rate_after_time_inc[0x1]; 2021 u8 reserved_at_69[0x17]; 2022 2023 u8 reserved_at_80[0x20]; 2024 2025 u8 rpg_time_reset[0x20]; 2026 2027 u8 rpg_byte_reset[0x20]; 2028 2029 u8 rpg_threshold[0x20]; 2030 2031 u8 rpg_max_rate[0x20]; 2032 2033 u8 rpg_ai_rate[0x20]; 2034 2035 u8 rpg_hai_rate[0x20]; 2036 2037 u8 rpg_gd[0x20]; 2038 2039 u8 rpg_min_dec_fac[0x20]; 2040 2041 u8 rpg_min_rate[0x20]; 2042 2043 u8 reserved_at_1c0[0xe0]; 2044 2045 u8 rate_to_set_on_first_cnp[0x20]; 2046 2047 u8 dce_tcp_g[0x20]; 2048 2049 u8 dce_tcp_rtt[0x20]; 2050 2051 u8 rate_reduce_monitor_period[0x20]; 2052 2053 u8 reserved_at_320[0x20]; 2054 2055 u8 initial_alpha_value[0x20]; 2056 2057 u8 reserved_at_360[0x4a0]; 2058 }; 2059 2060 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2061 u8 reserved_at_0[0x80]; 2062 2063 u8 rppp_max_rps[0x20]; 2064 2065 u8 rpg_time_reset[0x20]; 2066 2067 u8 rpg_byte_reset[0x20]; 2068 2069 u8 rpg_threshold[0x20]; 2070 2071 u8 rpg_max_rate[0x20]; 2072 2073 u8 rpg_ai_rate[0x20]; 2074 2075 u8 rpg_hai_rate[0x20]; 2076 2077 u8 rpg_gd[0x20]; 2078 2079 u8 rpg_min_dec_fac[0x20]; 2080 2081 u8 rpg_min_rate[0x20]; 2082 2083 u8 reserved_at_1c0[0x640]; 2084 }; 2085 2086 enum { 2087 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2088 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2089 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2090 }; 2091 2092 struct mlx5_ifc_resize_field_select_bits { 2093 u8 resize_field_select[0x20]; 2094 }; 2095 2096 struct mlx5_ifc_resource_dump_bits { 2097 u8 more_dump[0x1]; 2098 u8 inline_dump[0x1]; 2099 u8 reserved_at_2[0xa]; 2100 u8 seq_num[0x4]; 2101 u8 segment_type[0x10]; 2102 2103 u8 reserved_at_20[0x10]; 2104 u8 vhca_id[0x10]; 2105 2106 u8 index1[0x20]; 2107 2108 u8 index2[0x20]; 2109 2110 u8 num_of_obj1[0x10]; 2111 u8 num_of_obj2[0x10]; 2112 2113 u8 reserved_at_a0[0x20]; 2114 2115 u8 device_opaque[0x40]; 2116 2117 u8 mkey[0x20]; 2118 2119 u8 size[0x20]; 2120 2121 u8 address[0x40]; 2122 2123 u8 inline_data[52][0x20]; 2124 }; 2125 2126 struct mlx5_ifc_resource_dump_menu_record_bits { 2127 u8 reserved_at_0[0x4]; 2128 u8 num_of_obj2_supports_active[0x1]; 2129 u8 num_of_obj2_supports_all[0x1]; 2130 u8 must_have_num_of_obj2[0x1]; 2131 u8 support_num_of_obj2[0x1]; 2132 u8 num_of_obj1_supports_active[0x1]; 2133 u8 num_of_obj1_supports_all[0x1]; 2134 u8 must_have_num_of_obj1[0x1]; 2135 u8 support_num_of_obj1[0x1]; 2136 u8 must_have_index2[0x1]; 2137 u8 support_index2[0x1]; 2138 u8 must_have_index1[0x1]; 2139 u8 support_index1[0x1]; 2140 u8 segment_type[0x10]; 2141 2142 u8 segment_name[4][0x20]; 2143 2144 u8 index1_name[4][0x20]; 2145 2146 u8 index2_name[4][0x20]; 2147 }; 2148 2149 struct mlx5_ifc_resource_dump_segment_header_bits { 2150 u8 length_dw[0x10]; 2151 u8 segment_type[0x10]; 2152 }; 2153 2154 struct mlx5_ifc_resource_dump_command_segment_bits { 2155 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2156 2157 u8 segment_called[0x10]; 2158 u8 vhca_id[0x10]; 2159 2160 u8 index1[0x20]; 2161 2162 u8 index2[0x20]; 2163 2164 u8 num_of_obj1[0x10]; 2165 u8 num_of_obj2[0x10]; 2166 }; 2167 2168 struct mlx5_ifc_resource_dump_error_segment_bits { 2169 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2170 2171 u8 reserved_at_20[0x10]; 2172 u8 syndrome_id[0x10]; 2173 2174 u8 reserved_at_40[0x40]; 2175 2176 u8 error[8][0x20]; 2177 }; 2178 2179 struct mlx5_ifc_resource_dump_info_segment_bits { 2180 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2181 2182 u8 reserved_at_20[0x18]; 2183 u8 dump_version[0x8]; 2184 2185 u8 hw_version[0x20]; 2186 2187 u8 fw_version[0x20]; 2188 }; 2189 2190 struct mlx5_ifc_resource_dump_menu_segment_bits { 2191 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2192 2193 u8 reserved_at_20[0x10]; 2194 u8 num_of_records[0x10]; 2195 2196 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2197 }; 2198 2199 struct mlx5_ifc_resource_dump_resource_segment_bits { 2200 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2201 2202 u8 reserved_at_20[0x20]; 2203 2204 u8 index1[0x20]; 2205 2206 u8 index2[0x20]; 2207 2208 u8 payload[][0x20]; 2209 }; 2210 2211 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2212 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2213 }; 2214 2215 struct mlx5_ifc_menu_resource_dump_response_bits { 2216 struct mlx5_ifc_resource_dump_info_segment_bits info; 2217 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2218 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2219 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2220 }; 2221 2222 enum { 2223 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2224 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2225 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2226 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2227 }; 2228 2229 struct mlx5_ifc_modify_field_select_bits { 2230 u8 modify_field_select[0x20]; 2231 }; 2232 2233 struct mlx5_ifc_field_select_r_roce_np_bits { 2234 u8 field_select_r_roce_np[0x20]; 2235 }; 2236 2237 struct mlx5_ifc_field_select_r_roce_rp_bits { 2238 u8 field_select_r_roce_rp[0x20]; 2239 }; 2240 2241 enum { 2242 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2243 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2244 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2245 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2246 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2247 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2248 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2249 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2250 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2251 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2252 }; 2253 2254 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2255 u8 field_select_8021qaurp[0x20]; 2256 }; 2257 2258 struct mlx5_ifc_phys_layer_cntrs_bits { 2259 u8 time_since_last_clear_high[0x20]; 2260 2261 u8 time_since_last_clear_low[0x20]; 2262 2263 u8 symbol_errors_high[0x20]; 2264 2265 u8 symbol_errors_low[0x20]; 2266 2267 u8 sync_headers_errors_high[0x20]; 2268 2269 u8 sync_headers_errors_low[0x20]; 2270 2271 u8 edpl_bip_errors_lane0_high[0x20]; 2272 2273 u8 edpl_bip_errors_lane0_low[0x20]; 2274 2275 u8 edpl_bip_errors_lane1_high[0x20]; 2276 2277 u8 edpl_bip_errors_lane1_low[0x20]; 2278 2279 u8 edpl_bip_errors_lane2_high[0x20]; 2280 2281 u8 edpl_bip_errors_lane2_low[0x20]; 2282 2283 u8 edpl_bip_errors_lane3_high[0x20]; 2284 2285 u8 edpl_bip_errors_lane3_low[0x20]; 2286 2287 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2288 2289 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2290 2291 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2292 2293 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2294 2295 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2296 2297 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2298 2299 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2300 2301 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2302 2303 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2304 2305 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2306 2307 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2308 2309 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2310 2311 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2312 2313 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2314 2315 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2316 2317 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2318 2319 u8 rs_fec_corrected_blocks_high[0x20]; 2320 2321 u8 rs_fec_corrected_blocks_low[0x20]; 2322 2323 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2324 2325 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2326 2327 u8 rs_fec_no_errors_blocks_high[0x20]; 2328 2329 u8 rs_fec_no_errors_blocks_low[0x20]; 2330 2331 u8 rs_fec_single_error_blocks_high[0x20]; 2332 2333 u8 rs_fec_single_error_blocks_low[0x20]; 2334 2335 u8 rs_fec_corrected_symbols_total_high[0x20]; 2336 2337 u8 rs_fec_corrected_symbols_total_low[0x20]; 2338 2339 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2340 2341 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2342 2343 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2344 2345 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2346 2347 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2348 2349 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2350 2351 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2352 2353 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2354 2355 u8 link_down_events[0x20]; 2356 2357 u8 successful_recovery_events[0x20]; 2358 2359 u8 reserved_at_640[0x180]; 2360 }; 2361 2362 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2363 u8 time_since_last_clear_high[0x20]; 2364 2365 u8 time_since_last_clear_low[0x20]; 2366 2367 u8 phy_received_bits_high[0x20]; 2368 2369 u8 phy_received_bits_low[0x20]; 2370 2371 u8 phy_symbol_errors_high[0x20]; 2372 2373 u8 phy_symbol_errors_low[0x20]; 2374 2375 u8 phy_corrected_bits_high[0x20]; 2376 2377 u8 phy_corrected_bits_low[0x20]; 2378 2379 u8 phy_corrected_bits_lane0_high[0x20]; 2380 2381 u8 phy_corrected_bits_lane0_low[0x20]; 2382 2383 u8 phy_corrected_bits_lane1_high[0x20]; 2384 2385 u8 phy_corrected_bits_lane1_low[0x20]; 2386 2387 u8 phy_corrected_bits_lane2_high[0x20]; 2388 2389 u8 phy_corrected_bits_lane2_low[0x20]; 2390 2391 u8 phy_corrected_bits_lane3_high[0x20]; 2392 2393 u8 phy_corrected_bits_lane3_low[0x20]; 2394 2395 u8 reserved_at_200[0x5c0]; 2396 }; 2397 2398 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2399 u8 symbol_error_counter[0x10]; 2400 2401 u8 link_error_recovery_counter[0x8]; 2402 2403 u8 link_downed_counter[0x8]; 2404 2405 u8 port_rcv_errors[0x10]; 2406 2407 u8 port_rcv_remote_physical_errors[0x10]; 2408 2409 u8 port_rcv_switch_relay_errors[0x10]; 2410 2411 u8 port_xmit_discards[0x10]; 2412 2413 u8 port_xmit_constraint_errors[0x8]; 2414 2415 u8 port_rcv_constraint_errors[0x8]; 2416 2417 u8 reserved_at_70[0x8]; 2418 2419 u8 link_overrun_errors[0x8]; 2420 2421 u8 reserved_at_80[0x10]; 2422 2423 u8 vl_15_dropped[0x10]; 2424 2425 u8 reserved_at_a0[0x80]; 2426 2427 u8 port_xmit_wait[0x20]; 2428 }; 2429 2430 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2431 u8 transmit_queue_high[0x20]; 2432 2433 u8 transmit_queue_low[0x20]; 2434 2435 u8 no_buffer_discard_uc_high[0x20]; 2436 2437 u8 no_buffer_discard_uc_low[0x20]; 2438 2439 u8 reserved_at_80[0x740]; 2440 }; 2441 2442 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2443 u8 wred_discard_high[0x20]; 2444 2445 u8 wred_discard_low[0x20]; 2446 2447 u8 ecn_marked_tc_high[0x20]; 2448 2449 u8 ecn_marked_tc_low[0x20]; 2450 2451 u8 reserved_at_80[0x740]; 2452 }; 2453 2454 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2455 u8 rx_octets_high[0x20]; 2456 2457 u8 rx_octets_low[0x20]; 2458 2459 u8 reserved_at_40[0xc0]; 2460 2461 u8 rx_frames_high[0x20]; 2462 2463 u8 rx_frames_low[0x20]; 2464 2465 u8 tx_octets_high[0x20]; 2466 2467 u8 tx_octets_low[0x20]; 2468 2469 u8 reserved_at_180[0xc0]; 2470 2471 u8 tx_frames_high[0x20]; 2472 2473 u8 tx_frames_low[0x20]; 2474 2475 u8 rx_pause_high[0x20]; 2476 2477 u8 rx_pause_low[0x20]; 2478 2479 u8 rx_pause_duration_high[0x20]; 2480 2481 u8 rx_pause_duration_low[0x20]; 2482 2483 u8 tx_pause_high[0x20]; 2484 2485 u8 tx_pause_low[0x20]; 2486 2487 u8 tx_pause_duration_high[0x20]; 2488 2489 u8 tx_pause_duration_low[0x20]; 2490 2491 u8 rx_pause_transition_high[0x20]; 2492 2493 u8 rx_pause_transition_low[0x20]; 2494 2495 u8 rx_discards_high[0x20]; 2496 2497 u8 rx_discards_low[0x20]; 2498 2499 u8 device_stall_minor_watermark_cnt_high[0x20]; 2500 2501 u8 device_stall_minor_watermark_cnt_low[0x20]; 2502 2503 u8 device_stall_critical_watermark_cnt_high[0x20]; 2504 2505 u8 device_stall_critical_watermark_cnt_low[0x20]; 2506 2507 u8 reserved_at_480[0x340]; 2508 }; 2509 2510 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2511 u8 port_transmit_wait_high[0x20]; 2512 2513 u8 port_transmit_wait_low[0x20]; 2514 2515 u8 reserved_at_40[0x100]; 2516 2517 u8 rx_buffer_almost_full_high[0x20]; 2518 2519 u8 rx_buffer_almost_full_low[0x20]; 2520 2521 u8 rx_buffer_full_high[0x20]; 2522 2523 u8 rx_buffer_full_low[0x20]; 2524 2525 u8 rx_icrc_encapsulated_high[0x20]; 2526 2527 u8 rx_icrc_encapsulated_low[0x20]; 2528 2529 u8 reserved_at_200[0x5c0]; 2530 }; 2531 2532 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2533 u8 dot3stats_alignment_errors_high[0x20]; 2534 2535 u8 dot3stats_alignment_errors_low[0x20]; 2536 2537 u8 dot3stats_fcs_errors_high[0x20]; 2538 2539 u8 dot3stats_fcs_errors_low[0x20]; 2540 2541 u8 dot3stats_single_collision_frames_high[0x20]; 2542 2543 u8 dot3stats_single_collision_frames_low[0x20]; 2544 2545 u8 dot3stats_multiple_collision_frames_high[0x20]; 2546 2547 u8 dot3stats_multiple_collision_frames_low[0x20]; 2548 2549 u8 dot3stats_sqe_test_errors_high[0x20]; 2550 2551 u8 dot3stats_sqe_test_errors_low[0x20]; 2552 2553 u8 dot3stats_deferred_transmissions_high[0x20]; 2554 2555 u8 dot3stats_deferred_transmissions_low[0x20]; 2556 2557 u8 dot3stats_late_collisions_high[0x20]; 2558 2559 u8 dot3stats_late_collisions_low[0x20]; 2560 2561 u8 dot3stats_excessive_collisions_high[0x20]; 2562 2563 u8 dot3stats_excessive_collisions_low[0x20]; 2564 2565 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2566 2567 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2568 2569 u8 dot3stats_carrier_sense_errors_high[0x20]; 2570 2571 u8 dot3stats_carrier_sense_errors_low[0x20]; 2572 2573 u8 dot3stats_frame_too_longs_high[0x20]; 2574 2575 u8 dot3stats_frame_too_longs_low[0x20]; 2576 2577 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2578 2579 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2580 2581 u8 dot3stats_symbol_errors_high[0x20]; 2582 2583 u8 dot3stats_symbol_errors_low[0x20]; 2584 2585 u8 dot3control_in_unknown_opcodes_high[0x20]; 2586 2587 u8 dot3control_in_unknown_opcodes_low[0x20]; 2588 2589 u8 dot3in_pause_frames_high[0x20]; 2590 2591 u8 dot3in_pause_frames_low[0x20]; 2592 2593 u8 dot3out_pause_frames_high[0x20]; 2594 2595 u8 dot3out_pause_frames_low[0x20]; 2596 2597 u8 reserved_at_400[0x3c0]; 2598 }; 2599 2600 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2601 u8 ether_stats_drop_events_high[0x20]; 2602 2603 u8 ether_stats_drop_events_low[0x20]; 2604 2605 u8 ether_stats_octets_high[0x20]; 2606 2607 u8 ether_stats_octets_low[0x20]; 2608 2609 u8 ether_stats_pkts_high[0x20]; 2610 2611 u8 ether_stats_pkts_low[0x20]; 2612 2613 u8 ether_stats_broadcast_pkts_high[0x20]; 2614 2615 u8 ether_stats_broadcast_pkts_low[0x20]; 2616 2617 u8 ether_stats_multicast_pkts_high[0x20]; 2618 2619 u8 ether_stats_multicast_pkts_low[0x20]; 2620 2621 u8 ether_stats_crc_align_errors_high[0x20]; 2622 2623 u8 ether_stats_crc_align_errors_low[0x20]; 2624 2625 u8 ether_stats_undersize_pkts_high[0x20]; 2626 2627 u8 ether_stats_undersize_pkts_low[0x20]; 2628 2629 u8 ether_stats_oversize_pkts_high[0x20]; 2630 2631 u8 ether_stats_oversize_pkts_low[0x20]; 2632 2633 u8 ether_stats_fragments_high[0x20]; 2634 2635 u8 ether_stats_fragments_low[0x20]; 2636 2637 u8 ether_stats_jabbers_high[0x20]; 2638 2639 u8 ether_stats_jabbers_low[0x20]; 2640 2641 u8 ether_stats_collisions_high[0x20]; 2642 2643 u8 ether_stats_collisions_low[0x20]; 2644 2645 u8 ether_stats_pkts64octets_high[0x20]; 2646 2647 u8 ether_stats_pkts64octets_low[0x20]; 2648 2649 u8 ether_stats_pkts65to127octets_high[0x20]; 2650 2651 u8 ether_stats_pkts65to127octets_low[0x20]; 2652 2653 u8 ether_stats_pkts128to255octets_high[0x20]; 2654 2655 u8 ether_stats_pkts128to255octets_low[0x20]; 2656 2657 u8 ether_stats_pkts256to511octets_high[0x20]; 2658 2659 u8 ether_stats_pkts256to511octets_low[0x20]; 2660 2661 u8 ether_stats_pkts512to1023octets_high[0x20]; 2662 2663 u8 ether_stats_pkts512to1023octets_low[0x20]; 2664 2665 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2666 2667 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2668 2669 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2670 2671 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2672 2673 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2674 2675 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2676 2677 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2678 2679 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2680 2681 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2682 2683 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2684 2685 u8 reserved_at_540[0x280]; 2686 }; 2687 2688 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2689 u8 if_in_octets_high[0x20]; 2690 2691 u8 if_in_octets_low[0x20]; 2692 2693 u8 if_in_ucast_pkts_high[0x20]; 2694 2695 u8 if_in_ucast_pkts_low[0x20]; 2696 2697 u8 if_in_discards_high[0x20]; 2698 2699 u8 if_in_discards_low[0x20]; 2700 2701 u8 if_in_errors_high[0x20]; 2702 2703 u8 if_in_errors_low[0x20]; 2704 2705 u8 if_in_unknown_protos_high[0x20]; 2706 2707 u8 if_in_unknown_protos_low[0x20]; 2708 2709 u8 if_out_octets_high[0x20]; 2710 2711 u8 if_out_octets_low[0x20]; 2712 2713 u8 if_out_ucast_pkts_high[0x20]; 2714 2715 u8 if_out_ucast_pkts_low[0x20]; 2716 2717 u8 if_out_discards_high[0x20]; 2718 2719 u8 if_out_discards_low[0x20]; 2720 2721 u8 if_out_errors_high[0x20]; 2722 2723 u8 if_out_errors_low[0x20]; 2724 2725 u8 if_in_multicast_pkts_high[0x20]; 2726 2727 u8 if_in_multicast_pkts_low[0x20]; 2728 2729 u8 if_in_broadcast_pkts_high[0x20]; 2730 2731 u8 if_in_broadcast_pkts_low[0x20]; 2732 2733 u8 if_out_multicast_pkts_high[0x20]; 2734 2735 u8 if_out_multicast_pkts_low[0x20]; 2736 2737 u8 if_out_broadcast_pkts_high[0x20]; 2738 2739 u8 if_out_broadcast_pkts_low[0x20]; 2740 2741 u8 reserved_at_340[0x480]; 2742 }; 2743 2744 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2745 u8 a_frames_transmitted_ok_high[0x20]; 2746 2747 u8 a_frames_transmitted_ok_low[0x20]; 2748 2749 u8 a_frames_received_ok_high[0x20]; 2750 2751 u8 a_frames_received_ok_low[0x20]; 2752 2753 u8 a_frame_check_sequence_errors_high[0x20]; 2754 2755 u8 a_frame_check_sequence_errors_low[0x20]; 2756 2757 u8 a_alignment_errors_high[0x20]; 2758 2759 u8 a_alignment_errors_low[0x20]; 2760 2761 u8 a_octets_transmitted_ok_high[0x20]; 2762 2763 u8 a_octets_transmitted_ok_low[0x20]; 2764 2765 u8 a_octets_received_ok_high[0x20]; 2766 2767 u8 a_octets_received_ok_low[0x20]; 2768 2769 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2770 2771 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2772 2773 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2774 2775 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2776 2777 u8 a_multicast_frames_received_ok_high[0x20]; 2778 2779 u8 a_multicast_frames_received_ok_low[0x20]; 2780 2781 u8 a_broadcast_frames_received_ok_high[0x20]; 2782 2783 u8 a_broadcast_frames_received_ok_low[0x20]; 2784 2785 u8 a_in_range_length_errors_high[0x20]; 2786 2787 u8 a_in_range_length_errors_low[0x20]; 2788 2789 u8 a_out_of_range_length_field_high[0x20]; 2790 2791 u8 a_out_of_range_length_field_low[0x20]; 2792 2793 u8 a_frame_too_long_errors_high[0x20]; 2794 2795 u8 a_frame_too_long_errors_low[0x20]; 2796 2797 u8 a_symbol_error_during_carrier_high[0x20]; 2798 2799 u8 a_symbol_error_during_carrier_low[0x20]; 2800 2801 u8 a_mac_control_frames_transmitted_high[0x20]; 2802 2803 u8 a_mac_control_frames_transmitted_low[0x20]; 2804 2805 u8 a_mac_control_frames_received_high[0x20]; 2806 2807 u8 a_mac_control_frames_received_low[0x20]; 2808 2809 u8 a_unsupported_opcodes_received_high[0x20]; 2810 2811 u8 a_unsupported_opcodes_received_low[0x20]; 2812 2813 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2814 2815 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2816 2817 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2818 2819 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2820 2821 u8 reserved_at_4c0[0x300]; 2822 }; 2823 2824 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2825 u8 life_time_counter_high[0x20]; 2826 2827 u8 life_time_counter_low[0x20]; 2828 2829 u8 rx_errors[0x20]; 2830 2831 u8 tx_errors[0x20]; 2832 2833 u8 l0_to_recovery_eieos[0x20]; 2834 2835 u8 l0_to_recovery_ts[0x20]; 2836 2837 u8 l0_to_recovery_framing[0x20]; 2838 2839 u8 l0_to_recovery_retrain[0x20]; 2840 2841 u8 crc_error_dllp[0x20]; 2842 2843 u8 crc_error_tlp[0x20]; 2844 2845 u8 tx_overflow_buffer_pkt_high[0x20]; 2846 2847 u8 tx_overflow_buffer_pkt_low[0x20]; 2848 2849 u8 outbound_stalled_reads[0x20]; 2850 2851 u8 outbound_stalled_writes[0x20]; 2852 2853 u8 outbound_stalled_reads_events[0x20]; 2854 2855 u8 outbound_stalled_writes_events[0x20]; 2856 2857 u8 reserved_at_200[0x5c0]; 2858 }; 2859 2860 struct mlx5_ifc_cmd_inter_comp_event_bits { 2861 u8 command_completion_vector[0x20]; 2862 2863 u8 reserved_at_20[0xc0]; 2864 }; 2865 2866 struct mlx5_ifc_stall_vl_event_bits { 2867 u8 reserved_at_0[0x18]; 2868 u8 port_num[0x1]; 2869 u8 reserved_at_19[0x3]; 2870 u8 vl[0x4]; 2871 2872 u8 reserved_at_20[0xa0]; 2873 }; 2874 2875 struct mlx5_ifc_db_bf_congestion_event_bits { 2876 u8 event_subtype[0x8]; 2877 u8 reserved_at_8[0x8]; 2878 u8 congestion_level[0x8]; 2879 u8 reserved_at_18[0x8]; 2880 2881 u8 reserved_at_20[0xa0]; 2882 }; 2883 2884 struct mlx5_ifc_gpio_event_bits { 2885 u8 reserved_at_0[0x60]; 2886 2887 u8 gpio_event_hi[0x20]; 2888 2889 u8 gpio_event_lo[0x20]; 2890 2891 u8 reserved_at_a0[0x40]; 2892 }; 2893 2894 struct mlx5_ifc_port_state_change_event_bits { 2895 u8 reserved_at_0[0x40]; 2896 2897 u8 port_num[0x4]; 2898 u8 reserved_at_44[0x1c]; 2899 2900 u8 reserved_at_60[0x80]; 2901 }; 2902 2903 struct mlx5_ifc_dropped_packet_logged_bits { 2904 u8 reserved_at_0[0xe0]; 2905 }; 2906 2907 struct mlx5_ifc_default_timeout_bits { 2908 u8 to_multiplier[0x3]; 2909 u8 reserved_at_3[0x9]; 2910 u8 to_value[0x14]; 2911 }; 2912 2913 struct mlx5_ifc_dtor_reg_bits { 2914 u8 reserved_at_0[0x20]; 2915 2916 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2917 2918 u8 reserved_at_40[0x60]; 2919 2920 struct mlx5_ifc_default_timeout_bits health_poll_to; 2921 2922 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2923 2924 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2925 2926 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 2927 2928 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 2929 2930 struct mlx5_ifc_default_timeout_bits tear_down_to; 2931 2932 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 2933 2934 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 2935 2936 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 2937 2938 u8 reserved_at_1c0[0x40]; 2939 }; 2940 2941 enum { 2942 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2943 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2944 }; 2945 2946 struct mlx5_ifc_cq_error_bits { 2947 u8 reserved_at_0[0x8]; 2948 u8 cqn[0x18]; 2949 2950 u8 reserved_at_20[0x20]; 2951 2952 u8 reserved_at_40[0x18]; 2953 u8 syndrome[0x8]; 2954 2955 u8 reserved_at_60[0x80]; 2956 }; 2957 2958 struct mlx5_ifc_rdma_page_fault_event_bits { 2959 u8 bytes_committed[0x20]; 2960 2961 u8 r_key[0x20]; 2962 2963 u8 reserved_at_40[0x10]; 2964 u8 packet_len[0x10]; 2965 2966 u8 rdma_op_len[0x20]; 2967 2968 u8 rdma_va[0x40]; 2969 2970 u8 reserved_at_c0[0x5]; 2971 u8 rdma[0x1]; 2972 u8 write[0x1]; 2973 u8 requestor[0x1]; 2974 u8 qp_number[0x18]; 2975 }; 2976 2977 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2978 u8 bytes_committed[0x20]; 2979 2980 u8 reserved_at_20[0x10]; 2981 u8 wqe_index[0x10]; 2982 2983 u8 reserved_at_40[0x10]; 2984 u8 len[0x10]; 2985 2986 u8 reserved_at_60[0x60]; 2987 2988 u8 reserved_at_c0[0x5]; 2989 u8 rdma[0x1]; 2990 u8 write_read[0x1]; 2991 u8 requestor[0x1]; 2992 u8 qpn[0x18]; 2993 }; 2994 2995 struct mlx5_ifc_qp_events_bits { 2996 u8 reserved_at_0[0xa0]; 2997 2998 u8 type[0x8]; 2999 u8 reserved_at_a8[0x18]; 3000 3001 u8 reserved_at_c0[0x8]; 3002 u8 qpn_rqn_sqn[0x18]; 3003 }; 3004 3005 struct mlx5_ifc_dct_events_bits { 3006 u8 reserved_at_0[0xc0]; 3007 3008 u8 reserved_at_c0[0x8]; 3009 u8 dct_number[0x18]; 3010 }; 3011 3012 struct mlx5_ifc_comp_event_bits { 3013 u8 reserved_at_0[0xc0]; 3014 3015 u8 reserved_at_c0[0x8]; 3016 u8 cq_number[0x18]; 3017 }; 3018 3019 enum { 3020 MLX5_QPC_STATE_RST = 0x0, 3021 MLX5_QPC_STATE_INIT = 0x1, 3022 MLX5_QPC_STATE_RTR = 0x2, 3023 MLX5_QPC_STATE_RTS = 0x3, 3024 MLX5_QPC_STATE_SQER = 0x4, 3025 MLX5_QPC_STATE_ERR = 0x6, 3026 MLX5_QPC_STATE_SQD = 0x7, 3027 MLX5_QPC_STATE_SUSPENDED = 0x9, 3028 }; 3029 3030 enum { 3031 MLX5_QPC_ST_RC = 0x0, 3032 MLX5_QPC_ST_UC = 0x1, 3033 MLX5_QPC_ST_UD = 0x2, 3034 MLX5_QPC_ST_XRC = 0x3, 3035 MLX5_QPC_ST_DCI = 0x5, 3036 MLX5_QPC_ST_QP0 = 0x7, 3037 MLX5_QPC_ST_QP1 = 0x8, 3038 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3039 MLX5_QPC_ST_REG_UMR = 0xc, 3040 }; 3041 3042 enum { 3043 MLX5_QPC_PM_STATE_ARMED = 0x0, 3044 MLX5_QPC_PM_STATE_REARM = 0x1, 3045 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3046 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3047 }; 3048 3049 enum { 3050 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3051 }; 3052 3053 enum { 3054 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3055 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3056 }; 3057 3058 enum { 3059 MLX5_QPC_MTU_256_BYTES = 0x1, 3060 MLX5_QPC_MTU_512_BYTES = 0x2, 3061 MLX5_QPC_MTU_1K_BYTES = 0x3, 3062 MLX5_QPC_MTU_2K_BYTES = 0x4, 3063 MLX5_QPC_MTU_4K_BYTES = 0x5, 3064 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3065 }; 3066 3067 enum { 3068 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3069 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3070 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3071 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3072 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3073 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3074 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3075 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3076 }; 3077 3078 enum { 3079 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3080 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3081 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3082 }; 3083 3084 enum { 3085 MLX5_QPC_CS_RES_DISABLE = 0x0, 3086 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3087 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3088 }; 3089 3090 enum { 3091 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3092 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3093 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3094 }; 3095 3096 struct mlx5_ifc_qpc_bits { 3097 u8 state[0x4]; 3098 u8 lag_tx_port_affinity[0x4]; 3099 u8 st[0x8]; 3100 u8 reserved_at_10[0x2]; 3101 u8 isolate_vl_tc[0x1]; 3102 u8 pm_state[0x2]; 3103 u8 reserved_at_15[0x1]; 3104 u8 req_e2e_credit_mode[0x2]; 3105 u8 offload_type[0x4]; 3106 u8 end_padding_mode[0x2]; 3107 u8 reserved_at_1e[0x2]; 3108 3109 u8 wq_signature[0x1]; 3110 u8 block_lb_mc[0x1]; 3111 u8 atomic_like_write_en[0x1]; 3112 u8 latency_sensitive[0x1]; 3113 u8 reserved_at_24[0x1]; 3114 u8 drain_sigerr[0x1]; 3115 u8 reserved_at_26[0x2]; 3116 u8 pd[0x18]; 3117 3118 u8 mtu[0x3]; 3119 u8 log_msg_max[0x5]; 3120 u8 reserved_at_48[0x1]; 3121 u8 log_rq_size[0x4]; 3122 u8 log_rq_stride[0x3]; 3123 u8 no_sq[0x1]; 3124 u8 log_sq_size[0x4]; 3125 u8 reserved_at_55[0x3]; 3126 u8 ts_format[0x2]; 3127 u8 reserved_at_5a[0x1]; 3128 u8 rlky[0x1]; 3129 u8 ulp_stateless_offload_mode[0x4]; 3130 3131 u8 counter_set_id[0x8]; 3132 u8 uar_page[0x18]; 3133 3134 u8 reserved_at_80[0x8]; 3135 u8 user_index[0x18]; 3136 3137 u8 reserved_at_a0[0x3]; 3138 u8 log_page_size[0x5]; 3139 u8 remote_qpn[0x18]; 3140 3141 struct mlx5_ifc_ads_bits primary_address_path; 3142 3143 struct mlx5_ifc_ads_bits secondary_address_path; 3144 3145 u8 log_ack_req_freq[0x4]; 3146 u8 reserved_at_384[0x4]; 3147 u8 log_sra_max[0x3]; 3148 u8 reserved_at_38b[0x2]; 3149 u8 retry_count[0x3]; 3150 u8 rnr_retry[0x3]; 3151 u8 reserved_at_393[0x1]; 3152 u8 fre[0x1]; 3153 u8 cur_rnr_retry[0x3]; 3154 u8 cur_retry_count[0x3]; 3155 u8 reserved_at_39b[0x5]; 3156 3157 u8 reserved_at_3a0[0x20]; 3158 3159 u8 reserved_at_3c0[0x8]; 3160 u8 next_send_psn[0x18]; 3161 3162 u8 reserved_at_3e0[0x3]; 3163 u8 log_num_dci_stream_channels[0x5]; 3164 u8 cqn_snd[0x18]; 3165 3166 u8 reserved_at_400[0x3]; 3167 u8 log_num_dci_errored_streams[0x5]; 3168 u8 deth_sqpn[0x18]; 3169 3170 u8 reserved_at_420[0x20]; 3171 3172 u8 reserved_at_440[0x8]; 3173 u8 last_acked_psn[0x18]; 3174 3175 u8 reserved_at_460[0x8]; 3176 u8 ssn[0x18]; 3177 3178 u8 reserved_at_480[0x8]; 3179 u8 log_rra_max[0x3]; 3180 u8 reserved_at_48b[0x1]; 3181 u8 atomic_mode[0x4]; 3182 u8 rre[0x1]; 3183 u8 rwe[0x1]; 3184 u8 rae[0x1]; 3185 u8 reserved_at_493[0x1]; 3186 u8 page_offset[0x6]; 3187 u8 reserved_at_49a[0x3]; 3188 u8 cd_slave_receive[0x1]; 3189 u8 cd_slave_send[0x1]; 3190 u8 cd_master[0x1]; 3191 3192 u8 reserved_at_4a0[0x3]; 3193 u8 min_rnr_nak[0x5]; 3194 u8 next_rcv_psn[0x18]; 3195 3196 u8 reserved_at_4c0[0x8]; 3197 u8 xrcd[0x18]; 3198 3199 u8 reserved_at_4e0[0x8]; 3200 u8 cqn_rcv[0x18]; 3201 3202 u8 dbr_addr[0x40]; 3203 3204 u8 q_key[0x20]; 3205 3206 u8 reserved_at_560[0x5]; 3207 u8 rq_type[0x3]; 3208 u8 srqn_rmpn_xrqn[0x18]; 3209 3210 u8 reserved_at_580[0x8]; 3211 u8 rmsn[0x18]; 3212 3213 u8 hw_sq_wqebb_counter[0x10]; 3214 u8 sw_sq_wqebb_counter[0x10]; 3215 3216 u8 hw_rq_counter[0x20]; 3217 3218 u8 sw_rq_counter[0x20]; 3219 3220 u8 reserved_at_600[0x20]; 3221 3222 u8 reserved_at_620[0xf]; 3223 u8 cgs[0x1]; 3224 u8 cs_req[0x8]; 3225 u8 cs_res[0x8]; 3226 3227 u8 dc_access_key[0x40]; 3228 3229 u8 reserved_at_680[0x3]; 3230 u8 dbr_umem_valid[0x1]; 3231 3232 u8 reserved_at_684[0xbc]; 3233 }; 3234 3235 struct mlx5_ifc_roce_addr_layout_bits { 3236 u8 source_l3_address[16][0x8]; 3237 3238 u8 reserved_at_80[0x3]; 3239 u8 vlan_valid[0x1]; 3240 u8 vlan_id[0xc]; 3241 u8 source_mac_47_32[0x10]; 3242 3243 u8 source_mac_31_0[0x20]; 3244 3245 u8 reserved_at_c0[0x14]; 3246 u8 roce_l3_type[0x4]; 3247 u8 roce_version[0x8]; 3248 3249 u8 reserved_at_e0[0x20]; 3250 }; 3251 3252 struct mlx5_ifc_shampo_cap_bits { 3253 u8 reserved_at_0[0x3]; 3254 u8 shampo_log_max_reservation_size[0x5]; 3255 u8 reserved_at_8[0x3]; 3256 u8 shampo_log_min_reservation_size[0x5]; 3257 u8 shampo_min_mss_size[0x10]; 3258 3259 u8 reserved_at_20[0x3]; 3260 u8 shampo_max_log_headers_entry_size[0x5]; 3261 u8 reserved_at_28[0x18]; 3262 3263 u8 reserved_at_40[0x7c0]; 3264 }; 3265 3266 union mlx5_ifc_hca_cap_union_bits { 3267 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3268 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3269 struct mlx5_ifc_odp_cap_bits odp_cap; 3270 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3271 struct mlx5_ifc_roce_cap_bits roce_cap; 3272 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3273 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3274 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3275 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3276 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3277 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3278 struct mlx5_ifc_qos_cap_bits qos_cap; 3279 struct mlx5_ifc_debug_cap_bits debug_cap; 3280 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3281 struct mlx5_ifc_tls_cap_bits tls_cap; 3282 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3283 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3284 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3285 u8 reserved_at_0[0x8000]; 3286 }; 3287 3288 enum { 3289 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3290 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3291 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3292 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3293 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3294 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3295 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3296 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3297 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3298 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3299 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3300 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3301 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3302 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3303 }; 3304 3305 enum { 3306 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3307 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3308 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3309 }; 3310 3311 struct mlx5_ifc_vlan_bits { 3312 u8 ethtype[0x10]; 3313 u8 prio[0x3]; 3314 u8 cfi[0x1]; 3315 u8 vid[0xc]; 3316 }; 3317 3318 enum { 3319 MLX5_FLOW_METER_COLOR_RED = 0x0, 3320 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3321 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3322 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3323 }; 3324 3325 enum { 3326 MLX5_EXE_ASO_FLOW_METER = 0x2, 3327 }; 3328 3329 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3330 u8 return_reg_id[0x4]; 3331 u8 aso_type[0x4]; 3332 u8 reserved_at_8[0x14]; 3333 u8 action[0x1]; 3334 u8 init_color[0x2]; 3335 u8 meter_id[0x1]; 3336 }; 3337 3338 union mlx5_ifc_exe_aso_ctrl { 3339 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3340 }; 3341 3342 struct mlx5_ifc_execute_aso_bits { 3343 u8 valid[0x1]; 3344 u8 reserved_at_1[0x7]; 3345 u8 aso_object_id[0x18]; 3346 3347 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3348 }; 3349 3350 struct mlx5_ifc_flow_context_bits { 3351 struct mlx5_ifc_vlan_bits push_vlan; 3352 3353 u8 group_id[0x20]; 3354 3355 u8 reserved_at_40[0x8]; 3356 u8 flow_tag[0x18]; 3357 3358 u8 reserved_at_60[0x10]; 3359 u8 action[0x10]; 3360 3361 u8 extended_destination[0x1]; 3362 u8 reserved_at_81[0x1]; 3363 u8 flow_source[0x2]; 3364 u8 reserved_at_84[0x4]; 3365 u8 destination_list_size[0x18]; 3366 3367 u8 reserved_at_a0[0x8]; 3368 u8 flow_counter_list_size[0x18]; 3369 3370 u8 packet_reformat_id[0x20]; 3371 3372 u8 modify_header_id[0x20]; 3373 3374 struct mlx5_ifc_vlan_bits push_vlan_2; 3375 3376 u8 ipsec_obj_id[0x20]; 3377 u8 reserved_at_140[0xc0]; 3378 3379 struct mlx5_ifc_fte_match_param_bits match_value; 3380 3381 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3382 3383 u8 reserved_at_1300[0x500]; 3384 3385 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3386 }; 3387 3388 enum { 3389 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3390 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3391 }; 3392 3393 struct mlx5_ifc_xrc_srqc_bits { 3394 u8 state[0x4]; 3395 u8 log_xrc_srq_size[0x4]; 3396 u8 reserved_at_8[0x18]; 3397 3398 u8 wq_signature[0x1]; 3399 u8 cont_srq[0x1]; 3400 u8 reserved_at_22[0x1]; 3401 u8 rlky[0x1]; 3402 u8 basic_cyclic_rcv_wqe[0x1]; 3403 u8 log_rq_stride[0x3]; 3404 u8 xrcd[0x18]; 3405 3406 u8 page_offset[0x6]; 3407 u8 reserved_at_46[0x1]; 3408 u8 dbr_umem_valid[0x1]; 3409 u8 cqn[0x18]; 3410 3411 u8 reserved_at_60[0x20]; 3412 3413 u8 user_index_equal_xrc_srqn[0x1]; 3414 u8 reserved_at_81[0x1]; 3415 u8 log_page_size[0x6]; 3416 u8 user_index[0x18]; 3417 3418 u8 reserved_at_a0[0x20]; 3419 3420 u8 reserved_at_c0[0x8]; 3421 u8 pd[0x18]; 3422 3423 u8 lwm[0x10]; 3424 u8 wqe_cnt[0x10]; 3425 3426 u8 reserved_at_100[0x40]; 3427 3428 u8 db_record_addr_h[0x20]; 3429 3430 u8 db_record_addr_l[0x1e]; 3431 u8 reserved_at_17e[0x2]; 3432 3433 u8 reserved_at_180[0x80]; 3434 }; 3435 3436 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3437 u8 counter_error_queues[0x20]; 3438 3439 u8 total_error_queues[0x20]; 3440 3441 u8 send_queue_priority_update_flow[0x20]; 3442 3443 u8 reserved_at_60[0x20]; 3444 3445 u8 nic_receive_steering_discard[0x40]; 3446 3447 u8 receive_discard_vport_down[0x40]; 3448 3449 u8 transmit_discard_vport_down[0x40]; 3450 3451 u8 async_eq_overrun[0x20]; 3452 3453 u8 comp_eq_overrun[0x20]; 3454 3455 u8 reserved_at_180[0x20]; 3456 3457 u8 invalid_command[0x20]; 3458 3459 u8 quota_exceeded_command[0x20]; 3460 3461 u8 internal_rq_out_of_buffer[0x20]; 3462 3463 u8 cq_overrun[0x20]; 3464 3465 u8 reserved_at_220[0xde0]; 3466 }; 3467 3468 struct mlx5_ifc_traffic_counter_bits { 3469 u8 packets[0x40]; 3470 3471 u8 octets[0x40]; 3472 }; 3473 3474 struct mlx5_ifc_tisc_bits { 3475 u8 strict_lag_tx_port_affinity[0x1]; 3476 u8 tls_en[0x1]; 3477 u8 reserved_at_2[0x2]; 3478 u8 lag_tx_port_affinity[0x04]; 3479 3480 u8 reserved_at_8[0x4]; 3481 u8 prio[0x4]; 3482 u8 reserved_at_10[0x10]; 3483 3484 u8 reserved_at_20[0x100]; 3485 3486 u8 reserved_at_120[0x8]; 3487 u8 transport_domain[0x18]; 3488 3489 u8 reserved_at_140[0x8]; 3490 u8 underlay_qpn[0x18]; 3491 3492 u8 reserved_at_160[0x8]; 3493 u8 pd[0x18]; 3494 3495 u8 reserved_at_180[0x380]; 3496 }; 3497 3498 enum { 3499 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3500 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3501 }; 3502 3503 enum { 3504 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3505 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3506 }; 3507 3508 enum { 3509 MLX5_RX_HASH_FN_NONE = 0x0, 3510 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3511 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3512 }; 3513 3514 enum { 3515 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3516 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3517 }; 3518 3519 struct mlx5_ifc_tirc_bits { 3520 u8 reserved_at_0[0x20]; 3521 3522 u8 disp_type[0x4]; 3523 u8 tls_en[0x1]; 3524 u8 reserved_at_25[0x1b]; 3525 3526 u8 reserved_at_40[0x40]; 3527 3528 u8 reserved_at_80[0x4]; 3529 u8 lro_timeout_period_usecs[0x10]; 3530 u8 packet_merge_mask[0x4]; 3531 u8 lro_max_ip_payload_size[0x8]; 3532 3533 u8 reserved_at_a0[0x40]; 3534 3535 u8 reserved_at_e0[0x8]; 3536 u8 inline_rqn[0x18]; 3537 3538 u8 rx_hash_symmetric[0x1]; 3539 u8 reserved_at_101[0x1]; 3540 u8 tunneled_offload_en[0x1]; 3541 u8 reserved_at_103[0x5]; 3542 u8 indirect_table[0x18]; 3543 3544 u8 rx_hash_fn[0x4]; 3545 u8 reserved_at_124[0x2]; 3546 u8 self_lb_block[0x2]; 3547 u8 transport_domain[0x18]; 3548 3549 u8 rx_hash_toeplitz_key[10][0x20]; 3550 3551 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3552 3553 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3554 3555 u8 reserved_at_2c0[0x4c0]; 3556 }; 3557 3558 enum { 3559 MLX5_SRQC_STATE_GOOD = 0x0, 3560 MLX5_SRQC_STATE_ERROR = 0x1, 3561 }; 3562 3563 struct mlx5_ifc_srqc_bits { 3564 u8 state[0x4]; 3565 u8 log_srq_size[0x4]; 3566 u8 reserved_at_8[0x18]; 3567 3568 u8 wq_signature[0x1]; 3569 u8 cont_srq[0x1]; 3570 u8 reserved_at_22[0x1]; 3571 u8 rlky[0x1]; 3572 u8 reserved_at_24[0x1]; 3573 u8 log_rq_stride[0x3]; 3574 u8 xrcd[0x18]; 3575 3576 u8 page_offset[0x6]; 3577 u8 reserved_at_46[0x2]; 3578 u8 cqn[0x18]; 3579 3580 u8 reserved_at_60[0x20]; 3581 3582 u8 reserved_at_80[0x2]; 3583 u8 log_page_size[0x6]; 3584 u8 reserved_at_88[0x18]; 3585 3586 u8 reserved_at_a0[0x20]; 3587 3588 u8 reserved_at_c0[0x8]; 3589 u8 pd[0x18]; 3590 3591 u8 lwm[0x10]; 3592 u8 wqe_cnt[0x10]; 3593 3594 u8 reserved_at_100[0x40]; 3595 3596 u8 dbr_addr[0x40]; 3597 3598 u8 reserved_at_180[0x80]; 3599 }; 3600 3601 enum { 3602 MLX5_SQC_STATE_RST = 0x0, 3603 MLX5_SQC_STATE_RDY = 0x1, 3604 MLX5_SQC_STATE_ERR = 0x3, 3605 }; 3606 3607 struct mlx5_ifc_sqc_bits { 3608 u8 rlky[0x1]; 3609 u8 cd_master[0x1]; 3610 u8 fre[0x1]; 3611 u8 flush_in_error_en[0x1]; 3612 u8 allow_multi_pkt_send_wqe[0x1]; 3613 u8 min_wqe_inline_mode[0x3]; 3614 u8 state[0x4]; 3615 u8 reg_umr[0x1]; 3616 u8 allow_swp[0x1]; 3617 u8 hairpin[0x1]; 3618 u8 reserved_at_f[0xb]; 3619 u8 ts_format[0x2]; 3620 u8 reserved_at_1c[0x4]; 3621 3622 u8 reserved_at_20[0x8]; 3623 u8 user_index[0x18]; 3624 3625 u8 reserved_at_40[0x8]; 3626 u8 cqn[0x18]; 3627 3628 u8 reserved_at_60[0x8]; 3629 u8 hairpin_peer_rq[0x18]; 3630 3631 u8 reserved_at_80[0x10]; 3632 u8 hairpin_peer_vhca[0x10]; 3633 3634 u8 reserved_at_a0[0x20]; 3635 3636 u8 reserved_at_c0[0x8]; 3637 u8 ts_cqe_to_dest_cqn[0x18]; 3638 3639 u8 reserved_at_e0[0x10]; 3640 u8 packet_pacing_rate_limit_index[0x10]; 3641 u8 tis_lst_sz[0x10]; 3642 u8 qos_queue_group_id[0x10]; 3643 3644 u8 reserved_at_120[0x40]; 3645 3646 u8 reserved_at_160[0x8]; 3647 u8 tis_num_0[0x18]; 3648 3649 struct mlx5_ifc_wq_bits wq; 3650 }; 3651 3652 enum { 3653 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3654 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3655 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3656 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3657 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3658 }; 3659 3660 enum { 3661 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3662 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3663 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3664 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3665 }; 3666 3667 struct mlx5_ifc_scheduling_context_bits { 3668 u8 element_type[0x8]; 3669 u8 reserved_at_8[0x18]; 3670 3671 u8 element_attributes[0x20]; 3672 3673 u8 parent_element_id[0x20]; 3674 3675 u8 reserved_at_60[0x40]; 3676 3677 u8 bw_share[0x20]; 3678 3679 u8 max_average_bw[0x20]; 3680 3681 u8 reserved_at_e0[0x120]; 3682 }; 3683 3684 struct mlx5_ifc_rqtc_bits { 3685 u8 reserved_at_0[0xa0]; 3686 3687 u8 reserved_at_a0[0x5]; 3688 u8 list_q_type[0x3]; 3689 u8 reserved_at_a8[0x8]; 3690 u8 rqt_max_size[0x10]; 3691 3692 u8 rq_vhca_id_format[0x1]; 3693 u8 reserved_at_c1[0xf]; 3694 u8 rqt_actual_size[0x10]; 3695 3696 u8 reserved_at_e0[0x6a0]; 3697 3698 struct mlx5_ifc_rq_num_bits rq_num[]; 3699 }; 3700 3701 enum { 3702 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3703 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3704 }; 3705 3706 enum { 3707 MLX5_RQC_STATE_RST = 0x0, 3708 MLX5_RQC_STATE_RDY = 0x1, 3709 MLX5_RQC_STATE_ERR = 0x3, 3710 }; 3711 3712 enum { 3713 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3714 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3715 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3716 }; 3717 3718 enum { 3719 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3720 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3721 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3722 }; 3723 3724 struct mlx5_ifc_rqc_bits { 3725 u8 rlky[0x1]; 3726 u8 delay_drop_en[0x1]; 3727 u8 scatter_fcs[0x1]; 3728 u8 vsd[0x1]; 3729 u8 mem_rq_type[0x4]; 3730 u8 state[0x4]; 3731 u8 reserved_at_c[0x1]; 3732 u8 flush_in_error_en[0x1]; 3733 u8 hairpin[0x1]; 3734 u8 reserved_at_f[0xb]; 3735 u8 ts_format[0x2]; 3736 u8 reserved_at_1c[0x4]; 3737 3738 u8 reserved_at_20[0x8]; 3739 u8 user_index[0x18]; 3740 3741 u8 reserved_at_40[0x8]; 3742 u8 cqn[0x18]; 3743 3744 u8 counter_set_id[0x8]; 3745 u8 reserved_at_68[0x18]; 3746 3747 u8 reserved_at_80[0x8]; 3748 u8 rmpn[0x18]; 3749 3750 u8 reserved_at_a0[0x8]; 3751 u8 hairpin_peer_sq[0x18]; 3752 3753 u8 reserved_at_c0[0x10]; 3754 u8 hairpin_peer_vhca[0x10]; 3755 3756 u8 reserved_at_e0[0x46]; 3757 u8 shampo_no_match_alignment_granularity[0x2]; 3758 u8 reserved_at_128[0x6]; 3759 u8 shampo_match_criteria_type[0x2]; 3760 u8 reservation_timeout[0x10]; 3761 3762 u8 reserved_at_140[0x40]; 3763 3764 struct mlx5_ifc_wq_bits wq; 3765 }; 3766 3767 enum { 3768 MLX5_RMPC_STATE_RDY = 0x1, 3769 MLX5_RMPC_STATE_ERR = 0x3, 3770 }; 3771 3772 struct mlx5_ifc_rmpc_bits { 3773 u8 reserved_at_0[0x8]; 3774 u8 state[0x4]; 3775 u8 reserved_at_c[0x14]; 3776 3777 u8 basic_cyclic_rcv_wqe[0x1]; 3778 u8 reserved_at_21[0x1f]; 3779 3780 u8 reserved_at_40[0x140]; 3781 3782 struct mlx5_ifc_wq_bits wq; 3783 }; 3784 3785 struct mlx5_ifc_nic_vport_context_bits { 3786 u8 reserved_at_0[0x5]; 3787 u8 min_wqe_inline_mode[0x3]; 3788 u8 reserved_at_8[0x15]; 3789 u8 disable_mc_local_lb[0x1]; 3790 u8 disable_uc_local_lb[0x1]; 3791 u8 roce_en[0x1]; 3792 3793 u8 arm_change_event[0x1]; 3794 u8 reserved_at_21[0x1a]; 3795 u8 event_on_mtu[0x1]; 3796 u8 event_on_promisc_change[0x1]; 3797 u8 event_on_vlan_change[0x1]; 3798 u8 event_on_mc_address_change[0x1]; 3799 u8 event_on_uc_address_change[0x1]; 3800 3801 u8 reserved_at_40[0xc]; 3802 3803 u8 affiliation_criteria[0x4]; 3804 u8 affiliated_vhca_id[0x10]; 3805 3806 u8 reserved_at_60[0xd0]; 3807 3808 u8 mtu[0x10]; 3809 3810 u8 system_image_guid[0x40]; 3811 u8 port_guid[0x40]; 3812 u8 node_guid[0x40]; 3813 3814 u8 reserved_at_200[0x140]; 3815 u8 qkey_violation_counter[0x10]; 3816 u8 reserved_at_350[0x430]; 3817 3818 u8 promisc_uc[0x1]; 3819 u8 promisc_mc[0x1]; 3820 u8 promisc_all[0x1]; 3821 u8 reserved_at_783[0x2]; 3822 u8 allowed_list_type[0x3]; 3823 u8 reserved_at_788[0xc]; 3824 u8 allowed_list_size[0xc]; 3825 3826 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3827 3828 u8 reserved_at_7e0[0x20]; 3829 3830 u8 current_uc_mac_address[][0x40]; 3831 }; 3832 3833 enum { 3834 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3835 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3836 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3837 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3838 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3839 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3840 }; 3841 3842 struct mlx5_ifc_mkc_bits { 3843 u8 reserved_at_0[0x1]; 3844 u8 free[0x1]; 3845 u8 reserved_at_2[0x1]; 3846 u8 access_mode_4_2[0x3]; 3847 u8 reserved_at_6[0x7]; 3848 u8 relaxed_ordering_write[0x1]; 3849 u8 reserved_at_e[0x1]; 3850 u8 small_fence_on_rdma_read_response[0x1]; 3851 u8 umr_en[0x1]; 3852 u8 a[0x1]; 3853 u8 rw[0x1]; 3854 u8 rr[0x1]; 3855 u8 lw[0x1]; 3856 u8 lr[0x1]; 3857 u8 access_mode_1_0[0x2]; 3858 u8 reserved_at_18[0x8]; 3859 3860 u8 qpn[0x18]; 3861 u8 mkey_7_0[0x8]; 3862 3863 u8 reserved_at_40[0x20]; 3864 3865 u8 length64[0x1]; 3866 u8 bsf_en[0x1]; 3867 u8 sync_umr[0x1]; 3868 u8 reserved_at_63[0x2]; 3869 u8 expected_sigerr_count[0x1]; 3870 u8 reserved_at_66[0x1]; 3871 u8 en_rinval[0x1]; 3872 u8 pd[0x18]; 3873 3874 u8 start_addr[0x40]; 3875 3876 u8 len[0x40]; 3877 3878 u8 bsf_octword_size[0x20]; 3879 3880 u8 reserved_at_120[0x80]; 3881 3882 u8 translations_octword_size[0x20]; 3883 3884 u8 reserved_at_1c0[0x19]; 3885 u8 relaxed_ordering_read[0x1]; 3886 u8 reserved_at_1d9[0x1]; 3887 u8 log_page_size[0x5]; 3888 3889 u8 reserved_at_1e0[0x20]; 3890 }; 3891 3892 struct mlx5_ifc_pkey_bits { 3893 u8 reserved_at_0[0x10]; 3894 u8 pkey[0x10]; 3895 }; 3896 3897 struct mlx5_ifc_array128_auto_bits { 3898 u8 array128_auto[16][0x8]; 3899 }; 3900 3901 struct mlx5_ifc_hca_vport_context_bits { 3902 u8 field_select[0x20]; 3903 3904 u8 reserved_at_20[0xe0]; 3905 3906 u8 sm_virt_aware[0x1]; 3907 u8 has_smi[0x1]; 3908 u8 has_raw[0x1]; 3909 u8 grh_required[0x1]; 3910 u8 reserved_at_104[0xc]; 3911 u8 port_physical_state[0x4]; 3912 u8 vport_state_policy[0x4]; 3913 u8 port_state[0x4]; 3914 u8 vport_state[0x4]; 3915 3916 u8 reserved_at_120[0x20]; 3917 3918 u8 system_image_guid[0x40]; 3919 3920 u8 port_guid[0x40]; 3921 3922 u8 node_guid[0x40]; 3923 3924 u8 cap_mask1[0x20]; 3925 3926 u8 cap_mask1_field_select[0x20]; 3927 3928 u8 cap_mask2[0x20]; 3929 3930 u8 cap_mask2_field_select[0x20]; 3931 3932 u8 reserved_at_280[0x80]; 3933 3934 u8 lid[0x10]; 3935 u8 reserved_at_310[0x4]; 3936 u8 init_type_reply[0x4]; 3937 u8 lmc[0x3]; 3938 u8 subnet_timeout[0x5]; 3939 3940 u8 sm_lid[0x10]; 3941 u8 sm_sl[0x4]; 3942 u8 reserved_at_334[0xc]; 3943 3944 u8 qkey_violation_counter[0x10]; 3945 u8 pkey_violation_counter[0x10]; 3946 3947 u8 reserved_at_360[0xca0]; 3948 }; 3949 3950 struct mlx5_ifc_esw_vport_context_bits { 3951 u8 fdb_to_vport_reg_c[0x1]; 3952 u8 reserved_at_1[0x2]; 3953 u8 vport_svlan_strip[0x1]; 3954 u8 vport_cvlan_strip[0x1]; 3955 u8 vport_svlan_insert[0x1]; 3956 u8 vport_cvlan_insert[0x2]; 3957 u8 fdb_to_vport_reg_c_id[0x8]; 3958 u8 reserved_at_10[0x10]; 3959 3960 u8 reserved_at_20[0x20]; 3961 3962 u8 svlan_cfi[0x1]; 3963 u8 svlan_pcp[0x3]; 3964 u8 svlan_id[0xc]; 3965 u8 cvlan_cfi[0x1]; 3966 u8 cvlan_pcp[0x3]; 3967 u8 cvlan_id[0xc]; 3968 3969 u8 reserved_at_60[0x720]; 3970 3971 u8 sw_steering_vport_icm_address_rx[0x40]; 3972 3973 u8 sw_steering_vport_icm_address_tx[0x40]; 3974 }; 3975 3976 enum { 3977 MLX5_EQC_STATUS_OK = 0x0, 3978 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3979 }; 3980 3981 enum { 3982 MLX5_EQC_ST_ARMED = 0x9, 3983 MLX5_EQC_ST_FIRED = 0xa, 3984 }; 3985 3986 struct mlx5_ifc_eqc_bits { 3987 u8 status[0x4]; 3988 u8 reserved_at_4[0x9]; 3989 u8 ec[0x1]; 3990 u8 oi[0x1]; 3991 u8 reserved_at_f[0x5]; 3992 u8 st[0x4]; 3993 u8 reserved_at_18[0x8]; 3994 3995 u8 reserved_at_20[0x20]; 3996 3997 u8 reserved_at_40[0x14]; 3998 u8 page_offset[0x6]; 3999 u8 reserved_at_5a[0x6]; 4000 4001 u8 reserved_at_60[0x3]; 4002 u8 log_eq_size[0x5]; 4003 u8 uar_page[0x18]; 4004 4005 u8 reserved_at_80[0x20]; 4006 4007 u8 reserved_at_a0[0x14]; 4008 u8 intr[0xc]; 4009 4010 u8 reserved_at_c0[0x3]; 4011 u8 log_page_size[0x5]; 4012 u8 reserved_at_c8[0x18]; 4013 4014 u8 reserved_at_e0[0x60]; 4015 4016 u8 reserved_at_140[0x8]; 4017 u8 consumer_counter[0x18]; 4018 4019 u8 reserved_at_160[0x8]; 4020 u8 producer_counter[0x18]; 4021 4022 u8 reserved_at_180[0x80]; 4023 }; 4024 4025 enum { 4026 MLX5_DCTC_STATE_ACTIVE = 0x0, 4027 MLX5_DCTC_STATE_DRAINING = 0x1, 4028 MLX5_DCTC_STATE_DRAINED = 0x2, 4029 }; 4030 4031 enum { 4032 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4033 MLX5_DCTC_CS_RES_NA = 0x1, 4034 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4035 }; 4036 4037 enum { 4038 MLX5_DCTC_MTU_256_BYTES = 0x1, 4039 MLX5_DCTC_MTU_512_BYTES = 0x2, 4040 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4041 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4042 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4043 }; 4044 4045 struct mlx5_ifc_dctc_bits { 4046 u8 reserved_at_0[0x4]; 4047 u8 state[0x4]; 4048 u8 reserved_at_8[0x18]; 4049 4050 u8 reserved_at_20[0x8]; 4051 u8 user_index[0x18]; 4052 4053 u8 reserved_at_40[0x8]; 4054 u8 cqn[0x18]; 4055 4056 u8 counter_set_id[0x8]; 4057 u8 atomic_mode[0x4]; 4058 u8 rre[0x1]; 4059 u8 rwe[0x1]; 4060 u8 rae[0x1]; 4061 u8 atomic_like_write_en[0x1]; 4062 u8 latency_sensitive[0x1]; 4063 u8 rlky[0x1]; 4064 u8 free_ar[0x1]; 4065 u8 reserved_at_73[0xd]; 4066 4067 u8 reserved_at_80[0x8]; 4068 u8 cs_res[0x8]; 4069 u8 reserved_at_90[0x3]; 4070 u8 min_rnr_nak[0x5]; 4071 u8 reserved_at_98[0x8]; 4072 4073 u8 reserved_at_a0[0x8]; 4074 u8 srqn_xrqn[0x18]; 4075 4076 u8 reserved_at_c0[0x8]; 4077 u8 pd[0x18]; 4078 4079 u8 tclass[0x8]; 4080 u8 reserved_at_e8[0x4]; 4081 u8 flow_label[0x14]; 4082 4083 u8 dc_access_key[0x40]; 4084 4085 u8 reserved_at_140[0x5]; 4086 u8 mtu[0x3]; 4087 u8 port[0x8]; 4088 u8 pkey_index[0x10]; 4089 4090 u8 reserved_at_160[0x8]; 4091 u8 my_addr_index[0x8]; 4092 u8 reserved_at_170[0x8]; 4093 u8 hop_limit[0x8]; 4094 4095 u8 dc_access_key_violation_count[0x20]; 4096 4097 u8 reserved_at_1a0[0x14]; 4098 u8 dei_cfi[0x1]; 4099 u8 eth_prio[0x3]; 4100 u8 ecn[0x2]; 4101 u8 dscp[0x6]; 4102 4103 u8 reserved_at_1c0[0x20]; 4104 u8 ece[0x20]; 4105 }; 4106 4107 enum { 4108 MLX5_CQC_STATUS_OK = 0x0, 4109 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4110 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4111 }; 4112 4113 enum { 4114 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4115 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4116 }; 4117 4118 enum { 4119 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4120 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4121 MLX5_CQC_ST_FIRED = 0xa, 4122 }; 4123 4124 enum { 4125 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4126 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4127 MLX5_CQ_PERIOD_NUM_MODES 4128 }; 4129 4130 struct mlx5_ifc_cqc_bits { 4131 u8 status[0x4]; 4132 u8 reserved_at_4[0x2]; 4133 u8 dbr_umem_valid[0x1]; 4134 u8 apu_cq[0x1]; 4135 u8 cqe_sz[0x3]; 4136 u8 cc[0x1]; 4137 u8 reserved_at_c[0x1]; 4138 u8 scqe_break_moderation_en[0x1]; 4139 u8 oi[0x1]; 4140 u8 cq_period_mode[0x2]; 4141 u8 cqe_comp_en[0x1]; 4142 u8 mini_cqe_res_format[0x2]; 4143 u8 st[0x4]; 4144 u8 reserved_at_18[0x6]; 4145 u8 cqe_compression_layout[0x2]; 4146 4147 u8 reserved_at_20[0x20]; 4148 4149 u8 reserved_at_40[0x14]; 4150 u8 page_offset[0x6]; 4151 u8 reserved_at_5a[0x6]; 4152 4153 u8 reserved_at_60[0x3]; 4154 u8 log_cq_size[0x5]; 4155 u8 uar_page[0x18]; 4156 4157 u8 reserved_at_80[0x4]; 4158 u8 cq_period[0xc]; 4159 u8 cq_max_count[0x10]; 4160 4161 u8 c_eqn_or_apu_element[0x20]; 4162 4163 u8 reserved_at_c0[0x3]; 4164 u8 log_page_size[0x5]; 4165 u8 reserved_at_c8[0x18]; 4166 4167 u8 reserved_at_e0[0x20]; 4168 4169 u8 reserved_at_100[0x8]; 4170 u8 last_notified_index[0x18]; 4171 4172 u8 reserved_at_120[0x8]; 4173 u8 last_solicit_index[0x18]; 4174 4175 u8 reserved_at_140[0x8]; 4176 u8 consumer_counter[0x18]; 4177 4178 u8 reserved_at_160[0x8]; 4179 u8 producer_counter[0x18]; 4180 4181 u8 reserved_at_180[0x40]; 4182 4183 u8 dbr_addr[0x40]; 4184 }; 4185 4186 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4187 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4188 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4189 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4190 u8 reserved_at_0[0x800]; 4191 }; 4192 4193 struct mlx5_ifc_query_adapter_param_block_bits { 4194 u8 reserved_at_0[0xc0]; 4195 4196 u8 reserved_at_c0[0x8]; 4197 u8 ieee_vendor_id[0x18]; 4198 4199 u8 reserved_at_e0[0x10]; 4200 u8 vsd_vendor_id[0x10]; 4201 4202 u8 vsd[208][0x8]; 4203 4204 u8 vsd_contd_psid[16][0x8]; 4205 }; 4206 4207 enum { 4208 MLX5_XRQC_STATE_GOOD = 0x0, 4209 MLX5_XRQC_STATE_ERROR = 0x1, 4210 }; 4211 4212 enum { 4213 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4214 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4215 }; 4216 4217 enum { 4218 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4219 }; 4220 4221 struct mlx5_ifc_tag_matching_topology_context_bits { 4222 u8 log_matching_list_sz[0x4]; 4223 u8 reserved_at_4[0xc]; 4224 u8 append_next_index[0x10]; 4225 4226 u8 sw_phase_cnt[0x10]; 4227 u8 hw_phase_cnt[0x10]; 4228 4229 u8 reserved_at_40[0x40]; 4230 }; 4231 4232 struct mlx5_ifc_xrqc_bits { 4233 u8 state[0x4]; 4234 u8 rlkey[0x1]; 4235 u8 reserved_at_5[0xf]; 4236 u8 topology[0x4]; 4237 u8 reserved_at_18[0x4]; 4238 u8 offload[0x4]; 4239 4240 u8 reserved_at_20[0x8]; 4241 u8 user_index[0x18]; 4242 4243 u8 reserved_at_40[0x8]; 4244 u8 cqn[0x18]; 4245 4246 u8 reserved_at_60[0xa0]; 4247 4248 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4249 4250 u8 reserved_at_180[0x280]; 4251 4252 struct mlx5_ifc_wq_bits wq; 4253 }; 4254 4255 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4256 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4257 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4258 u8 reserved_at_0[0x20]; 4259 }; 4260 4261 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4262 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4263 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4264 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4265 u8 reserved_at_0[0x20]; 4266 }; 4267 4268 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4269 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4270 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4271 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4272 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4273 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4274 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4275 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4276 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4277 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4278 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4279 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4280 u8 reserved_at_0[0x7c0]; 4281 }; 4282 4283 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4284 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4285 u8 reserved_at_0[0x7c0]; 4286 }; 4287 4288 union mlx5_ifc_event_auto_bits { 4289 struct mlx5_ifc_comp_event_bits comp_event; 4290 struct mlx5_ifc_dct_events_bits dct_events; 4291 struct mlx5_ifc_qp_events_bits qp_events; 4292 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4293 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4294 struct mlx5_ifc_cq_error_bits cq_error; 4295 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4296 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4297 struct mlx5_ifc_gpio_event_bits gpio_event; 4298 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4299 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4300 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4301 u8 reserved_at_0[0xe0]; 4302 }; 4303 4304 struct mlx5_ifc_health_buffer_bits { 4305 u8 reserved_at_0[0x100]; 4306 4307 u8 assert_existptr[0x20]; 4308 4309 u8 assert_callra[0x20]; 4310 4311 u8 reserved_at_140[0x20]; 4312 4313 u8 time[0x20]; 4314 4315 u8 fw_version[0x20]; 4316 4317 u8 hw_id[0x20]; 4318 4319 u8 rfr[0x1]; 4320 u8 reserved_at_1c1[0x3]; 4321 u8 valid[0x1]; 4322 u8 severity[0x3]; 4323 u8 reserved_at_1c8[0x18]; 4324 4325 u8 irisc_index[0x8]; 4326 u8 synd[0x8]; 4327 u8 ext_synd[0x10]; 4328 }; 4329 4330 struct mlx5_ifc_register_loopback_control_bits { 4331 u8 no_lb[0x1]; 4332 u8 reserved_at_1[0x7]; 4333 u8 port[0x8]; 4334 u8 reserved_at_10[0x10]; 4335 4336 u8 reserved_at_20[0x60]; 4337 }; 4338 4339 struct mlx5_ifc_vport_tc_element_bits { 4340 u8 traffic_class[0x4]; 4341 u8 reserved_at_4[0xc]; 4342 u8 vport_number[0x10]; 4343 }; 4344 4345 struct mlx5_ifc_vport_element_bits { 4346 u8 reserved_at_0[0x10]; 4347 u8 vport_number[0x10]; 4348 }; 4349 4350 enum { 4351 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4352 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4353 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4354 }; 4355 4356 struct mlx5_ifc_tsar_element_bits { 4357 u8 reserved_at_0[0x8]; 4358 u8 tsar_type[0x8]; 4359 u8 reserved_at_10[0x10]; 4360 }; 4361 4362 enum { 4363 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4364 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4365 }; 4366 4367 struct mlx5_ifc_teardown_hca_out_bits { 4368 u8 status[0x8]; 4369 u8 reserved_at_8[0x18]; 4370 4371 u8 syndrome[0x20]; 4372 4373 u8 reserved_at_40[0x3f]; 4374 4375 u8 state[0x1]; 4376 }; 4377 4378 enum { 4379 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4380 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4381 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4382 }; 4383 4384 struct mlx5_ifc_teardown_hca_in_bits { 4385 u8 opcode[0x10]; 4386 u8 reserved_at_10[0x10]; 4387 4388 u8 reserved_at_20[0x10]; 4389 u8 op_mod[0x10]; 4390 4391 u8 reserved_at_40[0x10]; 4392 u8 profile[0x10]; 4393 4394 u8 reserved_at_60[0x20]; 4395 }; 4396 4397 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4398 u8 status[0x8]; 4399 u8 reserved_at_8[0x18]; 4400 4401 u8 syndrome[0x20]; 4402 4403 u8 reserved_at_40[0x40]; 4404 }; 4405 4406 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4407 u8 opcode[0x10]; 4408 u8 uid[0x10]; 4409 4410 u8 reserved_at_20[0x10]; 4411 u8 op_mod[0x10]; 4412 4413 u8 reserved_at_40[0x8]; 4414 u8 qpn[0x18]; 4415 4416 u8 reserved_at_60[0x20]; 4417 4418 u8 opt_param_mask[0x20]; 4419 4420 u8 reserved_at_a0[0x20]; 4421 4422 struct mlx5_ifc_qpc_bits qpc; 4423 4424 u8 reserved_at_800[0x80]; 4425 }; 4426 4427 struct mlx5_ifc_sqd2rts_qp_out_bits { 4428 u8 status[0x8]; 4429 u8 reserved_at_8[0x18]; 4430 4431 u8 syndrome[0x20]; 4432 4433 u8 reserved_at_40[0x40]; 4434 }; 4435 4436 struct mlx5_ifc_sqd2rts_qp_in_bits { 4437 u8 opcode[0x10]; 4438 u8 uid[0x10]; 4439 4440 u8 reserved_at_20[0x10]; 4441 u8 op_mod[0x10]; 4442 4443 u8 reserved_at_40[0x8]; 4444 u8 qpn[0x18]; 4445 4446 u8 reserved_at_60[0x20]; 4447 4448 u8 opt_param_mask[0x20]; 4449 4450 u8 reserved_at_a0[0x20]; 4451 4452 struct mlx5_ifc_qpc_bits qpc; 4453 4454 u8 reserved_at_800[0x80]; 4455 }; 4456 4457 struct mlx5_ifc_set_roce_address_out_bits { 4458 u8 status[0x8]; 4459 u8 reserved_at_8[0x18]; 4460 4461 u8 syndrome[0x20]; 4462 4463 u8 reserved_at_40[0x40]; 4464 }; 4465 4466 struct mlx5_ifc_set_roce_address_in_bits { 4467 u8 opcode[0x10]; 4468 u8 reserved_at_10[0x10]; 4469 4470 u8 reserved_at_20[0x10]; 4471 u8 op_mod[0x10]; 4472 4473 u8 roce_address_index[0x10]; 4474 u8 reserved_at_50[0xc]; 4475 u8 vhca_port_num[0x4]; 4476 4477 u8 reserved_at_60[0x20]; 4478 4479 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4480 }; 4481 4482 struct mlx5_ifc_set_mad_demux_out_bits { 4483 u8 status[0x8]; 4484 u8 reserved_at_8[0x18]; 4485 4486 u8 syndrome[0x20]; 4487 4488 u8 reserved_at_40[0x40]; 4489 }; 4490 4491 enum { 4492 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4493 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4494 }; 4495 4496 struct mlx5_ifc_set_mad_demux_in_bits { 4497 u8 opcode[0x10]; 4498 u8 reserved_at_10[0x10]; 4499 4500 u8 reserved_at_20[0x10]; 4501 u8 op_mod[0x10]; 4502 4503 u8 reserved_at_40[0x20]; 4504 4505 u8 reserved_at_60[0x6]; 4506 u8 demux_mode[0x2]; 4507 u8 reserved_at_68[0x18]; 4508 }; 4509 4510 struct mlx5_ifc_set_l2_table_entry_out_bits { 4511 u8 status[0x8]; 4512 u8 reserved_at_8[0x18]; 4513 4514 u8 syndrome[0x20]; 4515 4516 u8 reserved_at_40[0x40]; 4517 }; 4518 4519 struct mlx5_ifc_set_l2_table_entry_in_bits { 4520 u8 opcode[0x10]; 4521 u8 reserved_at_10[0x10]; 4522 4523 u8 reserved_at_20[0x10]; 4524 u8 op_mod[0x10]; 4525 4526 u8 reserved_at_40[0x60]; 4527 4528 u8 reserved_at_a0[0x8]; 4529 u8 table_index[0x18]; 4530 4531 u8 reserved_at_c0[0x20]; 4532 4533 u8 reserved_at_e0[0x13]; 4534 u8 vlan_valid[0x1]; 4535 u8 vlan[0xc]; 4536 4537 struct mlx5_ifc_mac_address_layout_bits mac_address; 4538 4539 u8 reserved_at_140[0xc0]; 4540 }; 4541 4542 struct mlx5_ifc_set_issi_out_bits { 4543 u8 status[0x8]; 4544 u8 reserved_at_8[0x18]; 4545 4546 u8 syndrome[0x20]; 4547 4548 u8 reserved_at_40[0x40]; 4549 }; 4550 4551 struct mlx5_ifc_set_issi_in_bits { 4552 u8 opcode[0x10]; 4553 u8 reserved_at_10[0x10]; 4554 4555 u8 reserved_at_20[0x10]; 4556 u8 op_mod[0x10]; 4557 4558 u8 reserved_at_40[0x10]; 4559 u8 current_issi[0x10]; 4560 4561 u8 reserved_at_60[0x20]; 4562 }; 4563 4564 struct mlx5_ifc_set_hca_cap_out_bits { 4565 u8 status[0x8]; 4566 u8 reserved_at_8[0x18]; 4567 4568 u8 syndrome[0x20]; 4569 4570 u8 reserved_at_40[0x40]; 4571 }; 4572 4573 struct mlx5_ifc_set_hca_cap_in_bits { 4574 u8 opcode[0x10]; 4575 u8 reserved_at_10[0x10]; 4576 4577 u8 reserved_at_20[0x10]; 4578 u8 op_mod[0x10]; 4579 4580 u8 other_function[0x1]; 4581 u8 reserved_at_41[0xf]; 4582 u8 function_id[0x10]; 4583 4584 u8 reserved_at_60[0x20]; 4585 4586 union mlx5_ifc_hca_cap_union_bits capability; 4587 }; 4588 4589 enum { 4590 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4591 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4592 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4593 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4594 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4595 }; 4596 4597 struct mlx5_ifc_set_fte_out_bits { 4598 u8 status[0x8]; 4599 u8 reserved_at_8[0x18]; 4600 4601 u8 syndrome[0x20]; 4602 4603 u8 reserved_at_40[0x40]; 4604 }; 4605 4606 struct mlx5_ifc_set_fte_in_bits { 4607 u8 opcode[0x10]; 4608 u8 reserved_at_10[0x10]; 4609 4610 u8 reserved_at_20[0x10]; 4611 u8 op_mod[0x10]; 4612 4613 u8 other_vport[0x1]; 4614 u8 reserved_at_41[0xf]; 4615 u8 vport_number[0x10]; 4616 4617 u8 reserved_at_60[0x20]; 4618 4619 u8 table_type[0x8]; 4620 u8 reserved_at_88[0x18]; 4621 4622 u8 reserved_at_a0[0x8]; 4623 u8 table_id[0x18]; 4624 4625 u8 ignore_flow_level[0x1]; 4626 u8 reserved_at_c1[0x17]; 4627 u8 modify_enable_mask[0x8]; 4628 4629 u8 reserved_at_e0[0x20]; 4630 4631 u8 flow_index[0x20]; 4632 4633 u8 reserved_at_120[0xe0]; 4634 4635 struct mlx5_ifc_flow_context_bits flow_context; 4636 }; 4637 4638 struct mlx5_ifc_rts2rts_qp_out_bits { 4639 u8 status[0x8]; 4640 u8 reserved_at_8[0x18]; 4641 4642 u8 syndrome[0x20]; 4643 4644 u8 reserved_at_40[0x20]; 4645 u8 ece[0x20]; 4646 }; 4647 4648 struct mlx5_ifc_rts2rts_qp_in_bits { 4649 u8 opcode[0x10]; 4650 u8 uid[0x10]; 4651 4652 u8 reserved_at_20[0x10]; 4653 u8 op_mod[0x10]; 4654 4655 u8 reserved_at_40[0x8]; 4656 u8 qpn[0x18]; 4657 4658 u8 reserved_at_60[0x20]; 4659 4660 u8 opt_param_mask[0x20]; 4661 4662 u8 ece[0x20]; 4663 4664 struct mlx5_ifc_qpc_bits qpc; 4665 4666 u8 reserved_at_800[0x80]; 4667 }; 4668 4669 struct mlx5_ifc_rtr2rts_qp_out_bits { 4670 u8 status[0x8]; 4671 u8 reserved_at_8[0x18]; 4672 4673 u8 syndrome[0x20]; 4674 4675 u8 reserved_at_40[0x20]; 4676 u8 ece[0x20]; 4677 }; 4678 4679 struct mlx5_ifc_rtr2rts_qp_in_bits { 4680 u8 opcode[0x10]; 4681 u8 uid[0x10]; 4682 4683 u8 reserved_at_20[0x10]; 4684 u8 op_mod[0x10]; 4685 4686 u8 reserved_at_40[0x8]; 4687 u8 qpn[0x18]; 4688 4689 u8 reserved_at_60[0x20]; 4690 4691 u8 opt_param_mask[0x20]; 4692 4693 u8 ece[0x20]; 4694 4695 struct mlx5_ifc_qpc_bits qpc; 4696 4697 u8 reserved_at_800[0x80]; 4698 }; 4699 4700 struct mlx5_ifc_rst2init_qp_out_bits { 4701 u8 status[0x8]; 4702 u8 reserved_at_8[0x18]; 4703 4704 u8 syndrome[0x20]; 4705 4706 u8 reserved_at_40[0x20]; 4707 u8 ece[0x20]; 4708 }; 4709 4710 struct mlx5_ifc_rst2init_qp_in_bits { 4711 u8 opcode[0x10]; 4712 u8 uid[0x10]; 4713 4714 u8 reserved_at_20[0x10]; 4715 u8 op_mod[0x10]; 4716 4717 u8 reserved_at_40[0x8]; 4718 u8 qpn[0x18]; 4719 4720 u8 reserved_at_60[0x20]; 4721 4722 u8 opt_param_mask[0x20]; 4723 4724 u8 ece[0x20]; 4725 4726 struct mlx5_ifc_qpc_bits qpc; 4727 4728 u8 reserved_at_800[0x80]; 4729 }; 4730 4731 struct mlx5_ifc_query_xrq_out_bits { 4732 u8 status[0x8]; 4733 u8 reserved_at_8[0x18]; 4734 4735 u8 syndrome[0x20]; 4736 4737 u8 reserved_at_40[0x40]; 4738 4739 struct mlx5_ifc_xrqc_bits xrq_context; 4740 }; 4741 4742 struct mlx5_ifc_query_xrq_in_bits { 4743 u8 opcode[0x10]; 4744 u8 reserved_at_10[0x10]; 4745 4746 u8 reserved_at_20[0x10]; 4747 u8 op_mod[0x10]; 4748 4749 u8 reserved_at_40[0x8]; 4750 u8 xrqn[0x18]; 4751 4752 u8 reserved_at_60[0x20]; 4753 }; 4754 4755 struct mlx5_ifc_query_xrc_srq_out_bits { 4756 u8 status[0x8]; 4757 u8 reserved_at_8[0x18]; 4758 4759 u8 syndrome[0x20]; 4760 4761 u8 reserved_at_40[0x40]; 4762 4763 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4764 4765 u8 reserved_at_280[0x600]; 4766 4767 u8 pas[][0x40]; 4768 }; 4769 4770 struct mlx5_ifc_query_xrc_srq_in_bits { 4771 u8 opcode[0x10]; 4772 u8 reserved_at_10[0x10]; 4773 4774 u8 reserved_at_20[0x10]; 4775 u8 op_mod[0x10]; 4776 4777 u8 reserved_at_40[0x8]; 4778 u8 xrc_srqn[0x18]; 4779 4780 u8 reserved_at_60[0x20]; 4781 }; 4782 4783 enum { 4784 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4785 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4786 }; 4787 4788 struct mlx5_ifc_query_vport_state_out_bits { 4789 u8 status[0x8]; 4790 u8 reserved_at_8[0x18]; 4791 4792 u8 syndrome[0x20]; 4793 4794 u8 reserved_at_40[0x20]; 4795 4796 u8 reserved_at_60[0x18]; 4797 u8 admin_state[0x4]; 4798 u8 state[0x4]; 4799 }; 4800 4801 enum { 4802 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4803 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4804 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4805 }; 4806 4807 struct mlx5_ifc_arm_monitor_counter_in_bits { 4808 u8 opcode[0x10]; 4809 u8 uid[0x10]; 4810 4811 u8 reserved_at_20[0x10]; 4812 u8 op_mod[0x10]; 4813 4814 u8 reserved_at_40[0x20]; 4815 4816 u8 reserved_at_60[0x20]; 4817 }; 4818 4819 struct mlx5_ifc_arm_monitor_counter_out_bits { 4820 u8 status[0x8]; 4821 u8 reserved_at_8[0x18]; 4822 4823 u8 syndrome[0x20]; 4824 4825 u8 reserved_at_40[0x40]; 4826 }; 4827 4828 enum { 4829 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4830 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4831 }; 4832 4833 enum mlx5_monitor_counter_ppcnt { 4834 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4835 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4836 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4837 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4838 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4839 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4840 }; 4841 4842 enum { 4843 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4844 }; 4845 4846 struct mlx5_ifc_monitor_counter_output_bits { 4847 u8 reserved_at_0[0x4]; 4848 u8 type[0x4]; 4849 u8 reserved_at_8[0x8]; 4850 u8 counter[0x10]; 4851 4852 u8 counter_group_id[0x20]; 4853 }; 4854 4855 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4856 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4857 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4858 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4859 4860 struct mlx5_ifc_set_monitor_counter_in_bits { 4861 u8 opcode[0x10]; 4862 u8 uid[0x10]; 4863 4864 u8 reserved_at_20[0x10]; 4865 u8 op_mod[0x10]; 4866 4867 u8 reserved_at_40[0x10]; 4868 u8 num_of_counters[0x10]; 4869 4870 u8 reserved_at_60[0x20]; 4871 4872 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4873 }; 4874 4875 struct mlx5_ifc_set_monitor_counter_out_bits { 4876 u8 status[0x8]; 4877 u8 reserved_at_8[0x18]; 4878 4879 u8 syndrome[0x20]; 4880 4881 u8 reserved_at_40[0x40]; 4882 }; 4883 4884 struct mlx5_ifc_query_vport_state_in_bits { 4885 u8 opcode[0x10]; 4886 u8 reserved_at_10[0x10]; 4887 4888 u8 reserved_at_20[0x10]; 4889 u8 op_mod[0x10]; 4890 4891 u8 other_vport[0x1]; 4892 u8 reserved_at_41[0xf]; 4893 u8 vport_number[0x10]; 4894 4895 u8 reserved_at_60[0x20]; 4896 }; 4897 4898 struct mlx5_ifc_query_vnic_env_out_bits { 4899 u8 status[0x8]; 4900 u8 reserved_at_8[0x18]; 4901 4902 u8 syndrome[0x20]; 4903 4904 u8 reserved_at_40[0x40]; 4905 4906 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4907 }; 4908 4909 enum { 4910 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4911 }; 4912 4913 struct mlx5_ifc_query_vnic_env_in_bits { 4914 u8 opcode[0x10]; 4915 u8 reserved_at_10[0x10]; 4916 4917 u8 reserved_at_20[0x10]; 4918 u8 op_mod[0x10]; 4919 4920 u8 other_vport[0x1]; 4921 u8 reserved_at_41[0xf]; 4922 u8 vport_number[0x10]; 4923 4924 u8 reserved_at_60[0x20]; 4925 }; 4926 4927 struct mlx5_ifc_query_vport_counter_out_bits { 4928 u8 status[0x8]; 4929 u8 reserved_at_8[0x18]; 4930 4931 u8 syndrome[0x20]; 4932 4933 u8 reserved_at_40[0x40]; 4934 4935 struct mlx5_ifc_traffic_counter_bits received_errors; 4936 4937 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4938 4939 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4940 4941 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4942 4943 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4944 4945 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4946 4947 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4948 4949 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4950 4951 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4952 4953 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4954 4955 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4956 4957 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4958 4959 u8 reserved_at_680[0xa00]; 4960 }; 4961 4962 enum { 4963 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4964 }; 4965 4966 struct mlx5_ifc_query_vport_counter_in_bits { 4967 u8 opcode[0x10]; 4968 u8 reserved_at_10[0x10]; 4969 4970 u8 reserved_at_20[0x10]; 4971 u8 op_mod[0x10]; 4972 4973 u8 other_vport[0x1]; 4974 u8 reserved_at_41[0xb]; 4975 u8 port_num[0x4]; 4976 u8 vport_number[0x10]; 4977 4978 u8 reserved_at_60[0x60]; 4979 4980 u8 clear[0x1]; 4981 u8 reserved_at_c1[0x1f]; 4982 4983 u8 reserved_at_e0[0x20]; 4984 }; 4985 4986 struct mlx5_ifc_query_tis_out_bits { 4987 u8 status[0x8]; 4988 u8 reserved_at_8[0x18]; 4989 4990 u8 syndrome[0x20]; 4991 4992 u8 reserved_at_40[0x40]; 4993 4994 struct mlx5_ifc_tisc_bits tis_context; 4995 }; 4996 4997 struct mlx5_ifc_query_tis_in_bits { 4998 u8 opcode[0x10]; 4999 u8 reserved_at_10[0x10]; 5000 5001 u8 reserved_at_20[0x10]; 5002 u8 op_mod[0x10]; 5003 5004 u8 reserved_at_40[0x8]; 5005 u8 tisn[0x18]; 5006 5007 u8 reserved_at_60[0x20]; 5008 }; 5009 5010 struct mlx5_ifc_query_tir_out_bits { 5011 u8 status[0x8]; 5012 u8 reserved_at_8[0x18]; 5013 5014 u8 syndrome[0x20]; 5015 5016 u8 reserved_at_40[0xc0]; 5017 5018 struct mlx5_ifc_tirc_bits tir_context; 5019 }; 5020 5021 struct mlx5_ifc_query_tir_in_bits { 5022 u8 opcode[0x10]; 5023 u8 reserved_at_10[0x10]; 5024 5025 u8 reserved_at_20[0x10]; 5026 u8 op_mod[0x10]; 5027 5028 u8 reserved_at_40[0x8]; 5029 u8 tirn[0x18]; 5030 5031 u8 reserved_at_60[0x20]; 5032 }; 5033 5034 struct mlx5_ifc_query_srq_out_bits { 5035 u8 status[0x8]; 5036 u8 reserved_at_8[0x18]; 5037 5038 u8 syndrome[0x20]; 5039 5040 u8 reserved_at_40[0x40]; 5041 5042 struct mlx5_ifc_srqc_bits srq_context_entry; 5043 5044 u8 reserved_at_280[0x600]; 5045 5046 u8 pas[][0x40]; 5047 }; 5048 5049 struct mlx5_ifc_query_srq_in_bits { 5050 u8 opcode[0x10]; 5051 u8 reserved_at_10[0x10]; 5052 5053 u8 reserved_at_20[0x10]; 5054 u8 op_mod[0x10]; 5055 5056 u8 reserved_at_40[0x8]; 5057 u8 srqn[0x18]; 5058 5059 u8 reserved_at_60[0x20]; 5060 }; 5061 5062 struct mlx5_ifc_query_sq_out_bits { 5063 u8 status[0x8]; 5064 u8 reserved_at_8[0x18]; 5065 5066 u8 syndrome[0x20]; 5067 5068 u8 reserved_at_40[0xc0]; 5069 5070 struct mlx5_ifc_sqc_bits sq_context; 5071 }; 5072 5073 struct mlx5_ifc_query_sq_in_bits { 5074 u8 opcode[0x10]; 5075 u8 reserved_at_10[0x10]; 5076 5077 u8 reserved_at_20[0x10]; 5078 u8 op_mod[0x10]; 5079 5080 u8 reserved_at_40[0x8]; 5081 u8 sqn[0x18]; 5082 5083 u8 reserved_at_60[0x20]; 5084 }; 5085 5086 struct mlx5_ifc_query_special_contexts_out_bits { 5087 u8 status[0x8]; 5088 u8 reserved_at_8[0x18]; 5089 5090 u8 syndrome[0x20]; 5091 5092 u8 dump_fill_mkey[0x20]; 5093 5094 u8 resd_lkey[0x20]; 5095 5096 u8 null_mkey[0x20]; 5097 5098 u8 reserved_at_a0[0x60]; 5099 }; 5100 5101 struct mlx5_ifc_query_special_contexts_in_bits { 5102 u8 opcode[0x10]; 5103 u8 reserved_at_10[0x10]; 5104 5105 u8 reserved_at_20[0x10]; 5106 u8 op_mod[0x10]; 5107 5108 u8 reserved_at_40[0x40]; 5109 }; 5110 5111 struct mlx5_ifc_query_scheduling_element_out_bits { 5112 u8 opcode[0x10]; 5113 u8 reserved_at_10[0x10]; 5114 5115 u8 reserved_at_20[0x10]; 5116 u8 op_mod[0x10]; 5117 5118 u8 reserved_at_40[0xc0]; 5119 5120 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5121 5122 u8 reserved_at_300[0x100]; 5123 }; 5124 5125 enum { 5126 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5127 SCHEDULING_HIERARCHY_NIC = 0x3, 5128 }; 5129 5130 struct mlx5_ifc_query_scheduling_element_in_bits { 5131 u8 opcode[0x10]; 5132 u8 reserved_at_10[0x10]; 5133 5134 u8 reserved_at_20[0x10]; 5135 u8 op_mod[0x10]; 5136 5137 u8 scheduling_hierarchy[0x8]; 5138 u8 reserved_at_48[0x18]; 5139 5140 u8 scheduling_element_id[0x20]; 5141 5142 u8 reserved_at_80[0x180]; 5143 }; 5144 5145 struct mlx5_ifc_query_rqt_out_bits { 5146 u8 status[0x8]; 5147 u8 reserved_at_8[0x18]; 5148 5149 u8 syndrome[0x20]; 5150 5151 u8 reserved_at_40[0xc0]; 5152 5153 struct mlx5_ifc_rqtc_bits rqt_context; 5154 }; 5155 5156 struct mlx5_ifc_query_rqt_in_bits { 5157 u8 opcode[0x10]; 5158 u8 reserved_at_10[0x10]; 5159 5160 u8 reserved_at_20[0x10]; 5161 u8 op_mod[0x10]; 5162 5163 u8 reserved_at_40[0x8]; 5164 u8 rqtn[0x18]; 5165 5166 u8 reserved_at_60[0x20]; 5167 }; 5168 5169 struct mlx5_ifc_query_rq_out_bits { 5170 u8 status[0x8]; 5171 u8 reserved_at_8[0x18]; 5172 5173 u8 syndrome[0x20]; 5174 5175 u8 reserved_at_40[0xc0]; 5176 5177 struct mlx5_ifc_rqc_bits rq_context; 5178 }; 5179 5180 struct mlx5_ifc_query_rq_in_bits { 5181 u8 opcode[0x10]; 5182 u8 reserved_at_10[0x10]; 5183 5184 u8 reserved_at_20[0x10]; 5185 u8 op_mod[0x10]; 5186 5187 u8 reserved_at_40[0x8]; 5188 u8 rqn[0x18]; 5189 5190 u8 reserved_at_60[0x20]; 5191 }; 5192 5193 struct mlx5_ifc_query_roce_address_out_bits { 5194 u8 status[0x8]; 5195 u8 reserved_at_8[0x18]; 5196 5197 u8 syndrome[0x20]; 5198 5199 u8 reserved_at_40[0x40]; 5200 5201 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5202 }; 5203 5204 struct mlx5_ifc_query_roce_address_in_bits { 5205 u8 opcode[0x10]; 5206 u8 reserved_at_10[0x10]; 5207 5208 u8 reserved_at_20[0x10]; 5209 u8 op_mod[0x10]; 5210 5211 u8 roce_address_index[0x10]; 5212 u8 reserved_at_50[0xc]; 5213 u8 vhca_port_num[0x4]; 5214 5215 u8 reserved_at_60[0x20]; 5216 }; 5217 5218 struct mlx5_ifc_query_rmp_out_bits { 5219 u8 status[0x8]; 5220 u8 reserved_at_8[0x18]; 5221 5222 u8 syndrome[0x20]; 5223 5224 u8 reserved_at_40[0xc0]; 5225 5226 struct mlx5_ifc_rmpc_bits rmp_context; 5227 }; 5228 5229 struct mlx5_ifc_query_rmp_in_bits { 5230 u8 opcode[0x10]; 5231 u8 reserved_at_10[0x10]; 5232 5233 u8 reserved_at_20[0x10]; 5234 u8 op_mod[0x10]; 5235 5236 u8 reserved_at_40[0x8]; 5237 u8 rmpn[0x18]; 5238 5239 u8 reserved_at_60[0x20]; 5240 }; 5241 5242 struct mlx5_ifc_query_qp_out_bits { 5243 u8 status[0x8]; 5244 u8 reserved_at_8[0x18]; 5245 5246 u8 syndrome[0x20]; 5247 5248 u8 reserved_at_40[0x40]; 5249 5250 u8 opt_param_mask[0x20]; 5251 5252 u8 ece[0x20]; 5253 5254 struct mlx5_ifc_qpc_bits qpc; 5255 5256 u8 reserved_at_800[0x80]; 5257 5258 u8 pas[][0x40]; 5259 }; 5260 5261 struct mlx5_ifc_query_qp_in_bits { 5262 u8 opcode[0x10]; 5263 u8 reserved_at_10[0x10]; 5264 5265 u8 reserved_at_20[0x10]; 5266 u8 op_mod[0x10]; 5267 5268 u8 reserved_at_40[0x8]; 5269 u8 qpn[0x18]; 5270 5271 u8 reserved_at_60[0x20]; 5272 }; 5273 5274 struct mlx5_ifc_query_q_counter_out_bits { 5275 u8 status[0x8]; 5276 u8 reserved_at_8[0x18]; 5277 5278 u8 syndrome[0x20]; 5279 5280 u8 reserved_at_40[0x40]; 5281 5282 u8 rx_write_requests[0x20]; 5283 5284 u8 reserved_at_a0[0x20]; 5285 5286 u8 rx_read_requests[0x20]; 5287 5288 u8 reserved_at_e0[0x20]; 5289 5290 u8 rx_atomic_requests[0x20]; 5291 5292 u8 reserved_at_120[0x20]; 5293 5294 u8 rx_dct_connect[0x20]; 5295 5296 u8 reserved_at_160[0x20]; 5297 5298 u8 out_of_buffer[0x20]; 5299 5300 u8 reserved_at_1a0[0x20]; 5301 5302 u8 out_of_sequence[0x20]; 5303 5304 u8 reserved_at_1e0[0x20]; 5305 5306 u8 duplicate_request[0x20]; 5307 5308 u8 reserved_at_220[0x20]; 5309 5310 u8 rnr_nak_retry_err[0x20]; 5311 5312 u8 reserved_at_260[0x20]; 5313 5314 u8 packet_seq_err[0x20]; 5315 5316 u8 reserved_at_2a0[0x20]; 5317 5318 u8 implied_nak_seq_err[0x20]; 5319 5320 u8 reserved_at_2e0[0x20]; 5321 5322 u8 local_ack_timeout_err[0x20]; 5323 5324 u8 reserved_at_320[0xa0]; 5325 5326 u8 resp_local_length_error[0x20]; 5327 5328 u8 req_local_length_error[0x20]; 5329 5330 u8 resp_local_qp_error[0x20]; 5331 5332 u8 local_operation_error[0x20]; 5333 5334 u8 resp_local_protection[0x20]; 5335 5336 u8 req_local_protection[0x20]; 5337 5338 u8 resp_cqe_error[0x20]; 5339 5340 u8 req_cqe_error[0x20]; 5341 5342 u8 req_mw_binding[0x20]; 5343 5344 u8 req_bad_response[0x20]; 5345 5346 u8 req_remote_invalid_request[0x20]; 5347 5348 u8 resp_remote_invalid_request[0x20]; 5349 5350 u8 req_remote_access_errors[0x20]; 5351 5352 u8 resp_remote_access_errors[0x20]; 5353 5354 u8 req_remote_operation_errors[0x20]; 5355 5356 u8 req_transport_retries_exceeded[0x20]; 5357 5358 u8 cq_overflow[0x20]; 5359 5360 u8 resp_cqe_flush_error[0x20]; 5361 5362 u8 req_cqe_flush_error[0x20]; 5363 5364 u8 reserved_at_620[0x20]; 5365 5366 u8 roce_adp_retrans[0x20]; 5367 5368 u8 roce_adp_retrans_to[0x20]; 5369 5370 u8 roce_slow_restart[0x20]; 5371 5372 u8 roce_slow_restart_cnps[0x20]; 5373 5374 u8 roce_slow_restart_trans[0x20]; 5375 5376 u8 reserved_at_6e0[0x120]; 5377 }; 5378 5379 struct mlx5_ifc_query_q_counter_in_bits { 5380 u8 opcode[0x10]; 5381 u8 reserved_at_10[0x10]; 5382 5383 u8 reserved_at_20[0x10]; 5384 u8 op_mod[0x10]; 5385 5386 u8 reserved_at_40[0x80]; 5387 5388 u8 clear[0x1]; 5389 u8 reserved_at_c1[0x1f]; 5390 5391 u8 reserved_at_e0[0x18]; 5392 u8 counter_set_id[0x8]; 5393 }; 5394 5395 struct mlx5_ifc_query_pages_out_bits { 5396 u8 status[0x8]; 5397 u8 reserved_at_8[0x18]; 5398 5399 u8 syndrome[0x20]; 5400 5401 u8 embedded_cpu_function[0x1]; 5402 u8 reserved_at_41[0xf]; 5403 u8 function_id[0x10]; 5404 5405 u8 num_pages[0x20]; 5406 }; 5407 5408 enum { 5409 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5410 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5411 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5412 }; 5413 5414 struct mlx5_ifc_query_pages_in_bits { 5415 u8 opcode[0x10]; 5416 u8 reserved_at_10[0x10]; 5417 5418 u8 reserved_at_20[0x10]; 5419 u8 op_mod[0x10]; 5420 5421 u8 embedded_cpu_function[0x1]; 5422 u8 reserved_at_41[0xf]; 5423 u8 function_id[0x10]; 5424 5425 u8 reserved_at_60[0x20]; 5426 }; 5427 5428 struct mlx5_ifc_query_nic_vport_context_out_bits { 5429 u8 status[0x8]; 5430 u8 reserved_at_8[0x18]; 5431 5432 u8 syndrome[0x20]; 5433 5434 u8 reserved_at_40[0x40]; 5435 5436 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5437 }; 5438 5439 struct mlx5_ifc_query_nic_vport_context_in_bits { 5440 u8 opcode[0x10]; 5441 u8 reserved_at_10[0x10]; 5442 5443 u8 reserved_at_20[0x10]; 5444 u8 op_mod[0x10]; 5445 5446 u8 other_vport[0x1]; 5447 u8 reserved_at_41[0xf]; 5448 u8 vport_number[0x10]; 5449 5450 u8 reserved_at_60[0x5]; 5451 u8 allowed_list_type[0x3]; 5452 u8 reserved_at_68[0x18]; 5453 }; 5454 5455 struct mlx5_ifc_query_mkey_out_bits { 5456 u8 status[0x8]; 5457 u8 reserved_at_8[0x18]; 5458 5459 u8 syndrome[0x20]; 5460 5461 u8 reserved_at_40[0x40]; 5462 5463 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5464 5465 u8 reserved_at_280[0x600]; 5466 5467 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5468 5469 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5470 }; 5471 5472 struct mlx5_ifc_query_mkey_in_bits { 5473 u8 opcode[0x10]; 5474 u8 reserved_at_10[0x10]; 5475 5476 u8 reserved_at_20[0x10]; 5477 u8 op_mod[0x10]; 5478 5479 u8 reserved_at_40[0x8]; 5480 u8 mkey_index[0x18]; 5481 5482 u8 pg_access[0x1]; 5483 u8 reserved_at_61[0x1f]; 5484 }; 5485 5486 struct mlx5_ifc_query_mad_demux_out_bits { 5487 u8 status[0x8]; 5488 u8 reserved_at_8[0x18]; 5489 5490 u8 syndrome[0x20]; 5491 5492 u8 reserved_at_40[0x40]; 5493 5494 u8 mad_dumux_parameters_block[0x20]; 5495 }; 5496 5497 struct mlx5_ifc_query_mad_demux_in_bits { 5498 u8 opcode[0x10]; 5499 u8 reserved_at_10[0x10]; 5500 5501 u8 reserved_at_20[0x10]; 5502 u8 op_mod[0x10]; 5503 5504 u8 reserved_at_40[0x40]; 5505 }; 5506 5507 struct mlx5_ifc_query_l2_table_entry_out_bits { 5508 u8 status[0x8]; 5509 u8 reserved_at_8[0x18]; 5510 5511 u8 syndrome[0x20]; 5512 5513 u8 reserved_at_40[0xa0]; 5514 5515 u8 reserved_at_e0[0x13]; 5516 u8 vlan_valid[0x1]; 5517 u8 vlan[0xc]; 5518 5519 struct mlx5_ifc_mac_address_layout_bits mac_address; 5520 5521 u8 reserved_at_140[0xc0]; 5522 }; 5523 5524 struct mlx5_ifc_query_l2_table_entry_in_bits { 5525 u8 opcode[0x10]; 5526 u8 reserved_at_10[0x10]; 5527 5528 u8 reserved_at_20[0x10]; 5529 u8 op_mod[0x10]; 5530 5531 u8 reserved_at_40[0x60]; 5532 5533 u8 reserved_at_a0[0x8]; 5534 u8 table_index[0x18]; 5535 5536 u8 reserved_at_c0[0x140]; 5537 }; 5538 5539 struct mlx5_ifc_query_issi_out_bits { 5540 u8 status[0x8]; 5541 u8 reserved_at_8[0x18]; 5542 5543 u8 syndrome[0x20]; 5544 5545 u8 reserved_at_40[0x10]; 5546 u8 current_issi[0x10]; 5547 5548 u8 reserved_at_60[0xa0]; 5549 5550 u8 reserved_at_100[76][0x8]; 5551 u8 supported_issi_dw0[0x20]; 5552 }; 5553 5554 struct mlx5_ifc_query_issi_in_bits { 5555 u8 opcode[0x10]; 5556 u8 reserved_at_10[0x10]; 5557 5558 u8 reserved_at_20[0x10]; 5559 u8 op_mod[0x10]; 5560 5561 u8 reserved_at_40[0x40]; 5562 }; 5563 5564 struct mlx5_ifc_set_driver_version_out_bits { 5565 u8 status[0x8]; 5566 u8 reserved_0[0x18]; 5567 5568 u8 syndrome[0x20]; 5569 u8 reserved_1[0x40]; 5570 }; 5571 5572 struct mlx5_ifc_set_driver_version_in_bits { 5573 u8 opcode[0x10]; 5574 u8 reserved_0[0x10]; 5575 5576 u8 reserved_1[0x10]; 5577 u8 op_mod[0x10]; 5578 5579 u8 reserved_2[0x40]; 5580 u8 driver_version[64][0x8]; 5581 }; 5582 5583 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5584 u8 status[0x8]; 5585 u8 reserved_at_8[0x18]; 5586 5587 u8 syndrome[0x20]; 5588 5589 u8 reserved_at_40[0x40]; 5590 5591 struct mlx5_ifc_pkey_bits pkey[]; 5592 }; 5593 5594 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5595 u8 opcode[0x10]; 5596 u8 reserved_at_10[0x10]; 5597 5598 u8 reserved_at_20[0x10]; 5599 u8 op_mod[0x10]; 5600 5601 u8 other_vport[0x1]; 5602 u8 reserved_at_41[0xb]; 5603 u8 port_num[0x4]; 5604 u8 vport_number[0x10]; 5605 5606 u8 reserved_at_60[0x10]; 5607 u8 pkey_index[0x10]; 5608 }; 5609 5610 enum { 5611 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5612 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5613 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5614 }; 5615 5616 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5617 u8 status[0x8]; 5618 u8 reserved_at_8[0x18]; 5619 5620 u8 syndrome[0x20]; 5621 5622 u8 reserved_at_40[0x20]; 5623 5624 u8 gids_num[0x10]; 5625 u8 reserved_at_70[0x10]; 5626 5627 struct mlx5_ifc_array128_auto_bits gid[]; 5628 }; 5629 5630 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5631 u8 opcode[0x10]; 5632 u8 reserved_at_10[0x10]; 5633 5634 u8 reserved_at_20[0x10]; 5635 u8 op_mod[0x10]; 5636 5637 u8 other_vport[0x1]; 5638 u8 reserved_at_41[0xb]; 5639 u8 port_num[0x4]; 5640 u8 vport_number[0x10]; 5641 5642 u8 reserved_at_60[0x10]; 5643 u8 gid_index[0x10]; 5644 }; 5645 5646 struct mlx5_ifc_query_hca_vport_context_out_bits { 5647 u8 status[0x8]; 5648 u8 reserved_at_8[0x18]; 5649 5650 u8 syndrome[0x20]; 5651 5652 u8 reserved_at_40[0x40]; 5653 5654 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5655 }; 5656 5657 struct mlx5_ifc_query_hca_vport_context_in_bits { 5658 u8 opcode[0x10]; 5659 u8 reserved_at_10[0x10]; 5660 5661 u8 reserved_at_20[0x10]; 5662 u8 op_mod[0x10]; 5663 5664 u8 other_vport[0x1]; 5665 u8 reserved_at_41[0xb]; 5666 u8 port_num[0x4]; 5667 u8 vport_number[0x10]; 5668 5669 u8 reserved_at_60[0x20]; 5670 }; 5671 5672 struct mlx5_ifc_query_hca_cap_out_bits { 5673 u8 status[0x8]; 5674 u8 reserved_at_8[0x18]; 5675 5676 u8 syndrome[0x20]; 5677 5678 u8 reserved_at_40[0x40]; 5679 5680 union mlx5_ifc_hca_cap_union_bits capability; 5681 }; 5682 5683 struct mlx5_ifc_query_hca_cap_in_bits { 5684 u8 opcode[0x10]; 5685 u8 reserved_at_10[0x10]; 5686 5687 u8 reserved_at_20[0x10]; 5688 u8 op_mod[0x10]; 5689 5690 u8 other_function[0x1]; 5691 u8 reserved_at_41[0xf]; 5692 u8 function_id[0x10]; 5693 5694 u8 reserved_at_60[0x20]; 5695 }; 5696 5697 struct mlx5_ifc_other_hca_cap_bits { 5698 u8 roce[0x1]; 5699 u8 reserved_at_1[0x27f]; 5700 }; 5701 5702 struct mlx5_ifc_query_other_hca_cap_out_bits { 5703 u8 status[0x8]; 5704 u8 reserved_at_8[0x18]; 5705 5706 u8 syndrome[0x20]; 5707 5708 u8 reserved_at_40[0x40]; 5709 5710 struct mlx5_ifc_other_hca_cap_bits other_capability; 5711 }; 5712 5713 struct mlx5_ifc_query_other_hca_cap_in_bits { 5714 u8 opcode[0x10]; 5715 u8 reserved_at_10[0x10]; 5716 5717 u8 reserved_at_20[0x10]; 5718 u8 op_mod[0x10]; 5719 5720 u8 reserved_at_40[0x10]; 5721 u8 function_id[0x10]; 5722 5723 u8 reserved_at_60[0x20]; 5724 }; 5725 5726 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5727 u8 status[0x8]; 5728 u8 reserved_at_8[0x18]; 5729 5730 u8 syndrome[0x20]; 5731 5732 u8 reserved_at_40[0x40]; 5733 }; 5734 5735 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5736 u8 opcode[0x10]; 5737 u8 reserved_at_10[0x10]; 5738 5739 u8 reserved_at_20[0x10]; 5740 u8 op_mod[0x10]; 5741 5742 u8 reserved_at_40[0x10]; 5743 u8 function_id[0x10]; 5744 u8 field_select[0x20]; 5745 5746 struct mlx5_ifc_other_hca_cap_bits other_capability; 5747 }; 5748 5749 struct mlx5_ifc_flow_table_context_bits { 5750 u8 reformat_en[0x1]; 5751 u8 decap_en[0x1]; 5752 u8 sw_owner[0x1]; 5753 u8 termination_table[0x1]; 5754 u8 table_miss_action[0x4]; 5755 u8 level[0x8]; 5756 u8 reserved_at_10[0x8]; 5757 u8 log_size[0x8]; 5758 5759 u8 reserved_at_20[0x8]; 5760 u8 table_miss_id[0x18]; 5761 5762 u8 reserved_at_40[0x8]; 5763 u8 lag_master_next_table_id[0x18]; 5764 5765 u8 reserved_at_60[0x60]; 5766 5767 u8 sw_owner_icm_root_1[0x40]; 5768 5769 u8 sw_owner_icm_root_0[0x40]; 5770 5771 }; 5772 5773 struct mlx5_ifc_query_flow_table_out_bits { 5774 u8 status[0x8]; 5775 u8 reserved_at_8[0x18]; 5776 5777 u8 syndrome[0x20]; 5778 5779 u8 reserved_at_40[0x80]; 5780 5781 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5782 }; 5783 5784 struct mlx5_ifc_query_flow_table_in_bits { 5785 u8 opcode[0x10]; 5786 u8 reserved_at_10[0x10]; 5787 5788 u8 reserved_at_20[0x10]; 5789 u8 op_mod[0x10]; 5790 5791 u8 reserved_at_40[0x40]; 5792 5793 u8 table_type[0x8]; 5794 u8 reserved_at_88[0x18]; 5795 5796 u8 reserved_at_a0[0x8]; 5797 u8 table_id[0x18]; 5798 5799 u8 reserved_at_c0[0x140]; 5800 }; 5801 5802 struct mlx5_ifc_query_fte_out_bits { 5803 u8 status[0x8]; 5804 u8 reserved_at_8[0x18]; 5805 5806 u8 syndrome[0x20]; 5807 5808 u8 reserved_at_40[0x1c0]; 5809 5810 struct mlx5_ifc_flow_context_bits flow_context; 5811 }; 5812 5813 struct mlx5_ifc_query_fte_in_bits { 5814 u8 opcode[0x10]; 5815 u8 reserved_at_10[0x10]; 5816 5817 u8 reserved_at_20[0x10]; 5818 u8 op_mod[0x10]; 5819 5820 u8 reserved_at_40[0x40]; 5821 5822 u8 table_type[0x8]; 5823 u8 reserved_at_88[0x18]; 5824 5825 u8 reserved_at_a0[0x8]; 5826 u8 table_id[0x18]; 5827 5828 u8 reserved_at_c0[0x40]; 5829 5830 u8 flow_index[0x20]; 5831 5832 u8 reserved_at_120[0xe0]; 5833 }; 5834 5835 struct mlx5_ifc_match_definer_format_0_bits { 5836 u8 reserved_at_0[0x100]; 5837 5838 u8 metadata_reg_c_0[0x20]; 5839 5840 u8 metadata_reg_c_1[0x20]; 5841 5842 u8 outer_dmac_47_16[0x20]; 5843 5844 u8 outer_dmac_15_0[0x10]; 5845 u8 outer_ethertype[0x10]; 5846 5847 u8 reserved_at_180[0x1]; 5848 u8 sx_sniffer[0x1]; 5849 u8 functional_lb[0x1]; 5850 u8 outer_ip_frag[0x1]; 5851 u8 outer_qp_type[0x2]; 5852 u8 outer_encap_type[0x2]; 5853 u8 port_number[0x2]; 5854 u8 outer_l3_type[0x2]; 5855 u8 outer_l4_type[0x2]; 5856 u8 outer_first_vlan_type[0x2]; 5857 u8 outer_first_vlan_prio[0x3]; 5858 u8 outer_first_vlan_cfi[0x1]; 5859 u8 outer_first_vlan_vid[0xc]; 5860 5861 u8 outer_l4_type_ext[0x4]; 5862 u8 reserved_at_1a4[0x2]; 5863 u8 outer_ipsec_layer[0x2]; 5864 u8 outer_l2_type[0x2]; 5865 u8 force_lb[0x1]; 5866 u8 outer_l2_ok[0x1]; 5867 u8 outer_l3_ok[0x1]; 5868 u8 outer_l4_ok[0x1]; 5869 u8 outer_second_vlan_type[0x2]; 5870 u8 outer_second_vlan_prio[0x3]; 5871 u8 outer_second_vlan_cfi[0x1]; 5872 u8 outer_second_vlan_vid[0xc]; 5873 5874 u8 outer_smac_47_16[0x20]; 5875 5876 u8 outer_smac_15_0[0x10]; 5877 u8 inner_ipv4_checksum_ok[0x1]; 5878 u8 inner_l4_checksum_ok[0x1]; 5879 u8 outer_ipv4_checksum_ok[0x1]; 5880 u8 outer_l4_checksum_ok[0x1]; 5881 u8 inner_l3_ok[0x1]; 5882 u8 inner_l4_ok[0x1]; 5883 u8 outer_l3_ok_duplicate[0x1]; 5884 u8 outer_l4_ok_duplicate[0x1]; 5885 u8 outer_tcp_cwr[0x1]; 5886 u8 outer_tcp_ece[0x1]; 5887 u8 outer_tcp_urg[0x1]; 5888 u8 outer_tcp_ack[0x1]; 5889 u8 outer_tcp_psh[0x1]; 5890 u8 outer_tcp_rst[0x1]; 5891 u8 outer_tcp_syn[0x1]; 5892 u8 outer_tcp_fin[0x1]; 5893 }; 5894 5895 struct mlx5_ifc_match_definer_format_22_bits { 5896 u8 reserved_at_0[0x100]; 5897 5898 u8 outer_ip_src_addr[0x20]; 5899 5900 u8 outer_ip_dest_addr[0x20]; 5901 5902 u8 outer_l4_sport[0x10]; 5903 u8 outer_l4_dport[0x10]; 5904 5905 u8 reserved_at_160[0x1]; 5906 u8 sx_sniffer[0x1]; 5907 u8 functional_lb[0x1]; 5908 u8 outer_ip_frag[0x1]; 5909 u8 outer_qp_type[0x2]; 5910 u8 outer_encap_type[0x2]; 5911 u8 port_number[0x2]; 5912 u8 outer_l3_type[0x2]; 5913 u8 outer_l4_type[0x2]; 5914 u8 outer_first_vlan_type[0x2]; 5915 u8 outer_first_vlan_prio[0x3]; 5916 u8 outer_first_vlan_cfi[0x1]; 5917 u8 outer_first_vlan_vid[0xc]; 5918 5919 u8 metadata_reg_c_0[0x20]; 5920 5921 u8 outer_dmac_47_16[0x20]; 5922 5923 u8 outer_smac_47_16[0x20]; 5924 5925 u8 outer_smac_15_0[0x10]; 5926 u8 outer_dmac_15_0[0x10]; 5927 }; 5928 5929 struct mlx5_ifc_match_definer_format_23_bits { 5930 u8 reserved_at_0[0x100]; 5931 5932 u8 inner_ip_src_addr[0x20]; 5933 5934 u8 inner_ip_dest_addr[0x20]; 5935 5936 u8 inner_l4_sport[0x10]; 5937 u8 inner_l4_dport[0x10]; 5938 5939 u8 reserved_at_160[0x1]; 5940 u8 sx_sniffer[0x1]; 5941 u8 functional_lb[0x1]; 5942 u8 inner_ip_frag[0x1]; 5943 u8 inner_qp_type[0x2]; 5944 u8 inner_encap_type[0x2]; 5945 u8 port_number[0x2]; 5946 u8 inner_l3_type[0x2]; 5947 u8 inner_l4_type[0x2]; 5948 u8 inner_first_vlan_type[0x2]; 5949 u8 inner_first_vlan_prio[0x3]; 5950 u8 inner_first_vlan_cfi[0x1]; 5951 u8 inner_first_vlan_vid[0xc]; 5952 5953 u8 tunnel_header_0[0x20]; 5954 5955 u8 inner_dmac_47_16[0x20]; 5956 5957 u8 inner_smac_47_16[0x20]; 5958 5959 u8 inner_smac_15_0[0x10]; 5960 u8 inner_dmac_15_0[0x10]; 5961 }; 5962 5963 struct mlx5_ifc_match_definer_format_29_bits { 5964 u8 reserved_at_0[0xc0]; 5965 5966 u8 outer_ip_dest_addr[0x80]; 5967 5968 u8 outer_ip_src_addr[0x80]; 5969 5970 u8 outer_l4_sport[0x10]; 5971 u8 outer_l4_dport[0x10]; 5972 5973 u8 reserved_at_1e0[0x20]; 5974 }; 5975 5976 struct mlx5_ifc_match_definer_format_30_bits { 5977 u8 reserved_at_0[0xa0]; 5978 5979 u8 outer_ip_dest_addr[0x80]; 5980 5981 u8 outer_ip_src_addr[0x80]; 5982 5983 u8 outer_dmac_47_16[0x20]; 5984 5985 u8 outer_smac_47_16[0x20]; 5986 5987 u8 outer_smac_15_0[0x10]; 5988 u8 outer_dmac_15_0[0x10]; 5989 }; 5990 5991 struct mlx5_ifc_match_definer_format_31_bits { 5992 u8 reserved_at_0[0xc0]; 5993 5994 u8 inner_ip_dest_addr[0x80]; 5995 5996 u8 inner_ip_src_addr[0x80]; 5997 5998 u8 inner_l4_sport[0x10]; 5999 u8 inner_l4_dport[0x10]; 6000 6001 u8 reserved_at_1e0[0x20]; 6002 }; 6003 6004 struct mlx5_ifc_match_definer_format_32_bits { 6005 u8 reserved_at_0[0xa0]; 6006 6007 u8 inner_ip_dest_addr[0x80]; 6008 6009 u8 inner_ip_src_addr[0x80]; 6010 6011 u8 inner_dmac_47_16[0x20]; 6012 6013 u8 inner_smac_47_16[0x20]; 6014 6015 u8 inner_smac_15_0[0x10]; 6016 u8 inner_dmac_15_0[0x10]; 6017 }; 6018 6019 struct mlx5_ifc_match_definer_bits { 6020 u8 modify_field_select[0x40]; 6021 6022 u8 reserved_at_40[0x40]; 6023 6024 u8 reserved_at_80[0x10]; 6025 u8 format_id[0x10]; 6026 6027 u8 reserved_at_a0[0x160]; 6028 6029 u8 match_mask[16][0x20]; 6030 }; 6031 6032 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6033 u8 opcode[0x10]; 6034 u8 uid[0x10]; 6035 6036 u8 vhca_tunnel_id[0x10]; 6037 u8 obj_type[0x10]; 6038 6039 u8 obj_id[0x20]; 6040 6041 u8 reserved_at_60[0x3]; 6042 u8 log_obj_range[0x5]; 6043 u8 reserved_at_68[0x18]; 6044 }; 6045 6046 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6047 u8 status[0x8]; 6048 u8 reserved_at_8[0x18]; 6049 6050 u8 syndrome[0x20]; 6051 6052 u8 obj_id[0x20]; 6053 6054 u8 reserved_at_60[0x20]; 6055 }; 6056 6057 struct mlx5_ifc_create_match_definer_in_bits { 6058 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6059 6060 struct mlx5_ifc_match_definer_bits obj_context; 6061 }; 6062 6063 struct mlx5_ifc_create_match_definer_out_bits { 6064 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6065 }; 6066 6067 enum { 6068 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6069 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6070 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6071 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6072 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6073 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6074 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6075 }; 6076 6077 struct mlx5_ifc_query_flow_group_out_bits { 6078 u8 status[0x8]; 6079 u8 reserved_at_8[0x18]; 6080 6081 u8 syndrome[0x20]; 6082 6083 u8 reserved_at_40[0xa0]; 6084 6085 u8 start_flow_index[0x20]; 6086 6087 u8 reserved_at_100[0x20]; 6088 6089 u8 end_flow_index[0x20]; 6090 6091 u8 reserved_at_140[0xa0]; 6092 6093 u8 reserved_at_1e0[0x18]; 6094 u8 match_criteria_enable[0x8]; 6095 6096 struct mlx5_ifc_fte_match_param_bits match_criteria; 6097 6098 u8 reserved_at_1200[0xe00]; 6099 }; 6100 6101 struct mlx5_ifc_query_flow_group_in_bits { 6102 u8 opcode[0x10]; 6103 u8 reserved_at_10[0x10]; 6104 6105 u8 reserved_at_20[0x10]; 6106 u8 op_mod[0x10]; 6107 6108 u8 reserved_at_40[0x40]; 6109 6110 u8 table_type[0x8]; 6111 u8 reserved_at_88[0x18]; 6112 6113 u8 reserved_at_a0[0x8]; 6114 u8 table_id[0x18]; 6115 6116 u8 group_id[0x20]; 6117 6118 u8 reserved_at_e0[0x120]; 6119 }; 6120 6121 struct mlx5_ifc_query_flow_counter_out_bits { 6122 u8 status[0x8]; 6123 u8 reserved_at_8[0x18]; 6124 6125 u8 syndrome[0x20]; 6126 6127 u8 reserved_at_40[0x40]; 6128 6129 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6130 }; 6131 6132 struct mlx5_ifc_query_flow_counter_in_bits { 6133 u8 opcode[0x10]; 6134 u8 reserved_at_10[0x10]; 6135 6136 u8 reserved_at_20[0x10]; 6137 u8 op_mod[0x10]; 6138 6139 u8 reserved_at_40[0x80]; 6140 6141 u8 clear[0x1]; 6142 u8 reserved_at_c1[0xf]; 6143 u8 num_of_counters[0x10]; 6144 6145 u8 flow_counter_id[0x20]; 6146 }; 6147 6148 struct mlx5_ifc_query_esw_vport_context_out_bits { 6149 u8 status[0x8]; 6150 u8 reserved_at_8[0x18]; 6151 6152 u8 syndrome[0x20]; 6153 6154 u8 reserved_at_40[0x40]; 6155 6156 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6157 }; 6158 6159 struct mlx5_ifc_query_esw_vport_context_in_bits { 6160 u8 opcode[0x10]; 6161 u8 reserved_at_10[0x10]; 6162 6163 u8 reserved_at_20[0x10]; 6164 u8 op_mod[0x10]; 6165 6166 u8 other_vport[0x1]; 6167 u8 reserved_at_41[0xf]; 6168 u8 vport_number[0x10]; 6169 6170 u8 reserved_at_60[0x20]; 6171 }; 6172 6173 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6174 u8 status[0x8]; 6175 u8 reserved_at_8[0x18]; 6176 6177 u8 syndrome[0x20]; 6178 6179 u8 reserved_at_40[0x40]; 6180 }; 6181 6182 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6183 u8 reserved_at_0[0x1b]; 6184 u8 fdb_to_vport_reg_c_id[0x1]; 6185 u8 vport_cvlan_insert[0x1]; 6186 u8 vport_svlan_insert[0x1]; 6187 u8 vport_cvlan_strip[0x1]; 6188 u8 vport_svlan_strip[0x1]; 6189 }; 6190 6191 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6192 u8 opcode[0x10]; 6193 u8 reserved_at_10[0x10]; 6194 6195 u8 reserved_at_20[0x10]; 6196 u8 op_mod[0x10]; 6197 6198 u8 other_vport[0x1]; 6199 u8 reserved_at_41[0xf]; 6200 u8 vport_number[0x10]; 6201 6202 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6203 6204 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6205 }; 6206 6207 struct mlx5_ifc_query_eq_out_bits { 6208 u8 status[0x8]; 6209 u8 reserved_at_8[0x18]; 6210 6211 u8 syndrome[0x20]; 6212 6213 u8 reserved_at_40[0x40]; 6214 6215 struct mlx5_ifc_eqc_bits eq_context_entry; 6216 6217 u8 reserved_at_280[0x40]; 6218 6219 u8 event_bitmask[0x40]; 6220 6221 u8 reserved_at_300[0x580]; 6222 6223 u8 pas[][0x40]; 6224 }; 6225 6226 struct mlx5_ifc_query_eq_in_bits { 6227 u8 opcode[0x10]; 6228 u8 reserved_at_10[0x10]; 6229 6230 u8 reserved_at_20[0x10]; 6231 u8 op_mod[0x10]; 6232 6233 u8 reserved_at_40[0x18]; 6234 u8 eq_number[0x8]; 6235 6236 u8 reserved_at_60[0x20]; 6237 }; 6238 6239 struct mlx5_ifc_packet_reformat_context_in_bits { 6240 u8 reformat_type[0x8]; 6241 u8 reserved_at_8[0x4]; 6242 u8 reformat_param_0[0x4]; 6243 u8 reserved_at_10[0x6]; 6244 u8 reformat_data_size[0xa]; 6245 6246 u8 reformat_param_1[0x8]; 6247 u8 reserved_at_28[0x8]; 6248 u8 reformat_data[2][0x8]; 6249 6250 u8 more_reformat_data[][0x8]; 6251 }; 6252 6253 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6254 u8 status[0x8]; 6255 u8 reserved_at_8[0x18]; 6256 6257 u8 syndrome[0x20]; 6258 6259 u8 reserved_at_40[0xa0]; 6260 6261 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6262 }; 6263 6264 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6265 u8 opcode[0x10]; 6266 u8 reserved_at_10[0x10]; 6267 6268 u8 reserved_at_20[0x10]; 6269 u8 op_mod[0x10]; 6270 6271 u8 packet_reformat_id[0x20]; 6272 6273 u8 reserved_at_60[0xa0]; 6274 }; 6275 6276 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6277 u8 status[0x8]; 6278 u8 reserved_at_8[0x18]; 6279 6280 u8 syndrome[0x20]; 6281 6282 u8 packet_reformat_id[0x20]; 6283 6284 u8 reserved_at_60[0x20]; 6285 }; 6286 6287 enum { 6288 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6289 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6290 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6291 }; 6292 6293 enum mlx5_reformat_ctx_type { 6294 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6295 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6296 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6297 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6298 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6299 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6300 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6301 }; 6302 6303 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6304 u8 opcode[0x10]; 6305 u8 reserved_at_10[0x10]; 6306 6307 u8 reserved_at_20[0x10]; 6308 u8 op_mod[0x10]; 6309 6310 u8 reserved_at_40[0xa0]; 6311 6312 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6313 }; 6314 6315 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6316 u8 status[0x8]; 6317 u8 reserved_at_8[0x18]; 6318 6319 u8 syndrome[0x20]; 6320 6321 u8 reserved_at_40[0x40]; 6322 }; 6323 6324 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6325 u8 opcode[0x10]; 6326 u8 reserved_at_10[0x10]; 6327 6328 u8 reserved_20[0x10]; 6329 u8 op_mod[0x10]; 6330 6331 u8 packet_reformat_id[0x20]; 6332 6333 u8 reserved_60[0x20]; 6334 }; 6335 6336 struct mlx5_ifc_set_action_in_bits { 6337 u8 action_type[0x4]; 6338 u8 field[0xc]; 6339 u8 reserved_at_10[0x3]; 6340 u8 offset[0x5]; 6341 u8 reserved_at_18[0x3]; 6342 u8 length[0x5]; 6343 6344 u8 data[0x20]; 6345 }; 6346 6347 struct mlx5_ifc_add_action_in_bits { 6348 u8 action_type[0x4]; 6349 u8 field[0xc]; 6350 u8 reserved_at_10[0x10]; 6351 6352 u8 data[0x20]; 6353 }; 6354 6355 struct mlx5_ifc_copy_action_in_bits { 6356 u8 action_type[0x4]; 6357 u8 src_field[0xc]; 6358 u8 reserved_at_10[0x3]; 6359 u8 src_offset[0x5]; 6360 u8 reserved_at_18[0x3]; 6361 u8 length[0x5]; 6362 6363 u8 reserved_at_20[0x4]; 6364 u8 dst_field[0xc]; 6365 u8 reserved_at_30[0x3]; 6366 u8 dst_offset[0x5]; 6367 u8 reserved_at_38[0x8]; 6368 }; 6369 6370 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6371 struct mlx5_ifc_set_action_in_bits set_action_in; 6372 struct mlx5_ifc_add_action_in_bits add_action_in; 6373 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6374 u8 reserved_at_0[0x40]; 6375 }; 6376 6377 enum { 6378 MLX5_ACTION_TYPE_SET = 0x1, 6379 MLX5_ACTION_TYPE_ADD = 0x2, 6380 MLX5_ACTION_TYPE_COPY = 0x3, 6381 }; 6382 6383 enum { 6384 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6385 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6386 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6387 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6388 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6389 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6390 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6391 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6392 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6393 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6394 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6395 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6396 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6397 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6398 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6399 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6400 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6401 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6402 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6403 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6404 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6405 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6406 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6407 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6408 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6409 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6410 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6411 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6412 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6413 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6414 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6415 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6416 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6417 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6418 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6419 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6420 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6421 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6422 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6423 }; 6424 6425 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6426 u8 status[0x8]; 6427 u8 reserved_at_8[0x18]; 6428 6429 u8 syndrome[0x20]; 6430 6431 u8 modify_header_id[0x20]; 6432 6433 u8 reserved_at_60[0x20]; 6434 }; 6435 6436 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6437 u8 opcode[0x10]; 6438 u8 reserved_at_10[0x10]; 6439 6440 u8 reserved_at_20[0x10]; 6441 u8 op_mod[0x10]; 6442 6443 u8 reserved_at_40[0x20]; 6444 6445 u8 table_type[0x8]; 6446 u8 reserved_at_68[0x10]; 6447 u8 num_of_actions[0x8]; 6448 6449 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6450 }; 6451 6452 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6453 u8 status[0x8]; 6454 u8 reserved_at_8[0x18]; 6455 6456 u8 syndrome[0x20]; 6457 6458 u8 reserved_at_40[0x40]; 6459 }; 6460 6461 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6462 u8 opcode[0x10]; 6463 u8 reserved_at_10[0x10]; 6464 6465 u8 reserved_at_20[0x10]; 6466 u8 op_mod[0x10]; 6467 6468 u8 modify_header_id[0x20]; 6469 6470 u8 reserved_at_60[0x20]; 6471 }; 6472 6473 struct mlx5_ifc_query_modify_header_context_in_bits { 6474 u8 opcode[0x10]; 6475 u8 uid[0x10]; 6476 6477 u8 reserved_at_20[0x10]; 6478 u8 op_mod[0x10]; 6479 6480 u8 modify_header_id[0x20]; 6481 6482 u8 reserved_at_60[0xa0]; 6483 }; 6484 6485 struct mlx5_ifc_query_dct_out_bits { 6486 u8 status[0x8]; 6487 u8 reserved_at_8[0x18]; 6488 6489 u8 syndrome[0x20]; 6490 6491 u8 reserved_at_40[0x40]; 6492 6493 struct mlx5_ifc_dctc_bits dct_context_entry; 6494 6495 u8 reserved_at_280[0x180]; 6496 }; 6497 6498 struct mlx5_ifc_query_dct_in_bits { 6499 u8 opcode[0x10]; 6500 u8 reserved_at_10[0x10]; 6501 6502 u8 reserved_at_20[0x10]; 6503 u8 op_mod[0x10]; 6504 6505 u8 reserved_at_40[0x8]; 6506 u8 dctn[0x18]; 6507 6508 u8 reserved_at_60[0x20]; 6509 }; 6510 6511 struct mlx5_ifc_query_cq_out_bits { 6512 u8 status[0x8]; 6513 u8 reserved_at_8[0x18]; 6514 6515 u8 syndrome[0x20]; 6516 6517 u8 reserved_at_40[0x40]; 6518 6519 struct mlx5_ifc_cqc_bits cq_context; 6520 6521 u8 reserved_at_280[0x600]; 6522 6523 u8 pas[][0x40]; 6524 }; 6525 6526 struct mlx5_ifc_query_cq_in_bits { 6527 u8 opcode[0x10]; 6528 u8 reserved_at_10[0x10]; 6529 6530 u8 reserved_at_20[0x10]; 6531 u8 op_mod[0x10]; 6532 6533 u8 reserved_at_40[0x8]; 6534 u8 cqn[0x18]; 6535 6536 u8 reserved_at_60[0x20]; 6537 }; 6538 6539 struct mlx5_ifc_query_cong_status_out_bits { 6540 u8 status[0x8]; 6541 u8 reserved_at_8[0x18]; 6542 6543 u8 syndrome[0x20]; 6544 6545 u8 reserved_at_40[0x20]; 6546 6547 u8 enable[0x1]; 6548 u8 tag_enable[0x1]; 6549 u8 reserved_at_62[0x1e]; 6550 }; 6551 6552 struct mlx5_ifc_query_cong_status_in_bits { 6553 u8 opcode[0x10]; 6554 u8 reserved_at_10[0x10]; 6555 6556 u8 reserved_at_20[0x10]; 6557 u8 op_mod[0x10]; 6558 6559 u8 reserved_at_40[0x18]; 6560 u8 priority[0x4]; 6561 u8 cong_protocol[0x4]; 6562 6563 u8 reserved_at_60[0x20]; 6564 }; 6565 6566 struct mlx5_ifc_query_cong_statistics_out_bits { 6567 u8 status[0x8]; 6568 u8 reserved_at_8[0x18]; 6569 6570 u8 syndrome[0x20]; 6571 6572 u8 reserved_at_40[0x40]; 6573 6574 u8 rp_cur_flows[0x20]; 6575 6576 u8 sum_flows[0x20]; 6577 6578 u8 rp_cnp_ignored_high[0x20]; 6579 6580 u8 rp_cnp_ignored_low[0x20]; 6581 6582 u8 rp_cnp_handled_high[0x20]; 6583 6584 u8 rp_cnp_handled_low[0x20]; 6585 6586 u8 reserved_at_140[0x100]; 6587 6588 u8 time_stamp_high[0x20]; 6589 6590 u8 time_stamp_low[0x20]; 6591 6592 u8 accumulators_period[0x20]; 6593 6594 u8 np_ecn_marked_roce_packets_high[0x20]; 6595 6596 u8 np_ecn_marked_roce_packets_low[0x20]; 6597 6598 u8 np_cnp_sent_high[0x20]; 6599 6600 u8 np_cnp_sent_low[0x20]; 6601 6602 u8 reserved_at_320[0x560]; 6603 }; 6604 6605 struct mlx5_ifc_query_cong_statistics_in_bits { 6606 u8 opcode[0x10]; 6607 u8 reserved_at_10[0x10]; 6608 6609 u8 reserved_at_20[0x10]; 6610 u8 op_mod[0x10]; 6611 6612 u8 clear[0x1]; 6613 u8 reserved_at_41[0x1f]; 6614 6615 u8 reserved_at_60[0x20]; 6616 }; 6617 6618 struct mlx5_ifc_query_cong_params_out_bits { 6619 u8 status[0x8]; 6620 u8 reserved_at_8[0x18]; 6621 6622 u8 syndrome[0x20]; 6623 6624 u8 reserved_at_40[0x40]; 6625 6626 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6627 }; 6628 6629 struct mlx5_ifc_query_cong_params_in_bits { 6630 u8 opcode[0x10]; 6631 u8 reserved_at_10[0x10]; 6632 6633 u8 reserved_at_20[0x10]; 6634 u8 op_mod[0x10]; 6635 6636 u8 reserved_at_40[0x1c]; 6637 u8 cong_protocol[0x4]; 6638 6639 u8 reserved_at_60[0x20]; 6640 }; 6641 6642 struct mlx5_ifc_query_adapter_out_bits { 6643 u8 status[0x8]; 6644 u8 reserved_at_8[0x18]; 6645 6646 u8 syndrome[0x20]; 6647 6648 u8 reserved_at_40[0x40]; 6649 6650 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6651 }; 6652 6653 struct mlx5_ifc_query_adapter_in_bits { 6654 u8 opcode[0x10]; 6655 u8 reserved_at_10[0x10]; 6656 6657 u8 reserved_at_20[0x10]; 6658 u8 op_mod[0x10]; 6659 6660 u8 reserved_at_40[0x40]; 6661 }; 6662 6663 struct mlx5_ifc_qp_2rst_out_bits { 6664 u8 status[0x8]; 6665 u8 reserved_at_8[0x18]; 6666 6667 u8 syndrome[0x20]; 6668 6669 u8 reserved_at_40[0x40]; 6670 }; 6671 6672 struct mlx5_ifc_qp_2rst_in_bits { 6673 u8 opcode[0x10]; 6674 u8 uid[0x10]; 6675 6676 u8 reserved_at_20[0x10]; 6677 u8 op_mod[0x10]; 6678 6679 u8 reserved_at_40[0x8]; 6680 u8 qpn[0x18]; 6681 6682 u8 reserved_at_60[0x20]; 6683 }; 6684 6685 struct mlx5_ifc_qp_2err_out_bits { 6686 u8 status[0x8]; 6687 u8 reserved_at_8[0x18]; 6688 6689 u8 syndrome[0x20]; 6690 6691 u8 reserved_at_40[0x40]; 6692 }; 6693 6694 struct mlx5_ifc_qp_2err_in_bits { 6695 u8 opcode[0x10]; 6696 u8 uid[0x10]; 6697 6698 u8 reserved_at_20[0x10]; 6699 u8 op_mod[0x10]; 6700 6701 u8 reserved_at_40[0x8]; 6702 u8 qpn[0x18]; 6703 6704 u8 reserved_at_60[0x20]; 6705 }; 6706 6707 struct mlx5_ifc_page_fault_resume_out_bits { 6708 u8 status[0x8]; 6709 u8 reserved_at_8[0x18]; 6710 6711 u8 syndrome[0x20]; 6712 6713 u8 reserved_at_40[0x40]; 6714 }; 6715 6716 struct mlx5_ifc_page_fault_resume_in_bits { 6717 u8 opcode[0x10]; 6718 u8 reserved_at_10[0x10]; 6719 6720 u8 reserved_at_20[0x10]; 6721 u8 op_mod[0x10]; 6722 6723 u8 error[0x1]; 6724 u8 reserved_at_41[0x4]; 6725 u8 page_fault_type[0x3]; 6726 u8 wq_number[0x18]; 6727 6728 u8 reserved_at_60[0x8]; 6729 u8 token[0x18]; 6730 }; 6731 6732 struct mlx5_ifc_nop_out_bits { 6733 u8 status[0x8]; 6734 u8 reserved_at_8[0x18]; 6735 6736 u8 syndrome[0x20]; 6737 6738 u8 reserved_at_40[0x40]; 6739 }; 6740 6741 struct mlx5_ifc_nop_in_bits { 6742 u8 opcode[0x10]; 6743 u8 reserved_at_10[0x10]; 6744 6745 u8 reserved_at_20[0x10]; 6746 u8 op_mod[0x10]; 6747 6748 u8 reserved_at_40[0x40]; 6749 }; 6750 6751 struct mlx5_ifc_modify_vport_state_out_bits { 6752 u8 status[0x8]; 6753 u8 reserved_at_8[0x18]; 6754 6755 u8 syndrome[0x20]; 6756 6757 u8 reserved_at_40[0x40]; 6758 }; 6759 6760 struct mlx5_ifc_modify_vport_state_in_bits { 6761 u8 opcode[0x10]; 6762 u8 reserved_at_10[0x10]; 6763 6764 u8 reserved_at_20[0x10]; 6765 u8 op_mod[0x10]; 6766 6767 u8 other_vport[0x1]; 6768 u8 reserved_at_41[0xf]; 6769 u8 vport_number[0x10]; 6770 6771 u8 reserved_at_60[0x18]; 6772 u8 admin_state[0x4]; 6773 u8 reserved_at_7c[0x4]; 6774 }; 6775 6776 struct mlx5_ifc_modify_tis_out_bits { 6777 u8 status[0x8]; 6778 u8 reserved_at_8[0x18]; 6779 6780 u8 syndrome[0x20]; 6781 6782 u8 reserved_at_40[0x40]; 6783 }; 6784 6785 struct mlx5_ifc_modify_tis_bitmask_bits { 6786 u8 reserved_at_0[0x20]; 6787 6788 u8 reserved_at_20[0x1d]; 6789 u8 lag_tx_port_affinity[0x1]; 6790 u8 strict_lag_tx_port_affinity[0x1]; 6791 u8 prio[0x1]; 6792 }; 6793 6794 struct mlx5_ifc_modify_tis_in_bits { 6795 u8 opcode[0x10]; 6796 u8 uid[0x10]; 6797 6798 u8 reserved_at_20[0x10]; 6799 u8 op_mod[0x10]; 6800 6801 u8 reserved_at_40[0x8]; 6802 u8 tisn[0x18]; 6803 6804 u8 reserved_at_60[0x20]; 6805 6806 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6807 6808 u8 reserved_at_c0[0x40]; 6809 6810 struct mlx5_ifc_tisc_bits ctx; 6811 }; 6812 6813 struct mlx5_ifc_modify_tir_bitmask_bits { 6814 u8 reserved_at_0[0x20]; 6815 6816 u8 reserved_at_20[0x1b]; 6817 u8 self_lb_en[0x1]; 6818 u8 reserved_at_3c[0x1]; 6819 u8 hash[0x1]; 6820 u8 reserved_at_3e[0x1]; 6821 u8 packet_merge[0x1]; 6822 }; 6823 6824 struct mlx5_ifc_modify_tir_out_bits { 6825 u8 status[0x8]; 6826 u8 reserved_at_8[0x18]; 6827 6828 u8 syndrome[0x20]; 6829 6830 u8 reserved_at_40[0x40]; 6831 }; 6832 6833 struct mlx5_ifc_modify_tir_in_bits { 6834 u8 opcode[0x10]; 6835 u8 uid[0x10]; 6836 6837 u8 reserved_at_20[0x10]; 6838 u8 op_mod[0x10]; 6839 6840 u8 reserved_at_40[0x8]; 6841 u8 tirn[0x18]; 6842 6843 u8 reserved_at_60[0x20]; 6844 6845 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6846 6847 u8 reserved_at_c0[0x40]; 6848 6849 struct mlx5_ifc_tirc_bits ctx; 6850 }; 6851 6852 struct mlx5_ifc_modify_sq_out_bits { 6853 u8 status[0x8]; 6854 u8 reserved_at_8[0x18]; 6855 6856 u8 syndrome[0x20]; 6857 6858 u8 reserved_at_40[0x40]; 6859 }; 6860 6861 struct mlx5_ifc_modify_sq_in_bits { 6862 u8 opcode[0x10]; 6863 u8 uid[0x10]; 6864 6865 u8 reserved_at_20[0x10]; 6866 u8 op_mod[0x10]; 6867 6868 u8 sq_state[0x4]; 6869 u8 reserved_at_44[0x4]; 6870 u8 sqn[0x18]; 6871 6872 u8 reserved_at_60[0x20]; 6873 6874 u8 modify_bitmask[0x40]; 6875 6876 u8 reserved_at_c0[0x40]; 6877 6878 struct mlx5_ifc_sqc_bits ctx; 6879 }; 6880 6881 struct mlx5_ifc_modify_scheduling_element_out_bits { 6882 u8 status[0x8]; 6883 u8 reserved_at_8[0x18]; 6884 6885 u8 syndrome[0x20]; 6886 6887 u8 reserved_at_40[0x1c0]; 6888 }; 6889 6890 enum { 6891 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6892 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6893 }; 6894 6895 struct mlx5_ifc_modify_scheduling_element_in_bits { 6896 u8 opcode[0x10]; 6897 u8 reserved_at_10[0x10]; 6898 6899 u8 reserved_at_20[0x10]; 6900 u8 op_mod[0x10]; 6901 6902 u8 scheduling_hierarchy[0x8]; 6903 u8 reserved_at_48[0x18]; 6904 6905 u8 scheduling_element_id[0x20]; 6906 6907 u8 reserved_at_80[0x20]; 6908 6909 u8 modify_bitmask[0x20]; 6910 6911 u8 reserved_at_c0[0x40]; 6912 6913 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6914 6915 u8 reserved_at_300[0x100]; 6916 }; 6917 6918 struct mlx5_ifc_modify_rqt_out_bits { 6919 u8 status[0x8]; 6920 u8 reserved_at_8[0x18]; 6921 6922 u8 syndrome[0x20]; 6923 6924 u8 reserved_at_40[0x40]; 6925 }; 6926 6927 struct mlx5_ifc_rqt_bitmask_bits { 6928 u8 reserved_at_0[0x20]; 6929 6930 u8 reserved_at_20[0x1f]; 6931 u8 rqn_list[0x1]; 6932 }; 6933 6934 struct mlx5_ifc_modify_rqt_in_bits { 6935 u8 opcode[0x10]; 6936 u8 uid[0x10]; 6937 6938 u8 reserved_at_20[0x10]; 6939 u8 op_mod[0x10]; 6940 6941 u8 reserved_at_40[0x8]; 6942 u8 rqtn[0x18]; 6943 6944 u8 reserved_at_60[0x20]; 6945 6946 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6947 6948 u8 reserved_at_c0[0x40]; 6949 6950 struct mlx5_ifc_rqtc_bits ctx; 6951 }; 6952 6953 struct mlx5_ifc_modify_rq_out_bits { 6954 u8 status[0x8]; 6955 u8 reserved_at_8[0x18]; 6956 6957 u8 syndrome[0x20]; 6958 6959 u8 reserved_at_40[0x40]; 6960 }; 6961 6962 enum { 6963 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6964 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6965 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6966 }; 6967 6968 struct mlx5_ifc_modify_rq_in_bits { 6969 u8 opcode[0x10]; 6970 u8 uid[0x10]; 6971 6972 u8 reserved_at_20[0x10]; 6973 u8 op_mod[0x10]; 6974 6975 u8 rq_state[0x4]; 6976 u8 reserved_at_44[0x4]; 6977 u8 rqn[0x18]; 6978 6979 u8 reserved_at_60[0x20]; 6980 6981 u8 modify_bitmask[0x40]; 6982 6983 u8 reserved_at_c0[0x40]; 6984 6985 struct mlx5_ifc_rqc_bits ctx; 6986 }; 6987 6988 struct mlx5_ifc_modify_rmp_out_bits { 6989 u8 status[0x8]; 6990 u8 reserved_at_8[0x18]; 6991 6992 u8 syndrome[0x20]; 6993 6994 u8 reserved_at_40[0x40]; 6995 }; 6996 6997 struct mlx5_ifc_rmp_bitmask_bits { 6998 u8 reserved_at_0[0x20]; 6999 7000 u8 reserved_at_20[0x1f]; 7001 u8 lwm[0x1]; 7002 }; 7003 7004 struct mlx5_ifc_modify_rmp_in_bits { 7005 u8 opcode[0x10]; 7006 u8 uid[0x10]; 7007 7008 u8 reserved_at_20[0x10]; 7009 u8 op_mod[0x10]; 7010 7011 u8 rmp_state[0x4]; 7012 u8 reserved_at_44[0x4]; 7013 u8 rmpn[0x18]; 7014 7015 u8 reserved_at_60[0x20]; 7016 7017 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7018 7019 u8 reserved_at_c0[0x40]; 7020 7021 struct mlx5_ifc_rmpc_bits ctx; 7022 }; 7023 7024 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7025 u8 status[0x8]; 7026 u8 reserved_at_8[0x18]; 7027 7028 u8 syndrome[0x20]; 7029 7030 u8 reserved_at_40[0x40]; 7031 }; 7032 7033 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7034 u8 reserved_at_0[0x12]; 7035 u8 affiliation[0x1]; 7036 u8 reserved_at_13[0x1]; 7037 u8 disable_uc_local_lb[0x1]; 7038 u8 disable_mc_local_lb[0x1]; 7039 u8 node_guid[0x1]; 7040 u8 port_guid[0x1]; 7041 u8 min_inline[0x1]; 7042 u8 mtu[0x1]; 7043 u8 change_event[0x1]; 7044 u8 promisc[0x1]; 7045 u8 permanent_address[0x1]; 7046 u8 addresses_list[0x1]; 7047 u8 roce_en[0x1]; 7048 u8 reserved_at_1f[0x1]; 7049 }; 7050 7051 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7052 u8 opcode[0x10]; 7053 u8 reserved_at_10[0x10]; 7054 7055 u8 reserved_at_20[0x10]; 7056 u8 op_mod[0x10]; 7057 7058 u8 other_vport[0x1]; 7059 u8 reserved_at_41[0xf]; 7060 u8 vport_number[0x10]; 7061 7062 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7063 7064 u8 reserved_at_80[0x780]; 7065 7066 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7067 }; 7068 7069 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7070 u8 status[0x8]; 7071 u8 reserved_at_8[0x18]; 7072 7073 u8 syndrome[0x20]; 7074 7075 u8 reserved_at_40[0x40]; 7076 }; 7077 7078 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7079 u8 opcode[0x10]; 7080 u8 reserved_at_10[0x10]; 7081 7082 u8 reserved_at_20[0x10]; 7083 u8 op_mod[0x10]; 7084 7085 u8 other_vport[0x1]; 7086 u8 reserved_at_41[0xb]; 7087 u8 port_num[0x4]; 7088 u8 vport_number[0x10]; 7089 7090 u8 reserved_at_60[0x20]; 7091 7092 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7093 }; 7094 7095 struct mlx5_ifc_modify_cq_out_bits { 7096 u8 status[0x8]; 7097 u8 reserved_at_8[0x18]; 7098 7099 u8 syndrome[0x20]; 7100 7101 u8 reserved_at_40[0x40]; 7102 }; 7103 7104 enum { 7105 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7106 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7107 }; 7108 7109 struct mlx5_ifc_modify_cq_in_bits { 7110 u8 opcode[0x10]; 7111 u8 uid[0x10]; 7112 7113 u8 reserved_at_20[0x10]; 7114 u8 op_mod[0x10]; 7115 7116 u8 reserved_at_40[0x8]; 7117 u8 cqn[0x18]; 7118 7119 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7120 7121 struct mlx5_ifc_cqc_bits cq_context; 7122 7123 u8 reserved_at_280[0x60]; 7124 7125 u8 cq_umem_valid[0x1]; 7126 u8 reserved_at_2e1[0x1f]; 7127 7128 u8 reserved_at_300[0x580]; 7129 7130 u8 pas[][0x40]; 7131 }; 7132 7133 struct mlx5_ifc_modify_cong_status_out_bits { 7134 u8 status[0x8]; 7135 u8 reserved_at_8[0x18]; 7136 7137 u8 syndrome[0x20]; 7138 7139 u8 reserved_at_40[0x40]; 7140 }; 7141 7142 struct mlx5_ifc_modify_cong_status_in_bits { 7143 u8 opcode[0x10]; 7144 u8 reserved_at_10[0x10]; 7145 7146 u8 reserved_at_20[0x10]; 7147 u8 op_mod[0x10]; 7148 7149 u8 reserved_at_40[0x18]; 7150 u8 priority[0x4]; 7151 u8 cong_protocol[0x4]; 7152 7153 u8 enable[0x1]; 7154 u8 tag_enable[0x1]; 7155 u8 reserved_at_62[0x1e]; 7156 }; 7157 7158 struct mlx5_ifc_modify_cong_params_out_bits { 7159 u8 status[0x8]; 7160 u8 reserved_at_8[0x18]; 7161 7162 u8 syndrome[0x20]; 7163 7164 u8 reserved_at_40[0x40]; 7165 }; 7166 7167 struct mlx5_ifc_modify_cong_params_in_bits { 7168 u8 opcode[0x10]; 7169 u8 reserved_at_10[0x10]; 7170 7171 u8 reserved_at_20[0x10]; 7172 u8 op_mod[0x10]; 7173 7174 u8 reserved_at_40[0x1c]; 7175 u8 cong_protocol[0x4]; 7176 7177 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7178 7179 u8 reserved_at_80[0x80]; 7180 7181 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7182 }; 7183 7184 struct mlx5_ifc_manage_pages_out_bits { 7185 u8 status[0x8]; 7186 u8 reserved_at_8[0x18]; 7187 7188 u8 syndrome[0x20]; 7189 7190 u8 output_num_entries[0x20]; 7191 7192 u8 reserved_at_60[0x20]; 7193 7194 u8 pas[][0x40]; 7195 }; 7196 7197 enum { 7198 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7199 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7200 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7201 }; 7202 7203 struct mlx5_ifc_manage_pages_in_bits { 7204 u8 opcode[0x10]; 7205 u8 reserved_at_10[0x10]; 7206 7207 u8 reserved_at_20[0x10]; 7208 u8 op_mod[0x10]; 7209 7210 u8 embedded_cpu_function[0x1]; 7211 u8 reserved_at_41[0xf]; 7212 u8 function_id[0x10]; 7213 7214 u8 input_num_entries[0x20]; 7215 7216 u8 pas[][0x40]; 7217 }; 7218 7219 struct mlx5_ifc_mad_ifc_out_bits { 7220 u8 status[0x8]; 7221 u8 reserved_at_8[0x18]; 7222 7223 u8 syndrome[0x20]; 7224 7225 u8 reserved_at_40[0x40]; 7226 7227 u8 response_mad_packet[256][0x8]; 7228 }; 7229 7230 struct mlx5_ifc_mad_ifc_in_bits { 7231 u8 opcode[0x10]; 7232 u8 reserved_at_10[0x10]; 7233 7234 u8 reserved_at_20[0x10]; 7235 u8 op_mod[0x10]; 7236 7237 u8 remote_lid[0x10]; 7238 u8 reserved_at_50[0x8]; 7239 u8 port[0x8]; 7240 7241 u8 reserved_at_60[0x20]; 7242 7243 u8 mad[256][0x8]; 7244 }; 7245 7246 struct mlx5_ifc_init_hca_out_bits { 7247 u8 status[0x8]; 7248 u8 reserved_at_8[0x18]; 7249 7250 u8 syndrome[0x20]; 7251 7252 u8 reserved_at_40[0x40]; 7253 }; 7254 7255 struct mlx5_ifc_init_hca_in_bits { 7256 u8 opcode[0x10]; 7257 u8 reserved_at_10[0x10]; 7258 7259 u8 reserved_at_20[0x10]; 7260 u8 op_mod[0x10]; 7261 7262 u8 reserved_at_40[0x40]; 7263 u8 sw_owner_id[4][0x20]; 7264 }; 7265 7266 struct mlx5_ifc_init2rtr_qp_out_bits { 7267 u8 status[0x8]; 7268 u8 reserved_at_8[0x18]; 7269 7270 u8 syndrome[0x20]; 7271 7272 u8 reserved_at_40[0x20]; 7273 u8 ece[0x20]; 7274 }; 7275 7276 struct mlx5_ifc_init2rtr_qp_in_bits { 7277 u8 opcode[0x10]; 7278 u8 uid[0x10]; 7279 7280 u8 reserved_at_20[0x10]; 7281 u8 op_mod[0x10]; 7282 7283 u8 reserved_at_40[0x8]; 7284 u8 qpn[0x18]; 7285 7286 u8 reserved_at_60[0x20]; 7287 7288 u8 opt_param_mask[0x20]; 7289 7290 u8 ece[0x20]; 7291 7292 struct mlx5_ifc_qpc_bits qpc; 7293 7294 u8 reserved_at_800[0x80]; 7295 }; 7296 7297 struct mlx5_ifc_init2init_qp_out_bits { 7298 u8 status[0x8]; 7299 u8 reserved_at_8[0x18]; 7300 7301 u8 syndrome[0x20]; 7302 7303 u8 reserved_at_40[0x20]; 7304 u8 ece[0x20]; 7305 }; 7306 7307 struct mlx5_ifc_init2init_qp_in_bits { 7308 u8 opcode[0x10]; 7309 u8 uid[0x10]; 7310 7311 u8 reserved_at_20[0x10]; 7312 u8 op_mod[0x10]; 7313 7314 u8 reserved_at_40[0x8]; 7315 u8 qpn[0x18]; 7316 7317 u8 reserved_at_60[0x20]; 7318 7319 u8 opt_param_mask[0x20]; 7320 7321 u8 ece[0x20]; 7322 7323 struct mlx5_ifc_qpc_bits qpc; 7324 7325 u8 reserved_at_800[0x80]; 7326 }; 7327 7328 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7329 u8 status[0x8]; 7330 u8 reserved_at_8[0x18]; 7331 7332 u8 syndrome[0x20]; 7333 7334 u8 reserved_at_40[0x40]; 7335 7336 u8 packet_headers_log[128][0x8]; 7337 7338 u8 packet_syndrome[64][0x8]; 7339 }; 7340 7341 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7342 u8 opcode[0x10]; 7343 u8 reserved_at_10[0x10]; 7344 7345 u8 reserved_at_20[0x10]; 7346 u8 op_mod[0x10]; 7347 7348 u8 reserved_at_40[0x40]; 7349 }; 7350 7351 struct mlx5_ifc_gen_eqe_in_bits { 7352 u8 opcode[0x10]; 7353 u8 reserved_at_10[0x10]; 7354 7355 u8 reserved_at_20[0x10]; 7356 u8 op_mod[0x10]; 7357 7358 u8 reserved_at_40[0x18]; 7359 u8 eq_number[0x8]; 7360 7361 u8 reserved_at_60[0x20]; 7362 7363 u8 eqe[64][0x8]; 7364 }; 7365 7366 struct mlx5_ifc_gen_eq_out_bits { 7367 u8 status[0x8]; 7368 u8 reserved_at_8[0x18]; 7369 7370 u8 syndrome[0x20]; 7371 7372 u8 reserved_at_40[0x40]; 7373 }; 7374 7375 struct mlx5_ifc_enable_hca_out_bits { 7376 u8 status[0x8]; 7377 u8 reserved_at_8[0x18]; 7378 7379 u8 syndrome[0x20]; 7380 7381 u8 reserved_at_40[0x20]; 7382 }; 7383 7384 struct mlx5_ifc_enable_hca_in_bits { 7385 u8 opcode[0x10]; 7386 u8 reserved_at_10[0x10]; 7387 7388 u8 reserved_at_20[0x10]; 7389 u8 op_mod[0x10]; 7390 7391 u8 embedded_cpu_function[0x1]; 7392 u8 reserved_at_41[0xf]; 7393 u8 function_id[0x10]; 7394 7395 u8 reserved_at_60[0x20]; 7396 }; 7397 7398 struct mlx5_ifc_drain_dct_out_bits { 7399 u8 status[0x8]; 7400 u8 reserved_at_8[0x18]; 7401 7402 u8 syndrome[0x20]; 7403 7404 u8 reserved_at_40[0x40]; 7405 }; 7406 7407 struct mlx5_ifc_drain_dct_in_bits { 7408 u8 opcode[0x10]; 7409 u8 uid[0x10]; 7410 7411 u8 reserved_at_20[0x10]; 7412 u8 op_mod[0x10]; 7413 7414 u8 reserved_at_40[0x8]; 7415 u8 dctn[0x18]; 7416 7417 u8 reserved_at_60[0x20]; 7418 }; 7419 7420 struct mlx5_ifc_disable_hca_out_bits { 7421 u8 status[0x8]; 7422 u8 reserved_at_8[0x18]; 7423 7424 u8 syndrome[0x20]; 7425 7426 u8 reserved_at_40[0x20]; 7427 }; 7428 7429 struct mlx5_ifc_disable_hca_in_bits { 7430 u8 opcode[0x10]; 7431 u8 reserved_at_10[0x10]; 7432 7433 u8 reserved_at_20[0x10]; 7434 u8 op_mod[0x10]; 7435 7436 u8 embedded_cpu_function[0x1]; 7437 u8 reserved_at_41[0xf]; 7438 u8 function_id[0x10]; 7439 7440 u8 reserved_at_60[0x20]; 7441 }; 7442 7443 struct mlx5_ifc_detach_from_mcg_out_bits { 7444 u8 status[0x8]; 7445 u8 reserved_at_8[0x18]; 7446 7447 u8 syndrome[0x20]; 7448 7449 u8 reserved_at_40[0x40]; 7450 }; 7451 7452 struct mlx5_ifc_detach_from_mcg_in_bits { 7453 u8 opcode[0x10]; 7454 u8 uid[0x10]; 7455 7456 u8 reserved_at_20[0x10]; 7457 u8 op_mod[0x10]; 7458 7459 u8 reserved_at_40[0x8]; 7460 u8 qpn[0x18]; 7461 7462 u8 reserved_at_60[0x20]; 7463 7464 u8 multicast_gid[16][0x8]; 7465 }; 7466 7467 struct mlx5_ifc_destroy_xrq_out_bits { 7468 u8 status[0x8]; 7469 u8 reserved_at_8[0x18]; 7470 7471 u8 syndrome[0x20]; 7472 7473 u8 reserved_at_40[0x40]; 7474 }; 7475 7476 struct mlx5_ifc_destroy_xrq_in_bits { 7477 u8 opcode[0x10]; 7478 u8 uid[0x10]; 7479 7480 u8 reserved_at_20[0x10]; 7481 u8 op_mod[0x10]; 7482 7483 u8 reserved_at_40[0x8]; 7484 u8 xrqn[0x18]; 7485 7486 u8 reserved_at_60[0x20]; 7487 }; 7488 7489 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7490 u8 status[0x8]; 7491 u8 reserved_at_8[0x18]; 7492 7493 u8 syndrome[0x20]; 7494 7495 u8 reserved_at_40[0x40]; 7496 }; 7497 7498 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7499 u8 opcode[0x10]; 7500 u8 uid[0x10]; 7501 7502 u8 reserved_at_20[0x10]; 7503 u8 op_mod[0x10]; 7504 7505 u8 reserved_at_40[0x8]; 7506 u8 xrc_srqn[0x18]; 7507 7508 u8 reserved_at_60[0x20]; 7509 }; 7510 7511 struct mlx5_ifc_destroy_tis_out_bits { 7512 u8 status[0x8]; 7513 u8 reserved_at_8[0x18]; 7514 7515 u8 syndrome[0x20]; 7516 7517 u8 reserved_at_40[0x40]; 7518 }; 7519 7520 struct mlx5_ifc_destroy_tis_in_bits { 7521 u8 opcode[0x10]; 7522 u8 uid[0x10]; 7523 7524 u8 reserved_at_20[0x10]; 7525 u8 op_mod[0x10]; 7526 7527 u8 reserved_at_40[0x8]; 7528 u8 tisn[0x18]; 7529 7530 u8 reserved_at_60[0x20]; 7531 }; 7532 7533 struct mlx5_ifc_destroy_tir_out_bits { 7534 u8 status[0x8]; 7535 u8 reserved_at_8[0x18]; 7536 7537 u8 syndrome[0x20]; 7538 7539 u8 reserved_at_40[0x40]; 7540 }; 7541 7542 struct mlx5_ifc_destroy_tir_in_bits { 7543 u8 opcode[0x10]; 7544 u8 uid[0x10]; 7545 7546 u8 reserved_at_20[0x10]; 7547 u8 op_mod[0x10]; 7548 7549 u8 reserved_at_40[0x8]; 7550 u8 tirn[0x18]; 7551 7552 u8 reserved_at_60[0x20]; 7553 }; 7554 7555 struct mlx5_ifc_destroy_srq_out_bits { 7556 u8 status[0x8]; 7557 u8 reserved_at_8[0x18]; 7558 7559 u8 syndrome[0x20]; 7560 7561 u8 reserved_at_40[0x40]; 7562 }; 7563 7564 struct mlx5_ifc_destroy_srq_in_bits { 7565 u8 opcode[0x10]; 7566 u8 uid[0x10]; 7567 7568 u8 reserved_at_20[0x10]; 7569 u8 op_mod[0x10]; 7570 7571 u8 reserved_at_40[0x8]; 7572 u8 srqn[0x18]; 7573 7574 u8 reserved_at_60[0x20]; 7575 }; 7576 7577 struct mlx5_ifc_destroy_sq_out_bits { 7578 u8 status[0x8]; 7579 u8 reserved_at_8[0x18]; 7580 7581 u8 syndrome[0x20]; 7582 7583 u8 reserved_at_40[0x40]; 7584 }; 7585 7586 struct mlx5_ifc_destroy_sq_in_bits { 7587 u8 opcode[0x10]; 7588 u8 uid[0x10]; 7589 7590 u8 reserved_at_20[0x10]; 7591 u8 op_mod[0x10]; 7592 7593 u8 reserved_at_40[0x8]; 7594 u8 sqn[0x18]; 7595 7596 u8 reserved_at_60[0x20]; 7597 }; 7598 7599 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7600 u8 status[0x8]; 7601 u8 reserved_at_8[0x18]; 7602 7603 u8 syndrome[0x20]; 7604 7605 u8 reserved_at_40[0x1c0]; 7606 }; 7607 7608 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7609 u8 opcode[0x10]; 7610 u8 reserved_at_10[0x10]; 7611 7612 u8 reserved_at_20[0x10]; 7613 u8 op_mod[0x10]; 7614 7615 u8 scheduling_hierarchy[0x8]; 7616 u8 reserved_at_48[0x18]; 7617 7618 u8 scheduling_element_id[0x20]; 7619 7620 u8 reserved_at_80[0x180]; 7621 }; 7622 7623 struct mlx5_ifc_destroy_rqt_out_bits { 7624 u8 status[0x8]; 7625 u8 reserved_at_8[0x18]; 7626 7627 u8 syndrome[0x20]; 7628 7629 u8 reserved_at_40[0x40]; 7630 }; 7631 7632 struct mlx5_ifc_destroy_rqt_in_bits { 7633 u8 opcode[0x10]; 7634 u8 uid[0x10]; 7635 7636 u8 reserved_at_20[0x10]; 7637 u8 op_mod[0x10]; 7638 7639 u8 reserved_at_40[0x8]; 7640 u8 rqtn[0x18]; 7641 7642 u8 reserved_at_60[0x20]; 7643 }; 7644 7645 struct mlx5_ifc_destroy_rq_out_bits { 7646 u8 status[0x8]; 7647 u8 reserved_at_8[0x18]; 7648 7649 u8 syndrome[0x20]; 7650 7651 u8 reserved_at_40[0x40]; 7652 }; 7653 7654 struct mlx5_ifc_destroy_rq_in_bits { 7655 u8 opcode[0x10]; 7656 u8 uid[0x10]; 7657 7658 u8 reserved_at_20[0x10]; 7659 u8 op_mod[0x10]; 7660 7661 u8 reserved_at_40[0x8]; 7662 u8 rqn[0x18]; 7663 7664 u8 reserved_at_60[0x20]; 7665 }; 7666 7667 struct mlx5_ifc_set_delay_drop_params_in_bits { 7668 u8 opcode[0x10]; 7669 u8 reserved_at_10[0x10]; 7670 7671 u8 reserved_at_20[0x10]; 7672 u8 op_mod[0x10]; 7673 7674 u8 reserved_at_40[0x20]; 7675 7676 u8 reserved_at_60[0x10]; 7677 u8 delay_drop_timeout[0x10]; 7678 }; 7679 7680 struct mlx5_ifc_set_delay_drop_params_out_bits { 7681 u8 status[0x8]; 7682 u8 reserved_at_8[0x18]; 7683 7684 u8 syndrome[0x20]; 7685 7686 u8 reserved_at_40[0x40]; 7687 }; 7688 7689 struct mlx5_ifc_destroy_rmp_out_bits { 7690 u8 status[0x8]; 7691 u8 reserved_at_8[0x18]; 7692 7693 u8 syndrome[0x20]; 7694 7695 u8 reserved_at_40[0x40]; 7696 }; 7697 7698 struct mlx5_ifc_destroy_rmp_in_bits { 7699 u8 opcode[0x10]; 7700 u8 uid[0x10]; 7701 7702 u8 reserved_at_20[0x10]; 7703 u8 op_mod[0x10]; 7704 7705 u8 reserved_at_40[0x8]; 7706 u8 rmpn[0x18]; 7707 7708 u8 reserved_at_60[0x20]; 7709 }; 7710 7711 struct mlx5_ifc_destroy_qp_out_bits { 7712 u8 status[0x8]; 7713 u8 reserved_at_8[0x18]; 7714 7715 u8 syndrome[0x20]; 7716 7717 u8 reserved_at_40[0x40]; 7718 }; 7719 7720 struct mlx5_ifc_destroy_qp_in_bits { 7721 u8 opcode[0x10]; 7722 u8 uid[0x10]; 7723 7724 u8 reserved_at_20[0x10]; 7725 u8 op_mod[0x10]; 7726 7727 u8 reserved_at_40[0x8]; 7728 u8 qpn[0x18]; 7729 7730 u8 reserved_at_60[0x20]; 7731 }; 7732 7733 struct mlx5_ifc_destroy_psv_out_bits { 7734 u8 status[0x8]; 7735 u8 reserved_at_8[0x18]; 7736 7737 u8 syndrome[0x20]; 7738 7739 u8 reserved_at_40[0x40]; 7740 }; 7741 7742 struct mlx5_ifc_destroy_psv_in_bits { 7743 u8 opcode[0x10]; 7744 u8 reserved_at_10[0x10]; 7745 7746 u8 reserved_at_20[0x10]; 7747 u8 op_mod[0x10]; 7748 7749 u8 reserved_at_40[0x8]; 7750 u8 psvn[0x18]; 7751 7752 u8 reserved_at_60[0x20]; 7753 }; 7754 7755 struct mlx5_ifc_destroy_mkey_out_bits { 7756 u8 status[0x8]; 7757 u8 reserved_at_8[0x18]; 7758 7759 u8 syndrome[0x20]; 7760 7761 u8 reserved_at_40[0x40]; 7762 }; 7763 7764 struct mlx5_ifc_destroy_mkey_in_bits { 7765 u8 opcode[0x10]; 7766 u8 uid[0x10]; 7767 7768 u8 reserved_at_20[0x10]; 7769 u8 op_mod[0x10]; 7770 7771 u8 reserved_at_40[0x8]; 7772 u8 mkey_index[0x18]; 7773 7774 u8 reserved_at_60[0x20]; 7775 }; 7776 7777 struct mlx5_ifc_destroy_flow_table_out_bits { 7778 u8 status[0x8]; 7779 u8 reserved_at_8[0x18]; 7780 7781 u8 syndrome[0x20]; 7782 7783 u8 reserved_at_40[0x40]; 7784 }; 7785 7786 struct mlx5_ifc_destroy_flow_table_in_bits { 7787 u8 opcode[0x10]; 7788 u8 reserved_at_10[0x10]; 7789 7790 u8 reserved_at_20[0x10]; 7791 u8 op_mod[0x10]; 7792 7793 u8 other_vport[0x1]; 7794 u8 reserved_at_41[0xf]; 7795 u8 vport_number[0x10]; 7796 7797 u8 reserved_at_60[0x20]; 7798 7799 u8 table_type[0x8]; 7800 u8 reserved_at_88[0x18]; 7801 7802 u8 reserved_at_a0[0x8]; 7803 u8 table_id[0x18]; 7804 7805 u8 reserved_at_c0[0x140]; 7806 }; 7807 7808 struct mlx5_ifc_destroy_flow_group_out_bits { 7809 u8 status[0x8]; 7810 u8 reserved_at_8[0x18]; 7811 7812 u8 syndrome[0x20]; 7813 7814 u8 reserved_at_40[0x40]; 7815 }; 7816 7817 struct mlx5_ifc_destroy_flow_group_in_bits { 7818 u8 opcode[0x10]; 7819 u8 reserved_at_10[0x10]; 7820 7821 u8 reserved_at_20[0x10]; 7822 u8 op_mod[0x10]; 7823 7824 u8 other_vport[0x1]; 7825 u8 reserved_at_41[0xf]; 7826 u8 vport_number[0x10]; 7827 7828 u8 reserved_at_60[0x20]; 7829 7830 u8 table_type[0x8]; 7831 u8 reserved_at_88[0x18]; 7832 7833 u8 reserved_at_a0[0x8]; 7834 u8 table_id[0x18]; 7835 7836 u8 group_id[0x20]; 7837 7838 u8 reserved_at_e0[0x120]; 7839 }; 7840 7841 struct mlx5_ifc_destroy_eq_out_bits { 7842 u8 status[0x8]; 7843 u8 reserved_at_8[0x18]; 7844 7845 u8 syndrome[0x20]; 7846 7847 u8 reserved_at_40[0x40]; 7848 }; 7849 7850 struct mlx5_ifc_destroy_eq_in_bits { 7851 u8 opcode[0x10]; 7852 u8 reserved_at_10[0x10]; 7853 7854 u8 reserved_at_20[0x10]; 7855 u8 op_mod[0x10]; 7856 7857 u8 reserved_at_40[0x18]; 7858 u8 eq_number[0x8]; 7859 7860 u8 reserved_at_60[0x20]; 7861 }; 7862 7863 struct mlx5_ifc_destroy_dct_out_bits { 7864 u8 status[0x8]; 7865 u8 reserved_at_8[0x18]; 7866 7867 u8 syndrome[0x20]; 7868 7869 u8 reserved_at_40[0x40]; 7870 }; 7871 7872 struct mlx5_ifc_destroy_dct_in_bits { 7873 u8 opcode[0x10]; 7874 u8 uid[0x10]; 7875 7876 u8 reserved_at_20[0x10]; 7877 u8 op_mod[0x10]; 7878 7879 u8 reserved_at_40[0x8]; 7880 u8 dctn[0x18]; 7881 7882 u8 reserved_at_60[0x20]; 7883 }; 7884 7885 struct mlx5_ifc_destroy_cq_out_bits { 7886 u8 status[0x8]; 7887 u8 reserved_at_8[0x18]; 7888 7889 u8 syndrome[0x20]; 7890 7891 u8 reserved_at_40[0x40]; 7892 }; 7893 7894 struct mlx5_ifc_destroy_cq_in_bits { 7895 u8 opcode[0x10]; 7896 u8 uid[0x10]; 7897 7898 u8 reserved_at_20[0x10]; 7899 u8 op_mod[0x10]; 7900 7901 u8 reserved_at_40[0x8]; 7902 u8 cqn[0x18]; 7903 7904 u8 reserved_at_60[0x20]; 7905 }; 7906 7907 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7908 u8 status[0x8]; 7909 u8 reserved_at_8[0x18]; 7910 7911 u8 syndrome[0x20]; 7912 7913 u8 reserved_at_40[0x40]; 7914 }; 7915 7916 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7917 u8 opcode[0x10]; 7918 u8 reserved_at_10[0x10]; 7919 7920 u8 reserved_at_20[0x10]; 7921 u8 op_mod[0x10]; 7922 7923 u8 reserved_at_40[0x20]; 7924 7925 u8 reserved_at_60[0x10]; 7926 u8 vxlan_udp_port[0x10]; 7927 }; 7928 7929 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7930 u8 status[0x8]; 7931 u8 reserved_at_8[0x18]; 7932 7933 u8 syndrome[0x20]; 7934 7935 u8 reserved_at_40[0x40]; 7936 }; 7937 7938 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7939 u8 opcode[0x10]; 7940 u8 reserved_at_10[0x10]; 7941 7942 u8 reserved_at_20[0x10]; 7943 u8 op_mod[0x10]; 7944 7945 u8 reserved_at_40[0x60]; 7946 7947 u8 reserved_at_a0[0x8]; 7948 u8 table_index[0x18]; 7949 7950 u8 reserved_at_c0[0x140]; 7951 }; 7952 7953 struct mlx5_ifc_delete_fte_out_bits { 7954 u8 status[0x8]; 7955 u8 reserved_at_8[0x18]; 7956 7957 u8 syndrome[0x20]; 7958 7959 u8 reserved_at_40[0x40]; 7960 }; 7961 7962 struct mlx5_ifc_delete_fte_in_bits { 7963 u8 opcode[0x10]; 7964 u8 reserved_at_10[0x10]; 7965 7966 u8 reserved_at_20[0x10]; 7967 u8 op_mod[0x10]; 7968 7969 u8 other_vport[0x1]; 7970 u8 reserved_at_41[0xf]; 7971 u8 vport_number[0x10]; 7972 7973 u8 reserved_at_60[0x20]; 7974 7975 u8 table_type[0x8]; 7976 u8 reserved_at_88[0x18]; 7977 7978 u8 reserved_at_a0[0x8]; 7979 u8 table_id[0x18]; 7980 7981 u8 reserved_at_c0[0x40]; 7982 7983 u8 flow_index[0x20]; 7984 7985 u8 reserved_at_120[0xe0]; 7986 }; 7987 7988 struct mlx5_ifc_dealloc_xrcd_out_bits { 7989 u8 status[0x8]; 7990 u8 reserved_at_8[0x18]; 7991 7992 u8 syndrome[0x20]; 7993 7994 u8 reserved_at_40[0x40]; 7995 }; 7996 7997 struct mlx5_ifc_dealloc_xrcd_in_bits { 7998 u8 opcode[0x10]; 7999 u8 uid[0x10]; 8000 8001 u8 reserved_at_20[0x10]; 8002 u8 op_mod[0x10]; 8003 8004 u8 reserved_at_40[0x8]; 8005 u8 xrcd[0x18]; 8006 8007 u8 reserved_at_60[0x20]; 8008 }; 8009 8010 struct mlx5_ifc_dealloc_uar_out_bits { 8011 u8 status[0x8]; 8012 u8 reserved_at_8[0x18]; 8013 8014 u8 syndrome[0x20]; 8015 8016 u8 reserved_at_40[0x40]; 8017 }; 8018 8019 struct mlx5_ifc_dealloc_uar_in_bits { 8020 u8 opcode[0x10]; 8021 u8 uid[0x10]; 8022 8023 u8 reserved_at_20[0x10]; 8024 u8 op_mod[0x10]; 8025 8026 u8 reserved_at_40[0x8]; 8027 u8 uar[0x18]; 8028 8029 u8 reserved_at_60[0x20]; 8030 }; 8031 8032 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8033 u8 status[0x8]; 8034 u8 reserved_at_8[0x18]; 8035 8036 u8 syndrome[0x20]; 8037 8038 u8 reserved_at_40[0x40]; 8039 }; 8040 8041 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8042 u8 opcode[0x10]; 8043 u8 uid[0x10]; 8044 8045 u8 reserved_at_20[0x10]; 8046 u8 op_mod[0x10]; 8047 8048 u8 reserved_at_40[0x8]; 8049 u8 transport_domain[0x18]; 8050 8051 u8 reserved_at_60[0x20]; 8052 }; 8053 8054 struct mlx5_ifc_dealloc_q_counter_out_bits { 8055 u8 status[0x8]; 8056 u8 reserved_at_8[0x18]; 8057 8058 u8 syndrome[0x20]; 8059 8060 u8 reserved_at_40[0x40]; 8061 }; 8062 8063 struct mlx5_ifc_dealloc_q_counter_in_bits { 8064 u8 opcode[0x10]; 8065 u8 reserved_at_10[0x10]; 8066 8067 u8 reserved_at_20[0x10]; 8068 u8 op_mod[0x10]; 8069 8070 u8 reserved_at_40[0x18]; 8071 u8 counter_set_id[0x8]; 8072 8073 u8 reserved_at_60[0x20]; 8074 }; 8075 8076 struct mlx5_ifc_dealloc_pd_out_bits { 8077 u8 status[0x8]; 8078 u8 reserved_at_8[0x18]; 8079 8080 u8 syndrome[0x20]; 8081 8082 u8 reserved_at_40[0x40]; 8083 }; 8084 8085 struct mlx5_ifc_dealloc_pd_in_bits { 8086 u8 opcode[0x10]; 8087 u8 uid[0x10]; 8088 8089 u8 reserved_at_20[0x10]; 8090 u8 op_mod[0x10]; 8091 8092 u8 reserved_at_40[0x8]; 8093 u8 pd[0x18]; 8094 8095 u8 reserved_at_60[0x20]; 8096 }; 8097 8098 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8099 u8 status[0x8]; 8100 u8 reserved_at_8[0x18]; 8101 8102 u8 syndrome[0x20]; 8103 8104 u8 reserved_at_40[0x40]; 8105 }; 8106 8107 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8108 u8 opcode[0x10]; 8109 u8 reserved_at_10[0x10]; 8110 8111 u8 reserved_at_20[0x10]; 8112 u8 op_mod[0x10]; 8113 8114 u8 flow_counter_id[0x20]; 8115 8116 u8 reserved_at_60[0x20]; 8117 }; 8118 8119 struct mlx5_ifc_create_xrq_out_bits { 8120 u8 status[0x8]; 8121 u8 reserved_at_8[0x18]; 8122 8123 u8 syndrome[0x20]; 8124 8125 u8 reserved_at_40[0x8]; 8126 u8 xrqn[0x18]; 8127 8128 u8 reserved_at_60[0x20]; 8129 }; 8130 8131 struct mlx5_ifc_create_xrq_in_bits { 8132 u8 opcode[0x10]; 8133 u8 uid[0x10]; 8134 8135 u8 reserved_at_20[0x10]; 8136 u8 op_mod[0x10]; 8137 8138 u8 reserved_at_40[0x40]; 8139 8140 struct mlx5_ifc_xrqc_bits xrq_context; 8141 }; 8142 8143 struct mlx5_ifc_create_xrc_srq_out_bits { 8144 u8 status[0x8]; 8145 u8 reserved_at_8[0x18]; 8146 8147 u8 syndrome[0x20]; 8148 8149 u8 reserved_at_40[0x8]; 8150 u8 xrc_srqn[0x18]; 8151 8152 u8 reserved_at_60[0x20]; 8153 }; 8154 8155 struct mlx5_ifc_create_xrc_srq_in_bits { 8156 u8 opcode[0x10]; 8157 u8 uid[0x10]; 8158 8159 u8 reserved_at_20[0x10]; 8160 u8 op_mod[0x10]; 8161 8162 u8 reserved_at_40[0x40]; 8163 8164 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8165 8166 u8 reserved_at_280[0x60]; 8167 8168 u8 xrc_srq_umem_valid[0x1]; 8169 u8 reserved_at_2e1[0x1f]; 8170 8171 u8 reserved_at_300[0x580]; 8172 8173 u8 pas[][0x40]; 8174 }; 8175 8176 struct mlx5_ifc_create_tis_out_bits { 8177 u8 status[0x8]; 8178 u8 reserved_at_8[0x18]; 8179 8180 u8 syndrome[0x20]; 8181 8182 u8 reserved_at_40[0x8]; 8183 u8 tisn[0x18]; 8184 8185 u8 reserved_at_60[0x20]; 8186 }; 8187 8188 struct mlx5_ifc_create_tis_in_bits { 8189 u8 opcode[0x10]; 8190 u8 uid[0x10]; 8191 8192 u8 reserved_at_20[0x10]; 8193 u8 op_mod[0x10]; 8194 8195 u8 reserved_at_40[0xc0]; 8196 8197 struct mlx5_ifc_tisc_bits ctx; 8198 }; 8199 8200 struct mlx5_ifc_create_tir_out_bits { 8201 u8 status[0x8]; 8202 u8 icm_address_63_40[0x18]; 8203 8204 u8 syndrome[0x20]; 8205 8206 u8 icm_address_39_32[0x8]; 8207 u8 tirn[0x18]; 8208 8209 u8 icm_address_31_0[0x20]; 8210 }; 8211 8212 struct mlx5_ifc_create_tir_in_bits { 8213 u8 opcode[0x10]; 8214 u8 uid[0x10]; 8215 8216 u8 reserved_at_20[0x10]; 8217 u8 op_mod[0x10]; 8218 8219 u8 reserved_at_40[0xc0]; 8220 8221 struct mlx5_ifc_tirc_bits ctx; 8222 }; 8223 8224 struct mlx5_ifc_create_srq_out_bits { 8225 u8 status[0x8]; 8226 u8 reserved_at_8[0x18]; 8227 8228 u8 syndrome[0x20]; 8229 8230 u8 reserved_at_40[0x8]; 8231 u8 srqn[0x18]; 8232 8233 u8 reserved_at_60[0x20]; 8234 }; 8235 8236 struct mlx5_ifc_create_srq_in_bits { 8237 u8 opcode[0x10]; 8238 u8 uid[0x10]; 8239 8240 u8 reserved_at_20[0x10]; 8241 u8 op_mod[0x10]; 8242 8243 u8 reserved_at_40[0x40]; 8244 8245 struct mlx5_ifc_srqc_bits srq_context_entry; 8246 8247 u8 reserved_at_280[0x600]; 8248 8249 u8 pas[][0x40]; 8250 }; 8251 8252 struct mlx5_ifc_create_sq_out_bits { 8253 u8 status[0x8]; 8254 u8 reserved_at_8[0x18]; 8255 8256 u8 syndrome[0x20]; 8257 8258 u8 reserved_at_40[0x8]; 8259 u8 sqn[0x18]; 8260 8261 u8 reserved_at_60[0x20]; 8262 }; 8263 8264 struct mlx5_ifc_create_sq_in_bits { 8265 u8 opcode[0x10]; 8266 u8 uid[0x10]; 8267 8268 u8 reserved_at_20[0x10]; 8269 u8 op_mod[0x10]; 8270 8271 u8 reserved_at_40[0xc0]; 8272 8273 struct mlx5_ifc_sqc_bits ctx; 8274 }; 8275 8276 struct mlx5_ifc_create_scheduling_element_out_bits { 8277 u8 status[0x8]; 8278 u8 reserved_at_8[0x18]; 8279 8280 u8 syndrome[0x20]; 8281 8282 u8 reserved_at_40[0x40]; 8283 8284 u8 scheduling_element_id[0x20]; 8285 8286 u8 reserved_at_a0[0x160]; 8287 }; 8288 8289 struct mlx5_ifc_create_scheduling_element_in_bits { 8290 u8 opcode[0x10]; 8291 u8 reserved_at_10[0x10]; 8292 8293 u8 reserved_at_20[0x10]; 8294 u8 op_mod[0x10]; 8295 8296 u8 scheduling_hierarchy[0x8]; 8297 u8 reserved_at_48[0x18]; 8298 8299 u8 reserved_at_60[0xa0]; 8300 8301 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8302 8303 u8 reserved_at_300[0x100]; 8304 }; 8305 8306 struct mlx5_ifc_create_rqt_out_bits { 8307 u8 status[0x8]; 8308 u8 reserved_at_8[0x18]; 8309 8310 u8 syndrome[0x20]; 8311 8312 u8 reserved_at_40[0x8]; 8313 u8 rqtn[0x18]; 8314 8315 u8 reserved_at_60[0x20]; 8316 }; 8317 8318 struct mlx5_ifc_create_rqt_in_bits { 8319 u8 opcode[0x10]; 8320 u8 uid[0x10]; 8321 8322 u8 reserved_at_20[0x10]; 8323 u8 op_mod[0x10]; 8324 8325 u8 reserved_at_40[0xc0]; 8326 8327 struct mlx5_ifc_rqtc_bits rqt_context; 8328 }; 8329 8330 struct mlx5_ifc_create_rq_out_bits { 8331 u8 status[0x8]; 8332 u8 reserved_at_8[0x18]; 8333 8334 u8 syndrome[0x20]; 8335 8336 u8 reserved_at_40[0x8]; 8337 u8 rqn[0x18]; 8338 8339 u8 reserved_at_60[0x20]; 8340 }; 8341 8342 struct mlx5_ifc_create_rq_in_bits { 8343 u8 opcode[0x10]; 8344 u8 uid[0x10]; 8345 8346 u8 reserved_at_20[0x10]; 8347 u8 op_mod[0x10]; 8348 8349 u8 reserved_at_40[0xc0]; 8350 8351 struct mlx5_ifc_rqc_bits ctx; 8352 }; 8353 8354 struct mlx5_ifc_create_rmp_out_bits { 8355 u8 status[0x8]; 8356 u8 reserved_at_8[0x18]; 8357 8358 u8 syndrome[0x20]; 8359 8360 u8 reserved_at_40[0x8]; 8361 u8 rmpn[0x18]; 8362 8363 u8 reserved_at_60[0x20]; 8364 }; 8365 8366 struct mlx5_ifc_create_rmp_in_bits { 8367 u8 opcode[0x10]; 8368 u8 uid[0x10]; 8369 8370 u8 reserved_at_20[0x10]; 8371 u8 op_mod[0x10]; 8372 8373 u8 reserved_at_40[0xc0]; 8374 8375 struct mlx5_ifc_rmpc_bits ctx; 8376 }; 8377 8378 struct mlx5_ifc_create_qp_out_bits { 8379 u8 status[0x8]; 8380 u8 reserved_at_8[0x18]; 8381 8382 u8 syndrome[0x20]; 8383 8384 u8 reserved_at_40[0x8]; 8385 u8 qpn[0x18]; 8386 8387 u8 ece[0x20]; 8388 }; 8389 8390 struct mlx5_ifc_create_qp_in_bits { 8391 u8 opcode[0x10]; 8392 u8 uid[0x10]; 8393 8394 u8 reserved_at_20[0x10]; 8395 u8 op_mod[0x10]; 8396 8397 u8 reserved_at_40[0x8]; 8398 u8 input_qpn[0x18]; 8399 8400 u8 reserved_at_60[0x20]; 8401 u8 opt_param_mask[0x20]; 8402 8403 u8 ece[0x20]; 8404 8405 struct mlx5_ifc_qpc_bits qpc; 8406 8407 u8 reserved_at_800[0x60]; 8408 8409 u8 wq_umem_valid[0x1]; 8410 u8 reserved_at_861[0x1f]; 8411 8412 u8 pas[][0x40]; 8413 }; 8414 8415 struct mlx5_ifc_create_psv_out_bits { 8416 u8 status[0x8]; 8417 u8 reserved_at_8[0x18]; 8418 8419 u8 syndrome[0x20]; 8420 8421 u8 reserved_at_40[0x40]; 8422 8423 u8 reserved_at_80[0x8]; 8424 u8 psv0_index[0x18]; 8425 8426 u8 reserved_at_a0[0x8]; 8427 u8 psv1_index[0x18]; 8428 8429 u8 reserved_at_c0[0x8]; 8430 u8 psv2_index[0x18]; 8431 8432 u8 reserved_at_e0[0x8]; 8433 u8 psv3_index[0x18]; 8434 }; 8435 8436 struct mlx5_ifc_create_psv_in_bits { 8437 u8 opcode[0x10]; 8438 u8 reserved_at_10[0x10]; 8439 8440 u8 reserved_at_20[0x10]; 8441 u8 op_mod[0x10]; 8442 8443 u8 num_psv[0x4]; 8444 u8 reserved_at_44[0x4]; 8445 u8 pd[0x18]; 8446 8447 u8 reserved_at_60[0x20]; 8448 }; 8449 8450 struct mlx5_ifc_create_mkey_out_bits { 8451 u8 status[0x8]; 8452 u8 reserved_at_8[0x18]; 8453 8454 u8 syndrome[0x20]; 8455 8456 u8 reserved_at_40[0x8]; 8457 u8 mkey_index[0x18]; 8458 8459 u8 reserved_at_60[0x20]; 8460 }; 8461 8462 struct mlx5_ifc_create_mkey_in_bits { 8463 u8 opcode[0x10]; 8464 u8 uid[0x10]; 8465 8466 u8 reserved_at_20[0x10]; 8467 u8 op_mod[0x10]; 8468 8469 u8 reserved_at_40[0x20]; 8470 8471 u8 pg_access[0x1]; 8472 u8 mkey_umem_valid[0x1]; 8473 u8 reserved_at_62[0x1e]; 8474 8475 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8476 8477 u8 reserved_at_280[0x80]; 8478 8479 u8 translations_octword_actual_size[0x20]; 8480 8481 u8 reserved_at_320[0x560]; 8482 8483 u8 klm_pas_mtt[][0x20]; 8484 }; 8485 8486 enum { 8487 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8488 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8489 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8490 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8491 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8492 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8493 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8494 }; 8495 8496 struct mlx5_ifc_create_flow_table_out_bits { 8497 u8 status[0x8]; 8498 u8 icm_address_63_40[0x18]; 8499 8500 u8 syndrome[0x20]; 8501 8502 u8 icm_address_39_32[0x8]; 8503 u8 table_id[0x18]; 8504 8505 u8 icm_address_31_0[0x20]; 8506 }; 8507 8508 struct mlx5_ifc_create_flow_table_in_bits { 8509 u8 opcode[0x10]; 8510 u8 reserved_at_10[0x10]; 8511 8512 u8 reserved_at_20[0x10]; 8513 u8 op_mod[0x10]; 8514 8515 u8 other_vport[0x1]; 8516 u8 reserved_at_41[0xf]; 8517 u8 vport_number[0x10]; 8518 8519 u8 reserved_at_60[0x20]; 8520 8521 u8 table_type[0x8]; 8522 u8 reserved_at_88[0x18]; 8523 8524 u8 reserved_at_a0[0x20]; 8525 8526 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8527 }; 8528 8529 struct mlx5_ifc_create_flow_group_out_bits { 8530 u8 status[0x8]; 8531 u8 reserved_at_8[0x18]; 8532 8533 u8 syndrome[0x20]; 8534 8535 u8 reserved_at_40[0x8]; 8536 u8 group_id[0x18]; 8537 8538 u8 reserved_at_60[0x20]; 8539 }; 8540 8541 enum { 8542 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8543 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8544 }; 8545 8546 enum { 8547 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8548 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8549 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8550 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8551 }; 8552 8553 struct mlx5_ifc_create_flow_group_in_bits { 8554 u8 opcode[0x10]; 8555 u8 reserved_at_10[0x10]; 8556 8557 u8 reserved_at_20[0x10]; 8558 u8 op_mod[0x10]; 8559 8560 u8 other_vport[0x1]; 8561 u8 reserved_at_41[0xf]; 8562 u8 vport_number[0x10]; 8563 8564 u8 reserved_at_60[0x20]; 8565 8566 u8 table_type[0x8]; 8567 u8 reserved_at_88[0x4]; 8568 u8 group_type[0x4]; 8569 u8 reserved_at_90[0x10]; 8570 8571 u8 reserved_at_a0[0x8]; 8572 u8 table_id[0x18]; 8573 8574 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8575 8576 u8 reserved_at_c1[0x1f]; 8577 8578 u8 start_flow_index[0x20]; 8579 8580 u8 reserved_at_100[0x20]; 8581 8582 u8 end_flow_index[0x20]; 8583 8584 u8 reserved_at_140[0x10]; 8585 u8 match_definer_id[0x10]; 8586 8587 u8 reserved_at_160[0x80]; 8588 8589 u8 reserved_at_1e0[0x18]; 8590 u8 match_criteria_enable[0x8]; 8591 8592 struct mlx5_ifc_fte_match_param_bits match_criteria; 8593 8594 u8 reserved_at_1200[0xe00]; 8595 }; 8596 8597 struct mlx5_ifc_create_eq_out_bits { 8598 u8 status[0x8]; 8599 u8 reserved_at_8[0x18]; 8600 8601 u8 syndrome[0x20]; 8602 8603 u8 reserved_at_40[0x18]; 8604 u8 eq_number[0x8]; 8605 8606 u8 reserved_at_60[0x20]; 8607 }; 8608 8609 struct mlx5_ifc_create_eq_in_bits { 8610 u8 opcode[0x10]; 8611 u8 uid[0x10]; 8612 8613 u8 reserved_at_20[0x10]; 8614 u8 op_mod[0x10]; 8615 8616 u8 reserved_at_40[0x40]; 8617 8618 struct mlx5_ifc_eqc_bits eq_context_entry; 8619 8620 u8 reserved_at_280[0x40]; 8621 8622 u8 event_bitmask[4][0x40]; 8623 8624 u8 reserved_at_3c0[0x4c0]; 8625 8626 u8 pas[][0x40]; 8627 }; 8628 8629 struct mlx5_ifc_create_dct_out_bits { 8630 u8 status[0x8]; 8631 u8 reserved_at_8[0x18]; 8632 8633 u8 syndrome[0x20]; 8634 8635 u8 reserved_at_40[0x8]; 8636 u8 dctn[0x18]; 8637 8638 u8 ece[0x20]; 8639 }; 8640 8641 struct mlx5_ifc_create_dct_in_bits { 8642 u8 opcode[0x10]; 8643 u8 uid[0x10]; 8644 8645 u8 reserved_at_20[0x10]; 8646 u8 op_mod[0x10]; 8647 8648 u8 reserved_at_40[0x40]; 8649 8650 struct mlx5_ifc_dctc_bits dct_context_entry; 8651 8652 u8 reserved_at_280[0x180]; 8653 }; 8654 8655 struct mlx5_ifc_create_cq_out_bits { 8656 u8 status[0x8]; 8657 u8 reserved_at_8[0x18]; 8658 8659 u8 syndrome[0x20]; 8660 8661 u8 reserved_at_40[0x8]; 8662 u8 cqn[0x18]; 8663 8664 u8 reserved_at_60[0x20]; 8665 }; 8666 8667 struct mlx5_ifc_create_cq_in_bits { 8668 u8 opcode[0x10]; 8669 u8 uid[0x10]; 8670 8671 u8 reserved_at_20[0x10]; 8672 u8 op_mod[0x10]; 8673 8674 u8 reserved_at_40[0x40]; 8675 8676 struct mlx5_ifc_cqc_bits cq_context; 8677 8678 u8 reserved_at_280[0x60]; 8679 8680 u8 cq_umem_valid[0x1]; 8681 u8 reserved_at_2e1[0x59f]; 8682 8683 u8 pas[][0x40]; 8684 }; 8685 8686 struct mlx5_ifc_config_int_moderation_out_bits { 8687 u8 status[0x8]; 8688 u8 reserved_at_8[0x18]; 8689 8690 u8 syndrome[0x20]; 8691 8692 u8 reserved_at_40[0x4]; 8693 u8 min_delay[0xc]; 8694 u8 int_vector[0x10]; 8695 8696 u8 reserved_at_60[0x20]; 8697 }; 8698 8699 enum { 8700 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8701 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8702 }; 8703 8704 struct mlx5_ifc_config_int_moderation_in_bits { 8705 u8 opcode[0x10]; 8706 u8 reserved_at_10[0x10]; 8707 8708 u8 reserved_at_20[0x10]; 8709 u8 op_mod[0x10]; 8710 8711 u8 reserved_at_40[0x4]; 8712 u8 min_delay[0xc]; 8713 u8 int_vector[0x10]; 8714 8715 u8 reserved_at_60[0x20]; 8716 }; 8717 8718 struct mlx5_ifc_attach_to_mcg_out_bits { 8719 u8 status[0x8]; 8720 u8 reserved_at_8[0x18]; 8721 8722 u8 syndrome[0x20]; 8723 8724 u8 reserved_at_40[0x40]; 8725 }; 8726 8727 struct mlx5_ifc_attach_to_mcg_in_bits { 8728 u8 opcode[0x10]; 8729 u8 uid[0x10]; 8730 8731 u8 reserved_at_20[0x10]; 8732 u8 op_mod[0x10]; 8733 8734 u8 reserved_at_40[0x8]; 8735 u8 qpn[0x18]; 8736 8737 u8 reserved_at_60[0x20]; 8738 8739 u8 multicast_gid[16][0x8]; 8740 }; 8741 8742 struct mlx5_ifc_arm_xrq_out_bits { 8743 u8 status[0x8]; 8744 u8 reserved_at_8[0x18]; 8745 8746 u8 syndrome[0x20]; 8747 8748 u8 reserved_at_40[0x40]; 8749 }; 8750 8751 struct mlx5_ifc_arm_xrq_in_bits { 8752 u8 opcode[0x10]; 8753 u8 reserved_at_10[0x10]; 8754 8755 u8 reserved_at_20[0x10]; 8756 u8 op_mod[0x10]; 8757 8758 u8 reserved_at_40[0x8]; 8759 u8 xrqn[0x18]; 8760 8761 u8 reserved_at_60[0x10]; 8762 u8 lwm[0x10]; 8763 }; 8764 8765 struct mlx5_ifc_arm_xrc_srq_out_bits { 8766 u8 status[0x8]; 8767 u8 reserved_at_8[0x18]; 8768 8769 u8 syndrome[0x20]; 8770 8771 u8 reserved_at_40[0x40]; 8772 }; 8773 8774 enum { 8775 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8776 }; 8777 8778 struct mlx5_ifc_arm_xrc_srq_in_bits { 8779 u8 opcode[0x10]; 8780 u8 uid[0x10]; 8781 8782 u8 reserved_at_20[0x10]; 8783 u8 op_mod[0x10]; 8784 8785 u8 reserved_at_40[0x8]; 8786 u8 xrc_srqn[0x18]; 8787 8788 u8 reserved_at_60[0x10]; 8789 u8 lwm[0x10]; 8790 }; 8791 8792 struct mlx5_ifc_arm_rq_out_bits { 8793 u8 status[0x8]; 8794 u8 reserved_at_8[0x18]; 8795 8796 u8 syndrome[0x20]; 8797 8798 u8 reserved_at_40[0x40]; 8799 }; 8800 8801 enum { 8802 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8803 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8804 }; 8805 8806 struct mlx5_ifc_arm_rq_in_bits { 8807 u8 opcode[0x10]; 8808 u8 uid[0x10]; 8809 8810 u8 reserved_at_20[0x10]; 8811 u8 op_mod[0x10]; 8812 8813 u8 reserved_at_40[0x8]; 8814 u8 srq_number[0x18]; 8815 8816 u8 reserved_at_60[0x10]; 8817 u8 lwm[0x10]; 8818 }; 8819 8820 struct mlx5_ifc_arm_dct_out_bits { 8821 u8 status[0x8]; 8822 u8 reserved_at_8[0x18]; 8823 8824 u8 syndrome[0x20]; 8825 8826 u8 reserved_at_40[0x40]; 8827 }; 8828 8829 struct mlx5_ifc_arm_dct_in_bits { 8830 u8 opcode[0x10]; 8831 u8 reserved_at_10[0x10]; 8832 8833 u8 reserved_at_20[0x10]; 8834 u8 op_mod[0x10]; 8835 8836 u8 reserved_at_40[0x8]; 8837 u8 dct_number[0x18]; 8838 8839 u8 reserved_at_60[0x20]; 8840 }; 8841 8842 struct mlx5_ifc_alloc_xrcd_out_bits { 8843 u8 status[0x8]; 8844 u8 reserved_at_8[0x18]; 8845 8846 u8 syndrome[0x20]; 8847 8848 u8 reserved_at_40[0x8]; 8849 u8 xrcd[0x18]; 8850 8851 u8 reserved_at_60[0x20]; 8852 }; 8853 8854 struct mlx5_ifc_alloc_xrcd_in_bits { 8855 u8 opcode[0x10]; 8856 u8 uid[0x10]; 8857 8858 u8 reserved_at_20[0x10]; 8859 u8 op_mod[0x10]; 8860 8861 u8 reserved_at_40[0x40]; 8862 }; 8863 8864 struct mlx5_ifc_alloc_uar_out_bits { 8865 u8 status[0x8]; 8866 u8 reserved_at_8[0x18]; 8867 8868 u8 syndrome[0x20]; 8869 8870 u8 reserved_at_40[0x8]; 8871 u8 uar[0x18]; 8872 8873 u8 reserved_at_60[0x20]; 8874 }; 8875 8876 struct mlx5_ifc_alloc_uar_in_bits { 8877 u8 opcode[0x10]; 8878 u8 uid[0x10]; 8879 8880 u8 reserved_at_20[0x10]; 8881 u8 op_mod[0x10]; 8882 8883 u8 reserved_at_40[0x40]; 8884 }; 8885 8886 struct mlx5_ifc_alloc_transport_domain_out_bits { 8887 u8 status[0x8]; 8888 u8 reserved_at_8[0x18]; 8889 8890 u8 syndrome[0x20]; 8891 8892 u8 reserved_at_40[0x8]; 8893 u8 transport_domain[0x18]; 8894 8895 u8 reserved_at_60[0x20]; 8896 }; 8897 8898 struct mlx5_ifc_alloc_transport_domain_in_bits { 8899 u8 opcode[0x10]; 8900 u8 uid[0x10]; 8901 8902 u8 reserved_at_20[0x10]; 8903 u8 op_mod[0x10]; 8904 8905 u8 reserved_at_40[0x40]; 8906 }; 8907 8908 struct mlx5_ifc_alloc_q_counter_out_bits { 8909 u8 status[0x8]; 8910 u8 reserved_at_8[0x18]; 8911 8912 u8 syndrome[0x20]; 8913 8914 u8 reserved_at_40[0x18]; 8915 u8 counter_set_id[0x8]; 8916 8917 u8 reserved_at_60[0x20]; 8918 }; 8919 8920 struct mlx5_ifc_alloc_q_counter_in_bits { 8921 u8 opcode[0x10]; 8922 u8 uid[0x10]; 8923 8924 u8 reserved_at_20[0x10]; 8925 u8 op_mod[0x10]; 8926 8927 u8 reserved_at_40[0x40]; 8928 }; 8929 8930 struct mlx5_ifc_alloc_pd_out_bits { 8931 u8 status[0x8]; 8932 u8 reserved_at_8[0x18]; 8933 8934 u8 syndrome[0x20]; 8935 8936 u8 reserved_at_40[0x8]; 8937 u8 pd[0x18]; 8938 8939 u8 reserved_at_60[0x20]; 8940 }; 8941 8942 struct mlx5_ifc_alloc_pd_in_bits { 8943 u8 opcode[0x10]; 8944 u8 uid[0x10]; 8945 8946 u8 reserved_at_20[0x10]; 8947 u8 op_mod[0x10]; 8948 8949 u8 reserved_at_40[0x40]; 8950 }; 8951 8952 struct mlx5_ifc_alloc_flow_counter_out_bits { 8953 u8 status[0x8]; 8954 u8 reserved_at_8[0x18]; 8955 8956 u8 syndrome[0x20]; 8957 8958 u8 flow_counter_id[0x20]; 8959 8960 u8 reserved_at_60[0x20]; 8961 }; 8962 8963 struct mlx5_ifc_alloc_flow_counter_in_bits { 8964 u8 opcode[0x10]; 8965 u8 reserved_at_10[0x10]; 8966 8967 u8 reserved_at_20[0x10]; 8968 u8 op_mod[0x10]; 8969 8970 u8 reserved_at_40[0x38]; 8971 u8 flow_counter_bulk[0x8]; 8972 }; 8973 8974 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8975 u8 status[0x8]; 8976 u8 reserved_at_8[0x18]; 8977 8978 u8 syndrome[0x20]; 8979 8980 u8 reserved_at_40[0x40]; 8981 }; 8982 8983 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8984 u8 opcode[0x10]; 8985 u8 reserved_at_10[0x10]; 8986 8987 u8 reserved_at_20[0x10]; 8988 u8 op_mod[0x10]; 8989 8990 u8 reserved_at_40[0x20]; 8991 8992 u8 reserved_at_60[0x10]; 8993 u8 vxlan_udp_port[0x10]; 8994 }; 8995 8996 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8997 u8 status[0x8]; 8998 u8 reserved_at_8[0x18]; 8999 9000 u8 syndrome[0x20]; 9001 9002 u8 reserved_at_40[0x40]; 9003 }; 9004 9005 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9006 u8 rate_limit[0x20]; 9007 9008 u8 burst_upper_bound[0x20]; 9009 9010 u8 reserved_at_40[0x10]; 9011 u8 typical_packet_size[0x10]; 9012 9013 u8 reserved_at_60[0x120]; 9014 }; 9015 9016 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9017 u8 opcode[0x10]; 9018 u8 uid[0x10]; 9019 9020 u8 reserved_at_20[0x10]; 9021 u8 op_mod[0x10]; 9022 9023 u8 reserved_at_40[0x10]; 9024 u8 rate_limit_index[0x10]; 9025 9026 u8 reserved_at_60[0x20]; 9027 9028 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9029 }; 9030 9031 struct mlx5_ifc_access_register_out_bits { 9032 u8 status[0x8]; 9033 u8 reserved_at_8[0x18]; 9034 9035 u8 syndrome[0x20]; 9036 9037 u8 reserved_at_40[0x40]; 9038 9039 u8 register_data[][0x20]; 9040 }; 9041 9042 enum { 9043 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9044 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9045 }; 9046 9047 struct mlx5_ifc_access_register_in_bits { 9048 u8 opcode[0x10]; 9049 u8 reserved_at_10[0x10]; 9050 9051 u8 reserved_at_20[0x10]; 9052 u8 op_mod[0x10]; 9053 9054 u8 reserved_at_40[0x10]; 9055 u8 register_id[0x10]; 9056 9057 u8 argument[0x20]; 9058 9059 u8 register_data[][0x20]; 9060 }; 9061 9062 struct mlx5_ifc_sltp_reg_bits { 9063 u8 status[0x4]; 9064 u8 version[0x4]; 9065 u8 local_port[0x8]; 9066 u8 pnat[0x2]; 9067 u8 reserved_at_12[0x2]; 9068 u8 lane[0x4]; 9069 u8 reserved_at_18[0x8]; 9070 9071 u8 reserved_at_20[0x20]; 9072 9073 u8 reserved_at_40[0x7]; 9074 u8 polarity[0x1]; 9075 u8 ob_tap0[0x8]; 9076 u8 ob_tap1[0x8]; 9077 u8 ob_tap2[0x8]; 9078 9079 u8 reserved_at_60[0xc]; 9080 u8 ob_preemp_mode[0x4]; 9081 u8 ob_reg[0x8]; 9082 u8 ob_bias[0x8]; 9083 9084 u8 reserved_at_80[0x20]; 9085 }; 9086 9087 struct mlx5_ifc_slrg_reg_bits { 9088 u8 status[0x4]; 9089 u8 version[0x4]; 9090 u8 local_port[0x8]; 9091 u8 pnat[0x2]; 9092 u8 reserved_at_12[0x2]; 9093 u8 lane[0x4]; 9094 u8 reserved_at_18[0x8]; 9095 9096 u8 time_to_link_up[0x10]; 9097 u8 reserved_at_30[0xc]; 9098 u8 grade_lane_speed[0x4]; 9099 9100 u8 grade_version[0x8]; 9101 u8 grade[0x18]; 9102 9103 u8 reserved_at_60[0x4]; 9104 u8 height_grade_type[0x4]; 9105 u8 height_grade[0x18]; 9106 9107 u8 height_dz[0x10]; 9108 u8 height_dv[0x10]; 9109 9110 u8 reserved_at_a0[0x10]; 9111 u8 height_sigma[0x10]; 9112 9113 u8 reserved_at_c0[0x20]; 9114 9115 u8 reserved_at_e0[0x4]; 9116 u8 phase_grade_type[0x4]; 9117 u8 phase_grade[0x18]; 9118 9119 u8 reserved_at_100[0x8]; 9120 u8 phase_eo_pos[0x8]; 9121 u8 reserved_at_110[0x8]; 9122 u8 phase_eo_neg[0x8]; 9123 9124 u8 ffe_set_tested[0x10]; 9125 u8 test_errors_per_lane[0x10]; 9126 }; 9127 9128 struct mlx5_ifc_pvlc_reg_bits { 9129 u8 reserved_at_0[0x8]; 9130 u8 local_port[0x8]; 9131 u8 reserved_at_10[0x10]; 9132 9133 u8 reserved_at_20[0x1c]; 9134 u8 vl_hw_cap[0x4]; 9135 9136 u8 reserved_at_40[0x1c]; 9137 u8 vl_admin[0x4]; 9138 9139 u8 reserved_at_60[0x1c]; 9140 u8 vl_operational[0x4]; 9141 }; 9142 9143 struct mlx5_ifc_pude_reg_bits { 9144 u8 swid[0x8]; 9145 u8 local_port[0x8]; 9146 u8 reserved_at_10[0x4]; 9147 u8 admin_status[0x4]; 9148 u8 reserved_at_18[0x4]; 9149 u8 oper_status[0x4]; 9150 9151 u8 reserved_at_20[0x60]; 9152 }; 9153 9154 struct mlx5_ifc_ptys_reg_bits { 9155 u8 reserved_at_0[0x1]; 9156 u8 an_disable_admin[0x1]; 9157 u8 an_disable_cap[0x1]; 9158 u8 reserved_at_3[0x5]; 9159 u8 local_port[0x8]; 9160 u8 reserved_at_10[0xd]; 9161 u8 proto_mask[0x3]; 9162 9163 u8 an_status[0x4]; 9164 u8 reserved_at_24[0xc]; 9165 u8 data_rate_oper[0x10]; 9166 9167 u8 ext_eth_proto_capability[0x20]; 9168 9169 u8 eth_proto_capability[0x20]; 9170 9171 u8 ib_link_width_capability[0x10]; 9172 u8 ib_proto_capability[0x10]; 9173 9174 u8 ext_eth_proto_admin[0x20]; 9175 9176 u8 eth_proto_admin[0x20]; 9177 9178 u8 ib_link_width_admin[0x10]; 9179 u8 ib_proto_admin[0x10]; 9180 9181 u8 ext_eth_proto_oper[0x20]; 9182 9183 u8 eth_proto_oper[0x20]; 9184 9185 u8 ib_link_width_oper[0x10]; 9186 u8 ib_proto_oper[0x10]; 9187 9188 u8 reserved_at_160[0x1c]; 9189 u8 connector_type[0x4]; 9190 9191 u8 eth_proto_lp_advertise[0x20]; 9192 9193 u8 reserved_at_1a0[0x60]; 9194 }; 9195 9196 struct mlx5_ifc_mlcr_reg_bits { 9197 u8 reserved_at_0[0x8]; 9198 u8 local_port[0x8]; 9199 u8 reserved_at_10[0x20]; 9200 9201 u8 beacon_duration[0x10]; 9202 u8 reserved_at_40[0x10]; 9203 9204 u8 beacon_remain[0x10]; 9205 }; 9206 9207 struct mlx5_ifc_ptas_reg_bits { 9208 u8 reserved_at_0[0x20]; 9209 9210 u8 algorithm_options[0x10]; 9211 u8 reserved_at_30[0x4]; 9212 u8 repetitions_mode[0x4]; 9213 u8 num_of_repetitions[0x8]; 9214 9215 u8 grade_version[0x8]; 9216 u8 height_grade_type[0x4]; 9217 u8 phase_grade_type[0x4]; 9218 u8 height_grade_weight[0x8]; 9219 u8 phase_grade_weight[0x8]; 9220 9221 u8 gisim_measure_bits[0x10]; 9222 u8 adaptive_tap_measure_bits[0x10]; 9223 9224 u8 ber_bath_high_error_threshold[0x10]; 9225 u8 ber_bath_mid_error_threshold[0x10]; 9226 9227 u8 ber_bath_low_error_threshold[0x10]; 9228 u8 one_ratio_high_threshold[0x10]; 9229 9230 u8 one_ratio_high_mid_threshold[0x10]; 9231 u8 one_ratio_low_mid_threshold[0x10]; 9232 9233 u8 one_ratio_low_threshold[0x10]; 9234 u8 ndeo_error_threshold[0x10]; 9235 9236 u8 mixer_offset_step_size[0x10]; 9237 u8 reserved_at_110[0x8]; 9238 u8 mix90_phase_for_voltage_bath[0x8]; 9239 9240 u8 mixer_offset_start[0x10]; 9241 u8 mixer_offset_end[0x10]; 9242 9243 u8 reserved_at_140[0x15]; 9244 u8 ber_test_time[0xb]; 9245 }; 9246 9247 struct mlx5_ifc_pspa_reg_bits { 9248 u8 swid[0x8]; 9249 u8 local_port[0x8]; 9250 u8 sub_port[0x8]; 9251 u8 reserved_at_18[0x8]; 9252 9253 u8 reserved_at_20[0x20]; 9254 }; 9255 9256 struct mlx5_ifc_pqdr_reg_bits { 9257 u8 reserved_at_0[0x8]; 9258 u8 local_port[0x8]; 9259 u8 reserved_at_10[0x5]; 9260 u8 prio[0x3]; 9261 u8 reserved_at_18[0x6]; 9262 u8 mode[0x2]; 9263 9264 u8 reserved_at_20[0x20]; 9265 9266 u8 reserved_at_40[0x10]; 9267 u8 min_threshold[0x10]; 9268 9269 u8 reserved_at_60[0x10]; 9270 u8 max_threshold[0x10]; 9271 9272 u8 reserved_at_80[0x10]; 9273 u8 mark_probability_denominator[0x10]; 9274 9275 u8 reserved_at_a0[0x60]; 9276 }; 9277 9278 struct mlx5_ifc_ppsc_reg_bits { 9279 u8 reserved_at_0[0x8]; 9280 u8 local_port[0x8]; 9281 u8 reserved_at_10[0x10]; 9282 9283 u8 reserved_at_20[0x60]; 9284 9285 u8 reserved_at_80[0x1c]; 9286 u8 wrps_admin[0x4]; 9287 9288 u8 reserved_at_a0[0x1c]; 9289 u8 wrps_status[0x4]; 9290 9291 u8 reserved_at_c0[0x8]; 9292 u8 up_threshold[0x8]; 9293 u8 reserved_at_d0[0x8]; 9294 u8 down_threshold[0x8]; 9295 9296 u8 reserved_at_e0[0x20]; 9297 9298 u8 reserved_at_100[0x1c]; 9299 u8 srps_admin[0x4]; 9300 9301 u8 reserved_at_120[0x1c]; 9302 u8 srps_status[0x4]; 9303 9304 u8 reserved_at_140[0x40]; 9305 }; 9306 9307 struct mlx5_ifc_pplr_reg_bits { 9308 u8 reserved_at_0[0x8]; 9309 u8 local_port[0x8]; 9310 u8 reserved_at_10[0x10]; 9311 9312 u8 reserved_at_20[0x8]; 9313 u8 lb_cap[0x8]; 9314 u8 reserved_at_30[0x8]; 9315 u8 lb_en[0x8]; 9316 }; 9317 9318 struct mlx5_ifc_pplm_reg_bits { 9319 u8 reserved_at_0[0x8]; 9320 u8 local_port[0x8]; 9321 u8 reserved_at_10[0x10]; 9322 9323 u8 reserved_at_20[0x20]; 9324 9325 u8 port_profile_mode[0x8]; 9326 u8 static_port_profile[0x8]; 9327 u8 active_port_profile[0x8]; 9328 u8 reserved_at_58[0x8]; 9329 9330 u8 retransmission_active[0x8]; 9331 u8 fec_mode_active[0x18]; 9332 9333 u8 rs_fec_correction_bypass_cap[0x4]; 9334 u8 reserved_at_84[0x8]; 9335 u8 fec_override_cap_56g[0x4]; 9336 u8 fec_override_cap_100g[0x4]; 9337 u8 fec_override_cap_50g[0x4]; 9338 u8 fec_override_cap_25g[0x4]; 9339 u8 fec_override_cap_10g_40g[0x4]; 9340 9341 u8 rs_fec_correction_bypass_admin[0x4]; 9342 u8 reserved_at_a4[0x8]; 9343 u8 fec_override_admin_56g[0x4]; 9344 u8 fec_override_admin_100g[0x4]; 9345 u8 fec_override_admin_50g[0x4]; 9346 u8 fec_override_admin_25g[0x4]; 9347 u8 fec_override_admin_10g_40g[0x4]; 9348 9349 u8 fec_override_cap_400g_8x[0x10]; 9350 u8 fec_override_cap_200g_4x[0x10]; 9351 9352 u8 fec_override_cap_100g_2x[0x10]; 9353 u8 fec_override_cap_50g_1x[0x10]; 9354 9355 u8 fec_override_admin_400g_8x[0x10]; 9356 u8 fec_override_admin_200g_4x[0x10]; 9357 9358 u8 fec_override_admin_100g_2x[0x10]; 9359 u8 fec_override_admin_50g_1x[0x10]; 9360 9361 u8 reserved_at_140[0x140]; 9362 }; 9363 9364 struct mlx5_ifc_ppcnt_reg_bits { 9365 u8 swid[0x8]; 9366 u8 local_port[0x8]; 9367 u8 pnat[0x2]; 9368 u8 reserved_at_12[0x8]; 9369 u8 grp[0x6]; 9370 9371 u8 clr[0x1]; 9372 u8 reserved_at_21[0x1c]; 9373 u8 prio_tc[0x3]; 9374 9375 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9376 }; 9377 9378 struct mlx5_ifc_mpein_reg_bits { 9379 u8 reserved_at_0[0x2]; 9380 u8 depth[0x6]; 9381 u8 pcie_index[0x8]; 9382 u8 node[0x8]; 9383 u8 reserved_at_18[0x8]; 9384 9385 u8 capability_mask[0x20]; 9386 9387 u8 reserved_at_40[0x8]; 9388 u8 link_width_enabled[0x8]; 9389 u8 link_speed_enabled[0x10]; 9390 9391 u8 lane0_physical_position[0x8]; 9392 u8 link_width_active[0x8]; 9393 u8 link_speed_active[0x10]; 9394 9395 u8 num_of_pfs[0x10]; 9396 u8 num_of_vfs[0x10]; 9397 9398 u8 bdf0[0x10]; 9399 u8 reserved_at_b0[0x10]; 9400 9401 u8 max_read_request_size[0x4]; 9402 u8 max_payload_size[0x4]; 9403 u8 reserved_at_c8[0x5]; 9404 u8 pwr_status[0x3]; 9405 u8 port_type[0x4]; 9406 u8 reserved_at_d4[0xb]; 9407 u8 lane_reversal[0x1]; 9408 9409 u8 reserved_at_e0[0x14]; 9410 u8 pci_power[0xc]; 9411 9412 u8 reserved_at_100[0x20]; 9413 9414 u8 device_status[0x10]; 9415 u8 port_state[0x8]; 9416 u8 reserved_at_138[0x8]; 9417 9418 u8 reserved_at_140[0x10]; 9419 u8 receiver_detect_result[0x10]; 9420 9421 u8 reserved_at_160[0x20]; 9422 }; 9423 9424 struct mlx5_ifc_mpcnt_reg_bits { 9425 u8 reserved_at_0[0x8]; 9426 u8 pcie_index[0x8]; 9427 u8 reserved_at_10[0xa]; 9428 u8 grp[0x6]; 9429 9430 u8 clr[0x1]; 9431 u8 reserved_at_21[0x1f]; 9432 9433 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9434 }; 9435 9436 struct mlx5_ifc_ppad_reg_bits { 9437 u8 reserved_at_0[0x3]; 9438 u8 single_mac[0x1]; 9439 u8 reserved_at_4[0x4]; 9440 u8 local_port[0x8]; 9441 u8 mac_47_32[0x10]; 9442 9443 u8 mac_31_0[0x20]; 9444 9445 u8 reserved_at_40[0x40]; 9446 }; 9447 9448 struct mlx5_ifc_pmtu_reg_bits { 9449 u8 reserved_at_0[0x8]; 9450 u8 local_port[0x8]; 9451 u8 reserved_at_10[0x10]; 9452 9453 u8 max_mtu[0x10]; 9454 u8 reserved_at_30[0x10]; 9455 9456 u8 admin_mtu[0x10]; 9457 u8 reserved_at_50[0x10]; 9458 9459 u8 oper_mtu[0x10]; 9460 u8 reserved_at_70[0x10]; 9461 }; 9462 9463 struct mlx5_ifc_pmpr_reg_bits { 9464 u8 reserved_at_0[0x8]; 9465 u8 module[0x8]; 9466 u8 reserved_at_10[0x10]; 9467 9468 u8 reserved_at_20[0x18]; 9469 u8 attenuation_5g[0x8]; 9470 9471 u8 reserved_at_40[0x18]; 9472 u8 attenuation_7g[0x8]; 9473 9474 u8 reserved_at_60[0x18]; 9475 u8 attenuation_12g[0x8]; 9476 }; 9477 9478 struct mlx5_ifc_pmpe_reg_bits { 9479 u8 reserved_at_0[0x8]; 9480 u8 module[0x8]; 9481 u8 reserved_at_10[0xc]; 9482 u8 module_status[0x4]; 9483 9484 u8 reserved_at_20[0x60]; 9485 }; 9486 9487 struct mlx5_ifc_pmpc_reg_bits { 9488 u8 module_state_updated[32][0x8]; 9489 }; 9490 9491 struct mlx5_ifc_pmlpn_reg_bits { 9492 u8 reserved_at_0[0x4]; 9493 u8 mlpn_status[0x4]; 9494 u8 local_port[0x8]; 9495 u8 reserved_at_10[0x10]; 9496 9497 u8 e[0x1]; 9498 u8 reserved_at_21[0x1f]; 9499 }; 9500 9501 struct mlx5_ifc_pmlp_reg_bits { 9502 u8 rxtx[0x1]; 9503 u8 reserved_at_1[0x7]; 9504 u8 local_port[0x8]; 9505 u8 reserved_at_10[0x8]; 9506 u8 width[0x8]; 9507 9508 u8 lane0_module_mapping[0x20]; 9509 9510 u8 lane1_module_mapping[0x20]; 9511 9512 u8 lane2_module_mapping[0x20]; 9513 9514 u8 lane3_module_mapping[0x20]; 9515 9516 u8 reserved_at_a0[0x160]; 9517 }; 9518 9519 struct mlx5_ifc_pmaos_reg_bits { 9520 u8 reserved_at_0[0x8]; 9521 u8 module[0x8]; 9522 u8 reserved_at_10[0x4]; 9523 u8 admin_status[0x4]; 9524 u8 reserved_at_18[0x4]; 9525 u8 oper_status[0x4]; 9526 9527 u8 ase[0x1]; 9528 u8 ee[0x1]; 9529 u8 reserved_at_22[0x1c]; 9530 u8 e[0x2]; 9531 9532 u8 reserved_at_40[0x40]; 9533 }; 9534 9535 struct mlx5_ifc_plpc_reg_bits { 9536 u8 reserved_at_0[0x4]; 9537 u8 profile_id[0xc]; 9538 u8 reserved_at_10[0x4]; 9539 u8 proto_mask[0x4]; 9540 u8 reserved_at_18[0x8]; 9541 9542 u8 reserved_at_20[0x10]; 9543 u8 lane_speed[0x10]; 9544 9545 u8 reserved_at_40[0x17]; 9546 u8 lpbf[0x1]; 9547 u8 fec_mode_policy[0x8]; 9548 9549 u8 retransmission_capability[0x8]; 9550 u8 fec_mode_capability[0x18]; 9551 9552 u8 retransmission_support_admin[0x8]; 9553 u8 fec_mode_support_admin[0x18]; 9554 9555 u8 retransmission_request_admin[0x8]; 9556 u8 fec_mode_request_admin[0x18]; 9557 9558 u8 reserved_at_c0[0x80]; 9559 }; 9560 9561 struct mlx5_ifc_plib_reg_bits { 9562 u8 reserved_at_0[0x8]; 9563 u8 local_port[0x8]; 9564 u8 reserved_at_10[0x8]; 9565 u8 ib_port[0x8]; 9566 9567 u8 reserved_at_20[0x60]; 9568 }; 9569 9570 struct mlx5_ifc_plbf_reg_bits { 9571 u8 reserved_at_0[0x8]; 9572 u8 local_port[0x8]; 9573 u8 reserved_at_10[0xd]; 9574 u8 lbf_mode[0x3]; 9575 9576 u8 reserved_at_20[0x20]; 9577 }; 9578 9579 struct mlx5_ifc_pipg_reg_bits { 9580 u8 reserved_at_0[0x8]; 9581 u8 local_port[0x8]; 9582 u8 reserved_at_10[0x10]; 9583 9584 u8 dic[0x1]; 9585 u8 reserved_at_21[0x19]; 9586 u8 ipg[0x4]; 9587 u8 reserved_at_3e[0x2]; 9588 }; 9589 9590 struct mlx5_ifc_pifr_reg_bits { 9591 u8 reserved_at_0[0x8]; 9592 u8 local_port[0x8]; 9593 u8 reserved_at_10[0x10]; 9594 9595 u8 reserved_at_20[0xe0]; 9596 9597 u8 port_filter[8][0x20]; 9598 9599 u8 port_filter_update_en[8][0x20]; 9600 }; 9601 9602 struct mlx5_ifc_pfcc_reg_bits { 9603 u8 reserved_at_0[0x8]; 9604 u8 local_port[0x8]; 9605 u8 reserved_at_10[0xb]; 9606 u8 ppan_mask_n[0x1]; 9607 u8 minor_stall_mask[0x1]; 9608 u8 critical_stall_mask[0x1]; 9609 u8 reserved_at_1e[0x2]; 9610 9611 u8 ppan[0x4]; 9612 u8 reserved_at_24[0x4]; 9613 u8 prio_mask_tx[0x8]; 9614 u8 reserved_at_30[0x8]; 9615 u8 prio_mask_rx[0x8]; 9616 9617 u8 pptx[0x1]; 9618 u8 aptx[0x1]; 9619 u8 pptx_mask_n[0x1]; 9620 u8 reserved_at_43[0x5]; 9621 u8 pfctx[0x8]; 9622 u8 reserved_at_50[0x10]; 9623 9624 u8 pprx[0x1]; 9625 u8 aprx[0x1]; 9626 u8 pprx_mask_n[0x1]; 9627 u8 reserved_at_63[0x5]; 9628 u8 pfcrx[0x8]; 9629 u8 reserved_at_70[0x10]; 9630 9631 u8 device_stall_minor_watermark[0x10]; 9632 u8 device_stall_critical_watermark[0x10]; 9633 9634 u8 reserved_at_a0[0x60]; 9635 }; 9636 9637 struct mlx5_ifc_pelc_reg_bits { 9638 u8 op[0x4]; 9639 u8 reserved_at_4[0x4]; 9640 u8 local_port[0x8]; 9641 u8 reserved_at_10[0x10]; 9642 9643 u8 op_admin[0x8]; 9644 u8 op_capability[0x8]; 9645 u8 op_request[0x8]; 9646 u8 op_active[0x8]; 9647 9648 u8 admin[0x40]; 9649 9650 u8 capability[0x40]; 9651 9652 u8 request[0x40]; 9653 9654 u8 active[0x40]; 9655 9656 u8 reserved_at_140[0x80]; 9657 }; 9658 9659 struct mlx5_ifc_peir_reg_bits { 9660 u8 reserved_at_0[0x8]; 9661 u8 local_port[0x8]; 9662 u8 reserved_at_10[0x10]; 9663 9664 u8 reserved_at_20[0xc]; 9665 u8 error_count[0x4]; 9666 u8 reserved_at_30[0x10]; 9667 9668 u8 reserved_at_40[0xc]; 9669 u8 lane[0x4]; 9670 u8 reserved_at_50[0x8]; 9671 u8 error_type[0x8]; 9672 }; 9673 9674 struct mlx5_ifc_mpegc_reg_bits { 9675 u8 reserved_at_0[0x30]; 9676 u8 field_select[0x10]; 9677 9678 u8 tx_overflow_sense[0x1]; 9679 u8 mark_cqe[0x1]; 9680 u8 mark_cnp[0x1]; 9681 u8 reserved_at_43[0x1b]; 9682 u8 tx_lossy_overflow_oper[0x2]; 9683 9684 u8 reserved_at_60[0x100]; 9685 }; 9686 9687 enum { 9688 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9689 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9690 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9691 }; 9692 9693 struct mlx5_ifc_mtutc_reg_bits { 9694 u8 reserved_at_0[0x1c]; 9695 u8 operation[0x4]; 9696 9697 u8 freq_adjustment[0x20]; 9698 9699 u8 reserved_at_40[0x40]; 9700 9701 u8 utc_sec[0x20]; 9702 9703 u8 reserved_at_a0[0x2]; 9704 u8 utc_nsec[0x1e]; 9705 9706 u8 time_adjustment[0x20]; 9707 }; 9708 9709 struct mlx5_ifc_pcam_enhanced_features_bits { 9710 u8 reserved_at_0[0x68]; 9711 u8 fec_50G_per_lane_in_pplm[0x1]; 9712 u8 reserved_at_69[0x4]; 9713 u8 rx_icrc_encapsulated_counter[0x1]; 9714 u8 reserved_at_6e[0x4]; 9715 u8 ptys_extended_ethernet[0x1]; 9716 u8 reserved_at_73[0x3]; 9717 u8 pfcc_mask[0x1]; 9718 u8 reserved_at_77[0x3]; 9719 u8 per_lane_error_counters[0x1]; 9720 u8 rx_buffer_fullness_counters[0x1]; 9721 u8 ptys_connector_type[0x1]; 9722 u8 reserved_at_7d[0x1]; 9723 u8 ppcnt_discard_group[0x1]; 9724 u8 ppcnt_statistical_group[0x1]; 9725 }; 9726 9727 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9728 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9729 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9730 9731 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9732 u8 pplm[0x1]; 9733 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9734 9735 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9736 u8 pbmc[0x1]; 9737 u8 pptb[0x1]; 9738 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9739 u8 ppcnt[0x1]; 9740 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9741 }; 9742 9743 struct mlx5_ifc_pcam_reg_bits { 9744 u8 reserved_at_0[0x8]; 9745 u8 feature_group[0x8]; 9746 u8 reserved_at_10[0x8]; 9747 u8 access_reg_group[0x8]; 9748 9749 u8 reserved_at_20[0x20]; 9750 9751 union { 9752 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9753 u8 reserved_at_0[0x80]; 9754 } port_access_reg_cap_mask; 9755 9756 u8 reserved_at_c0[0x80]; 9757 9758 union { 9759 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9760 u8 reserved_at_0[0x80]; 9761 } feature_cap_mask; 9762 9763 u8 reserved_at_1c0[0xc0]; 9764 }; 9765 9766 struct mlx5_ifc_mcam_enhanced_features_bits { 9767 u8 reserved_at_0[0x5d]; 9768 u8 mcia_32dwords[0x1]; 9769 u8 reserved_at_5e[0xc]; 9770 u8 reset_state[0x1]; 9771 u8 ptpcyc2realtime_modify[0x1]; 9772 u8 reserved_at_6c[0x2]; 9773 u8 pci_status_and_power[0x1]; 9774 u8 reserved_at_6f[0x5]; 9775 u8 mark_tx_action_cnp[0x1]; 9776 u8 mark_tx_action_cqe[0x1]; 9777 u8 dynamic_tx_overflow[0x1]; 9778 u8 reserved_at_77[0x4]; 9779 u8 pcie_outbound_stalled[0x1]; 9780 u8 tx_overflow_buffer_pkt[0x1]; 9781 u8 mtpps_enh_out_per_adj[0x1]; 9782 u8 mtpps_fs[0x1]; 9783 u8 pcie_performance_group[0x1]; 9784 }; 9785 9786 struct mlx5_ifc_mcam_access_reg_bits { 9787 u8 reserved_at_0[0x1c]; 9788 u8 mcda[0x1]; 9789 u8 mcc[0x1]; 9790 u8 mcqi[0x1]; 9791 u8 mcqs[0x1]; 9792 9793 u8 regs_95_to_87[0x9]; 9794 u8 mpegc[0x1]; 9795 u8 mtutc[0x1]; 9796 u8 regs_84_to_68[0x11]; 9797 u8 tracer_registers[0x4]; 9798 9799 u8 regs_63_to_46[0x12]; 9800 u8 mrtc[0x1]; 9801 u8 regs_44_to_32[0xd]; 9802 9803 u8 regs_31_to_0[0x20]; 9804 }; 9805 9806 struct mlx5_ifc_mcam_access_reg_bits1 { 9807 u8 regs_127_to_96[0x20]; 9808 9809 u8 regs_95_to_64[0x20]; 9810 9811 u8 regs_63_to_32[0x20]; 9812 9813 u8 regs_31_to_0[0x20]; 9814 }; 9815 9816 struct mlx5_ifc_mcam_access_reg_bits2 { 9817 u8 regs_127_to_99[0x1d]; 9818 u8 mirc[0x1]; 9819 u8 regs_97_to_96[0x2]; 9820 9821 u8 regs_95_to_64[0x20]; 9822 9823 u8 regs_63_to_32[0x20]; 9824 9825 u8 regs_31_to_0[0x20]; 9826 }; 9827 9828 struct mlx5_ifc_mcam_reg_bits { 9829 u8 reserved_at_0[0x8]; 9830 u8 feature_group[0x8]; 9831 u8 reserved_at_10[0x8]; 9832 u8 access_reg_group[0x8]; 9833 9834 u8 reserved_at_20[0x20]; 9835 9836 union { 9837 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9838 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9839 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9840 u8 reserved_at_0[0x80]; 9841 } mng_access_reg_cap_mask; 9842 9843 u8 reserved_at_c0[0x80]; 9844 9845 union { 9846 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9847 u8 reserved_at_0[0x80]; 9848 } mng_feature_cap_mask; 9849 9850 u8 reserved_at_1c0[0x80]; 9851 }; 9852 9853 struct mlx5_ifc_qcam_access_reg_cap_mask { 9854 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9855 u8 qpdpm[0x1]; 9856 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9857 u8 qdpm[0x1]; 9858 u8 qpts[0x1]; 9859 u8 qcap[0x1]; 9860 u8 qcam_access_reg_cap_mask_0[0x1]; 9861 }; 9862 9863 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9864 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9865 u8 qpts_trust_both[0x1]; 9866 }; 9867 9868 struct mlx5_ifc_qcam_reg_bits { 9869 u8 reserved_at_0[0x8]; 9870 u8 feature_group[0x8]; 9871 u8 reserved_at_10[0x8]; 9872 u8 access_reg_group[0x8]; 9873 u8 reserved_at_20[0x20]; 9874 9875 union { 9876 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9877 u8 reserved_at_0[0x80]; 9878 } qos_access_reg_cap_mask; 9879 9880 u8 reserved_at_c0[0x80]; 9881 9882 union { 9883 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9884 u8 reserved_at_0[0x80]; 9885 } qos_feature_cap_mask; 9886 9887 u8 reserved_at_1c0[0x80]; 9888 }; 9889 9890 struct mlx5_ifc_core_dump_reg_bits { 9891 u8 reserved_at_0[0x18]; 9892 u8 core_dump_type[0x8]; 9893 9894 u8 reserved_at_20[0x30]; 9895 u8 vhca_id[0x10]; 9896 9897 u8 reserved_at_60[0x8]; 9898 u8 qpn[0x18]; 9899 u8 reserved_at_80[0x180]; 9900 }; 9901 9902 struct mlx5_ifc_pcap_reg_bits { 9903 u8 reserved_at_0[0x8]; 9904 u8 local_port[0x8]; 9905 u8 reserved_at_10[0x10]; 9906 9907 u8 port_capability_mask[4][0x20]; 9908 }; 9909 9910 struct mlx5_ifc_paos_reg_bits { 9911 u8 swid[0x8]; 9912 u8 local_port[0x8]; 9913 u8 reserved_at_10[0x4]; 9914 u8 admin_status[0x4]; 9915 u8 reserved_at_18[0x4]; 9916 u8 oper_status[0x4]; 9917 9918 u8 ase[0x1]; 9919 u8 ee[0x1]; 9920 u8 reserved_at_22[0x1c]; 9921 u8 e[0x2]; 9922 9923 u8 reserved_at_40[0x40]; 9924 }; 9925 9926 struct mlx5_ifc_pamp_reg_bits { 9927 u8 reserved_at_0[0x8]; 9928 u8 opamp_group[0x8]; 9929 u8 reserved_at_10[0xc]; 9930 u8 opamp_group_type[0x4]; 9931 9932 u8 start_index[0x10]; 9933 u8 reserved_at_30[0x4]; 9934 u8 num_of_indices[0xc]; 9935 9936 u8 index_data[18][0x10]; 9937 }; 9938 9939 struct mlx5_ifc_pcmr_reg_bits { 9940 u8 reserved_at_0[0x8]; 9941 u8 local_port[0x8]; 9942 u8 reserved_at_10[0x10]; 9943 9944 u8 entropy_force_cap[0x1]; 9945 u8 entropy_calc_cap[0x1]; 9946 u8 entropy_gre_calc_cap[0x1]; 9947 u8 reserved_at_23[0xf]; 9948 u8 rx_ts_over_crc_cap[0x1]; 9949 u8 reserved_at_33[0xb]; 9950 u8 fcs_cap[0x1]; 9951 u8 reserved_at_3f[0x1]; 9952 9953 u8 entropy_force[0x1]; 9954 u8 entropy_calc[0x1]; 9955 u8 entropy_gre_calc[0x1]; 9956 u8 reserved_at_43[0xf]; 9957 u8 rx_ts_over_crc[0x1]; 9958 u8 reserved_at_53[0xb]; 9959 u8 fcs_chk[0x1]; 9960 u8 reserved_at_5f[0x1]; 9961 }; 9962 9963 struct mlx5_ifc_lane_2_module_mapping_bits { 9964 u8 reserved_at_0[0x4]; 9965 u8 rx_lane[0x4]; 9966 u8 reserved_at_8[0x4]; 9967 u8 tx_lane[0x4]; 9968 u8 reserved_at_10[0x8]; 9969 u8 module[0x8]; 9970 }; 9971 9972 struct mlx5_ifc_bufferx_reg_bits { 9973 u8 reserved_at_0[0x6]; 9974 u8 lossy[0x1]; 9975 u8 epsb[0x1]; 9976 u8 reserved_at_8[0x8]; 9977 u8 size[0x10]; 9978 9979 u8 xoff_threshold[0x10]; 9980 u8 xon_threshold[0x10]; 9981 }; 9982 9983 struct mlx5_ifc_set_node_in_bits { 9984 u8 node_description[64][0x8]; 9985 }; 9986 9987 struct mlx5_ifc_register_power_settings_bits { 9988 u8 reserved_at_0[0x18]; 9989 u8 power_settings_level[0x8]; 9990 9991 u8 reserved_at_20[0x60]; 9992 }; 9993 9994 struct mlx5_ifc_register_host_endianness_bits { 9995 u8 he[0x1]; 9996 u8 reserved_at_1[0x1f]; 9997 9998 u8 reserved_at_20[0x60]; 9999 }; 10000 10001 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10002 u8 reserved_at_0[0x20]; 10003 10004 u8 mkey[0x20]; 10005 10006 u8 addressh_63_32[0x20]; 10007 10008 u8 addressl_31_0[0x20]; 10009 }; 10010 10011 struct mlx5_ifc_ud_adrs_vector_bits { 10012 u8 dc_key[0x40]; 10013 10014 u8 ext[0x1]; 10015 u8 reserved_at_41[0x7]; 10016 u8 destination_qp_dct[0x18]; 10017 10018 u8 static_rate[0x4]; 10019 u8 sl_eth_prio[0x4]; 10020 u8 fl[0x1]; 10021 u8 mlid[0x7]; 10022 u8 rlid_udp_sport[0x10]; 10023 10024 u8 reserved_at_80[0x20]; 10025 10026 u8 rmac_47_16[0x20]; 10027 10028 u8 rmac_15_0[0x10]; 10029 u8 tclass[0x8]; 10030 u8 hop_limit[0x8]; 10031 10032 u8 reserved_at_e0[0x1]; 10033 u8 grh[0x1]; 10034 u8 reserved_at_e2[0x2]; 10035 u8 src_addr_index[0x8]; 10036 u8 flow_label[0x14]; 10037 10038 u8 rgid_rip[16][0x8]; 10039 }; 10040 10041 struct mlx5_ifc_pages_req_event_bits { 10042 u8 reserved_at_0[0x10]; 10043 u8 function_id[0x10]; 10044 10045 u8 num_pages[0x20]; 10046 10047 u8 reserved_at_40[0xa0]; 10048 }; 10049 10050 struct mlx5_ifc_eqe_bits { 10051 u8 reserved_at_0[0x8]; 10052 u8 event_type[0x8]; 10053 u8 reserved_at_10[0x8]; 10054 u8 event_sub_type[0x8]; 10055 10056 u8 reserved_at_20[0xe0]; 10057 10058 union mlx5_ifc_event_auto_bits event_data; 10059 10060 u8 reserved_at_1e0[0x10]; 10061 u8 signature[0x8]; 10062 u8 reserved_at_1f8[0x7]; 10063 u8 owner[0x1]; 10064 }; 10065 10066 enum { 10067 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10068 }; 10069 10070 struct mlx5_ifc_cmd_queue_entry_bits { 10071 u8 type[0x8]; 10072 u8 reserved_at_8[0x18]; 10073 10074 u8 input_length[0x20]; 10075 10076 u8 input_mailbox_pointer_63_32[0x20]; 10077 10078 u8 input_mailbox_pointer_31_9[0x17]; 10079 u8 reserved_at_77[0x9]; 10080 10081 u8 command_input_inline_data[16][0x8]; 10082 10083 u8 command_output_inline_data[16][0x8]; 10084 10085 u8 output_mailbox_pointer_63_32[0x20]; 10086 10087 u8 output_mailbox_pointer_31_9[0x17]; 10088 u8 reserved_at_1b7[0x9]; 10089 10090 u8 output_length[0x20]; 10091 10092 u8 token[0x8]; 10093 u8 signature[0x8]; 10094 u8 reserved_at_1f0[0x8]; 10095 u8 status[0x7]; 10096 u8 ownership[0x1]; 10097 }; 10098 10099 struct mlx5_ifc_cmd_out_bits { 10100 u8 status[0x8]; 10101 u8 reserved_at_8[0x18]; 10102 10103 u8 syndrome[0x20]; 10104 10105 u8 command_output[0x20]; 10106 }; 10107 10108 struct mlx5_ifc_cmd_in_bits { 10109 u8 opcode[0x10]; 10110 u8 reserved_at_10[0x10]; 10111 10112 u8 reserved_at_20[0x10]; 10113 u8 op_mod[0x10]; 10114 10115 u8 command[][0x20]; 10116 }; 10117 10118 struct mlx5_ifc_cmd_if_box_bits { 10119 u8 mailbox_data[512][0x8]; 10120 10121 u8 reserved_at_1000[0x180]; 10122 10123 u8 next_pointer_63_32[0x20]; 10124 10125 u8 next_pointer_31_10[0x16]; 10126 u8 reserved_at_11b6[0xa]; 10127 10128 u8 block_number[0x20]; 10129 10130 u8 reserved_at_11e0[0x8]; 10131 u8 token[0x8]; 10132 u8 ctrl_signature[0x8]; 10133 u8 signature[0x8]; 10134 }; 10135 10136 struct mlx5_ifc_mtt_bits { 10137 u8 ptag_63_32[0x20]; 10138 10139 u8 ptag_31_8[0x18]; 10140 u8 reserved_at_38[0x6]; 10141 u8 wr_en[0x1]; 10142 u8 rd_en[0x1]; 10143 }; 10144 10145 struct mlx5_ifc_query_wol_rol_out_bits { 10146 u8 status[0x8]; 10147 u8 reserved_at_8[0x18]; 10148 10149 u8 syndrome[0x20]; 10150 10151 u8 reserved_at_40[0x10]; 10152 u8 rol_mode[0x8]; 10153 u8 wol_mode[0x8]; 10154 10155 u8 reserved_at_60[0x20]; 10156 }; 10157 10158 struct mlx5_ifc_query_wol_rol_in_bits { 10159 u8 opcode[0x10]; 10160 u8 reserved_at_10[0x10]; 10161 10162 u8 reserved_at_20[0x10]; 10163 u8 op_mod[0x10]; 10164 10165 u8 reserved_at_40[0x40]; 10166 }; 10167 10168 struct mlx5_ifc_set_wol_rol_out_bits { 10169 u8 status[0x8]; 10170 u8 reserved_at_8[0x18]; 10171 10172 u8 syndrome[0x20]; 10173 10174 u8 reserved_at_40[0x40]; 10175 }; 10176 10177 struct mlx5_ifc_set_wol_rol_in_bits { 10178 u8 opcode[0x10]; 10179 u8 reserved_at_10[0x10]; 10180 10181 u8 reserved_at_20[0x10]; 10182 u8 op_mod[0x10]; 10183 10184 u8 rol_mode_valid[0x1]; 10185 u8 wol_mode_valid[0x1]; 10186 u8 reserved_at_42[0xe]; 10187 u8 rol_mode[0x8]; 10188 u8 wol_mode[0x8]; 10189 10190 u8 reserved_at_60[0x20]; 10191 }; 10192 10193 enum { 10194 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10195 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10196 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10197 }; 10198 10199 enum { 10200 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10201 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10202 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10203 }; 10204 10205 enum { 10206 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10207 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10208 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10209 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10210 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10211 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10212 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10213 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10214 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10215 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10216 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10217 }; 10218 10219 struct mlx5_ifc_initial_seg_bits { 10220 u8 fw_rev_minor[0x10]; 10221 u8 fw_rev_major[0x10]; 10222 10223 u8 cmd_interface_rev[0x10]; 10224 u8 fw_rev_subminor[0x10]; 10225 10226 u8 reserved_at_40[0x40]; 10227 10228 u8 cmdq_phy_addr_63_32[0x20]; 10229 10230 u8 cmdq_phy_addr_31_12[0x14]; 10231 u8 reserved_at_b4[0x2]; 10232 u8 nic_interface[0x2]; 10233 u8 log_cmdq_size[0x4]; 10234 u8 log_cmdq_stride[0x4]; 10235 10236 u8 command_doorbell_vector[0x20]; 10237 10238 u8 reserved_at_e0[0xf00]; 10239 10240 u8 initializing[0x1]; 10241 u8 reserved_at_fe1[0x4]; 10242 u8 nic_interface_supported[0x3]; 10243 u8 embedded_cpu[0x1]; 10244 u8 reserved_at_fe9[0x17]; 10245 10246 struct mlx5_ifc_health_buffer_bits health_buffer; 10247 10248 u8 no_dram_nic_offset[0x20]; 10249 10250 u8 reserved_at_1220[0x6e40]; 10251 10252 u8 reserved_at_8060[0x1f]; 10253 u8 clear_int[0x1]; 10254 10255 u8 health_syndrome[0x8]; 10256 u8 health_counter[0x18]; 10257 10258 u8 reserved_at_80a0[0x17fc0]; 10259 }; 10260 10261 struct mlx5_ifc_mtpps_reg_bits { 10262 u8 reserved_at_0[0xc]; 10263 u8 cap_number_of_pps_pins[0x4]; 10264 u8 reserved_at_10[0x4]; 10265 u8 cap_max_num_of_pps_in_pins[0x4]; 10266 u8 reserved_at_18[0x4]; 10267 u8 cap_max_num_of_pps_out_pins[0x4]; 10268 10269 u8 reserved_at_20[0x24]; 10270 u8 cap_pin_3_mode[0x4]; 10271 u8 reserved_at_48[0x4]; 10272 u8 cap_pin_2_mode[0x4]; 10273 u8 reserved_at_50[0x4]; 10274 u8 cap_pin_1_mode[0x4]; 10275 u8 reserved_at_58[0x4]; 10276 u8 cap_pin_0_mode[0x4]; 10277 10278 u8 reserved_at_60[0x4]; 10279 u8 cap_pin_7_mode[0x4]; 10280 u8 reserved_at_68[0x4]; 10281 u8 cap_pin_6_mode[0x4]; 10282 u8 reserved_at_70[0x4]; 10283 u8 cap_pin_5_mode[0x4]; 10284 u8 reserved_at_78[0x4]; 10285 u8 cap_pin_4_mode[0x4]; 10286 10287 u8 field_select[0x20]; 10288 u8 reserved_at_a0[0x60]; 10289 10290 u8 enable[0x1]; 10291 u8 reserved_at_101[0xb]; 10292 u8 pattern[0x4]; 10293 u8 reserved_at_110[0x4]; 10294 u8 pin_mode[0x4]; 10295 u8 pin[0x8]; 10296 10297 u8 reserved_at_120[0x20]; 10298 10299 u8 time_stamp[0x40]; 10300 10301 u8 out_pulse_duration[0x10]; 10302 u8 out_periodic_adjustment[0x10]; 10303 u8 enhanced_out_periodic_adjustment[0x20]; 10304 10305 u8 reserved_at_1c0[0x20]; 10306 }; 10307 10308 struct mlx5_ifc_mtppse_reg_bits { 10309 u8 reserved_at_0[0x18]; 10310 u8 pin[0x8]; 10311 u8 event_arm[0x1]; 10312 u8 reserved_at_21[0x1b]; 10313 u8 event_generation_mode[0x4]; 10314 u8 reserved_at_40[0x40]; 10315 }; 10316 10317 struct mlx5_ifc_mcqs_reg_bits { 10318 u8 last_index_flag[0x1]; 10319 u8 reserved_at_1[0x7]; 10320 u8 fw_device[0x8]; 10321 u8 component_index[0x10]; 10322 10323 u8 reserved_at_20[0x10]; 10324 u8 identifier[0x10]; 10325 10326 u8 reserved_at_40[0x17]; 10327 u8 component_status[0x5]; 10328 u8 component_update_state[0x4]; 10329 10330 u8 last_update_state_changer_type[0x4]; 10331 u8 last_update_state_changer_host_id[0x4]; 10332 u8 reserved_at_68[0x18]; 10333 }; 10334 10335 struct mlx5_ifc_mcqi_cap_bits { 10336 u8 supported_info_bitmask[0x20]; 10337 10338 u8 component_size[0x20]; 10339 10340 u8 max_component_size[0x20]; 10341 10342 u8 log_mcda_word_size[0x4]; 10343 u8 reserved_at_64[0xc]; 10344 u8 mcda_max_write_size[0x10]; 10345 10346 u8 rd_en[0x1]; 10347 u8 reserved_at_81[0x1]; 10348 u8 match_chip_id[0x1]; 10349 u8 match_psid[0x1]; 10350 u8 check_user_timestamp[0x1]; 10351 u8 match_base_guid_mac[0x1]; 10352 u8 reserved_at_86[0x1a]; 10353 }; 10354 10355 struct mlx5_ifc_mcqi_version_bits { 10356 u8 reserved_at_0[0x2]; 10357 u8 build_time_valid[0x1]; 10358 u8 user_defined_time_valid[0x1]; 10359 u8 reserved_at_4[0x14]; 10360 u8 version_string_length[0x8]; 10361 10362 u8 version[0x20]; 10363 10364 u8 build_time[0x40]; 10365 10366 u8 user_defined_time[0x40]; 10367 10368 u8 build_tool_version[0x20]; 10369 10370 u8 reserved_at_e0[0x20]; 10371 10372 u8 version_string[92][0x8]; 10373 }; 10374 10375 struct mlx5_ifc_mcqi_activation_method_bits { 10376 u8 pending_server_ac_power_cycle[0x1]; 10377 u8 pending_server_dc_power_cycle[0x1]; 10378 u8 pending_server_reboot[0x1]; 10379 u8 pending_fw_reset[0x1]; 10380 u8 auto_activate[0x1]; 10381 u8 all_hosts_sync[0x1]; 10382 u8 device_hw_reset[0x1]; 10383 u8 reserved_at_7[0x19]; 10384 }; 10385 10386 union mlx5_ifc_mcqi_reg_data_bits { 10387 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10388 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10389 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10390 }; 10391 10392 struct mlx5_ifc_mcqi_reg_bits { 10393 u8 read_pending_component[0x1]; 10394 u8 reserved_at_1[0xf]; 10395 u8 component_index[0x10]; 10396 10397 u8 reserved_at_20[0x20]; 10398 10399 u8 reserved_at_40[0x1b]; 10400 u8 info_type[0x5]; 10401 10402 u8 info_size[0x20]; 10403 10404 u8 offset[0x20]; 10405 10406 u8 reserved_at_a0[0x10]; 10407 u8 data_size[0x10]; 10408 10409 union mlx5_ifc_mcqi_reg_data_bits data[]; 10410 }; 10411 10412 struct mlx5_ifc_mcc_reg_bits { 10413 u8 reserved_at_0[0x4]; 10414 u8 time_elapsed_since_last_cmd[0xc]; 10415 u8 reserved_at_10[0x8]; 10416 u8 instruction[0x8]; 10417 10418 u8 reserved_at_20[0x10]; 10419 u8 component_index[0x10]; 10420 10421 u8 reserved_at_40[0x8]; 10422 u8 update_handle[0x18]; 10423 10424 u8 handle_owner_type[0x4]; 10425 u8 handle_owner_host_id[0x4]; 10426 u8 reserved_at_68[0x1]; 10427 u8 control_progress[0x7]; 10428 u8 error_code[0x8]; 10429 u8 reserved_at_78[0x4]; 10430 u8 control_state[0x4]; 10431 10432 u8 component_size[0x20]; 10433 10434 u8 reserved_at_a0[0x60]; 10435 }; 10436 10437 struct mlx5_ifc_mcda_reg_bits { 10438 u8 reserved_at_0[0x8]; 10439 u8 update_handle[0x18]; 10440 10441 u8 offset[0x20]; 10442 10443 u8 reserved_at_40[0x10]; 10444 u8 size[0x10]; 10445 10446 u8 reserved_at_60[0x20]; 10447 10448 u8 data[][0x20]; 10449 }; 10450 10451 enum { 10452 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10453 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10454 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10455 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10456 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10457 }; 10458 10459 enum { 10460 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10461 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10462 }; 10463 10464 enum { 10465 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10466 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10467 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10468 }; 10469 10470 struct mlx5_ifc_mfrl_reg_bits { 10471 u8 reserved_at_0[0x20]; 10472 10473 u8 reserved_at_20[0x2]; 10474 u8 pci_sync_for_fw_update_start[0x1]; 10475 u8 pci_sync_for_fw_update_resp[0x2]; 10476 u8 rst_type_sel[0x3]; 10477 u8 reserved_at_28[0x4]; 10478 u8 reset_state[0x4]; 10479 u8 reset_type[0x8]; 10480 u8 reset_level[0x8]; 10481 }; 10482 10483 struct mlx5_ifc_mirc_reg_bits { 10484 u8 reserved_at_0[0x18]; 10485 u8 status_code[0x8]; 10486 10487 u8 reserved_at_20[0x20]; 10488 }; 10489 10490 struct mlx5_ifc_pddr_monitor_opcode_bits { 10491 u8 reserved_at_0[0x10]; 10492 u8 monitor_opcode[0x10]; 10493 }; 10494 10495 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10496 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10497 u8 reserved_at_0[0x20]; 10498 }; 10499 10500 enum { 10501 /* Monitor opcodes */ 10502 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10503 }; 10504 10505 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10506 u8 reserved_at_0[0x10]; 10507 u8 group_opcode[0x10]; 10508 10509 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10510 10511 u8 reserved_at_40[0x20]; 10512 10513 u8 status_message[59][0x20]; 10514 }; 10515 10516 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10517 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10518 u8 reserved_at_0[0x7c0]; 10519 }; 10520 10521 enum { 10522 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10523 }; 10524 10525 struct mlx5_ifc_pddr_reg_bits { 10526 u8 reserved_at_0[0x8]; 10527 u8 local_port[0x8]; 10528 u8 pnat[0x2]; 10529 u8 reserved_at_12[0xe]; 10530 10531 u8 reserved_at_20[0x18]; 10532 u8 page_select[0x8]; 10533 10534 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10535 }; 10536 10537 struct mlx5_ifc_mrtc_reg_bits { 10538 u8 time_synced[0x1]; 10539 u8 reserved_at_1[0x1f]; 10540 10541 u8 reserved_at_20[0x20]; 10542 10543 u8 time_h[0x20]; 10544 10545 u8 time_l[0x20]; 10546 }; 10547 10548 union mlx5_ifc_ports_control_registers_document_bits { 10549 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10550 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10551 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10552 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10553 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10554 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10555 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10556 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10557 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10558 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10559 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10560 struct mlx5_ifc_paos_reg_bits paos_reg; 10561 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10562 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10563 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10564 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10565 struct mlx5_ifc_peir_reg_bits peir_reg; 10566 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10567 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10568 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10569 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10570 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10571 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10572 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10573 struct mlx5_ifc_plib_reg_bits plib_reg; 10574 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10575 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10576 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10577 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10578 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10579 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10580 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10581 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10582 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10583 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10584 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10585 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10586 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10587 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10588 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10589 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10590 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10591 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10592 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10593 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10594 struct mlx5_ifc_pude_reg_bits pude_reg; 10595 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10596 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10597 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10598 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10599 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10600 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10601 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10602 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10603 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10604 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10605 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10606 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10607 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10608 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10609 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10610 u8 reserved_at_0[0x60e0]; 10611 }; 10612 10613 union mlx5_ifc_debug_enhancements_document_bits { 10614 struct mlx5_ifc_health_buffer_bits health_buffer; 10615 u8 reserved_at_0[0x200]; 10616 }; 10617 10618 union mlx5_ifc_uplink_pci_interface_document_bits { 10619 struct mlx5_ifc_initial_seg_bits initial_seg; 10620 u8 reserved_at_0[0x20060]; 10621 }; 10622 10623 struct mlx5_ifc_set_flow_table_root_out_bits { 10624 u8 status[0x8]; 10625 u8 reserved_at_8[0x18]; 10626 10627 u8 syndrome[0x20]; 10628 10629 u8 reserved_at_40[0x40]; 10630 }; 10631 10632 struct mlx5_ifc_set_flow_table_root_in_bits { 10633 u8 opcode[0x10]; 10634 u8 reserved_at_10[0x10]; 10635 10636 u8 reserved_at_20[0x10]; 10637 u8 op_mod[0x10]; 10638 10639 u8 other_vport[0x1]; 10640 u8 reserved_at_41[0xf]; 10641 u8 vport_number[0x10]; 10642 10643 u8 reserved_at_60[0x20]; 10644 10645 u8 table_type[0x8]; 10646 u8 reserved_at_88[0x7]; 10647 u8 table_of_other_vport[0x1]; 10648 u8 table_vport_number[0x10]; 10649 10650 u8 reserved_at_a0[0x8]; 10651 u8 table_id[0x18]; 10652 10653 u8 reserved_at_c0[0x8]; 10654 u8 underlay_qpn[0x18]; 10655 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10656 u8 reserved_at_e1[0xf]; 10657 u8 table_eswitch_owner_vhca_id[0x10]; 10658 u8 reserved_at_100[0x100]; 10659 }; 10660 10661 enum { 10662 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10663 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10664 }; 10665 10666 struct mlx5_ifc_modify_flow_table_out_bits { 10667 u8 status[0x8]; 10668 u8 reserved_at_8[0x18]; 10669 10670 u8 syndrome[0x20]; 10671 10672 u8 reserved_at_40[0x40]; 10673 }; 10674 10675 struct mlx5_ifc_modify_flow_table_in_bits { 10676 u8 opcode[0x10]; 10677 u8 reserved_at_10[0x10]; 10678 10679 u8 reserved_at_20[0x10]; 10680 u8 op_mod[0x10]; 10681 10682 u8 other_vport[0x1]; 10683 u8 reserved_at_41[0xf]; 10684 u8 vport_number[0x10]; 10685 10686 u8 reserved_at_60[0x10]; 10687 u8 modify_field_select[0x10]; 10688 10689 u8 table_type[0x8]; 10690 u8 reserved_at_88[0x18]; 10691 10692 u8 reserved_at_a0[0x8]; 10693 u8 table_id[0x18]; 10694 10695 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10696 }; 10697 10698 struct mlx5_ifc_ets_tcn_config_reg_bits { 10699 u8 g[0x1]; 10700 u8 b[0x1]; 10701 u8 r[0x1]; 10702 u8 reserved_at_3[0x9]; 10703 u8 group[0x4]; 10704 u8 reserved_at_10[0x9]; 10705 u8 bw_allocation[0x7]; 10706 10707 u8 reserved_at_20[0xc]; 10708 u8 max_bw_units[0x4]; 10709 u8 reserved_at_30[0x8]; 10710 u8 max_bw_value[0x8]; 10711 }; 10712 10713 struct mlx5_ifc_ets_global_config_reg_bits { 10714 u8 reserved_at_0[0x2]; 10715 u8 r[0x1]; 10716 u8 reserved_at_3[0x1d]; 10717 10718 u8 reserved_at_20[0xc]; 10719 u8 max_bw_units[0x4]; 10720 u8 reserved_at_30[0x8]; 10721 u8 max_bw_value[0x8]; 10722 }; 10723 10724 struct mlx5_ifc_qetc_reg_bits { 10725 u8 reserved_at_0[0x8]; 10726 u8 port_number[0x8]; 10727 u8 reserved_at_10[0x30]; 10728 10729 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10730 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10731 }; 10732 10733 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10734 u8 e[0x1]; 10735 u8 reserved_at_01[0x0b]; 10736 u8 prio[0x04]; 10737 }; 10738 10739 struct mlx5_ifc_qpdpm_reg_bits { 10740 u8 reserved_at_0[0x8]; 10741 u8 local_port[0x8]; 10742 u8 reserved_at_10[0x10]; 10743 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10744 }; 10745 10746 struct mlx5_ifc_qpts_reg_bits { 10747 u8 reserved_at_0[0x8]; 10748 u8 local_port[0x8]; 10749 u8 reserved_at_10[0x2d]; 10750 u8 trust_state[0x3]; 10751 }; 10752 10753 struct mlx5_ifc_pptb_reg_bits { 10754 u8 reserved_at_0[0x2]; 10755 u8 mm[0x2]; 10756 u8 reserved_at_4[0x4]; 10757 u8 local_port[0x8]; 10758 u8 reserved_at_10[0x6]; 10759 u8 cm[0x1]; 10760 u8 um[0x1]; 10761 u8 pm[0x8]; 10762 10763 u8 prio_x_buff[0x20]; 10764 10765 u8 pm_msb[0x8]; 10766 u8 reserved_at_48[0x10]; 10767 u8 ctrl_buff[0x4]; 10768 u8 untagged_buff[0x4]; 10769 }; 10770 10771 struct mlx5_ifc_sbcam_reg_bits { 10772 u8 reserved_at_0[0x8]; 10773 u8 feature_group[0x8]; 10774 u8 reserved_at_10[0x8]; 10775 u8 access_reg_group[0x8]; 10776 10777 u8 reserved_at_20[0x20]; 10778 10779 u8 sb_access_reg_cap_mask[4][0x20]; 10780 10781 u8 reserved_at_c0[0x80]; 10782 10783 u8 sb_feature_cap_mask[4][0x20]; 10784 10785 u8 reserved_at_1c0[0x40]; 10786 10787 u8 cap_total_buffer_size[0x20]; 10788 10789 u8 cap_cell_size[0x10]; 10790 u8 cap_max_pg_buffers[0x8]; 10791 u8 cap_num_pool_supported[0x8]; 10792 10793 u8 reserved_at_240[0x8]; 10794 u8 cap_sbsr_stat_size[0x8]; 10795 u8 cap_max_tclass_data[0x8]; 10796 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10797 }; 10798 10799 struct mlx5_ifc_pbmc_reg_bits { 10800 u8 reserved_at_0[0x8]; 10801 u8 local_port[0x8]; 10802 u8 reserved_at_10[0x10]; 10803 10804 u8 xoff_timer_value[0x10]; 10805 u8 xoff_refresh[0x10]; 10806 10807 u8 reserved_at_40[0x9]; 10808 u8 fullness_threshold[0x7]; 10809 u8 port_buffer_size[0x10]; 10810 10811 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10812 10813 u8 reserved_at_2e0[0x80]; 10814 }; 10815 10816 struct mlx5_ifc_qtct_reg_bits { 10817 u8 reserved_at_0[0x8]; 10818 u8 port_number[0x8]; 10819 u8 reserved_at_10[0xd]; 10820 u8 prio[0x3]; 10821 10822 u8 reserved_at_20[0x1d]; 10823 u8 tclass[0x3]; 10824 }; 10825 10826 struct mlx5_ifc_mcia_reg_bits { 10827 u8 l[0x1]; 10828 u8 reserved_at_1[0x7]; 10829 u8 module[0x8]; 10830 u8 reserved_at_10[0x8]; 10831 u8 status[0x8]; 10832 10833 u8 i2c_device_address[0x8]; 10834 u8 page_number[0x8]; 10835 u8 device_address[0x10]; 10836 10837 u8 reserved_at_40[0x10]; 10838 u8 size[0x10]; 10839 10840 u8 reserved_at_60[0x20]; 10841 10842 u8 dword_0[0x20]; 10843 u8 dword_1[0x20]; 10844 u8 dword_2[0x20]; 10845 u8 dword_3[0x20]; 10846 u8 dword_4[0x20]; 10847 u8 dword_5[0x20]; 10848 u8 dword_6[0x20]; 10849 u8 dword_7[0x20]; 10850 u8 dword_8[0x20]; 10851 u8 dword_9[0x20]; 10852 u8 dword_10[0x20]; 10853 u8 dword_11[0x20]; 10854 }; 10855 10856 struct mlx5_ifc_dcbx_param_bits { 10857 u8 dcbx_cee_cap[0x1]; 10858 u8 dcbx_ieee_cap[0x1]; 10859 u8 dcbx_standby_cap[0x1]; 10860 u8 reserved_at_3[0x5]; 10861 u8 port_number[0x8]; 10862 u8 reserved_at_10[0xa]; 10863 u8 max_application_table_size[6]; 10864 u8 reserved_at_20[0x15]; 10865 u8 version_oper[0x3]; 10866 u8 reserved_at_38[5]; 10867 u8 version_admin[0x3]; 10868 u8 willing_admin[0x1]; 10869 u8 reserved_at_41[0x3]; 10870 u8 pfc_cap_oper[0x4]; 10871 u8 reserved_at_48[0x4]; 10872 u8 pfc_cap_admin[0x4]; 10873 u8 reserved_at_50[0x4]; 10874 u8 num_of_tc_oper[0x4]; 10875 u8 reserved_at_58[0x4]; 10876 u8 num_of_tc_admin[0x4]; 10877 u8 remote_willing[0x1]; 10878 u8 reserved_at_61[3]; 10879 u8 remote_pfc_cap[4]; 10880 u8 reserved_at_68[0x14]; 10881 u8 remote_num_of_tc[0x4]; 10882 u8 reserved_at_80[0x18]; 10883 u8 error[0x8]; 10884 u8 reserved_at_a0[0x160]; 10885 }; 10886 10887 enum { 10888 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10889 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 10890 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 10891 }; 10892 10893 struct mlx5_ifc_lagc_bits { 10894 u8 fdb_selection_mode[0x1]; 10895 u8 reserved_at_1[0x14]; 10896 u8 port_select_mode[0x3]; 10897 u8 reserved_at_18[0x5]; 10898 u8 lag_state[0x3]; 10899 10900 u8 reserved_at_20[0x14]; 10901 u8 tx_remap_affinity_2[0x4]; 10902 u8 reserved_at_38[0x4]; 10903 u8 tx_remap_affinity_1[0x4]; 10904 }; 10905 10906 struct mlx5_ifc_create_lag_out_bits { 10907 u8 status[0x8]; 10908 u8 reserved_at_8[0x18]; 10909 10910 u8 syndrome[0x20]; 10911 10912 u8 reserved_at_40[0x40]; 10913 }; 10914 10915 struct mlx5_ifc_create_lag_in_bits { 10916 u8 opcode[0x10]; 10917 u8 reserved_at_10[0x10]; 10918 10919 u8 reserved_at_20[0x10]; 10920 u8 op_mod[0x10]; 10921 10922 struct mlx5_ifc_lagc_bits ctx; 10923 }; 10924 10925 struct mlx5_ifc_modify_lag_out_bits { 10926 u8 status[0x8]; 10927 u8 reserved_at_8[0x18]; 10928 10929 u8 syndrome[0x20]; 10930 10931 u8 reserved_at_40[0x40]; 10932 }; 10933 10934 struct mlx5_ifc_modify_lag_in_bits { 10935 u8 opcode[0x10]; 10936 u8 reserved_at_10[0x10]; 10937 10938 u8 reserved_at_20[0x10]; 10939 u8 op_mod[0x10]; 10940 10941 u8 reserved_at_40[0x20]; 10942 u8 field_select[0x20]; 10943 10944 struct mlx5_ifc_lagc_bits ctx; 10945 }; 10946 10947 struct mlx5_ifc_query_lag_out_bits { 10948 u8 status[0x8]; 10949 u8 reserved_at_8[0x18]; 10950 10951 u8 syndrome[0x20]; 10952 10953 struct mlx5_ifc_lagc_bits ctx; 10954 }; 10955 10956 struct mlx5_ifc_query_lag_in_bits { 10957 u8 opcode[0x10]; 10958 u8 reserved_at_10[0x10]; 10959 10960 u8 reserved_at_20[0x10]; 10961 u8 op_mod[0x10]; 10962 10963 u8 reserved_at_40[0x40]; 10964 }; 10965 10966 struct mlx5_ifc_destroy_lag_out_bits { 10967 u8 status[0x8]; 10968 u8 reserved_at_8[0x18]; 10969 10970 u8 syndrome[0x20]; 10971 10972 u8 reserved_at_40[0x40]; 10973 }; 10974 10975 struct mlx5_ifc_destroy_lag_in_bits { 10976 u8 opcode[0x10]; 10977 u8 reserved_at_10[0x10]; 10978 10979 u8 reserved_at_20[0x10]; 10980 u8 op_mod[0x10]; 10981 10982 u8 reserved_at_40[0x40]; 10983 }; 10984 10985 struct mlx5_ifc_create_vport_lag_out_bits { 10986 u8 status[0x8]; 10987 u8 reserved_at_8[0x18]; 10988 10989 u8 syndrome[0x20]; 10990 10991 u8 reserved_at_40[0x40]; 10992 }; 10993 10994 struct mlx5_ifc_create_vport_lag_in_bits { 10995 u8 opcode[0x10]; 10996 u8 reserved_at_10[0x10]; 10997 10998 u8 reserved_at_20[0x10]; 10999 u8 op_mod[0x10]; 11000 11001 u8 reserved_at_40[0x40]; 11002 }; 11003 11004 struct mlx5_ifc_destroy_vport_lag_out_bits { 11005 u8 status[0x8]; 11006 u8 reserved_at_8[0x18]; 11007 11008 u8 syndrome[0x20]; 11009 11010 u8 reserved_at_40[0x40]; 11011 }; 11012 11013 struct mlx5_ifc_destroy_vport_lag_in_bits { 11014 u8 opcode[0x10]; 11015 u8 reserved_at_10[0x10]; 11016 11017 u8 reserved_at_20[0x10]; 11018 u8 op_mod[0x10]; 11019 11020 u8 reserved_at_40[0x40]; 11021 }; 11022 11023 enum { 11024 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11025 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11026 }; 11027 11028 struct mlx5_ifc_modify_memic_in_bits { 11029 u8 opcode[0x10]; 11030 u8 uid[0x10]; 11031 11032 u8 reserved_at_20[0x10]; 11033 u8 op_mod[0x10]; 11034 11035 u8 reserved_at_40[0x20]; 11036 11037 u8 reserved_at_60[0x18]; 11038 u8 memic_operation_type[0x8]; 11039 11040 u8 memic_start_addr[0x40]; 11041 11042 u8 reserved_at_c0[0x140]; 11043 }; 11044 11045 struct mlx5_ifc_modify_memic_out_bits { 11046 u8 status[0x8]; 11047 u8 reserved_at_8[0x18]; 11048 11049 u8 syndrome[0x20]; 11050 11051 u8 reserved_at_40[0x40]; 11052 11053 u8 memic_operation_addr[0x40]; 11054 11055 u8 reserved_at_c0[0x140]; 11056 }; 11057 11058 struct mlx5_ifc_alloc_memic_in_bits { 11059 u8 opcode[0x10]; 11060 u8 reserved_at_10[0x10]; 11061 11062 u8 reserved_at_20[0x10]; 11063 u8 op_mod[0x10]; 11064 11065 u8 reserved_at_30[0x20]; 11066 11067 u8 reserved_at_40[0x18]; 11068 u8 log_memic_addr_alignment[0x8]; 11069 11070 u8 range_start_addr[0x40]; 11071 11072 u8 range_size[0x20]; 11073 11074 u8 memic_size[0x20]; 11075 }; 11076 11077 struct mlx5_ifc_alloc_memic_out_bits { 11078 u8 status[0x8]; 11079 u8 reserved_at_8[0x18]; 11080 11081 u8 syndrome[0x20]; 11082 11083 u8 memic_start_addr[0x40]; 11084 }; 11085 11086 struct mlx5_ifc_dealloc_memic_in_bits { 11087 u8 opcode[0x10]; 11088 u8 reserved_at_10[0x10]; 11089 11090 u8 reserved_at_20[0x10]; 11091 u8 op_mod[0x10]; 11092 11093 u8 reserved_at_40[0x40]; 11094 11095 u8 memic_start_addr[0x40]; 11096 11097 u8 memic_size[0x20]; 11098 11099 u8 reserved_at_e0[0x20]; 11100 }; 11101 11102 struct mlx5_ifc_dealloc_memic_out_bits { 11103 u8 status[0x8]; 11104 u8 reserved_at_8[0x18]; 11105 11106 u8 syndrome[0x20]; 11107 11108 u8 reserved_at_40[0x40]; 11109 }; 11110 11111 struct mlx5_ifc_umem_bits { 11112 u8 reserved_at_0[0x80]; 11113 11114 u8 reserved_at_80[0x1b]; 11115 u8 log_page_size[0x5]; 11116 11117 u8 page_offset[0x20]; 11118 11119 u8 num_of_mtt[0x40]; 11120 11121 struct mlx5_ifc_mtt_bits mtt[]; 11122 }; 11123 11124 struct mlx5_ifc_uctx_bits { 11125 u8 cap[0x20]; 11126 11127 u8 reserved_at_20[0x160]; 11128 }; 11129 11130 struct mlx5_ifc_sw_icm_bits { 11131 u8 modify_field_select[0x40]; 11132 11133 u8 reserved_at_40[0x18]; 11134 u8 log_sw_icm_size[0x8]; 11135 11136 u8 reserved_at_60[0x20]; 11137 11138 u8 sw_icm_start_addr[0x40]; 11139 11140 u8 reserved_at_c0[0x140]; 11141 }; 11142 11143 struct mlx5_ifc_geneve_tlv_option_bits { 11144 u8 modify_field_select[0x40]; 11145 11146 u8 reserved_at_40[0x18]; 11147 u8 geneve_option_fte_index[0x8]; 11148 11149 u8 option_class[0x10]; 11150 u8 option_type[0x8]; 11151 u8 reserved_at_78[0x3]; 11152 u8 option_data_length[0x5]; 11153 11154 u8 reserved_at_80[0x180]; 11155 }; 11156 11157 struct mlx5_ifc_create_umem_in_bits { 11158 u8 opcode[0x10]; 11159 u8 uid[0x10]; 11160 11161 u8 reserved_at_20[0x10]; 11162 u8 op_mod[0x10]; 11163 11164 u8 reserved_at_40[0x40]; 11165 11166 struct mlx5_ifc_umem_bits umem; 11167 }; 11168 11169 struct mlx5_ifc_create_umem_out_bits { 11170 u8 status[0x8]; 11171 u8 reserved_at_8[0x18]; 11172 11173 u8 syndrome[0x20]; 11174 11175 u8 reserved_at_40[0x8]; 11176 u8 umem_id[0x18]; 11177 11178 u8 reserved_at_60[0x20]; 11179 }; 11180 11181 struct mlx5_ifc_destroy_umem_in_bits { 11182 u8 opcode[0x10]; 11183 u8 uid[0x10]; 11184 11185 u8 reserved_at_20[0x10]; 11186 u8 op_mod[0x10]; 11187 11188 u8 reserved_at_40[0x8]; 11189 u8 umem_id[0x18]; 11190 11191 u8 reserved_at_60[0x20]; 11192 }; 11193 11194 struct mlx5_ifc_destroy_umem_out_bits { 11195 u8 status[0x8]; 11196 u8 reserved_at_8[0x18]; 11197 11198 u8 syndrome[0x20]; 11199 11200 u8 reserved_at_40[0x40]; 11201 }; 11202 11203 struct mlx5_ifc_create_uctx_in_bits { 11204 u8 opcode[0x10]; 11205 u8 reserved_at_10[0x10]; 11206 11207 u8 reserved_at_20[0x10]; 11208 u8 op_mod[0x10]; 11209 11210 u8 reserved_at_40[0x40]; 11211 11212 struct mlx5_ifc_uctx_bits uctx; 11213 }; 11214 11215 struct mlx5_ifc_create_uctx_out_bits { 11216 u8 status[0x8]; 11217 u8 reserved_at_8[0x18]; 11218 11219 u8 syndrome[0x20]; 11220 11221 u8 reserved_at_40[0x10]; 11222 u8 uid[0x10]; 11223 11224 u8 reserved_at_60[0x20]; 11225 }; 11226 11227 struct mlx5_ifc_destroy_uctx_in_bits { 11228 u8 opcode[0x10]; 11229 u8 reserved_at_10[0x10]; 11230 11231 u8 reserved_at_20[0x10]; 11232 u8 op_mod[0x10]; 11233 11234 u8 reserved_at_40[0x10]; 11235 u8 uid[0x10]; 11236 11237 u8 reserved_at_60[0x20]; 11238 }; 11239 11240 struct mlx5_ifc_destroy_uctx_out_bits { 11241 u8 status[0x8]; 11242 u8 reserved_at_8[0x18]; 11243 11244 u8 syndrome[0x20]; 11245 11246 u8 reserved_at_40[0x40]; 11247 }; 11248 11249 struct mlx5_ifc_create_sw_icm_in_bits { 11250 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11251 struct mlx5_ifc_sw_icm_bits sw_icm; 11252 }; 11253 11254 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11255 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11256 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11257 }; 11258 11259 struct mlx5_ifc_mtrc_string_db_param_bits { 11260 u8 string_db_base_address[0x20]; 11261 11262 u8 reserved_at_20[0x8]; 11263 u8 string_db_size[0x18]; 11264 }; 11265 11266 struct mlx5_ifc_mtrc_cap_bits { 11267 u8 trace_owner[0x1]; 11268 u8 trace_to_memory[0x1]; 11269 u8 reserved_at_2[0x4]; 11270 u8 trc_ver[0x2]; 11271 u8 reserved_at_8[0x14]; 11272 u8 num_string_db[0x4]; 11273 11274 u8 first_string_trace[0x8]; 11275 u8 num_string_trace[0x8]; 11276 u8 reserved_at_30[0x28]; 11277 11278 u8 log_max_trace_buffer_size[0x8]; 11279 11280 u8 reserved_at_60[0x20]; 11281 11282 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11283 11284 u8 reserved_at_280[0x180]; 11285 }; 11286 11287 struct mlx5_ifc_mtrc_conf_bits { 11288 u8 reserved_at_0[0x1c]; 11289 u8 trace_mode[0x4]; 11290 u8 reserved_at_20[0x18]; 11291 u8 log_trace_buffer_size[0x8]; 11292 u8 trace_mkey[0x20]; 11293 u8 reserved_at_60[0x3a0]; 11294 }; 11295 11296 struct mlx5_ifc_mtrc_stdb_bits { 11297 u8 string_db_index[0x4]; 11298 u8 reserved_at_4[0x4]; 11299 u8 read_size[0x18]; 11300 u8 start_offset[0x20]; 11301 u8 string_db_data[]; 11302 }; 11303 11304 struct mlx5_ifc_mtrc_ctrl_bits { 11305 u8 trace_status[0x2]; 11306 u8 reserved_at_2[0x2]; 11307 u8 arm_event[0x1]; 11308 u8 reserved_at_5[0xb]; 11309 u8 modify_field_select[0x10]; 11310 u8 reserved_at_20[0x2b]; 11311 u8 current_timestamp52_32[0x15]; 11312 u8 current_timestamp31_0[0x20]; 11313 u8 reserved_at_80[0x180]; 11314 }; 11315 11316 struct mlx5_ifc_host_params_context_bits { 11317 u8 host_number[0x8]; 11318 u8 reserved_at_8[0x7]; 11319 u8 host_pf_disabled[0x1]; 11320 u8 host_num_of_vfs[0x10]; 11321 11322 u8 host_total_vfs[0x10]; 11323 u8 host_pci_bus[0x10]; 11324 11325 u8 reserved_at_40[0x10]; 11326 u8 host_pci_device[0x10]; 11327 11328 u8 reserved_at_60[0x10]; 11329 u8 host_pci_function[0x10]; 11330 11331 u8 reserved_at_80[0x180]; 11332 }; 11333 11334 struct mlx5_ifc_query_esw_functions_in_bits { 11335 u8 opcode[0x10]; 11336 u8 reserved_at_10[0x10]; 11337 11338 u8 reserved_at_20[0x10]; 11339 u8 op_mod[0x10]; 11340 11341 u8 reserved_at_40[0x40]; 11342 }; 11343 11344 struct mlx5_ifc_query_esw_functions_out_bits { 11345 u8 status[0x8]; 11346 u8 reserved_at_8[0x18]; 11347 11348 u8 syndrome[0x20]; 11349 11350 u8 reserved_at_40[0x40]; 11351 11352 struct mlx5_ifc_host_params_context_bits host_params_context; 11353 11354 u8 reserved_at_280[0x180]; 11355 u8 host_sf_enable[][0x40]; 11356 }; 11357 11358 struct mlx5_ifc_sf_partition_bits { 11359 u8 reserved_at_0[0x10]; 11360 u8 log_num_sf[0x8]; 11361 u8 log_sf_bar_size[0x8]; 11362 }; 11363 11364 struct mlx5_ifc_query_sf_partitions_out_bits { 11365 u8 status[0x8]; 11366 u8 reserved_at_8[0x18]; 11367 11368 u8 syndrome[0x20]; 11369 11370 u8 reserved_at_40[0x18]; 11371 u8 num_sf_partitions[0x8]; 11372 11373 u8 reserved_at_60[0x20]; 11374 11375 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11376 }; 11377 11378 struct mlx5_ifc_query_sf_partitions_in_bits { 11379 u8 opcode[0x10]; 11380 u8 reserved_at_10[0x10]; 11381 11382 u8 reserved_at_20[0x10]; 11383 u8 op_mod[0x10]; 11384 11385 u8 reserved_at_40[0x40]; 11386 }; 11387 11388 struct mlx5_ifc_dealloc_sf_out_bits { 11389 u8 status[0x8]; 11390 u8 reserved_at_8[0x18]; 11391 11392 u8 syndrome[0x20]; 11393 11394 u8 reserved_at_40[0x40]; 11395 }; 11396 11397 struct mlx5_ifc_dealloc_sf_in_bits { 11398 u8 opcode[0x10]; 11399 u8 reserved_at_10[0x10]; 11400 11401 u8 reserved_at_20[0x10]; 11402 u8 op_mod[0x10]; 11403 11404 u8 reserved_at_40[0x10]; 11405 u8 function_id[0x10]; 11406 11407 u8 reserved_at_60[0x20]; 11408 }; 11409 11410 struct mlx5_ifc_alloc_sf_out_bits { 11411 u8 status[0x8]; 11412 u8 reserved_at_8[0x18]; 11413 11414 u8 syndrome[0x20]; 11415 11416 u8 reserved_at_40[0x40]; 11417 }; 11418 11419 struct mlx5_ifc_alloc_sf_in_bits { 11420 u8 opcode[0x10]; 11421 u8 reserved_at_10[0x10]; 11422 11423 u8 reserved_at_20[0x10]; 11424 u8 op_mod[0x10]; 11425 11426 u8 reserved_at_40[0x10]; 11427 u8 function_id[0x10]; 11428 11429 u8 reserved_at_60[0x20]; 11430 }; 11431 11432 struct mlx5_ifc_affiliated_event_header_bits { 11433 u8 reserved_at_0[0x10]; 11434 u8 obj_type[0x10]; 11435 11436 u8 obj_id[0x20]; 11437 }; 11438 11439 enum { 11440 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11441 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11442 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11443 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11444 }; 11445 11446 enum { 11447 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11448 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11449 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11450 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11451 }; 11452 11453 enum { 11454 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11455 }; 11456 11457 struct mlx5_ifc_ipsec_obj_bits { 11458 u8 modify_field_select[0x40]; 11459 u8 full_offload[0x1]; 11460 u8 reserved_at_41[0x1]; 11461 u8 esn_en[0x1]; 11462 u8 esn_overlap[0x1]; 11463 u8 reserved_at_44[0x2]; 11464 u8 icv_length[0x2]; 11465 u8 reserved_at_48[0x4]; 11466 u8 aso_return_reg[0x4]; 11467 u8 reserved_at_50[0x10]; 11468 11469 u8 esn_msb[0x20]; 11470 11471 u8 reserved_at_80[0x8]; 11472 u8 dekn[0x18]; 11473 11474 u8 salt[0x20]; 11475 11476 u8 implicit_iv[0x40]; 11477 11478 u8 reserved_at_100[0x700]; 11479 }; 11480 11481 struct mlx5_ifc_create_ipsec_obj_in_bits { 11482 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11483 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11484 }; 11485 11486 enum { 11487 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11488 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11489 }; 11490 11491 struct mlx5_ifc_query_ipsec_obj_out_bits { 11492 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11493 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11494 }; 11495 11496 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11497 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11498 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11499 }; 11500 11501 struct mlx5_ifc_encryption_key_obj_bits { 11502 u8 modify_field_select[0x40]; 11503 11504 u8 reserved_at_40[0x14]; 11505 u8 key_size[0x4]; 11506 u8 reserved_at_58[0x4]; 11507 u8 key_type[0x4]; 11508 11509 u8 reserved_at_60[0x8]; 11510 u8 pd[0x18]; 11511 11512 u8 reserved_at_80[0x180]; 11513 u8 key[8][0x20]; 11514 11515 u8 reserved_at_300[0x500]; 11516 }; 11517 11518 struct mlx5_ifc_create_encryption_key_in_bits { 11519 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11520 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11521 }; 11522 11523 enum { 11524 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 11525 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 11526 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 11527 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 11528 }; 11529 11530 struct mlx5_ifc_flow_meter_parameters_bits { 11531 u8 valid[0x1]; 11532 u8 bucket_overflow[0x1]; 11533 u8 start_color[0x2]; 11534 u8 both_buckets_on_green[0x1]; 11535 u8 reserved_at_5[0x1]; 11536 u8 meter_mode[0x2]; 11537 u8 reserved_at_8[0x18]; 11538 11539 u8 reserved_at_20[0x20]; 11540 11541 u8 reserved_at_40[0x3]; 11542 u8 cbs_exponent[0x5]; 11543 u8 cbs_mantissa[0x8]; 11544 u8 reserved_at_50[0x3]; 11545 u8 cir_exponent[0x5]; 11546 u8 cir_mantissa[0x8]; 11547 11548 u8 reserved_at_60[0x20]; 11549 11550 u8 reserved_at_80[0x3]; 11551 u8 ebs_exponent[0x5]; 11552 u8 ebs_mantissa[0x8]; 11553 u8 reserved_at_90[0x3]; 11554 u8 eir_exponent[0x5]; 11555 u8 eir_mantissa[0x8]; 11556 11557 u8 reserved_at_a0[0x60]; 11558 }; 11559 11560 struct mlx5_ifc_flow_meter_aso_obj_bits { 11561 u8 modify_field_select[0x40]; 11562 11563 u8 reserved_at_40[0x40]; 11564 11565 u8 reserved_at_80[0x8]; 11566 u8 meter_aso_access_pd[0x18]; 11567 11568 u8 reserved_at_a0[0x160]; 11569 11570 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 11571 }; 11572 11573 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 11574 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11575 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 11576 }; 11577 11578 struct mlx5_ifc_sampler_obj_bits { 11579 u8 modify_field_select[0x40]; 11580 11581 u8 table_type[0x8]; 11582 u8 level[0x8]; 11583 u8 reserved_at_50[0xf]; 11584 u8 ignore_flow_level[0x1]; 11585 11586 u8 sample_ratio[0x20]; 11587 11588 u8 reserved_at_80[0x8]; 11589 u8 sample_table_id[0x18]; 11590 11591 u8 reserved_at_a0[0x8]; 11592 u8 default_table_id[0x18]; 11593 11594 u8 sw_steering_icm_address_rx[0x40]; 11595 u8 sw_steering_icm_address_tx[0x40]; 11596 11597 u8 reserved_at_140[0xa0]; 11598 }; 11599 11600 struct mlx5_ifc_create_sampler_obj_in_bits { 11601 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11602 struct mlx5_ifc_sampler_obj_bits sampler_object; 11603 }; 11604 11605 struct mlx5_ifc_query_sampler_obj_out_bits { 11606 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11607 struct mlx5_ifc_sampler_obj_bits sampler_object; 11608 }; 11609 11610 enum { 11611 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11612 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11613 }; 11614 11615 enum { 11616 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11617 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11618 }; 11619 11620 struct mlx5_ifc_tls_static_params_bits { 11621 u8 const_2[0x2]; 11622 u8 tls_version[0x4]; 11623 u8 const_1[0x2]; 11624 u8 reserved_at_8[0x14]; 11625 u8 encryption_standard[0x4]; 11626 11627 u8 reserved_at_20[0x20]; 11628 11629 u8 initial_record_number[0x40]; 11630 11631 u8 resync_tcp_sn[0x20]; 11632 11633 u8 gcm_iv[0x20]; 11634 11635 u8 implicit_iv[0x40]; 11636 11637 u8 reserved_at_100[0x8]; 11638 u8 dek_index[0x18]; 11639 11640 u8 reserved_at_120[0xe0]; 11641 }; 11642 11643 struct mlx5_ifc_tls_progress_params_bits { 11644 u8 next_record_tcp_sn[0x20]; 11645 11646 u8 hw_resync_tcp_sn[0x20]; 11647 11648 u8 record_tracker_state[0x2]; 11649 u8 auth_state[0x2]; 11650 u8 reserved_at_44[0x4]; 11651 u8 hw_offset_record_number[0x18]; 11652 }; 11653 11654 enum { 11655 MLX5_MTT_PERM_READ = 1 << 0, 11656 MLX5_MTT_PERM_WRITE = 1 << 1, 11657 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11658 }; 11659 11660 enum { 11661 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11662 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11663 }; 11664 11665 struct mlx5_ifc_suspend_vhca_in_bits { 11666 u8 opcode[0x10]; 11667 u8 uid[0x10]; 11668 11669 u8 reserved_at_20[0x10]; 11670 u8 op_mod[0x10]; 11671 11672 u8 reserved_at_40[0x10]; 11673 u8 vhca_id[0x10]; 11674 11675 u8 reserved_at_60[0x20]; 11676 }; 11677 11678 struct mlx5_ifc_suspend_vhca_out_bits { 11679 u8 status[0x8]; 11680 u8 reserved_at_8[0x18]; 11681 11682 u8 syndrome[0x20]; 11683 11684 u8 reserved_at_40[0x40]; 11685 }; 11686 11687 enum { 11688 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 11689 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 11690 }; 11691 11692 struct mlx5_ifc_resume_vhca_in_bits { 11693 u8 opcode[0x10]; 11694 u8 uid[0x10]; 11695 11696 u8 reserved_at_20[0x10]; 11697 u8 op_mod[0x10]; 11698 11699 u8 reserved_at_40[0x10]; 11700 u8 vhca_id[0x10]; 11701 11702 u8 reserved_at_60[0x20]; 11703 }; 11704 11705 struct mlx5_ifc_resume_vhca_out_bits { 11706 u8 status[0x8]; 11707 u8 reserved_at_8[0x18]; 11708 11709 u8 syndrome[0x20]; 11710 11711 u8 reserved_at_40[0x40]; 11712 }; 11713 11714 struct mlx5_ifc_query_vhca_migration_state_in_bits { 11715 u8 opcode[0x10]; 11716 u8 uid[0x10]; 11717 11718 u8 reserved_at_20[0x10]; 11719 u8 op_mod[0x10]; 11720 11721 u8 reserved_at_40[0x10]; 11722 u8 vhca_id[0x10]; 11723 11724 u8 reserved_at_60[0x20]; 11725 }; 11726 11727 struct mlx5_ifc_query_vhca_migration_state_out_bits { 11728 u8 status[0x8]; 11729 u8 reserved_at_8[0x18]; 11730 11731 u8 syndrome[0x20]; 11732 11733 u8 reserved_at_40[0x40]; 11734 11735 u8 required_umem_size[0x20]; 11736 11737 u8 reserved_at_a0[0x160]; 11738 }; 11739 11740 struct mlx5_ifc_save_vhca_state_in_bits { 11741 u8 opcode[0x10]; 11742 u8 uid[0x10]; 11743 11744 u8 reserved_at_20[0x10]; 11745 u8 op_mod[0x10]; 11746 11747 u8 reserved_at_40[0x10]; 11748 u8 vhca_id[0x10]; 11749 11750 u8 reserved_at_60[0x20]; 11751 11752 u8 va[0x40]; 11753 11754 u8 mkey[0x20]; 11755 11756 u8 size[0x20]; 11757 }; 11758 11759 struct mlx5_ifc_save_vhca_state_out_bits { 11760 u8 status[0x8]; 11761 u8 reserved_at_8[0x18]; 11762 11763 u8 syndrome[0x20]; 11764 11765 u8 actual_image_size[0x20]; 11766 11767 u8 reserved_at_60[0x20]; 11768 }; 11769 11770 struct mlx5_ifc_load_vhca_state_in_bits { 11771 u8 opcode[0x10]; 11772 u8 uid[0x10]; 11773 11774 u8 reserved_at_20[0x10]; 11775 u8 op_mod[0x10]; 11776 11777 u8 reserved_at_40[0x10]; 11778 u8 vhca_id[0x10]; 11779 11780 u8 reserved_at_60[0x20]; 11781 11782 u8 va[0x40]; 11783 11784 u8 mkey[0x20]; 11785 11786 u8 size[0x20]; 11787 }; 11788 11789 struct mlx5_ifc_load_vhca_state_out_bits { 11790 u8 status[0x8]; 11791 u8 reserved_at_8[0x18]; 11792 11793 u8 syndrome[0x20]; 11794 11795 u8 reserved_at_40[0x40]; 11796 }; 11797 11798 #endif /* MLX5_IFC_H */ 11799