1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 97 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 98 MLX5_OBJ_TYPE_MKEY = 0xff01, 99 MLX5_OBJ_TYPE_QP = 0xff02, 100 MLX5_OBJ_TYPE_PSV = 0xff03, 101 MLX5_OBJ_TYPE_RMP = 0xff04, 102 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 103 MLX5_OBJ_TYPE_RQ = 0xff06, 104 MLX5_OBJ_TYPE_SQ = 0xff07, 105 MLX5_OBJ_TYPE_TIR = 0xff08, 106 MLX5_OBJ_TYPE_TIS = 0xff09, 107 MLX5_OBJ_TYPE_DCT = 0xff0a, 108 MLX5_OBJ_TYPE_XRQ = 0xff0b, 109 MLX5_OBJ_TYPE_RQT = 0xff0e, 110 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 111 MLX5_OBJ_TYPE_CQ = 0xff10, 112 }; 113 114 enum { 115 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 116 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 117 MLX5_CMD_OP_INIT_HCA = 0x102, 118 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 119 MLX5_CMD_OP_ENABLE_HCA = 0x104, 120 MLX5_CMD_OP_DISABLE_HCA = 0x105, 121 MLX5_CMD_OP_QUERY_PAGES = 0x107, 122 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 123 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 124 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 125 MLX5_CMD_OP_SET_ISSI = 0x10b, 126 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 127 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 128 MLX5_CMD_OP_ALLOC_SF = 0x113, 129 MLX5_CMD_OP_DEALLOC_SF = 0x114, 130 MLX5_CMD_OP_CREATE_MKEY = 0x200, 131 MLX5_CMD_OP_QUERY_MKEY = 0x201, 132 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 133 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 134 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 135 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 136 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 137 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 138 MLX5_CMD_OP_CREATE_EQ = 0x301, 139 MLX5_CMD_OP_DESTROY_EQ = 0x302, 140 MLX5_CMD_OP_QUERY_EQ = 0x303, 141 MLX5_CMD_OP_GEN_EQE = 0x304, 142 MLX5_CMD_OP_CREATE_CQ = 0x400, 143 MLX5_CMD_OP_DESTROY_CQ = 0x401, 144 MLX5_CMD_OP_QUERY_CQ = 0x402, 145 MLX5_CMD_OP_MODIFY_CQ = 0x403, 146 MLX5_CMD_OP_CREATE_QP = 0x500, 147 MLX5_CMD_OP_DESTROY_QP = 0x501, 148 MLX5_CMD_OP_RST2INIT_QP = 0x502, 149 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 150 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 151 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 152 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 153 MLX5_CMD_OP_2ERR_QP = 0x507, 154 MLX5_CMD_OP_2RST_QP = 0x50a, 155 MLX5_CMD_OP_QUERY_QP = 0x50b, 156 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 157 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 158 MLX5_CMD_OP_CREATE_PSV = 0x600, 159 MLX5_CMD_OP_DESTROY_PSV = 0x601, 160 MLX5_CMD_OP_CREATE_SRQ = 0x700, 161 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 162 MLX5_CMD_OP_QUERY_SRQ = 0x702, 163 MLX5_CMD_OP_ARM_RQ = 0x703, 164 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 165 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 166 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 167 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 168 MLX5_CMD_OP_CREATE_DCT = 0x710, 169 MLX5_CMD_OP_DESTROY_DCT = 0x711, 170 MLX5_CMD_OP_DRAIN_DCT = 0x712, 171 MLX5_CMD_OP_QUERY_DCT = 0x713, 172 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 173 MLX5_CMD_OP_CREATE_XRQ = 0x717, 174 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 175 MLX5_CMD_OP_QUERY_XRQ = 0x719, 176 MLX5_CMD_OP_ARM_XRQ = 0x71a, 177 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 178 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 179 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 180 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 181 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 182 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 183 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 184 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 185 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 186 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 187 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 188 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 189 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 190 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 192 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 194 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 195 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 196 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 197 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 198 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 199 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 200 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 201 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 202 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 203 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 204 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 205 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 206 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 207 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 208 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 209 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 210 MLX5_CMD_OP_ALLOC_PD = 0x800, 211 MLX5_CMD_OP_DEALLOC_PD = 0x801, 212 MLX5_CMD_OP_ALLOC_UAR = 0x802, 213 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 214 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 215 MLX5_CMD_OP_ACCESS_REG = 0x805, 216 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 217 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 218 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 219 MLX5_CMD_OP_MAD_IFC = 0x50d, 220 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 221 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 222 MLX5_CMD_OP_NOP = 0x80d, 223 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 224 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 225 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 226 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 227 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 228 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 229 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 230 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 231 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 232 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 233 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 234 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 235 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 236 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 237 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 238 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 239 MLX5_CMD_OP_CREATE_LAG = 0x840, 240 MLX5_CMD_OP_MODIFY_LAG = 0x841, 241 MLX5_CMD_OP_QUERY_LAG = 0x842, 242 MLX5_CMD_OP_DESTROY_LAG = 0x843, 243 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 244 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 245 MLX5_CMD_OP_CREATE_TIR = 0x900, 246 MLX5_CMD_OP_MODIFY_TIR = 0x901, 247 MLX5_CMD_OP_DESTROY_TIR = 0x902, 248 MLX5_CMD_OP_QUERY_TIR = 0x903, 249 MLX5_CMD_OP_CREATE_SQ = 0x904, 250 MLX5_CMD_OP_MODIFY_SQ = 0x905, 251 MLX5_CMD_OP_DESTROY_SQ = 0x906, 252 MLX5_CMD_OP_QUERY_SQ = 0x907, 253 MLX5_CMD_OP_CREATE_RQ = 0x908, 254 MLX5_CMD_OP_MODIFY_RQ = 0x909, 255 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 256 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 257 MLX5_CMD_OP_QUERY_RQ = 0x90b, 258 MLX5_CMD_OP_CREATE_RMP = 0x90c, 259 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 260 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 261 MLX5_CMD_OP_QUERY_RMP = 0x90f, 262 MLX5_CMD_OP_CREATE_TIS = 0x912, 263 MLX5_CMD_OP_MODIFY_TIS = 0x913, 264 MLX5_CMD_OP_DESTROY_TIS = 0x914, 265 MLX5_CMD_OP_QUERY_TIS = 0x915, 266 MLX5_CMD_OP_CREATE_RQT = 0x916, 267 MLX5_CMD_OP_MODIFY_RQT = 0x917, 268 MLX5_CMD_OP_DESTROY_RQT = 0x918, 269 MLX5_CMD_OP_QUERY_RQT = 0x919, 270 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 271 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 272 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 273 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 274 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 275 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 276 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 277 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 278 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 279 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 280 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 281 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 282 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 283 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 284 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 285 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 286 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 287 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 288 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 289 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 290 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 291 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 292 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 293 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 294 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 295 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 296 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 297 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 298 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 299 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 300 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 301 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 302 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 303 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 304 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 305 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 306 MLX5_CMD_OP_MAX 307 }; 308 309 /* Valid range for general commands that don't work over an object */ 310 enum { 311 MLX5_CMD_OP_GENERAL_START = 0xb00, 312 MLX5_CMD_OP_GENERAL_END = 0xd00, 313 }; 314 315 struct mlx5_ifc_flow_table_fields_supported_bits { 316 u8 outer_dmac[0x1]; 317 u8 outer_smac[0x1]; 318 u8 outer_ether_type[0x1]; 319 u8 outer_ip_version[0x1]; 320 u8 outer_first_prio[0x1]; 321 u8 outer_first_cfi[0x1]; 322 u8 outer_first_vid[0x1]; 323 u8 outer_ipv4_ttl[0x1]; 324 u8 outer_second_prio[0x1]; 325 u8 outer_second_cfi[0x1]; 326 u8 outer_second_vid[0x1]; 327 u8 reserved_at_b[0x1]; 328 u8 outer_sip[0x1]; 329 u8 outer_dip[0x1]; 330 u8 outer_frag[0x1]; 331 u8 outer_ip_protocol[0x1]; 332 u8 outer_ip_ecn[0x1]; 333 u8 outer_ip_dscp[0x1]; 334 u8 outer_udp_sport[0x1]; 335 u8 outer_udp_dport[0x1]; 336 u8 outer_tcp_sport[0x1]; 337 u8 outer_tcp_dport[0x1]; 338 u8 outer_tcp_flags[0x1]; 339 u8 outer_gre_protocol[0x1]; 340 u8 outer_gre_key[0x1]; 341 u8 outer_vxlan_vni[0x1]; 342 u8 outer_geneve_vni[0x1]; 343 u8 outer_geneve_oam[0x1]; 344 u8 outer_geneve_protocol_type[0x1]; 345 u8 outer_geneve_opt_len[0x1]; 346 u8 source_vhca_port[0x1]; 347 u8 source_eswitch_port[0x1]; 348 349 u8 inner_dmac[0x1]; 350 u8 inner_smac[0x1]; 351 u8 inner_ether_type[0x1]; 352 u8 inner_ip_version[0x1]; 353 u8 inner_first_prio[0x1]; 354 u8 inner_first_cfi[0x1]; 355 u8 inner_first_vid[0x1]; 356 u8 reserved_at_27[0x1]; 357 u8 inner_second_prio[0x1]; 358 u8 inner_second_cfi[0x1]; 359 u8 inner_second_vid[0x1]; 360 u8 reserved_at_2b[0x1]; 361 u8 inner_sip[0x1]; 362 u8 inner_dip[0x1]; 363 u8 inner_frag[0x1]; 364 u8 inner_ip_protocol[0x1]; 365 u8 inner_ip_ecn[0x1]; 366 u8 inner_ip_dscp[0x1]; 367 u8 inner_udp_sport[0x1]; 368 u8 inner_udp_dport[0x1]; 369 u8 inner_tcp_sport[0x1]; 370 u8 inner_tcp_dport[0x1]; 371 u8 inner_tcp_flags[0x1]; 372 u8 reserved_at_37[0x9]; 373 374 u8 geneve_tlv_option_0_data[0x1]; 375 u8 reserved_at_41[0x4]; 376 u8 outer_first_mpls_over_udp[0x4]; 377 u8 outer_first_mpls_over_gre[0x4]; 378 u8 inner_first_mpls[0x4]; 379 u8 outer_first_mpls[0x4]; 380 u8 reserved_at_55[0x2]; 381 u8 outer_esp_spi[0x1]; 382 u8 reserved_at_58[0x2]; 383 u8 bth_dst_qp[0x1]; 384 u8 reserved_at_5b[0x5]; 385 386 u8 reserved_at_60[0x18]; 387 u8 metadata_reg_c_7[0x1]; 388 u8 metadata_reg_c_6[0x1]; 389 u8 metadata_reg_c_5[0x1]; 390 u8 metadata_reg_c_4[0x1]; 391 u8 metadata_reg_c_3[0x1]; 392 u8 metadata_reg_c_2[0x1]; 393 u8 metadata_reg_c_1[0x1]; 394 u8 metadata_reg_c_0[0x1]; 395 }; 396 397 struct mlx5_ifc_flow_table_fields_supported_2_bits { 398 u8 reserved_at_0[0xe]; 399 u8 bth_opcode[0x1]; 400 u8 reserved_at_f[0x11]; 401 402 u8 reserved_at_20[0x60]; 403 }; 404 405 struct mlx5_ifc_flow_table_prop_layout_bits { 406 u8 ft_support[0x1]; 407 u8 reserved_at_1[0x1]; 408 u8 flow_counter[0x1]; 409 u8 flow_modify_en[0x1]; 410 u8 modify_root[0x1]; 411 u8 identified_miss_table_mode[0x1]; 412 u8 flow_table_modify[0x1]; 413 u8 reformat[0x1]; 414 u8 decap[0x1]; 415 u8 reserved_at_9[0x1]; 416 u8 pop_vlan[0x1]; 417 u8 push_vlan[0x1]; 418 u8 reserved_at_c[0x1]; 419 u8 pop_vlan_2[0x1]; 420 u8 push_vlan_2[0x1]; 421 u8 reformat_and_vlan_action[0x1]; 422 u8 reserved_at_10[0x1]; 423 u8 sw_owner[0x1]; 424 u8 reformat_l3_tunnel_to_l2[0x1]; 425 u8 reformat_l2_to_l3_tunnel[0x1]; 426 u8 reformat_and_modify_action[0x1]; 427 u8 ignore_flow_level[0x1]; 428 u8 reserved_at_16[0x1]; 429 u8 table_miss_action_domain[0x1]; 430 u8 termination_table[0x1]; 431 u8 reformat_and_fwd_to_table[0x1]; 432 u8 reserved_at_1a[0x2]; 433 u8 ipsec_encrypt[0x1]; 434 u8 ipsec_decrypt[0x1]; 435 u8 sw_owner_v2[0x1]; 436 u8 reserved_at_1f[0x1]; 437 438 u8 termination_table_raw_traffic[0x1]; 439 u8 reserved_at_21[0x1]; 440 u8 log_max_ft_size[0x6]; 441 u8 log_max_modify_header_context[0x8]; 442 u8 max_modify_header_actions[0x8]; 443 u8 max_ft_level[0x8]; 444 445 u8 reserved_at_40[0x20]; 446 447 u8 reserved_at_60[0x2]; 448 u8 reformat_insert[0x1]; 449 u8 reformat_remove[0x1]; 450 u8 reserver_at_64[0x14]; 451 u8 log_max_ft_num[0x8]; 452 453 u8 reserved_at_80[0x10]; 454 u8 log_max_flow_counter[0x8]; 455 u8 log_max_destination[0x8]; 456 457 u8 reserved_at_a0[0x18]; 458 u8 log_max_flow[0x8]; 459 460 u8 reserved_at_c0[0x40]; 461 462 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 463 464 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 465 }; 466 467 struct mlx5_ifc_odp_per_transport_service_cap_bits { 468 u8 send[0x1]; 469 u8 receive[0x1]; 470 u8 write[0x1]; 471 u8 read[0x1]; 472 u8 atomic[0x1]; 473 u8 srq_receive[0x1]; 474 u8 reserved_at_6[0x1a]; 475 }; 476 477 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 478 u8 smac_47_16[0x20]; 479 480 u8 smac_15_0[0x10]; 481 u8 ethertype[0x10]; 482 483 u8 dmac_47_16[0x20]; 484 485 u8 dmac_15_0[0x10]; 486 u8 first_prio[0x3]; 487 u8 first_cfi[0x1]; 488 u8 first_vid[0xc]; 489 490 u8 ip_protocol[0x8]; 491 u8 ip_dscp[0x6]; 492 u8 ip_ecn[0x2]; 493 u8 cvlan_tag[0x1]; 494 u8 svlan_tag[0x1]; 495 u8 frag[0x1]; 496 u8 ip_version[0x4]; 497 u8 tcp_flags[0x9]; 498 499 u8 tcp_sport[0x10]; 500 u8 tcp_dport[0x10]; 501 502 u8 reserved_at_c0[0x18]; 503 u8 ttl_hoplimit[0x8]; 504 505 u8 udp_sport[0x10]; 506 u8 udp_dport[0x10]; 507 508 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 509 510 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 511 }; 512 513 struct mlx5_ifc_nvgre_key_bits { 514 u8 hi[0x18]; 515 u8 lo[0x8]; 516 }; 517 518 union mlx5_ifc_gre_key_bits { 519 struct mlx5_ifc_nvgre_key_bits nvgre; 520 u8 key[0x20]; 521 }; 522 523 struct mlx5_ifc_fte_match_set_misc_bits { 524 u8 gre_c_present[0x1]; 525 u8 reserved_at_1[0x1]; 526 u8 gre_k_present[0x1]; 527 u8 gre_s_present[0x1]; 528 u8 source_vhca_port[0x4]; 529 u8 source_sqn[0x18]; 530 531 u8 source_eswitch_owner_vhca_id[0x10]; 532 u8 source_port[0x10]; 533 534 u8 outer_second_prio[0x3]; 535 u8 outer_second_cfi[0x1]; 536 u8 outer_second_vid[0xc]; 537 u8 inner_second_prio[0x3]; 538 u8 inner_second_cfi[0x1]; 539 u8 inner_second_vid[0xc]; 540 541 u8 outer_second_cvlan_tag[0x1]; 542 u8 inner_second_cvlan_tag[0x1]; 543 u8 outer_second_svlan_tag[0x1]; 544 u8 inner_second_svlan_tag[0x1]; 545 u8 reserved_at_64[0xc]; 546 u8 gre_protocol[0x10]; 547 548 union mlx5_ifc_gre_key_bits gre_key; 549 550 u8 vxlan_vni[0x18]; 551 u8 bth_opcode[0x8]; 552 553 u8 geneve_vni[0x18]; 554 u8 reserved_at_d8[0x7]; 555 u8 geneve_oam[0x1]; 556 557 u8 reserved_at_e0[0xc]; 558 u8 outer_ipv6_flow_label[0x14]; 559 560 u8 reserved_at_100[0xc]; 561 u8 inner_ipv6_flow_label[0x14]; 562 563 u8 reserved_at_120[0xa]; 564 u8 geneve_opt_len[0x6]; 565 u8 geneve_protocol_type[0x10]; 566 567 u8 reserved_at_140[0x8]; 568 u8 bth_dst_qp[0x18]; 569 u8 reserved_at_160[0x20]; 570 u8 outer_esp_spi[0x20]; 571 u8 reserved_at_1a0[0x60]; 572 }; 573 574 struct mlx5_ifc_fte_match_mpls_bits { 575 u8 mpls_label[0x14]; 576 u8 mpls_exp[0x3]; 577 u8 mpls_s_bos[0x1]; 578 u8 mpls_ttl[0x8]; 579 }; 580 581 struct mlx5_ifc_fte_match_set_misc2_bits { 582 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 583 584 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 585 586 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 587 588 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 589 590 u8 metadata_reg_c_7[0x20]; 591 592 u8 metadata_reg_c_6[0x20]; 593 594 u8 metadata_reg_c_5[0x20]; 595 596 u8 metadata_reg_c_4[0x20]; 597 598 u8 metadata_reg_c_3[0x20]; 599 600 u8 metadata_reg_c_2[0x20]; 601 602 u8 metadata_reg_c_1[0x20]; 603 604 u8 metadata_reg_c_0[0x20]; 605 606 u8 metadata_reg_a[0x20]; 607 608 u8 reserved_at_1a0[0x60]; 609 }; 610 611 struct mlx5_ifc_fte_match_set_misc3_bits { 612 u8 inner_tcp_seq_num[0x20]; 613 614 u8 outer_tcp_seq_num[0x20]; 615 616 u8 inner_tcp_ack_num[0x20]; 617 618 u8 outer_tcp_ack_num[0x20]; 619 620 u8 reserved_at_80[0x8]; 621 u8 outer_vxlan_gpe_vni[0x18]; 622 623 u8 outer_vxlan_gpe_next_protocol[0x8]; 624 u8 outer_vxlan_gpe_flags[0x8]; 625 u8 reserved_at_b0[0x10]; 626 627 u8 icmp_header_data[0x20]; 628 629 u8 icmpv6_header_data[0x20]; 630 631 u8 icmp_type[0x8]; 632 u8 icmp_code[0x8]; 633 u8 icmpv6_type[0x8]; 634 u8 icmpv6_code[0x8]; 635 636 u8 geneve_tlv_option_0_data[0x20]; 637 638 u8 gtpu_teid[0x20]; 639 640 u8 gtpu_msg_type[0x8]; 641 u8 gtpu_msg_flags[0x8]; 642 u8 reserved_at_170[0x10]; 643 644 u8 gtpu_dw_2[0x20]; 645 646 u8 gtpu_first_ext_dw_0[0x20]; 647 648 u8 gtpu_dw_0[0x20]; 649 650 u8 reserved_at_1e0[0x20]; 651 }; 652 653 struct mlx5_ifc_fte_match_set_misc4_bits { 654 u8 prog_sample_field_value_0[0x20]; 655 656 u8 prog_sample_field_id_0[0x20]; 657 658 u8 prog_sample_field_value_1[0x20]; 659 660 u8 prog_sample_field_id_1[0x20]; 661 662 u8 prog_sample_field_value_2[0x20]; 663 664 u8 prog_sample_field_id_2[0x20]; 665 666 u8 prog_sample_field_value_3[0x20]; 667 668 u8 prog_sample_field_id_3[0x20]; 669 670 u8 reserved_at_100[0x100]; 671 }; 672 673 struct mlx5_ifc_cmd_pas_bits { 674 u8 pa_h[0x20]; 675 676 u8 pa_l[0x14]; 677 u8 reserved_at_34[0xc]; 678 }; 679 680 struct mlx5_ifc_uint64_bits { 681 u8 hi[0x20]; 682 683 u8 lo[0x20]; 684 }; 685 686 enum { 687 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 688 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 689 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 690 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 691 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 692 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 693 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 694 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 695 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 696 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 697 }; 698 699 struct mlx5_ifc_ads_bits { 700 u8 fl[0x1]; 701 u8 free_ar[0x1]; 702 u8 reserved_at_2[0xe]; 703 u8 pkey_index[0x10]; 704 705 u8 reserved_at_20[0x8]; 706 u8 grh[0x1]; 707 u8 mlid[0x7]; 708 u8 rlid[0x10]; 709 710 u8 ack_timeout[0x5]; 711 u8 reserved_at_45[0x3]; 712 u8 src_addr_index[0x8]; 713 u8 reserved_at_50[0x4]; 714 u8 stat_rate[0x4]; 715 u8 hop_limit[0x8]; 716 717 u8 reserved_at_60[0x4]; 718 u8 tclass[0x8]; 719 u8 flow_label[0x14]; 720 721 u8 rgid_rip[16][0x8]; 722 723 u8 reserved_at_100[0x4]; 724 u8 f_dscp[0x1]; 725 u8 f_ecn[0x1]; 726 u8 reserved_at_106[0x1]; 727 u8 f_eth_prio[0x1]; 728 u8 ecn[0x2]; 729 u8 dscp[0x6]; 730 u8 udp_sport[0x10]; 731 732 u8 dei_cfi[0x1]; 733 u8 eth_prio[0x3]; 734 u8 sl[0x4]; 735 u8 vhca_port_num[0x8]; 736 u8 rmac_47_32[0x10]; 737 738 u8 rmac_31_0[0x20]; 739 }; 740 741 struct mlx5_ifc_flow_table_nic_cap_bits { 742 u8 nic_rx_multi_path_tirs[0x1]; 743 u8 nic_rx_multi_path_tirs_fts[0x1]; 744 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 745 u8 reserved_at_3[0x4]; 746 u8 sw_owner_reformat_supported[0x1]; 747 u8 reserved_at_8[0x18]; 748 749 u8 encap_general_header[0x1]; 750 u8 reserved_at_21[0xa]; 751 u8 log_max_packet_reformat_context[0x5]; 752 u8 reserved_at_30[0x6]; 753 u8 max_encap_header_size[0xa]; 754 u8 reserved_at_40[0x1c0]; 755 756 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 757 758 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 759 760 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 761 762 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 763 764 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 765 766 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 767 768 u8 reserved_at_e00[0x700]; 769 770 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 771 772 u8 reserved_at_1580[0x280]; 773 774 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 775 776 u8 reserved_at_1880[0x780]; 777 778 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 779 780 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 781 782 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 783 784 u8 reserved_at_20c0[0x5f40]; 785 }; 786 787 struct mlx5_ifc_port_selection_cap_bits { 788 u8 reserved_at_0[0x10]; 789 u8 port_select_flow_table[0x1]; 790 u8 reserved_at_11[0xf]; 791 792 u8 reserved_at_20[0x1e0]; 793 794 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 795 796 u8 reserved_at_400[0x7c00]; 797 }; 798 799 enum { 800 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 801 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 802 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 803 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 804 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 805 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 806 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 807 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 808 }; 809 810 struct mlx5_ifc_flow_table_eswitch_cap_bits { 811 u8 fdb_to_vport_reg_c_id[0x8]; 812 u8 reserved_at_8[0xd]; 813 u8 fdb_modify_header_fwd_to_table[0x1]; 814 u8 reserved_at_16[0x1]; 815 u8 flow_source[0x1]; 816 u8 reserved_at_18[0x2]; 817 u8 multi_fdb_encap[0x1]; 818 u8 egress_acl_forward_to_vport[0x1]; 819 u8 fdb_multi_path_to_table[0x1]; 820 u8 reserved_at_1d[0x3]; 821 822 u8 reserved_at_20[0x1e0]; 823 824 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 825 826 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 827 828 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 829 830 u8 reserved_at_800[0x1000]; 831 832 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 833 834 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 835 836 u8 sw_steering_uplink_icm_address_rx[0x40]; 837 838 u8 sw_steering_uplink_icm_address_tx[0x40]; 839 840 u8 reserved_at_1900[0x6700]; 841 }; 842 843 enum { 844 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 845 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 846 }; 847 848 struct mlx5_ifc_e_switch_cap_bits { 849 u8 vport_svlan_strip[0x1]; 850 u8 vport_cvlan_strip[0x1]; 851 u8 vport_svlan_insert[0x1]; 852 u8 vport_cvlan_insert_if_not_exist[0x1]; 853 u8 vport_cvlan_insert_overwrite[0x1]; 854 u8 reserved_at_5[0x2]; 855 u8 esw_shared_ingress_acl[0x1]; 856 u8 esw_uplink_ingress_acl[0x1]; 857 u8 root_ft_on_other_esw[0x1]; 858 u8 reserved_at_a[0xf]; 859 u8 esw_functions_changed[0x1]; 860 u8 reserved_at_1a[0x1]; 861 u8 ecpf_vport_exists[0x1]; 862 u8 counter_eswitch_affinity[0x1]; 863 u8 merged_eswitch[0x1]; 864 u8 nic_vport_node_guid_modify[0x1]; 865 u8 nic_vport_port_guid_modify[0x1]; 866 867 u8 vxlan_encap_decap[0x1]; 868 u8 nvgre_encap_decap[0x1]; 869 u8 reserved_at_22[0x1]; 870 u8 log_max_fdb_encap_uplink[0x5]; 871 u8 reserved_at_21[0x3]; 872 u8 log_max_packet_reformat_context[0x5]; 873 u8 reserved_2b[0x6]; 874 u8 max_encap_header_size[0xa]; 875 876 u8 reserved_at_40[0xb]; 877 u8 log_max_esw_sf[0x5]; 878 u8 esw_sf_base_id[0x10]; 879 880 u8 reserved_at_60[0x7a0]; 881 882 }; 883 884 struct mlx5_ifc_qos_cap_bits { 885 u8 packet_pacing[0x1]; 886 u8 esw_scheduling[0x1]; 887 u8 esw_bw_share[0x1]; 888 u8 esw_rate_limit[0x1]; 889 u8 reserved_at_4[0x1]; 890 u8 packet_pacing_burst_bound[0x1]; 891 u8 packet_pacing_typical_size[0x1]; 892 u8 reserved_at_7[0x1]; 893 u8 nic_sq_scheduling[0x1]; 894 u8 nic_bw_share[0x1]; 895 u8 nic_rate_limit[0x1]; 896 u8 packet_pacing_uid[0x1]; 897 u8 log_esw_max_sched_depth[0x4]; 898 u8 reserved_at_10[0x10]; 899 900 u8 reserved_at_20[0xb]; 901 u8 log_max_qos_nic_queue_group[0x5]; 902 u8 reserved_at_30[0x10]; 903 904 u8 packet_pacing_max_rate[0x20]; 905 906 u8 packet_pacing_min_rate[0x20]; 907 908 u8 reserved_at_80[0x10]; 909 u8 packet_pacing_rate_table_size[0x10]; 910 911 u8 esw_element_type[0x10]; 912 u8 esw_tsar_type[0x10]; 913 914 u8 reserved_at_c0[0x10]; 915 u8 max_qos_para_vport[0x10]; 916 917 u8 max_tsar_bw_share[0x20]; 918 919 u8 reserved_at_100[0x700]; 920 }; 921 922 struct mlx5_ifc_debug_cap_bits { 923 u8 core_dump_general[0x1]; 924 u8 core_dump_qp[0x1]; 925 u8 reserved_at_2[0x7]; 926 u8 resource_dump[0x1]; 927 u8 reserved_at_a[0x16]; 928 929 u8 reserved_at_20[0x2]; 930 u8 stall_detect[0x1]; 931 u8 reserved_at_23[0x1d]; 932 933 u8 reserved_at_40[0x7c0]; 934 }; 935 936 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 937 u8 csum_cap[0x1]; 938 u8 vlan_cap[0x1]; 939 u8 lro_cap[0x1]; 940 u8 lro_psh_flag[0x1]; 941 u8 lro_time_stamp[0x1]; 942 u8 reserved_at_5[0x2]; 943 u8 wqe_vlan_insert[0x1]; 944 u8 self_lb_en_modifiable[0x1]; 945 u8 reserved_at_9[0x2]; 946 u8 max_lso_cap[0x5]; 947 u8 multi_pkt_send_wqe[0x2]; 948 u8 wqe_inline_mode[0x2]; 949 u8 rss_ind_tbl_cap[0x4]; 950 u8 reg_umr_sq[0x1]; 951 u8 scatter_fcs[0x1]; 952 u8 enhanced_multi_pkt_send_wqe[0x1]; 953 u8 tunnel_lso_const_out_ip_id[0x1]; 954 u8 tunnel_lro_gre[0x1]; 955 u8 tunnel_lro_vxlan[0x1]; 956 u8 tunnel_stateless_gre[0x1]; 957 u8 tunnel_stateless_vxlan[0x1]; 958 959 u8 swp[0x1]; 960 u8 swp_csum[0x1]; 961 u8 swp_lso[0x1]; 962 u8 cqe_checksum_full[0x1]; 963 u8 tunnel_stateless_geneve_tx[0x1]; 964 u8 tunnel_stateless_mpls_over_udp[0x1]; 965 u8 tunnel_stateless_mpls_over_gre[0x1]; 966 u8 tunnel_stateless_vxlan_gpe[0x1]; 967 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 968 u8 tunnel_stateless_ip_over_ip[0x1]; 969 u8 insert_trailer[0x1]; 970 u8 reserved_at_2b[0x1]; 971 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 972 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 973 u8 reserved_at_2e[0x2]; 974 u8 max_vxlan_udp_ports[0x8]; 975 u8 reserved_at_38[0x6]; 976 u8 max_geneve_opt_len[0x1]; 977 u8 tunnel_stateless_geneve_rx[0x1]; 978 979 u8 reserved_at_40[0x10]; 980 u8 lro_min_mss_size[0x10]; 981 982 u8 reserved_at_60[0x120]; 983 984 u8 lro_timer_supported_periods[4][0x20]; 985 986 u8 reserved_at_200[0x600]; 987 }; 988 989 enum { 990 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 991 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 992 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 993 }; 994 995 struct mlx5_ifc_roce_cap_bits { 996 u8 roce_apm[0x1]; 997 u8 reserved_at_1[0x3]; 998 u8 sw_r_roce_src_udp_port[0x1]; 999 u8 fl_rc_qp_when_roce_disabled[0x1]; 1000 u8 fl_rc_qp_when_roce_enabled[0x1]; 1001 u8 reserved_at_7[0x17]; 1002 u8 qp_ts_format[0x2]; 1003 1004 u8 reserved_at_20[0x60]; 1005 1006 u8 reserved_at_80[0xc]; 1007 u8 l3_type[0x4]; 1008 u8 reserved_at_90[0x8]; 1009 u8 roce_version[0x8]; 1010 1011 u8 reserved_at_a0[0x10]; 1012 u8 r_roce_dest_udp_port[0x10]; 1013 1014 u8 r_roce_max_src_udp_port[0x10]; 1015 u8 r_roce_min_src_udp_port[0x10]; 1016 1017 u8 reserved_at_e0[0x10]; 1018 u8 roce_address_table_size[0x10]; 1019 1020 u8 reserved_at_100[0x700]; 1021 }; 1022 1023 struct mlx5_ifc_sync_steering_in_bits { 1024 u8 opcode[0x10]; 1025 u8 uid[0x10]; 1026 1027 u8 reserved_at_20[0x10]; 1028 u8 op_mod[0x10]; 1029 1030 u8 reserved_at_40[0xc0]; 1031 }; 1032 1033 struct mlx5_ifc_sync_steering_out_bits { 1034 u8 status[0x8]; 1035 u8 reserved_at_8[0x18]; 1036 1037 u8 syndrome[0x20]; 1038 1039 u8 reserved_at_40[0x40]; 1040 }; 1041 1042 struct mlx5_ifc_device_mem_cap_bits { 1043 u8 memic[0x1]; 1044 u8 reserved_at_1[0x1f]; 1045 1046 u8 reserved_at_20[0xb]; 1047 u8 log_min_memic_alloc_size[0x5]; 1048 u8 reserved_at_30[0x8]; 1049 u8 log_max_memic_addr_alignment[0x8]; 1050 1051 u8 memic_bar_start_addr[0x40]; 1052 1053 u8 memic_bar_size[0x20]; 1054 1055 u8 max_memic_size[0x20]; 1056 1057 u8 steering_sw_icm_start_address[0x40]; 1058 1059 u8 reserved_at_100[0x8]; 1060 u8 log_header_modify_sw_icm_size[0x8]; 1061 u8 reserved_at_110[0x2]; 1062 u8 log_sw_icm_alloc_granularity[0x6]; 1063 u8 log_steering_sw_icm_size[0x8]; 1064 1065 u8 reserved_at_120[0x20]; 1066 1067 u8 header_modify_sw_icm_start_address[0x40]; 1068 1069 u8 reserved_at_180[0x80]; 1070 1071 u8 memic_operations[0x20]; 1072 1073 u8 reserved_at_220[0x5e0]; 1074 }; 1075 1076 struct mlx5_ifc_device_event_cap_bits { 1077 u8 user_affiliated_events[4][0x40]; 1078 1079 u8 user_unaffiliated_events[4][0x40]; 1080 }; 1081 1082 struct mlx5_ifc_virtio_emulation_cap_bits { 1083 u8 desc_tunnel_offload_type[0x1]; 1084 u8 eth_frame_offload_type[0x1]; 1085 u8 virtio_version_1_0[0x1]; 1086 u8 device_features_bits_mask[0xd]; 1087 u8 event_mode[0x8]; 1088 u8 virtio_queue_type[0x8]; 1089 1090 u8 max_tunnel_desc[0x10]; 1091 u8 reserved_at_30[0x3]; 1092 u8 log_doorbell_stride[0x5]; 1093 u8 reserved_at_38[0x3]; 1094 u8 log_doorbell_bar_size[0x5]; 1095 1096 u8 doorbell_bar_offset[0x40]; 1097 1098 u8 max_emulated_devices[0x8]; 1099 u8 max_num_virtio_queues[0x18]; 1100 1101 u8 reserved_at_a0[0x60]; 1102 1103 u8 umem_1_buffer_param_a[0x20]; 1104 1105 u8 umem_1_buffer_param_b[0x20]; 1106 1107 u8 umem_2_buffer_param_a[0x20]; 1108 1109 u8 umem_2_buffer_param_b[0x20]; 1110 1111 u8 umem_3_buffer_param_a[0x20]; 1112 1113 u8 umem_3_buffer_param_b[0x20]; 1114 1115 u8 reserved_at_1c0[0x640]; 1116 }; 1117 1118 enum { 1119 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1120 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1121 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1122 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1123 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1124 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1125 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1126 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1127 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1128 }; 1129 1130 enum { 1131 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1132 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1133 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1134 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1135 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1136 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1137 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1138 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1139 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1140 }; 1141 1142 struct mlx5_ifc_atomic_caps_bits { 1143 u8 reserved_at_0[0x40]; 1144 1145 u8 atomic_req_8B_endianness_mode[0x2]; 1146 u8 reserved_at_42[0x4]; 1147 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1148 1149 u8 reserved_at_47[0x19]; 1150 1151 u8 reserved_at_60[0x20]; 1152 1153 u8 reserved_at_80[0x10]; 1154 u8 atomic_operations[0x10]; 1155 1156 u8 reserved_at_a0[0x10]; 1157 u8 atomic_size_qp[0x10]; 1158 1159 u8 reserved_at_c0[0x10]; 1160 u8 atomic_size_dc[0x10]; 1161 1162 u8 reserved_at_e0[0x720]; 1163 }; 1164 1165 struct mlx5_ifc_odp_cap_bits { 1166 u8 reserved_at_0[0x40]; 1167 1168 u8 sig[0x1]; 1169 u8 reserved_at_41[0x1f]; 1170 1171 u8 reserved_at_60[0x20]; 1172 1173 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1174 1175 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1176 1177 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1178 1179 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1180 1181 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1182 1183 u8 reserved_at_120[0x6E0]; 1184 }; 1185 1186 struct mlx5_ifc_calc_op { 1187 u8 reserved_at_0[0x10]; 1188 u8 reserved_at_10[0x9]; 1189 u8 op_swap_endianness[0x1]; 1190 u8 op_min[0x1]; 1191 u8 op_xor[0x1]; 1192 u8 op_or[0x1]; 1193 u8 op_and[0x1]; 1194 u8 op_max[0x1]; 1195 u8 op_add[0x1]; 1196 }; 1197 1198 struct mlx5_ifc_vector_calc_cap_bits { 1199 u8 calc_matrix[0x1]; 1200 u8 reserved_at_1[0x1f]; 1201 u8 reserved_at_20[0x8]; 1202 u8 max_vec_count[0x8]; 1203 u8 reserved_at_30[0xd]; 1204 u8 max_chunk_size[0x3]; 1205 struct mlx5_ifc_calc_op calc0; 1206 struct mlx5_ifc_calc_op calc1; 1207 struct mlx5_ifc_calc_op calc2; 1208 struct mlx5_ifc_calc_op calc3; 1209 1210 u8 reserved_at_c0[0x720]; 1211 }; 1212 1213 struct mlx5_ifc_tls_cap_bits { 1214 u8 tls_1_2_aes_gcm_128[0x1]; 1215 u8 tls_1_3_aes_gcm_128[0x1]; 1216 u8 tls_1_2_aes_gcm_256[0x1]; 1217 u8 tls_1_3_aes_gcm_256[0x1]; 1218 u8 reserved_at_4[0x1c]; 1219 1220 u8 reserved_at_20[0x7e0]; 1221 }; 1222 1223 struct mlx5_ifc_ipsec_cap_bits { 1224 u8 ipsec_full_offload[0x1]; 1225 u8 ipsec_crypto_offload[0x1]; 1226 u8 ipsec_esn[0x1]; 1227 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1228 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1229 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1230 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1231 u8 reserved_at_7[0x4]; 1232 u8 log_max_ipsec_offload[0x5]; 1233 u8 reserved_at_10[0x10]; 1234 1235 u8 min_log_ipsec_full_replay_window[0x8]; 1236 u8 max_log_ipsec_full_replay_window[0x8]; 1237 u8 reserved_at_30[0x7d0]; 1238 }; 1239 1240 enum { 1241 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1242 MLX5_WQ_TYPE_CYCLIC = 0x1, 1243 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1244 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1245 }; 1246 1247 enum { 1248 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1249 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1250 }; 1251 1252 enum { 1253 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1254 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1255 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1256 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1257 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1258 }; 1259 1260 enum { 1261 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1262 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1263 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1264 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1265 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1266 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1267 }; 1268 1269 enum { 1270 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1271 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1272 }; 1273 1274 enum { 1275 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1276 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1277 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1278 }; 1279 1280 enum { 1281 MLX5_CAP_PORT_TYPE_IB = 0x0, 1282 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1283 }; 1284 1285 enum { 1286 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1287 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1288 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1289 }; 1290 1291 enum { 1292 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1293 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1294 mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1295 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1296 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1297 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1298 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1299 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1300 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1301 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1302 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1303 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1304 }; 1305 1306 enum { 1307 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1308 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1309 }; 1310 1311 #define MLX5_FC_BULK_SIZE_FACTOR 128 1312 1313 enum mlx5_fc_bulk_alloc_bitmask { 1314 MLX5_FC_BULK_128 = (1 << 0), 1315 MLX5_FC_BULK_256 = (1 << 1), 1316 MLX5_FC_BULK_512 = (1 << 2), 1317 MLX5_FC_BULK_1024 = (1 << 3), 1318 MLX5_FC_BULK_2048 = (1 << 4), 1319 MLX5_FC_BULK_4096 = (1 << 5), 1320 MLX5_FC_BULK_8192 = (1 << 6), 1321 MLX5_FC_BULK_16384 = (1 << 7), 1322 }; 1323 1324 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1325 1326 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1327 1328 enum { 1329 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1330 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1331 }; 1332 1333 struct mlx5_ifc_cmd_hca_cap_bits { 1334 u8 reserved_at_0[0x1f]; 1335 u8 vhca_resource_manager[0x1]; 1336 1337 u8 hca_cap_2[0x1]; 1338 u8 reserved_at_21[0x1]; 1339 u8 dtor[0x1]; 1340 u8 event_on_vhca_state_teardown_request[0x1]; 1341 u8 event_on_vhca_state_in_use[0x1]; 1342 u8 event_on_vhca_state_active[0x1]; 1343 u8 event_on_vhca_state_allocated[0x1]; 1344 u8 event_on_vhca_state_invalid[0x1]; 1345 u8 reserved_at_28[0x8]; 1346 u8 vhca_id[0x10]; 1347 1348 u8 reserved_at_40[0x40]; 1349 1350 u8 log_max_srq_sz[0x8]; 1351 u8 log_max_qp_sz[0x8]; 1352 u8 event_cap[0x1]; 1353 u8 reserved_at_91[0x2]; 1354 u8 isolate_vl_tc_new[0x1]; 1355 u8 reserved_at_94[0x4]; 1356 u8 prio_tag_required[0x1]; 1357 u8 reserved_at_99[0x2]; 1358 u8 log_max_qp[0x5]; 1359 1360 u8 reserved_at_a0[0x3]; 1361 u8 ece_support[0x1]; 1362 u8 reserved_at_a4[0x5]; 1363 u8 reg_c_preserve[0x1]; 1364 u8 reserved_at_aa[0x1]; 1365 u8 log_max_srq[0x5]; 1366 u8 reserved_at_b0[0x1]; 1367 u8 uplink_follow[0x1]; 1368 u8 ts_cqe_to_dest_cqn[0x1]; 1369 u8 reserved_at_b3[0x7]; 1370 u8 shampo[0x1]; 1371 u8 reserved_at_bb[0x5]; 1372 1373 u8 max_sgl_for_optimized_performance[0x8]; 1374 u8 log_max_cq_sz[0x8]; 1375 u8 relaxed_ordering_write_umr[0x1]; 1376 u8 relaxed_ordering_read_umr[0x1]; 1377 u8 reserved_at_d2[0x7]; 1378 u8 virtio_net_device_emualtion_manager[0x1]; 1379 u8 virtio_blk_device_emualtion_manager[0x1]; 1380 u8 log_max_cq[0x5]; 1381 1382 u8 log_max_eq_sz[0x8]; 1383 u8 relaxed_ordering_write[0x1]; 1384 u8 relaxed_ordering_read[0x1]; 1385 u8 log_max_mkey[0x6]; 1386 u8 reserved_at_f0[0x8]; 1387 u8 dump_fill_mkey[0x1]; 1388 u8 reserved_at_f9[0x2]; 1389 u8 fast_teardown[0x1]; 1390 u8 log_max_eq[0x4]; 1391 1392 u8 max_indirection[0x8]; 1393 u8 fixed_buffer_size[0x1]; 1394 u8 log_max_mrw_sz[0x7]; 1395 u8 force_teardown[0x1]; 1396 u8 reserved_at_111[0x1]; 1397 u8 log_max_bsf_list_size[0x6]; 1398 u8 umr_extended_translation_offset[0x1]; 1399 u8 null_mkey[0x1]; 1400 u8 log_max_klm_list_size[0x6]; 1401 1402 u8 reserved_at_120[0xa]; 1403 u8 log_max_ra_req_dc[0x6]; 1404 u8 reserved_at_130[0xa]; 1405 u8 log_max_ra_res_dc[0x6]; 1406 1407 u8 reserved_at_140[0x6]; 1408 u8 release_all_pages[0x1]; 1409 u8 reserved_at_147[0x2]; 1410 u8 roce_accl[0x1]; 1411 u8 log_max_ra_req_qp[0x6]; 1412 u8 reserved_at_150[0xa]; 1413 u8 log_max_ra_res_qp[0x6]; 1414 1415 u8 end_pad[0x1]; 1416 u8 cc_query_allowed[0x1]; 1417 u8 cc_modify_allowed[0x1]; 1418 u8 start_pad[0x1]; 1419 u8 cache_line_128byte[0x1]; 1420 u8 reserved_at_165[0x4]; 1421 u8 rts2rts_qp_counters_set_id[0x1]; 1422 u8 reserved_at_16a[0x2]; 1423 u8 vnic_env_int_rq_oob[0x1]; 1424 u8 sbcam_reg[0x1]; 1425 u8 reserved_at_16e[0x1]; 1426 u8 qcam_reg[0x1]; 1427 u8 gid_table_size[0x10]; 1428 1429 u8 out_of_seq_cnt[0x1]; 1430 u8 vport_counters[0x1]; 1431 u8 retransmission_q_counters[0x1]; 1432 u8 debug[0x1]; 1433 u8 modify_rq_counter_set_id[0x1]; 1434 u8 rq_delay_drop[0x1]; 1435 u8 max_qp_cnt[0xa]; 1436 u8 pkey_table_size[0x10]; 1437 1438 u8 vport_group_manager[0x1]; 1439 u8 vhca_group_manager[0x1]; 1440 u8 ib_virt[0x1]; 1441 u8 eth_virt[0x1]; 1442 u8 vnic_env_queue_counters[0x1]; 1443 u8 ets[0x1]; 1444 u8 nic_flow_table[0x1]; 1445 u8 eswitch_manager[0x1]; 1446 u8 device_memory[0x1]; 1447 u8 mcam_reg[0x1]; 1448 u8 pcam_reg[0x1]; 1449 u8 local_ca_ack_delay[0x5]; 1450 u8 port_module_event[0x1]; 1451 u8 enhanced_error_q_counters[0x1]; 1452 u8 ports_check[0x1]; 1453 u8 reserved_at_1b3[0x1]; 1454 u8 disable_link_up[0x1]; 1455 u8 beacon_led[0x1]; 1456 u8 port_type[0x2]; 1457 u8 num_ports[0x8]; 1458 1459 u8 reserved_at_1c0[0x1]; 1460 u8 pps[0x1]; 1461 u8 pps_modify[0x1]; 1462 u8 log_max_msg[0x5]; 1463 u8 reserved_at_1c8[0x4]; 1464 u8 max_tc[0x4]; 1465 u8 temp_warn_event[0x1]; 1466 u8 dcbx[0x1]; 1467 u8 general_notification_event[0x1]; 1468 u8 reserved_at_1d3[0x2]; 1469 u8 fpga[0x1]; 1470 u8 rol_s[0x1]; 1471 u8 rol_g[0x1]; 1472 u8 reserved_at_1d8[0x1]; 1473 u8 wol_s[0x1]; 1474 u8 wol_g[0x1]; 1475 u8 wol_a[0x1]; 1476 u8 wol_b[0x1]; 1477 u8 wol_m[0x1]; 1478 u8 wol_u[0x1]; 1479 u8 wol_p[0x1]; 1480 1481 u8 stat_rate_support[0x10]; 1482 u8 reserved_at_1f0[0x1]; 1483 u8 pci_sync_for_fw_update_event[0x1]; 1484 u8 reserved_at_1f2[0x6]; 1485 u8 init2_lag_tx_port_affinity[0x1]; 1486 u8 reserved_at_1fa[0x3]; 1487 u8 cqe_version[0x4]; 1488 1489 u8 compact_address_vector[0x1]; 1490 u8 striding_rq[0x1]; 1491 u8 reserved_at_202[0x1]; 1492 u8 ipoib_enhanced_offloads[0x1]; 1493 u8 ipoib_basic_offloads[0x1]; 1494 u8 reserved_at_205[0x1]; 1495 u8 repeated_block_disabled[0x1]; 1496 u8 umr_modify_entity_size_disabled[0x1]; 1497 u8 umr_modify_atomic_disabled[0x1]; 1498 u8 umr_indirect_mkey_disabled[0x1]; 1499 u8 umr_fence[0x2]; 1500 u8 dc_req_scat_data_cqe[0x1]; 1501 u8 reserved_at_20d[0x2]; 1502 u8 drain_sigerr[0x1]; 1503 u8 cmdif_checksum[0x2]; 1504 u8 sigerr_cqe[0x1]; 1505 u8 reserved_at_213[0x1]; 1506 u8 wq_signature[0x1]; 1507 u8 sctr_data_cqe[0x1]; 1508 u8 reserved_at_216[0x1]; 1509 u8 sho[0x1]; 1510 u8 tph[0x1]; 1511 u8 rf[0x1]; 1512 u8 dct[0x1]; 1513 u8 qos[0x1]; 1514 u8 eth_net_offloads[0x1]; 1515 u8 roce[0x1]; 1516 u8 atomic[0x1]; 1517 u8 reserved_at_21f[0x1]; 1518 1519 u8 cq_oi[0x1]; 1520 u8 cq_resize[0x1]; 1521 u8 cq_moderation[0x1]; 1522 u8 reserved_at_223[0x3]; 1523 u8 cq_eq_remap[0x1]; 1524 u8 pg[0x1]; 1525 u8 block_lb_mc[0x1]; 1526 u8 reserved_at_229[0x1]; 1527 u8 scqe_break_moderation[0x1]; 1528 u8 cq_period_start_from_cqe[0x1]; 1529 u8 cd[0x1]; 1530 u8 reserved_at_22d[0x1]; 1531 u8 apm[0x1]; 1532 u8 vector_calc[0x1]; 1533 u8 umr_ptr_rlky[0x1]; 1534 u8 imaicl[0x1]; 1535 u8 qp_packet_based[0x1]; 1536 u8 reserved_at_233[0x3]; 1537 u8 qkv[0x1]; 1538 u8 pkv[0x1]; 1539 u8 set_deth_sqpn[0x1]; 1540 u8 reserved_at_239[0x3]; 1541 u8 xrc[0x1]; 1542 u8 ud[0x1]; 1543 u8 uc[0x1]; 1544 u8 rc[0x1]; 1545 1546 u8 uar_4k[0x1]; 1547 u8 reserved_at_241[0x9]; 1548 u8 uar_sz[0x6]; 1549 u8 port_selection_cap[0x1]; 1550 u8 reserved_at_248[0x1]; 1551 u8 umem_uid_0[0x1]; 1552 u8 reserved_at_250[0x5]; 1553 u8 log_pg_sz[0x8]; 1554 1555 u8 bf[0x1]; 1556 u8 driver_version[0x1]; 1557 u8 pad_tx_eth_packet[0x1]; 1558 u8 reserved_at_263[0x3]; 1559 u8 mkey_by_name[0x1]; 1560 u8 reserved_at_267[0x4]; 1561 1562 u8 log_bf_reg_size[0x5]; 1563 1564 u8 reserved_at_270[0x6]; 1565 u8 lag_dct[0x2]; 1566 u8 lag_tx_port_affinity[0x1]; 1567 u8 lag_native_fdb_selection[0x1]; 1568 u8 reserved_at_27a[0x1]; 1569 u8 lag_master[0x1]; 1570 u8 num_lag_ports[0x4]; 1571 1572 u8 reserved_at_280[0x10]; 1573 u8 max_wqe_sz_sq[0x10]; 1574 1575 u8 reserved_at_2a0[0x10]; 1576 u8 max_wqe_sz_rq[0x10]; 1577 1578 u8 max_flow_counter_31_16[0x10]; 1579 u8 max_wqe_sz_sq_dc[0x10]; 1580 1581 u8 reserved_at_2e0[0x7]; 1582 u8 max_qp_mcg[0x19]; 1583 1584 u8 reserved_at_300[0x10]; 1585 u8 flow_counter_bulk_alloc[0x8]; 1586 u8 log_max_mcg[0x8]; 1587 1588 u8 reserved_at_320[0x3]; 1589 u8 log_max_transport_domain[0x5]; 1590 u8 reserved_at_328[0x3]; 1591 u8 log_max_pd[0x5]; 1592 u8 reserved_at_330[0xb]; 1593 u8 log_max_xrcd[0x5]; 1594 1595 u8 nic_receive_steering_discard[0x1]; 1596 u8 receive_discard_vport_down[0x1]; 1597 u8 transmit_discard_vport_down[0x1]; 1598 u8 reserved_at_343[0x5]; 1599 u8 log_max_flow_counter_bulk[0x8]; 1600 u8 max_flow_counter_15_0[0x10]; 1601 1602 1603 u8 reserved_at_360[0x3]; 1604 u8 log_max_rq[0x5]; 1605 u8 reserved_at_368[0x3]; 1606 u8 log_max_sq[0x5]; 1607 u8 reserved_at_370[0x3]; 1608 u8 log_max_tir[0x5]; 1609 u8 reserved_at_378[0x3]; 1610 u8 log_max_tis[0x5]; 1611 1612 u8 basic_cyclic_rcv_wqe[0x1]; 1613 u8 reserved_at_381[0x2]; 1614 u8 log_max_rmp[0x5]; 1615 u8 reserved_at_388[0x3]; 1616 u8 log_max_rqt[0x5]; 1617 u8 reserved_at_390[0x3]; 1618 u8 log_max_rqt_size[0x5]; 1619 u8 reserved_at_398[0x3]; 1620 u8 log_max_tis_per_sq[0x5]; 1621 1622 u8 ext_stride_num_range[0x1]; 1623 u8 roce_rw_supported[0x1]; 1624 u8 reserved_at_3a2[0x1]; 1625 u8 log_max_stride_sz_rq[0x5]; 1626 u8 reserved_at_3a8[0x3]; 1627 u8 log_min_stride_sz_rq[0x5]; 1628 u8 reserved_at_3b0[0x3]; 1629 u8 log_max_stride_sz_sq[0x5]; 1630 u8 reserved_at_3b8[0x3]; 1631 u8 log_min_stride_sz_sq[0x5]; 1632 1633 u8 hairpin[0x1]; 1634 u8 reserved_at_3c1[0x2]; 1635 u8 log_max_hairpin_queues[0x5]; 1636 u8 reserved_at_3c8[0x3]; 1637 u8 log_max_hairpin_wq_data_sz[0x5]; 1638 u8 reserved_at_3d0[0x3]; 1639 u8 log_max_hairpin_num_packets[0x5]; 1640 u8 reserved_at_3d8[0x3]; 1641 u8 log_max_wq_sz[0x5]; 1642 1643 u8 nic_vport_change_event[0x1]; 1644 u8 disable_local_lb_uc[0x1]; 1645 u8 disable_local_lb_mc[0x1]; 1646 u8 log_min_hairpin_wq_data_sz[0x5]; 1647 u8 reserved_at_3e8[0x2]; 1648 u8 vhca_state[0x1]; 1649 u8 log_max_vlan_list[0x5]; 1650 u8 reserved_at_3f0[0x3]; 1651 u8 log_max_current_mc_list[0x5]; 1652 u8 reserved_at_3f8[0x3]; 1653 u8 log_max_current_uc_list[0x5]; 1654 1655 u8 general_obj_types[0x40]; 1656 1657 u8 sq_ts_format[0x2]; 1658 u8 rq_ts_format[0x2]; 1659 u8 steering_format_version[0x4]; 1660 u8 create_qp_start_hint[0x18]; 1661 1662 u8 reserved_at_460[0x3]; 1663 u8 log_max_uctx[0x5]; 1664 u8 reserved_at_468[0x2]; 1665 u8 ipsec_offload[0x1]; 1666 u8 log_max_umem[0x5]; 1667 u8 max_num_eqs[0x10]; 1668 1669 u8 reserved_at_480[0x1]; 1670 u8 tls_tx[0x1]; 1671 u8 tls_rx[0x1]; 1672 u8 log_max_l2_table[0x5]; 1673 u8 reserved_at_488[0x8]; 1674 u8 log_uar_page_sz[0x10]; 1675 1676 u8 reserved_at_4a0[0x20]; 1677 u8 device_frequency_mhz[0x20]; 1678 u8 device_frequency_khz[0x20]; 1679 1680 u8 reserved_at_500[0x20]; 1681 u8 num_of_uars_per_page[0x20]; 1682 1683 u8 flex_parser_protocols[0x20]; 1684 1685 u8 max_geneve_tlv_options[0x8]; 1686 u8 reserved_at_568[0x3]; 1687 u8 max_geneve_tlv_option_data_len[0x5]; 1688 u8 reserved_at_570[0x10]; 1689 1690 u8 reserved_at_580[0xb]; 1691 u8 log_max_dci_stream_channels[0x5]; 1692 u8 reserved_at_590[0x3]; 1693 u8 log_max_dci_errored_streams[0x5]; 1694 u8 reserved_at_598[0x8]; 1695 1696 u8 reserved_at_5a0[0x13]; 1697 u8 log_max_dek[0x5]; 1698 u8 reserved_at_5b8[0x4]; 1699 u8 mini_cqe_resp_stride_index[0x1]; 1700 u8 cqe_128_always[0x1]; 1701 u8 cqe_compression_128[0x1]; 1702 u8 cqe_compression[0x1]; 1703 1704 u8 cqe_compression_timeout[0x10]; 1705 u8 cqe_compression_max_num[0x10]; 1706 1707 u8 reserved_at_5e0[0x8]; 1708 u8 flex_parser_id_gtpu_dw_0[0x4]; 1709 u8 reserved_at_5ec[0x4]; 1710 u8 tag_matching[0x1]; 1711 u8 rndv_offload_rc[0x1]; 1712 u8 rndv_offload_dc[0x1]; 1713 u8 log_tag_matching_list_sz[0x5]; 1714 u8 reserved_at_5f8[0x3]; 1715 u8 log_max_xrq[0x5]; 1716 1717 u8 affiliate_nic_vport_criteria[0x8]; 1718 u8 native_port_num[0x8]; 1719 u8 num_vhca_ports[0x8]; 1720 u8 flex_parser_id_gtpu_teid[0x4]; 1721 u8 reserved_at_61c[0x2]; 1722 u8 sw_owner_id[0x1]; 1723 u8 reserved_at_61f[0x1]; 1724 1725 u8 max_num_of_monitor_counters[0x10]; 1726 u8 num_ppcnt_monitor_counters[0x10]; 1727 1728 u8 max_num_sf[0x10]; 1729 u8 num_q_monitor_counters[0x10]; 1730 1731 u8 reserved_at_660[0x20]; 1732 1733 u8 sf[0x1]; 1734 u8 sf_set_partition[0x1]; 1735 u8 reserved_at_682[0x1]; 1736 u8 log_max_sf[0x5]; 1737 u8 apu[0x1]; 1738 u8 reserved_at_689[0x7]; 1739 u8 log_min_sf_size[0x8]; 1740 u8 max_num_sf_partitions[0x8]; 1741 1742 u8 uctx_cap[0x20]; 1743 1744 u8 reserved_at_6c0[0x4]; 1745 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1746 u8 flex_parser_id_icmp_dw1[0x4]; 1747 u8 flex_parser_id_icmp_dw0[0x4]; 1748 u8 flex_parser_id_icmpv6_dw1[0x4]; 1749 u8 flex_parser_id_icmpv6_dw0[0x4]; 1750 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1751 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1752 1753 u8 max_num_match_definer[0x10]; 1754 u8 sf_base_id[0x10]; 1755 1756 u8 flex_parser_id_gtpu_dw_2[0x4]; 1757 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1758 u8 num_total_dynamic_vf_msix[0x18]; 1759 u8 reserved_at_720[0x14]; 1760 u8 dynamic_msix_table_size[0xc]; 1761 u8 reserved_at_740[0xc]; 1762 u8 min_dynamic_vf_msix_table_size[0x4]; 1763 u8 reserved_at_750[0x4]; 1764 u8 max_dynamic_vf_msix_table_size[0xc]; 1765 1766 u8 reserved_at_760[0x20]; 1767 u8 vhca_tunnel_commands[0x40]; 1768 u8 match_definer_format_supported[0x40]; 1769 }; 1770 1771 struct mlx5_ifc_cmd_hca_cap_2_bits { 1772 u8 reserved_at_0[0xa0]; 1773 1774 u8 max_reformat_insert_size[0x8]; 1775 u8 max_reformat_insert_offset[0x8]; 1776 u8 max_reformat_remove_size[0x8]; 1777 u8 max_reformat_remove_offset[0x8]; 1778 1779 u8 reserved_at_c0[0x740]; 1780 }; 1781 1782 enum mlx5_flow_destination_type { 1783 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1784 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1785 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1786 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1787 MLX5_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1788 1789 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1790 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1791 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1792 }; 1793 1794 enum mlx5_flow_table_miss_action { 1795 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1796 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1797 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1798 }; 1799 1800 struct mlx5_ifc_dest_format_struct_bits { 1801 u8 destination_type[0x8]; 1802 u8 destination_id[0x18]; 1803 1804 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1805 u8 packet_reformat[0x1]; 1806 u8 reserved_at_22[0xe]; 1807 u8 destination_eswitch_owner_vhca_id[0x10]; 1808 }; 1809 1810 struct mlx5_ifc_flow_counter_list_bits { 1811 u8 flow_counter_id[0x20]; 1812 1813 u8 reserved_at_20[0x20]; 1814 }; 1815 1816 struct mlx5_ifc_extended_dest_format_bits { 1817 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1818 1819 u8 packet_reformat_id[0x20]; 1820 1821 u8 reserved_at_60[0x20]; 1822 }; 1823 1824 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1825 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1826 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1827 }; 1828 1829 struct mlx5_ifc_fte_match_param_bits { 1830 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1831 1832 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1833 1834 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1835 1836 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1837 1838 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1839 1840 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1841 1842 u8 reserved_at_c00[0x400]; 1843 }; 1844 1845 enum { 1846 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1847 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1848 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1849 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1850 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1851 }; 1852 1853 struct mlx5_ifc_rx_hash_field_select_bits { 1854 u8 l3_prot_type[0x1]; 1855 u8 l4_prot_type[0x1]; 1856 u8 selected_fields[0x1e]; 1857 }; 1858 1859 enum { 1860 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1861 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1862 }; 1863 1864 enum { 1865 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1866 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1867 }; 1868 1869 struct mlx5_ifc_wq_bits { 1870 u8 wq_type[0x4]; 1871 u8 wq_signature[0x1]; 1872 u8 end_padding_mode[0x2]; 1873 u8 cd_slave[0x1]; 1874 u8 reserved_at_8[0x18]; 1875 1876 u8 hds_skip_first_sge[0x1]; 1877 u8 log2_hds_buf_size[0x3]; 1878 u8 reserved_at_24[0x7]; 1879 u8 page_offset[0x5]; 1880 u8 lwm[0x10]; 1881 1882 u8 reserved_at_40[0x8]; 1883 u8 pd[0x18]; 1884 1885 u8 reserved_at_60[0x8]; 1886 u8 uar_page[0x18]; 1887 1888 u8 dbr_addr[0x40]; 1889 1890 u8 hw_counter[0x20]; 1891 1892 u8 sw_counter[0x20]; 1893 1894 u8 reserved_at_100[0xc]; 1895 u8 log_wq_stride[0x4]; 1896 u8 reserved_at_110[0x3]; 1897 u8 log_wq_pg_sz[0x5]; 1898 u8 reserved_at_118[0x3]; 1899 u8 log_wq_sz[0x5]; 1900 1901 u8 dbr_umem_valid[0x1]; 1902 u8 wq_umem_valid[0x1]; 1903 u8 reserved_at_122[0x1]; 1904 u8 log_hairpin_num_packets[0x5]; 1905 u8 reserved_at_128[0x3]; 1906 u8 log_hairpin_data_sz[0x5]; 1907 1908 u8 reserved_at_130[0x4]; 1909 u8 log_wqe_num_of_strides[0x4]; 1910 u8 two_byte_shift_en[0x1]; 1911 u8 reserved_at_139[0x4]; 1912 u8 log_wqe_stride_size[0x3]; 1913 1914 u8 reserved_at_140[0x80]; 1915 1916 u8 headers_mkey[0x20]; 1917 1918 u8 shampo_enable[0x1]; 1919 u8 reserved_at_1e1[0x4]; 1920 u8 log_reservation_size[0x3]; 1921 u8 reserved_at_1e8[0x5]; 1922 u8 log_max_num_of_packets_per_reservation[0x3]; 1923 u8 reserved_at_1f0[0x6]; 1924 u8 log_headers_entry_size[0x2]; 1925 u8 reserved_at_1f8[0x4]; 1926 u8 log_headers_buffer_entry_num[0x4]; 1927 1928 u8 reserved_at_200[0x400]; 1929 1930 struct mlx5_ifc_cmd_pas_bits pas[]; 1931 }; 1932 1933 struct mlx5_ifc_rq_num_bits { 1934 u8 reserved_at_0[0x8]; 1935 u8 rq_num[0x18]; 1936 }; 1937 1938 struct mlx5_ifc_mac_address_layout_bits { 1939 u8 reserved_at_0[0x10]; 1940 u8 mac_addr_47_32[0x10]; 1941 1942 u8 mac_addr_31_0[0x20]; 1943 }; 1944 1945 struct mlx5_ifc_vlan_layout_bits { 1946 u8 reserved_at_0[0x14]; 1947 u8 vlan[0x0c]; 1948 1949 u8 reserved_at_20[0x20]; 1950 }; 1951 1952 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1953 u8 reserved_at_0[0xa0]; 1954 1955 u8 min_time_between_cnps[0x20]; 1956 1957 u8 reserved_at_c0[0x12]; 1958 u8 cnp_dscp[0x6]; 1959 u8 reserved_at_d8[0x4]; 1960 u8 cnp_prio_mode[0x1]; 1961 u8 cnp_802p_prio[0x3]; 1962 1963 u8 reserved_at_e0[0x720]; 1964 }; 1965 1966 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1967 u8 reserved_at_0[0x60]; 1968 1969 u8 reserved_at_60[0x4]; 1970 u8 clamp_tgt_rate[0x1]; 1971 u8 reserved_at_65[0x3]; 1972 u8 clamp_tgt_rate_after_time_inc[0x1]; 1973 u8 reserved_at_69[0x17]; 1974 1975 u8 reserved_at_80[0x20]; 1976 1977 u8 rpg_time_reset[0x20]; 1978 1979 u8 rpg_byte_reset[0x20]; 1980 1981 u8 rpg_threshold[0x20]; 1982 1983 u8 rpg_max_rate[0x20]; 1984 1985 u8 rpg_ai_rate[0x20]; 1986 1987 u8 rpg_hai_rate[0x20]; 1988 1989 u8 rpg_gd[0x20]; 1990 1991 u8 rpg_min_dec_fac[0x20]; 1992 1993 u8 rpg_min_rate[0x20]; 1994 1995 u8 reserved_at_1c0[0xe0]; 1996 1997 u8 rate_to_set_on_first_cnp[0x20]; 1998 1999 u8 dce_tcp_g[0x20]; 2000 2001 u8 dce_tcp_rtt[0x20]; 2002 2003 u8 rate_reduce_monitor_period[0x20]; 2004 2005 u8 reserved_at_320[0x20]; 2006 2007 u8 initial_alpha_value[0x20]; 2008 2009 u8 reserved_at_360[0x4a0]; 2010 }; 2011 2012 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2013 u8 reserved_at_0[0x80]; 2014 2015 u8 rppp_max_rps[0x20]; 2016 2017 u8 rpg_time_reset[0x20]; 2018 2019 u8 rpg_byte_reset[0x20]; 2020 2021 u8 rpg_threshold[0x20]; 2022 2023 u8 rpg_max_rate[0x20]; 2024 2025 u8 rpg_ai_rate[0x20]; 2026 2027 u8 rpg_hai_rate[0x20]; 2028 2029 u8 rpg_gd[0x20]; 2030 2031 u8 rpg_min_dec_fac[0x20]; 2032 2033 u8 rpg_min_rate[0x20]; 2034 2035 u8 reserved_at_1c0[0x640]; 2036 }; 2037 2038 enum { 2039 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2040 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2041 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2042 }; 2043 2044 struct mlx5_ifc_resize_field_select_bits { 2045 u8 resize_field_select[0x20]; 2046 }; 2047 2048 struct mlx5_ifc_resource_dump_bits { 2049 u8 more_dump[0x1]; 2050 u8 inline_dump[0x1]; 2051 u8 reserved_at_2[0xa]; 2052 u8 seq_num[0x4]; 2053 u8 segment_type[0x10]; 2054 2055 u8 reserved_at_20[0x10]; 2056 u8 vhca_id[0x10]; 2057 2058 u8 index1[0x20]; 2059 2060 u8 index2[0x20]; 2061 2062 u8 num_of_obj1[0x10]; 2063 u8 num_of_obj2[0x10]; 2064 2065 u8 reserved_at_a0[0x20]; 2066 2067 u8 device_opaque[0x40]; 2068 2069 u8 mkey[0x20]; 2070 2071 u8 size[0x20]; 2072 2073 u8 address[0x40]; 2074 2075 u8 inline_data[52][0x20]; 2076 }; 2077 2078 struct mlx5_ifc_resource_dump_menu_record_bits { 2079 u8 reserved_at_0[0x4]; 2080 u8 num_of_obj2_supports_active[0x1]; 2081 u8 num_of_obj2_supports_all[0x1]; 2082 u8 must_have_num_of_obj2[0x1]; 2083 u8 support_num_of_obj2[0x1]; 2084 u8 num_of_obj1_supports_active[0x1]; 2085 u8 num_of_obj1_supports_all[0x1]; 2086 u8 must_have_num_of_obj1[0x1]; 2087 u8 support_num_of_obj1[0x1]; 2088 u8 must_have_index2[0x1]; 2089 u8 support_index2[0x1]; 2090 u8 must_have_index1[0x1]; 2091 u8 support_index1[0x1]; 2092 u8 segment_type[0x10]; 2093 2094 u8 segment_name[4][0x20]; 2095 2096 u8 index1_name[4][0x20]; 2097 2098 u8 index2_name[4][0x20]; 2099 }; 2100 2101 struct mlx5_ifc_resource_dump_segment_header_bits { 2102 u8 length_dw[0x10]; 2103 u8 segment_type[0x10]; 2104 }; 2105 2106 struct mlx5_ifc_resource_dump_command_segment_bits { 2107 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2108 2109 u8 segment_called[0x10]; 2110 u8 vhca_id[0x10]; 2111 2112 u8 index1[0x20]; 2113 2114 u8 index2[0x20]; 2115 2116 u8 num_of_obj1[0x10]; 2117 u8 num_of_obj2[0x10]; 2118 }; 2119 2120 struct mlx5_ifc_resource_dump_error_segment_bits { 2121 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2122 2123 u8 reserved_at_20[0x10]; 2124 u8 syndrome_id[0x10]; 2125 2126 u8 reserved_at_40[0x40]; 2127 2128 u8 error[8][0x20]; 2129 }; 2130 2131 struct mlx5_ifc_resource_dump_info_segment_bits { 2132 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2133 2134 u8 reserved_at_20[0x18]; 2135 u8 dump_version[0x8]; 2136 2137 u8 hw_version[0x20]; 2138 2139 u8 fw_version[0x20]; 2140 }; 2141 2142 struct mlx5_ifc_resource_dump_menu_segment_bits { 2143 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2144 2145 u8 reserved_at_20[0x10]; 2146 u8 num_of_records[0x10]; 2147 2148 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2149 }; 2150 2151 struct mlx5_ifc_resource_dump_resource_segment_bits { 2152 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2153 2154 u8 reserved_at_20[0x20]; 2155 2156 u8 index1[0x20]; 2157 2158 u8 index2[0x20]; 2159 2160 u8 payload[][0x20]; 2161 }; 2162 2163 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2164 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2165 }; 2166 2167 struct mlx5_ifc_menu_resource_dump_response_bits { 2168 struct mlx5_ifc_resource_dump_info_segment_bits info; 2169 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2170 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2171 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2172 }; 2173 2174 enum { 2175 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2176 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2177 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2178 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2179 }; 2180 2181 struct mlx5_ifc_modify_field_select_bits { 2182 u8 modify_field_select[0x20]; 2183 }; 2184 2185 struct mlx5_ifc_field_select_r_roce_np_bits { 2186 u8 field_select_r_roce_np[0x20]; 2187 }; 2188 2189 struct mlx5_ifc_field_select_r_roce_rp_bits { 2190 u8 field_select_r_roce_rp[0x20]; 2191 }; 2192 2193 enum { 2194 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2195 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2196 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2197 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2198 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2199 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2200 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2201 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2202 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2203 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2204 }; 2205 2206 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2207 u8 field_select_8021qaurp[0x20]; 2208 }; 2209 2210 struct mlx5_ifc_phys_layer_cntrs_bits { 2211 u8 time_since_last_clear_high[0x20]; 2212 2213 u8 time_since_last_clear_low[0x20]; 2214 2215 u8 symbol_errors_high[0x20]; 2216 2217 u8 symbol_errors_low[0x20]; 2218 2219 u8 sync_headers_errors_high[0x20]; 2220 2221 u8 sync_headers_errors_low[0x20]; 2222 2223 u8 edpl_bip_errors_lane0_high[0x20]; 2224 2225 u8 edpl_bip_errors_lane0_low[0x20]; 2226 2227 u8 edpl_bip_errors_lane1_high[0x20]; 2228 2229 u8 edpl_bip_errors_lane1_low[0x20]; 2230 2231 u8 edpl_bip_errors_lane2_high[0x20]; 2232 2233 u8 edpl_bip_errors_lane2_low[0x20]; 2234 2235 u8 edpl_bip_errors_lane3_high[0x20]; 2236 2237 u8 edpl_bip_errors_lane3_low[0x20]; 2238 2239 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2240 2241 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2242 2243 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2244 2245 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2246 2247 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2248 2249 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2250 2251 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2252 2253 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2254 2255 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2256 2257 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2258 2259 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2260 2261 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2262 2263 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2264 2265 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2266 2267 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2268 2269 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2270 2271 u8 rs_fec_corrected_blocks_high[0x20]; 2272 2273 u8 rs_fec_corrected_blocks_low[0x20]; 2274 2275 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2276 2277 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2278 2279 u8 rs_fec_no_errors_blocks_high[0x20]; 2280 2281 u8 rs_fec_no_errors_blocks_low[0x20]; 2282 2283 u8 rs_fec_single_error_blocks_high[0x20]; 2284 2285 u8 rs_fec_single_error_blocks_low[0x20]; 2286 2287 u8 rs_fec_corrected_symbols_total_high[0x20]; 2288 2289 u8 rs_fec_corrected_symbols_total_low[0x20]; 2290 2291 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2292 2293 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2294 2295 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2296 2297 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2298 2299 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2300 2301 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2302 2303 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2304 2305 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2306 2307 u8 link_down_events[0x20]; 2308 2309 u8 successful_recovery_events[0x20]; 2310 2311 u8 reserved_at_640[0x180]; 2312 }; 2313 2314 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2315 u8 time_since_last_clear_high[0x20]; 2316 2317 u8 time_since_last_clear_low[0x20]; 2318 2319 u8 phy_received_bits_high[0x20]; 2320 2321 u8 phy_received_bits_low[0x20]; 2322 2323 u8 phy_symbol_errors_high[0x20]; 2324 2325 u8 phy_symbol_errors_low[0x20]; 2326 2327 u8 phy_corrected_bits_high[0x20]; 2328 2329 u8 phy_corrected_bits_low[0x20]; 2330 2331 u8 phy_corrected_bits_lane0_high[0x20]; 2332 2333 u8 phy_corrected_bits_lane0_low[0x20]; 2334 2335 u8 phy_corrected_bits_lane1_high[0x20]; 2336 2337 u8 phy_corrected_bits_lane1_low[0x20]; 2338 2339 u8 phy_corrected_bits_lane2_high[0x20]; 2340 2341 u8 phy_corrected_bits_lane2_low[0x20]; 2342 2343 u8 phy_corrected_bits_lane3_high[0x20]; 2344 2345 u8 phy_corrected_bits_lane3_low[0x20]; 2346 2347 u8 reserved_at_200[0x5c0]; 2348 }; 2349 2350 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2351 u8 symbol_error_counter[0x10]; 2352 2353 u8 link_error_recovery_counter[0x8]; 2354 2355 u8 link_downed_counter[0x8]; 2356 2357 u8 port_rcv_errors[0x10]; 2358 2359 u8 port_rcv_remote_physical_errors[0x10]; 2360 2361 u8 port_rcv_switch_relay_errors[0x10]; 2362 2363 u8 port_xmit_discards[0x10]; 2364 2365 u8 port_xmit_constraint_errors[0x8]; 2366 2367 u8 port_rcv_constraint_errors[0x8]; 2368 2369 u8 reserved_at_70[0x8]; 2370 2371 u8 link_overrun_errors[0x8]; 2372 2373 u8 reserved_at_80[0x10]; 2374 2375 u8 vl_15_dropped[0x10]; 2376 2377 u8 reserved_at_a0[0x80]; 2378 2379 u8 port_xmit_wait[0x20]; 2380 }; 2381 2382 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2383 u8 transmit_queue_high[0x20]; 2384 2385 u8 transmit_queue_low[0x20]; 2386 2387 u8 no_buffer_discard_uc_high[0x20]; 2388 2389 u8 no_buffer_discard_uc_low[0x20]; 2390 2391 u8 reserved_at_80[0x740]; 2392 }; 2393 2394 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2395 u8 wred_discard_high[0x20]; 2396 2397 u8 wred_discard_low[0x20]; 2398 2399 u8 ecn_marked_tc_high[0x20]; 2400 2401 u8 ecn_marked_tc_low[0x20]; 2402 2403 u8 reserved_at_80[0x740]; 2404 }; 2405 2406 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2407 u8 rx_octets_high[0x20]; 2408 2409 u8 rx_octets_low[0x20]; 2410 2411 u8 reserved_at_40[0xc0]; 2412 2413 u8 rx_frames_high[0x20]; 2414 2415 u8 rx_frames_low[0x20]; 2416 2417 u8 tx_octets_high[0x20]; 2418 2419 u8 tx_octets_low[0x20]; 2420 2421 u8 reserved_at_180[0xc0]; 2422 2423 u8 tx_frames_high[0x20]; 2424 2425 u8 tx_frames_low[0x20]; 2426 2427 u8 rx_pause_high[0x20]; 2428 2429 u8 rx_pause_low[0x20]; 2430 2431 u8 rx_pause_duration_high[0x20]; 2432 2433 u8 rx_pause_duration_low[0x20]; 2434 2435 u8 tx_pause_high[0x20]; 2436 2437 u8 tx_pause_low[0x20]; 2438 2439 u8 tx_pause_duration_high[0x20]; 2440 2441 u8 tx_pause_duration_low[0x20]; 2442 2443 u8 rx_pause_transition_high[0x20]; 2444 2445 u8 rx_pause_transition_low[0x20]; 2446 2447 u8 rx_discards_high[0x20]; 2448 2449 u8 rx_discards_low[0x20]; 2450 2451 u8 device_stall_minor_watermark_cnt_high[0x20]; 2452 2453 u8 device_stall_minor_watermark_cnt_low[0x20]; 2454 2455 u8 device_stall_critical_watermark_cnt_high[0x20]; 2456 2457 u8 device_stall_critical_watermark_cnt_low[0x20]; 2458 2459 u8 reserved_at_480[0x340]; 2460 }; 2461 2462 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2463 u8 port_transmit_wait_high[0x20]; 2464 2465 u8 port_transmit_wait_low[0x20]; 2466 2467 u8 reserved_at_40[0x100]; 2468 2469 u8 rx_buffer_almost_full_high[0x20]; 2470 2471 u8 rx_buffer_almost_full_low[0x20]; 2472 2473 u8 rx_buffer_full_high[0x20]; 2474 2475 u8 rx_buffer_full_low[0x20]; 2476 2477 u8 rx_icrc_encapsulated_high[0x20]; 2478 2479 u8 rx_icrc_encapsulated_low[0x20]; 2480 2481 u8 reserved_at_200[0x5c0]; 2482 }; 2483 2484 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2485 u8 dot3stats_alignment_errors_high[0x20]; 2486 2487 u8 dot3stats_alignment_errors_low[0x20]; 2488 2489 u8 dot3stats_fcs_errors_high[0x20]; 2490 2491 u8 dot3stats_fcs_errors_low[0x20]; 2492 2493 u8 dot3stats_single_collision_frames_high[0x20]; 2494 2495 u8 dot3stats_single_collision_frames_low[0x20]; 2496 2497 u8 dot3stats_multiple_collision_frames_high[0x20]; 2498 2499 u8 dot3stats_multiple_collision_frames_low[0x20]; 2500 2501 u8 dot3stats_sqe_test_errors_high[0x20]; 2502 2503 u8 dot3stats_sqe_test_errors_low[0x20]; 2504 2505 u8 dot3stats_deferred_transmissions_high[0x20]; 2506 2507 u8 dot3stats_deferred_transmissions_low[0x20]; 2508 2509 u8 dot3stats_late_collisions_high[0x20]; 2510 2511 u8 dot3stats_late_collisions_low[0x20]; 2512 2513 u8 dot3stats_excessive_collisions_high[0x20]; 2514 2515 u8 dot3stats_excessive_collisions_low[0x20]; 2516 2517 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2518 2519 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2520 2521 u8 dot3stats_carrier_sense_errors_high[0x20]; 2522 2523 u8 dot3stats_carrier_sense_errors_low[0x20]; 2524 2525 u8 dot3stats_frame_too_longs_high[0x20]; 2526 2527 u8 dot3stats_frame_too_longs_low[0x20]; 2528 2529 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2530 2531 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2532 2533 u8 dot3stats_symbol_errors_high[0x20]; 2534 2535 u8 dot3stats_symbol_errors_low[0x20]; 2536 2537 u8 dot3control_in_unknown_opcodes_high[0x20]; 2538 2539 u8 dot3control_in_unknown_opcodes_low[0x20]; 2540 2541 u8 dot3in_pause_frames_high[0x20]; 2542 2543 u8 dot3in_pause_frames_low[0x20]; 2544 2545 u8 dot3out_pause_frames_high[0x20]; 2546 2547 u8 dot3out_pause_frames_low[0x20]; 2548 2549 u8 reserved_at_400[0x3c0]; 2550 }; 2551 2552 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2553 u8 ether_stats_drop_events_high[0x20]; 2554 2555 u8 ether_stats_drop_events_low[0x20]; 2556 2557 u8 ether_stats_octets_high[0x20]; 2558 2559 u8 ether_stats_octets_low[0x20]; 2560 2561 u8 ether_stats_pkts_high[0x20]; 2562 2563 u8 ether_stats_pkts_low[0x20]; 2564 2565 u8 ether_stats_broadcast_pkts_high[0x20]; 2566 2567 u8 ether_stats_broadcast_pkts_low[0x20]; 2568 2569 u8 ether_stats_multicast_pkts_high[0x20]; 2570 2571 u8 ether_stats_multicast_pkts_low[0x20]; 2572 2573 u8 ether_stats_crc_align_errors_high[0x20]; 2574 2575 u8 ether_stats_crc_align_errors_low[0x20]; 2576 2577 u8 ether_stats_undersize_pkts_high[0x20]; 2578 2579 u8 ether_stats_undersize_pkts_low[0x20]; 2580 2581 u8 ether_stats_oversize_pkts_high[0x20]; 2582 2583 u8 ether_stats_oversize_pkts_low[0x20]; 2584 2585 u8 ether_stats_fragments_high[0x20]; 2586 2587 u8 ether_stats_fragments_low[0x20]; 2588 2589 u8 ether_stats_jabbers_high[0x20]; 2590 2591 u8 ether_stats_jabbers_low[0x20]; 2592 2593 u8 ether_stats_collisions_high[0x20]; 2594 2595 u8 ether_stats_collisions_low[0x20]; 2596 2597 u8 ether_stats_pkts64octets_high[0x20]; 2598 2599 u8 ether_stats_pkts64octets_low[0x20]; 2600 2601 u8 ether_stats_pkts65to127octets_high[0x20]; 2602 2603 u8 ether_stats_pkts65to127octets_low[0x20]; 2604 2605 u8 ether_stats_pkts128to255octets_high[0x20]; 2606 2607 u8 ether_stats_pkts128to255octets_low[0x20]; 2608 2609 u8 ether_stats_pkts256to511octets_high[0x20]; 2610 2611 u8 ether_stats_pkts256to511octets_low[0x20]; 2612 2613 u8 ether_stats_pkts512to1023octets_high[0x20]; 2614 2615 u8 ether_stats_pkts512to1023octets_low[0x20]; 2616 2617 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2618 2619 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2620 2621 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2622 2623 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2624 2625 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2626 2627 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2628 2629 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2630 2631 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2632 2633 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2634 2635 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2636 2637 u8 reserved_at_540[0x280]; 2638 }; 2639 2640 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2641 u8 if_in_octets_high[0x20]; 2642 2643 u8 if_in_octets_low[0x20]; 2644 2645 u8 if_in_ucast_pkts_high[0x20]; 2646 2647 u8 if_in_ucast_pkts_low[0x20]; 2648 2649 u8 if_in_discards_high[0x20]; 2650 2651 u8 if_in_discards_low[0x20]; 2652 2653 u8 if_in_errors_high[0x20]; 2654 2655 u8 if_in_errors_low[0x20]; 2656 2657 u8 if_in_unknown_protos_high[0x20]; 2658 2659 u8 if_in_unknown_protos_low[0x20]; 2660 2661 u8 if_out_octets_high[0x20]; 2662 2663 u8 if_out_octets_low[0x20]; 2664 2665 u8 if_out_ucast_pkts_high[0x20]; 2666 2667 u8 if_out_ucast_pkts_low[0x20]; 2668 2669 u8 if_out_discards_high[0x20]; 2670 2671 u8 if_out_discards_low[0x20]; 2672 2673 u8 if_out_errors_high[0x20]; 2674 2675 u8 if_out_errors_low[0x20]; 2676 2677 u8 if_in_multicast_pkts_high[0x20]; 2678 2679 u8 if_in_multicast_pkts_low[0x20]; 2680 2681 u8 if_in_broadcast_pkts_high[0x20]; 2682 2683 u8 if_in_broadcast_pkts_low[0x20]; 2684 2685 u8 if_out_multicast_pkts_high[0x20]; 2686 2687 u8 if_out_multicast_pkts_low[0x20]; 2688 2689 u8 if_out_broadcast_pkts_high[0x20]; 2690 2691 u8 if_out_broadcast_pkts_low[0x20]; 2692 2693 u8 reserved_at_340[0x480]; 2694 }; 2695 2696 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2697 u8 a_frames_transmitted_ok_high[0x20]; 2698 2699 u8 a_frames_transmitted_ok_low[0x20]; 2700 2701 u8 a_frames_received_ok_high[0x20]; 2702 2703 u8 a_frames_received_ok_low[0x20]; 2704 2705 u8 a_frame_check_sequence_errors_high[0x20]; 2706 2707 u8 a_frame_check_sequence_errors_low[0x20]; 2708 2709 u8 a_alignment_errors_high[0x20]; 2710 2711 u8 a_alignment_errors_low[0x20]; 2712 2713 u8 a_octets_transmitted_ok_high[0x20]; 2714 2715 u8 a_octets_transmitted_ok_low[0x20]; 2716 2717 u8 a_octets_received_ok_high[0x20]; 2718 2719 u8 a_octets_received_ok_low[0x20]; 2720 2721 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2722 2723 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2724 2725 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2726 2727 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2728 2729 u8 a_multicast_frames_received_ok_high[0x20]; 2730 2731 u8 a_multicast_frames_received_ok_low[0x20]; 2732 2733 u8 a_broadcast_frames_received_ok_high[0x20]; 2734 2735 u8 a_broadcast_frames_received_ok_low[0x20]; 2736 2737 u8 a_in_range_length_errors_high[0x20]; 2738 2739 u8 a_in_range_length_errors_low[0x20]; 2740 2741 u8 a_out_of_range_length_field_high[0x20]; 2742 2743 u8 a_out_of_range_length_field_low[0x20]; 2744 2745 u8 a_frame_too_long_errors_high[0x20]; 2746 2747 u8 a_frame_too_long_errors_low[0x20]; 2748 2749 u8 a_symbol_error_during_carrier_high[0x20]; 2750 2751 u8 a_symbol_error_during_carrier_low[0x20]; 2752 2753 u8 a_mac_control_frames_transmitted_high[0x20]; 2754 2755 u8 a_mac_control_frames_transmitted_low[0x20]; 2756 2757 u8 a_mac_control_frames_received_high[0x20]; 2758 2759 u8 a_mac_control_frames_received_low[0x20]; 2760 2761 u8 a_unsupported_opcodes_received_high[0x20]; 2762 2763 u8 a_unsupported_opcodes_received_low[0x20]; 2764 2765 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2766 2767 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2768 2769 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2770 2771 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2772 2773 u8 reserved_at_4c0[0x300]; 2774 }; 2775 2776 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2777 u8 life_time_counter_high[0x20]; 2778 2779 u8 life_time_counter_low[0x20]; 2780 2781 u8 rx_errors[0x20]; 2782 2783 u8 tx_errors[0x20]; 2784 2785 u8 l0_to_recovery_eieos[0x20]; 2786 2787 u8 l0_to_recovery_ts[0x20]; 2788 2789 u8 l0_to_recovery_framing[0x20]; 2790 2791 u8 l0_to_recovery_retrain[0x20]; 2792 2793 u8 crc_error_dllp[0x20]; 2794 2795 u8 crc_error_tlp[0x20]; 2796 2797 u8 tx_overflow_buffer_pkt_high[0x20]; 2798 2799 u8 tx_overflow_buffer_pkt_low[0x20]; 2800 2801 u8 outbound_stalled_reads[0x20]; 2802 2803 u8 outbound_stalled_writes[0x20]; 2804 2805 u8 outbound_stalled_reads_events[0x20]; 2806 2807 u8 outbound_stalled_writes_events[0x20]; 2808 2809 u8 reserved_at_200[0x5c0]; 2810 }; 2811 2812 struct mlx5_ifc_cmd_inter_comp_event_bits { 2813 u8 command_completion_vector[0x20]; 2814 2815 u8 reserved_at_20[0xc0]; 2816 }; 2817 2818 struct mlx5_ifc_stall_vl_event_bits { 2819 u8 reserved_at_0[0x18]; 2820 u8 port_num[0x1]; 2821 u8 reserved_at_19[0x3]; 2822 u8 vl[0x4]; 2823 2824 u8 reserved_at_20[0xa0]; 2825 }; 2826 2827 struct mlx5_ifc_db_bf_congestion_event_bits { 2828 u8 event_subtype[0x8]; 2829 u8 reserved_at_8[0x8]; 2830 u8 congestion_level[0x8]; 2831 u8 reserved_at_18[0x8]; 2832 2833 u8 reserved_at_20[0xa0]; 2834 }; 2835 2836 struct mlx5_ifc_gpio_event_bits { 2837 u8 reserved_at_0[0x60]; 2838 2839 u8 gpio_event_hi[0x20]; 2840 2841 u8 gpio_event_lo[0x20]; 2842 2843 u8 reserved_at_a0[0x40]; 2844 }; 2845 2846 struct mlx5_ifc_port_state_change_event_bits { 2847 u8 reserved_at_0[0x40]; 2848 2849 u8 port_num[0x4]; 2850 u8 reserved_at_44[0x1c]; 2851 2852 u8 reserved_at_60[0x80]; 2853 }; 2854 2855 struct mlx5_ifc_dropped_packet_logged_bits { 2856 u8 reserved_at_0[0xe0]; 2857 }; 2858 2859 struct mlx5_ifc_default_timeout_bits { 2860 u8 to_multiplier[0x3]; 2861 u8 reserved_at_3[0x9]; 2862 u8 to_value[0x14]; 2863 }; 2864 2865 struct mlx5_ifc_dtor_reg_bits { 2866 u8 reserved_at_0[0x20]; 2867 2868 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2869 2870 u8 reserved_at_40[0x60]; 2871 2872 struct mlx5_ifc_default_timeout_bits health_poll_to; 2873 2874 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2875 2876 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2877 2878 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 2879 2880 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 2881 2882 struct mlx5_ifc_default_timeout_bits tear_down_to; 2883 2884 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 2885 2886 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 2887 2888 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 2889 2890 u8 reserved_at_1c0[0x40]; 2891 }; 2892 2893 enum { 2894 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2895 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2896 }; 2897 2898 struct mlx5_ifc_cq_error_bits { 2899 u8 reserved_at_0[0x8]; 2900 u8 cqn[0x18]; 2901 2902 u8 reserved_at_20[0x20]; 2903 2904 u8 reserved_at_40[0x18]; 2905 u8 syndrome[0x8]; 2906 2907 u8 reserved_at_60[0x80]; 2908 }; 2909 2910 struct mlx5_ifc_rdma_page_fault_event_bits { 2911 u8 bytes_committed[0x20]; 2912 2913 u8 r_key[0x20]; 2914 2915 u8 reserved_at_40[0x10]; 2916 u8 packet_len[0x10]; 2917 2918 u8 rdma_op_len[0x20]; 2919 2920 u8 rdma_va[0x40]; 2921 2922 u8 reserved_at_c0[0x5]; 2923 u8 rdma[0x1]; 2924 u8 write[0x1]; 2925 u8 requestor[0x1]; 2926 u8 qp_number[0x18]; 2927 }; 2928 2929 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2930 u8 bytes_committed[0x20]; 2931 2932 u8 reserved_at_20[0x10]; 2933 u8 wqe_index[0x10]; 2934 2935 u8 reserved_at_40[0x10]; 2936 u8 len[0x10]; 2937 2938 u8 reserved_at_60[0x60]; 2939 2940 u8 reserved_at_c0[0x5]; 2941 u8 rdma[0x1]; 2942 u8 write_read[0x1]; 2943 u8 requestor[0x1]; 2944 u8 qpn[0x18]; 2945 }; 2946 2947 struct mlx5_ifc_qp_events_bits { 2948 u8 reserved_at_0[0xa0]; 2949 2950 u8 type[0x8]; 2951 u8 reserved_at_a8[0x18]; 2952 2953 u8 reserved_at_c0[0x8]; 2954 u8 qpn_rqn_sqn[0x18]; 2955 }; 2956 2957 struct mlx5_ifc_dct_events_bits { 2958 u8 reserved_at_0[0xc0]; 2959 2960 u8 reserved_at_c0[0x8]; 2961 u8 dct_number[0x18]; 2962 }; 2963 2964 struct mlx5_ifc_comp_event_bits { 2965 u8 reserved_at_0[0xc0]; 2966 2967 u8 reserved_at_c0[0x8]; 2968 u8 cq_number[0x18]; 2969 }; 2970 2971 enum { 2972 MLX5_QPC_STATE_RST = 0x0, 2973 MLX5_QPC_STATE_INIT = 0x1, 2974 MLX5_QPC_STATE_RTR = 0x2, 2975 MLX5_QPC_STATE_RTS = 0x3, 2976 MLX5_QPC_STATE_SQER = 0x4, 2977 MLX5_QPC_STATE_ERR = 0x6, 2978 MLX5_QPC_STATE_SQD = 0x7, 2979 MLX5_QPC_STATE_SUSPENDED = 0x9, 2980 }; 2981 2982 enum { 2983 MLX5_QPC_ST_RC = 0x0, 2984 MLX5_QPC_ST_UC = 0x1, 2985 MLX5_QPC_ST_UD = 0x2, 2986 MLX5_QPC_ST_XRC = 0x3, 2987 MLX5_QPC_ST_DCI = 0x5, 2988 MLX5_QPC_ST_QP0 = 0x7, 2989 MLX5_QPC_ST_QP1 = 0x8, 2990 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2991 MLX5_QPC_ST_REG_UMR = 0xc, 2992 }; 2993 2994 enum { 2995 MLX5_QPC_PM_STATE_ARMED = 0x0, 2996 MLX5_QPC_PM_STATE_REARM = 0x1, 2997 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2998 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2999 }; 3000 3001 enum { 3002 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3003 }; 3004 3005 enum { 3006 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3007 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3008 }; 3009 3010 enum { 3011 MLX5_QPC_MTU_256_BYTES = 0x1, 3012 MLX5_QPC_MTU_512_BYTES = 0x2, 3013 MLX5_QPC_MTU_1K_BYTES = 0x3, 3014 MLX5_QPC_MTU_2K_BYTES = 0x4, 3015 MLX5_QPC_MTU_4K_BYTES = 0x5, 3016 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3017 }; 3018 3019 enum { 3020 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3021 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3022 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3023 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3024 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3025 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3026 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3027 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3028 }; 3029 3030 enum { 3031 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3032 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3033 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3034 }; 3035 3036 enum { 3037 MLX5_QPC_CS_RES_DISABLE = 0x0, 3038 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3039 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3040 }; 3041 3042 enum { 3043 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3044 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3045 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3046 }; 3047 3048 struct mlx5_ifc_qpc_bits { 3049 u8 state[0x4]; 3050 u8 lag_tx_port_affinity[0x4]; 3051 u8 st[0x8]; 3052 u8 reserved_at_10[0x2]; 3053 u8 isolate_vl_tc[0x1]; 3054 u8 pm_state[0x2]; 3055 u8 reserved_at_15[0x1]; 3056 u8 req_e2e_credit_mode[0x2]; 3057 u8 offload_type[0x4]; 3058 u8 end_padding_mode[0x2]; 3059 u8 reserved_at_1e[0x2]; 3060 3061 u8 wq_signature[0x1]; 3062 u8 block_lb_mc[0x1]; 3063 u8 atomic_like_write_en[0x1]; 3064 u8 latency_sensitive[0x1]; 3065 u8 reserved_at_24[0x1]; 3066 u8 drain_sigerr[0x1]; 3067 u8 reserved_at_26[0x2]; 3068 u8 pd[0x18]; 3069 3070 u8 mtu[0x3]; 3071 u8 log_msg_max[0x5]; 3072 u8 reserved_at_48[0x1]; 3073 u8 log_rq_size[0x4]; 3074 u8 log_rq_stride[0x3]; 3075 u8 no_sq[0x1]; 3076 u8 log_sq_size[0x4]; 3077 u8 reserved_at_55[0x3]; 3078 u8 ts_format[0x2]; 3079 u8 reserved_at_5a[0x1]; 3080 u8 rlky[0x1]; 3081 u8 ulp_stateless_offload_mode[0x4]; 3082 3083 u8 counter_set_id[0x8]; 3084 u8 uar_page[0x18]; 3085 3086 u8 reserved_at_80[0x8]; 3087 u8 user_index[0x18]; 3088 3089 u8 reserved_at_a0[0x3]; 3090 u8 log_page_size[0x5]; 3091 u8 remote_qpn[0x18]; 3092 3093 struct mlx5_ifc_ads_bits primary_address_path; 3094 3095 struct mlx5_ifc_ads_bits secondary_address_path; 3096 3097 u8 log_ack_req_freq[0x4]; 3098 u8 reserved_at_384[0x4]; 3099 u8 log_sra_max[0x3]; 3100 u8 reserved_at_38b[0x2]; 3101 u8 retry_count[0x3]; 3102 u8 rnr_retry[0x3]; 3103 u8 reserved_at_393[0x1]; 3104 u8 fre[0x1]; 3105 u8 cur_rnr_retry[0x3]; 3106 u8 cur_retry_count[0x3]; 3107 u8 reserved_at_39b[0x5]; 3108 3109 u8 reserved_at_3a0[0x20]; 3110 3111 u8 reserved_at_3c0[0x8]; 3112 u8 next_send_psn[0x18]; 3113 3114 u8 reserved_at_3e0[0x3]; 3115 u8 log_num_dci_stream_channels[0x5]; 3116 u8 cqn_snd[0x18]; 3117 3118 u8 reserved_at_400[0x3]; 3119 u8 log_num_dci_errored_streams[0x5]; 3120 u8 deth_sqpn[0x18]; 3121 3122 u8 reserved_at_420[0x20]; 3123 3124 u8 reserved_at_440[0x8]; 3125 u8 last_acked_psn[0x18]; 3126 3127 u8 reserved_at_460[0x8]; 3128 u8 ssn[0x18]; 3129 3130 u8 reserved_at_480[0x8]; 3131 u8 log_rra_max[0x3]; 3132 u8 reserved_at_48b[0x1]; 3133 u8 atomic_mode[0x4]; 3134 u8 rre[0x1]; 3135 u8 rwe[0x1]; 3136 u8 rae[0x1]; 3137 u8 reserved_at_493[0x1]; 3138 u8 page_offset[0x6]; 3139 u8 reserved_at_49a[0x3]; 3140 u8 cd_slave_receive[0x1]; 3141 u8 cd_slave_send[0x1]; 3142 u8 cd_master[0x1]; 3143 3144 u8 reserved_at_4a0[0x3]; 3145 u8 min_rnr_nak[0x5]; 3146 u8 next_rcv_psn[0x18]; 3147 3148 u8 reserved_at_4c0[0x8]; 3149 u8 xrcd[0x18]; 3150 3151 u8 reserved_at_4e0[0x8]; 3152 u8 cqn_rcv[0x18]; 3153 3154 u8 dbr_addr[0x40]; 3155 3156 u8 q_key[0x20]; 3157 3158 u8 reserved_at_560[0x5]; 3159 u8 rq_type[0x3]; 3160 u8 srqn_rmpn_xrqn[0x18]; 3161 3162 u8 reserved_at_580[0x8]; 3163 u8 rmsn[0x18]; 3164 3165 u8 hw_sq_wqebb_counter[0x10]; 3166 u8 sw_sq_wqebb_counter[0x10]; 3167 3168 u8 hw_rq_counter[0x20]; 3169 3170 u8 sw_rq_counter[0x20]; 3171 3172 u8 reserved_at_600[0x20]; 3173 3174 u8 reserved_at_620[0xf]; 3175 u8 cgs[0x1]; 3176 u8 cs_req[0x8]; 3177 u8 cs_res[0x8]; 3178 3179 u8 dc_access_key[0x40]; 3180 3181 u8 reserved_at_680[0x3]; 3182 u8 dbr_umem_valid[0x1]; 3183 3184 u8 reserved_at_684[0xbc]; 3185 }; 3186 3187 struct mlx5_ifc_roce_addr_layout_bits { 3188 u8 source_l3_address[16][0x8]; 3189 3190 u8 reserved_at_80[0x3]; 3191 u8 vlan_valid[0x1]; 3192 u8 vlan_id[0xc]; 3193 u8 source_mac_47_32[0x10]; 3194 3195 u8 source_mac_31_0[0x20]; 3196 3197 u8 reserved_at_c0[0x14]; 3198 u8 roce_l3_type[0x4]; 3199 u8 roce_version[0x8]; 3200 3201 u8 reserved_at_e0[0x20]; 3202 }; 3203 3204 struct mlx5_ifc_shampo_cap_bits { 3205 u8 reserved_at_0[0x3]; 3206 u8 shampo_log_max_reservation_size[0x5]; 3207 u8 reserved_at_8[0x3]; 3208 u8 shampo_log_min_reservation_size[0x5]; 3209 u8 shampo_min_mss_size[0x10]; 3210 3211 u8 reserved_at_20[0x3]; 3212 u8 shampo_max_log_headers_entry_size[0x5]; 3213 u8 reserved_at_28[0x18]; 3214 3215 u8 reserved_at_40[0x7c0]; 3216 }; 3217 3218 union mlx5_ifc_hca_cap_union_bits { 3219 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3220 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3221 struct mlx5_ifc_odp_cap_bits odp_cap; 3222 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3223 struct mlx5_ifc_roce_cap_bits roce_cap; 3224 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3225 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3226 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3227 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3228 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3229 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3230 struct mlx5_ifc_qos_cap_bits qos_cap; 3231 struct mlx5_ifc_debug_cap_bits debug_cap; 3232 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3233 struct mlx5_ifc_tls_cap_bits tls_cap; 3234 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3235 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3236 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3237 u8 reserved_at_0[0x8000]; 3238 }; 3239 3240 enum { 3241 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3242 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3243 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3244 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3245 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3246 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3247 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3248 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3249 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3250 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3251 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3252 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3253 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3254 }; 3255 3256 enum { 3257 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3258 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3259 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3260 }; 3261 3262 struct mlx5_ifc_vlan_bits { 3263 u8 ethtype[0x10]; 3264 u8 prio[0x3]; 3265 u8 cfi[0x1]; 3266 u8 vid[0xc]; 3267 }; 3268 3269 struct mlx5_ifc_flow_context_bits { 3270 struct mlx5_ifc_vlan_bits push_vlan; 3271 3272 u8 group_id[0x20]; 3273 3274 u8 reserved_at_40[0x8]; 3275 u8 flow_tag[0x18]; 3276 3277 u8 reserved_at_60[0x10]; 3278 u8 action[0x10]; 3279 3280 u8 extended_destination[0x1]; 3281 u8 reserved_at_81[0x1]; 3282 u8 flow_source[0x2]; 3283 u8 reserved_at_84[0x4]; 3284 u8 destination_list_size[0x18]; 3285 3286 u8 reserved_at_a0[0x8]; 3287 u8 flow_counter_list_size[0x18]; 3288 3289 u8 packet_reformat_id[0x20]; 3290 3291 u8 modify_header_id[0x20]; 3292 3293 struct mlx5_ifc_vlan_bits push_vlan_2; 3294 3295 u8 ipsec_obj_id[0x20]; 3296 u8 reserved_at_140[0xc0]; 3297 3298 struct mlx5_ifc_fte_match_param_bits match_value; 3299 3300 u8 reserved_at_1200[0x600]; 3301 3302 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3303 }; 3304 3305 enum { 3306 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3307 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3308 }; 3309 3310 struct mlx5_ifc_xrc_srqc_bits { 3311 u8 state[0x4]; 3312 u8 log_xrc_srq_size[0x4]; 3313 u8 reserved_at_8[0x18]; 3314 3315 u8 wq_signature[0x1]; 3316 u8 cont_srq[0x1]; 3317 u8 reserved_at_22[0x1]; 3318 u8 rlky[0x1]; 3319 u8 basic_cyclic_rcv_wqe[0x1]; 3320 u8 log_rq_stride[0x3]; 3321 u8 xrcd[0x18]; 3322 3323 u8 page_offset[0x6]; 3324 u8 reserved_at_46[0x1]; 3325 u8 dbr_umem_valid[0x1]; 3326 u8 cqn[0x18]; 3327 3328 u8 reserved_at_60[0x20]; 3329 3330 u8 user_index_equal_xrc_srqn[0x1]; 3331 u8 reserved_at_81[0x1]; 3332 u8 log_page_size[0x6]; 3333 u8 user_index[0x18]; 3334 3335 u8 reserved_at_a0[0x20]; 3336 3337 u8 reserved_at_c0[0x8]; 3338 u8 pd[0x18]; 3339 3340 u8 lwm[0x10]; 3341 u8 wqe_cnt[0x10]; 3342 3343 u8 reserved_at_100[0x40]; 3344 3345 u8 db_record_addr_h[0x20]; 3346 3347 u8 db_record_addr_l[0x1e]; 3348 u8 reserved_at_17e[0x2]; 3349 3350 u8 reserved_at_180[0x80]; 3351 }; 3352 3353 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3354 u8 counter_error_queues[0x20]; 3355 3356 u8 total_error_queues[0x20]; 3357 3358 u8 send_queue_priority_update_flow[0x20]; 3359 3360 u8 reserved_at_60[0x20]; 3361 3362 u8 nic_receive_steering_discard[0x40]; 3363 3364 u8 receive_discard_vport_down[0x40]; 3365 3366 u8 transmit_discard_vport_down[0x40]; 3367 3368 u8 reserved_at_140[0xa0]; 3369 3370 u8 internal_rq_out_of_buffer[0x20]; 3371 3372 u8 reserved_at_200[0xe00]; 3373 }; 3374 3375 struct mlx5_ifc_traffic_counter_bits { 3376 u8 packets[0x40]; 3377 3378 u8 octets[0x40]; 3379 }; 3380 3381 struct mlx5_ifc_tisc_bits { 3382 u8 strict_lag_tx_port_affinity[0x1]; 3383 u8 tls_en[0x1]; 3384 u8 reserved_at_2[0x2]; 3385 u8 lag_tx_port_affinity[0x04]; 3386 3387 u8 reserved_at_8[0x4]; 3388 u8 prio[0x4]; 3389 u8 reserved_at_10[0x10]; 3390 3391 u8 reserved_at_20[0x100]; 3392 3393 u8 reserved_at_120[0x8]; 3394 u8 transport_domain[0x18]; 3395 3396 u8 reserved_at_140[0x8]; 3397 u8 underlay_qpn[0x18]; 3398 3399 u8 reserved_at_160[0x8]; 3400 u8 pd[0x18]; 3401 3402 u8 reserved_at_180[0x380]; 3403 }; 3404 3405 enum { 3406 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3407 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3408 }; 3409 3410 enum { 3411 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3412 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3413 MLX5_TIRC_PACKET_MERGE_MASK_SHAMPO = BIT(2), 3414 }; 3415 3416 enum { 3417 MLX5_RX_HASH_FN_NONE = 0x0, 3418 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3419 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3420 }; 3421 3422 enum { 3423 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3424 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3425 }; 3426 3427 struct mlx5_ifc_tirc_bits { 3428 u8 reserved_at_0[0x20]; 3429 3430 u8 disp_type[0x4]; 3431 u8 tls_en[0x1]; 3432 u8 reserved_at_25[0x1b]; 3433 3434 u8 reserved_at_40[0x40]; 3435 3436 u8 reserved_at_80[0x4]; 3437 u8 lro_timeout_period_usecs[0x10]; 3438 u8 packet_merge_mask[0x4]; 3439 u8 lro_max_ip_payload_size[0x8]; 3440 3441 u8 reserved_at_a0[0x40]; 3442 3443 u8 reserved_at_e0[0x8]; 3444 u8 inline_rqn[0x18]; 3445 3446 u8 rx_hash_symmetric[0x1]; 3447 u8 reserved_at_101[0x1]; 3448 u8 tunneled_offload_en[0x1]; 3449 u8 reserved_at_103[0x5]; 3450 u8 indirect_table[0x18]; 3451 3452 u8 rx_hash_fn[0x4]; 3453 u8 reserved_at_124[0x2]; 3454 u8 self_lb_block[0x2]; 3455 u8 transport_domain[0x18]; 3456 3457 u8 rx_hash_toeplitz_key[10][0x20]; 3458 3459 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3460 3461 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3462 3463 u8 reserved_at_2c0[0x4c0]; 3464 }; 3465 3466 enum { 3467 MLX5_SRQC_STATE_GOOD = 0x0, 3468 MLX5_SRQC_STATE_ERROR = 0x1, 3469 }; 3470 3471 struct mlx5_ifc_srqc_bits { 3472 u8 state[0x4]; 3473 u8 log_srq_size[0x4]; 3474 u8 reserved_at_8[0x18]; 3475 3476 u8 wq_signature[0x1]; 3477 u8 cont_srq[0x1]; 3478 u8 reserved_at_22[0x1]; 3479 u8 rlky[0x1]; 3480 u8 reserved_at_24[0x1]; 3481 u8 log_rq_stride[0x3]; 3482 u8 xrcd[0x18]; 3483 3484 u8 page_offset[0x6]; 3485 u8 reserved_at_46[0x2]; 3486 u8 cqn[0x18]; 3487 3488 u8 reserved_at_60[0x20]; 3489 3490 u8 reserved_at_80[0x2]; 3491 u8 log_page_size[0x6]; 3492 u8 reserved_at_88[0x18]; 3493 3494 u8 reserved_at_a0[0x20]; 3495 3496 u8 reserved_at_c0[0x8]; 3497 u8 pd[0x18]; 3498 3499 u8 lwm[0x10]; 3500 u8 wqe_cnt[0x10]; 3501 3502 u8 reserved_at_100[0x40]; 3503 3504 u8 dbr_addr[0x40]; 3505 3506 u8 reserved_at_180[0x80]; 3507 }; 3508 3509 enum { 3510 MLX5_SQC_STATE_RST = 0x0, 3511 MLX5_SQC_STATE_RDY = 0x1, 3512 MLX5_SQC_STATE_ERR = 0x3, 3513 }; 3514 3515 struct mlx5_ifc_sqc_bits { 3516 u8 rlky[0x1]; 3517 u8 cd_master[0x1]; 3518 u8 fre[0x1]; 3519 u8 flush_in_error_en[0x1]; 3520 u8 allow_multi_pkt_send_wqe[0x1]; 3521 u8 min_wqe_inline_mode[0x3]; 3522 u8 state[0x4]; 3523 u8 reg_umr[0x1]; 3524 u8 allow_swp[0x1]; 3525 u8 hairpin[0x1]; 3526 u8 reserved_at_f[0xb]; 3527 u8 ts_format[0x2]; 3528 u8 reserved_at_1c[0x4]; 3529 3530 u8 reserved_at_20[0x8]; 3531 u8 user_index[0x18]; 3532 3533 u8 reserved_at_40[0x8]; 3534 u8 cqn[0x18]; 3535 3536 u8 reserved_at_60[0x8]; 3537 u8 hairpin_peer_rq[0x18]; 3538 3539 u8 reserved_at_80[0x10]; 3540 u8 hairpin_peer_vhca[0x10]; 3541 3542 u8 reserved_at_a0[0x20]; 3543 3544 u8 reserved_at_c0[0x8]; 3545 u8 ts_cqe_to_dest_cqn[0x18]; 3546 3547 u8 reserved_at_e0[0x10]; 3548 u8 packet_pacing_rate_limit_index[0x10]; 3549 u8 tis_lst_sz[0x10]; 3550 u8 qos_queue_group_id[0x10]; 3551 3552 u8 reserved_at_120[0x40]; 3553 3554 u8 reserved_at_160[0x8]; 3555 u8 tis_num_0[0x18]; 3556 3557 struct mlx5_ifc_wq_bits wq; 3558 }; 3559 3560 enum { 3561 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3562 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3563 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3564 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3565 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3566 }; 3567 3568 enum { 3569 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3570 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3571 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3572 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3573 }; 3574 3575 struct mlx5_ifc_scheduling_context_bits { 3576 u8 element_type[0x8]; 3577 u8 reserved_at_8[0x18]; 3578 3579 u8 element_attributes[0x20]; 3580 3581 u8 parent_element_id[0x20]; 3582 3583 u8 reserved_at_60[0x40]; 3584 3585 u8 bw_share[0x20]; 3586 3587 u8 max_average_bw[0x20]; 3588 3589 u8 reserved_at_e0[0x120]; 3590 }; 3591 3592 struct mlx5_ifc_rqtc_bits { 3593 u8 reserved_at_0[0xa0]; 3594 3595 u8 reserved_at_a0[0x5]; 3596 u8 list_q_type[0x3]; 3597 u8 reserved_at_a8[0x8]; 3598 u8 rqt_max_size[0x10]; 3599 3600 u8 rq_vhca_id_format[0x1]; 3601 u8 reserved_at_c1[0xf]; 3602 u8 rqt_actual_size[0x10]; 3603 3604 u8 reserved_at_e0[0x6a0]; 3605 3606 struct mlx5_ifc_rq_num_bits rq_num[]; 3607 }; 3608 3609 enum { 3610 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3611 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3612 }; 3613 3614 enum { 3615 MLX5_RQC_STATE_RST = 0x0, 3616 MLX5_RQC_STATE_RDY = 0x1, 3617 MLX5_RQC_STATE_ERR = 0x3, 3618 }; 3619 3620 enum { 3621 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3622 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3623 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3624 }; 3625 3626 enum { 3627 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3628 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3629 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3630 }; 3631 3632 struct mlx5_ifc_rqc_bits { 3633 u8 rlky[0x1]; 3634 u8 delay_drop_en[0x1]; 3635 u8 scatter_fcs[0x1]; 3636 u8 vsd[0x1]; 3637 u8 mem_rq_type[0x4]; 3638 u8 state[0x4]; 3639 u8 reserved_at_c[0x1]; 3640 u8 flush_in_error_en[0x1]; 3641 u8 hairpin[0x1]; 3642 u8 reserved_at_f[0xb]; 3643 u8 ts_format[0x2]; 3644 u8 reserved_at_1c[0x4]; 3645 3646 u8 reserved_at_20[0x8]; 3647 u8 user_index[0x18]; 3648 3649 u8 reserved_at_40[0x8]; 3650 u8 cqn[0x18]; 3651 3652 u8 counter_set_id[0x8]; 3653 u8 reserved_at_68[0x18]; 3654 3655 u8 reserved_at_80[0x8]; 3656 u8 rmpn[0x18]; 3657 3658 u8 reserved_at_a0[0x8]; 3659 u8 hairpin_peer_sq[0x18]; 3660 3661 u8 reserved_at_c0[0x10]; 3662 u8 hairpin_peer_vhca[0x10]; 3663 3664 u8 reserved_at_e0[0x46]; 3665 u8 shampo_no_match_alignment_granularity[0x2]; 3666 u8 reserved_at_128[0x6]; 3667 u8 shampo_match_criteria_type[0x2]; 3668 u8 reservation_timeout[0x10]; 3669 3670 u8 reserved_at_140[0x40]; 3671 3672 struct mlx5_ifc_wq_bits wq; 3673 }; 3674 3675 enum { 3676 MLX5_RMPC_STATE_RDY = 0x1, 3677 MLX5_RMPC_STATE_ERR = 0x3, 3678 }; 3679 3680 struct mlx5_ifc_rmpc_bits { 3681 u8 reserved_at_0[0x8]; 3682 u8 state[0x4]; 3683 u8 reserved_at_c[0x14]; 3684 3685 u8 basic_cyclic_rcv_wqe[0x1]; 3686 u8 reserved_at_21[0x1f]; 3687 3688 u8 reserved_at_40[0x140]; 3689 3690 struct mlx5_ifc_wq_bits wq; 3691 }; 3692 3693 struct mlx5_ifc_nic_vport_context_bits { 3694 u8 reserved_at_0[0x5]; 3695 u8 min_wqe_inline_mode[0x3]; 3696 u8 reserved_at_8[0x15]; 3697 u8 disable_mc_local_lb[0x1]; 3698 u8 disable_uc_local_lb[0x1]; 3699 u8 roce_en[0x1]; 3700 3701 u8 arm_change_event[0x1]; 3702 u8 reserved_at_21[0x1a]; 3703 u8 event_on_mtu[0x1]; 3704 u8 event_on_promisc_change[0x1]; 3705 u8 event_on_vlan_change[0x1]; 3706 u8 event_on_mc_address_change[0x1]; 3707 u8 event_on_uc_address_change[0x1]; 3708 3709 u8 reserved_at_40[0xc]; 3710 3711 u8 affiliation_criteria[0x4]; 3712 u8 affiliated_vhca_id[0x10]; 3713 3714 u8 reserved_at_60[0xd0]; 3715 3716 u8 mtu[0x10]; 3717 3718 u8 system_image_guid[0x40]; 3719 u8 port_guid[0x40]; 3720 u8 node_guid[0x40]; 3721 3722 u8 reserved_at_200[0x140]; 3723 u8 qkey_violation_counter[0x10]; 3724 u8 reserved_at_350[0x430]; 3725 3726 u8 promisc_uc[0x1]; 3727 u8 promisc_mc[0x1]; 3728 u8 promisc_all[0x1]; 3729 u8 reserved_at_783[0x2]; 3730 u8 allowed_list_type[0x3]; 3731 u8 reserved_at_788[0xc]; 3732 u8 allowed_list_size[0xc]; 3733 3734 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3735 3736 u8 reserved_at_7e0[0x20]; 3737 3738 u8 current_uc_mac_address[][0x40]; 3739 }; 3740 3741 enum { 3742 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3743 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3744 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3745 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3746 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3747 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3748 }; 3749 3750 struct mlx5_ifc_mkc_bits { 3751 u8 reserved_at_0[0x1]; 3752 u8 free[0x1]; 3753 u8 reserved_at_2[0x1]; 3754 u8 access_mode_4_2[0x3]; 3755 u8 reserved_at_6[0x7]; 3756 u8 relaxed_ordering_write[0x1]; 3757 u8 reserved_at_e[0x1]; 3758 u8 small_fence_on_rdma_read_response[0x1]; 3759 u8 umr_en[0x1]; 3760 u8 a[0x1]; 3761 u8 rw[0x1]; 3762 u8 rr[0x1]; 3763 u8 lw[0x1]; 3764 u8 lr[0x1]; 3765 u8 access_mode_1_0[0x2]; 3766 u8 reserved_at_18[0x8]; 3767 3768 u8 qpn[0x18]; 3769 u8 mkey_7_0[0x8]; 3770 3771 u8 reserved_at_40[0x20]; 3772 3773 u8 length64[0x1]; 3774 u8 bsf_en[0x1]; 3775 u8 sync_umr[0x1]; 3776 u8 reserved_at_63[0x2]; 3777 u8 expected_sigerr_count[0x1]; 3778 u8 reserved_at_66[0x1]; 3779 u8 en_rinval[0x1]; 3780 u8 pd[0x18]; 3781 3782 u8 start_addr[0x40]; 3783 3784 u8 len[0x40]; 3785 3786 u8 bsf_octword_size[0x20]; 3787 3788 u8 reserved_at_120[0x80]; 3789 3790 u8 translations_octword_size[0x20]; 3791 3792 u8 reserved_at_1c0[0x19]; 3793 u8 relaxed_ordering_read[0x1]; 3794 u8 reserved_at_1d9[0x1]; 3795 u8 log_page_size[0x5]; 3796 3797 u8 reserved_at_1e0[0x20]; 3798 }; 3799 3800 struct mlx5_ifc_pkey_bits { 3801 u8 reserved_at_0[0x10]; 3802 u8 pkey[0x10]; 3803 }; 3804 3805 struct mlx5_ifc_array128_auto_bits { 3806 u8 array128_auto[16][0x8]; 3807 }; 3808 3809 struct mlx5_ifc_hca_vport_context_bits { 3810 u8 field_select[0x20]; 3811 3812 u8 reserved_at_20[0xe0]; 3813 3814 u8 sm_virt_aware[0x1]; 3815 u8 has_smi[0x1]; 3816 u8 has_raw[0x1]; 3817 u8 grh_required[0x1]; 3818 u8 reserved_at_104[0xc]; 3819 u8 port_physical_state[0x4]; 3820 u8 vport_state_policy[0x4]; 3821 u8 port_state[0x4]; 3822 u8 vport_state[0x4]; 3823 3824 u8 reserved_at_120[0x20]; 3825 3826 u8 system_image_guid[0x40]; 3827 3828 u8 port_guid[0x40]; 3829 3830 u8 node_guid[0x40]; 3831 3832 u8 cap_mask1[0x20]; 3833 3834 u8 cap_mask1_field_select[0x20]; 3835 3836 u8 cap_mask2[0x20]; 3837 3838 u8 cap_mask2_field_select[0x20]; 3839 3840 u8 reserved_at_280[0x80]; 3841 3842 u8 lid[0x10]; 3843 u8 reserved_at_310[0x4]; 3844 u8 init_type_reply[0x4]; 3845 u8 lmc[0x3]; 3846 u8 subnet_timeout[0x5]; 3847 3848 u8 sm_lid[0x10]; 3849 u8 sm_sl[0x4]; 3850 u8 reserved_at_334[0xc]; 3851 3852 u8 qkey_violation_counter[0x10]; 3853 u8 pkey_violation_counter[0x10]; 3854 3855 u8 reserved_at_360[0xca0]; 3856 }; 3857 3858 struct mlx5_ifc_esw_vport_context_bits { 3859 u8 fdb_to_vport_reg_c[0x1]; 3860 u8 reserved_at_1[0x2]; 3861 u8 vport_svlan_strip[0x1]; 3862 u8 vport_cvlan_strip[0x1]; 3863 u8 vport_svlan_insert[0x1]; 3864 u8 vport_cvlan_insert[0x2]; 3865 u8 fdb_to_vport_reg_c_id[0x8]; 3866 u8 reserved_at_10[0x10]; 3867 3868 u8 reserved_at_20[0x20]; 3869 3870 u8 svlan_cfi[0x1]; 3871 u8 svlan_pcp[0x3]; 3872 u8 svlan_id[0xc]; 3873 u8 cvlan_cfi[0x1]; 3874 u8 cvlan_pcp[0x3]; 3875 u8 cvlan_id[0xc]; 3876 3877 u8 reserved_at_60[0x720]; 3878 3879 u8 sw_steering_vport_icm_address_rx[0x40]; 3880 3881 u8 sw_steering_vport_icm_address_tx[0x40]; 3882 }; 3883 3884 enum { 3885 MLX5_EQC_STATUS_OK = 0x0, 3886 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3887 }; 3888 3889 enum { 3890 MLX5_EQC_ST_ARMED = 0x9, 3891 MLX5_EQC_ST_FIRED = 0xa, 3892 }; 3893 3894 struct mlx5_ifc_eqc_bits { 3895 u8 status[0x4]; 3896 u8 reserved_at_4[0x9]; 3897 u8 ec[0x1]; 3898 u8 oi[0x1]; 3899 u8 reserved_at_f[0x5]; 3900 u8 st[0x4]; 3901 u8 reserved_at_18[0x8]; 3902 3903 u8 reserved_at_20[0x20]; 3904 3905 u8 reserved_at_40[0x14]; 3906 u8 page_offset[0x6]; 3907 u8 reserved_at_5a[0x6]; 3908 3909 u8 reserved_at_60[0x3]; 3910 u8 log_eq_size[0x5]; 3911 u8 uar_page[0x18]; 3912 3913 u8 reserved_at_80[0x20]; 3914 3915 u8 reserved_at_a0[0x14]; 3916 u8 intr[0xc]; 3917 3918 u8 reserved_at_c0[0x3]; 3919 u8 log_page_size[0x5]; 3920 u8 reserved_at_c8[0x18]; 3921 3922 u8 reserved_at_e0[0x60]; 3923 3924 u8 reserved_at_140[0x8]; 3925 u8 consumer_counter[0x18]; 3926 3927 u8 reserved_at_160[0x8]; 3928 u8 producer_counter[0x18]; 3929 3930 u8 reserved_at_180[0x80]; 3931 }; 3932 3933 enum { 3934 MLX5_DCTC_STATE_ACTIVE = 0x0, 3935 MLX5_DCTC_STATE_DRAINING = 0x1, 3936 MLX5_DCTC_STATE_DRAINED = 0x2, 3937 }; 3938 3939 enum { 3940 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3941 MLX5_DCTC_CS_RES_NA = 0x1, 3942 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3943 }; 3944 3945 enum { 3946 MLX5_DCTC_MTU_256_BYTES = 0x1, 3947 MLX5_DCTC_MTU_512_BYTES = 0x2, 3948 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3949 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3950 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3951 }; 3952 3953 struct mlx5_ifc_dctc_bits { 3954 u8 reserved_at_0[0x4]; 3955 u8 state[0x4]; 3956 u8 reserved_at_8[0x18]; 3957 3958 u8 reserved_at_20[0x8]; 3959 u8 user_index[0x18]; 3960 3961 u8 reserved_at_40[0x8]; 3962 u8 cqn[0x18]; 3963 3964 u8 counter_set_id[0x8]; 3965 u8 atomic_mode[0x4]; 3966 u8 rre[0x1]; 3967 u8 rwe[0x1]; 3968 u8 rae[0x1]; 3969 u8 atomic_like_write_en[0x1]; 3970 u8 latency_sensitive[0x1]; 3971 u8 rlky[0x1]; 3972 u8 free_ar[0x1]; 3973 u8 reserved_at_73[0xd]; 3974 3975 u8 reserved_at_80[0x8]; 3976 u8 cs_res[0x8]; 3977 u8 reserved_at_90[0x3]; 3978 u8 min_rnr_nak[0x5]; 3979 u8 reserved_at_98[0x8]; 3980 3981 u8 reserved_at_a0[0x8]; 3982 u8 srqn_xrqn[0x18]; 3983 3984 u8 reserved_at_c0[0x8]; 3985 u8 pd[0x18]; 3986 3987 u8 tclass[0x8]; 3988 u8 reserved_at_e8[0x4]; 3989 u8 flow_label[0x14]; 3990 3991 u8 dc_access_key[0x40]; 3992 3993 u8 reserved_at_140[0x5]; 3994 u8 mtu[0x3]; 3995 u8 port[0x8]; 3996 u8 pkey_index[0x10]; 3997 3998 u8 reserved_at_160[0x8]; 3999 u8 my_addr_index[0x8]; 4000 u8 reserved_at_170[0x8]; 4001 u8 hop_limit[0x8]; 4002 4003 u8 dc_access_key_violation_count[0x20]; 4004 4005 u8 reserved_at_1a0[0x14]; 4006 u8 dei_cfi[0x1]; 4007 u8 eth_prio[0x3]; 4008 u8 ecn[0x2]; 4009 u8 dscp[0x6]; 4010 4011 u8 reserved_at_1c0[0x20]; 4012 u8 ece[0x20]; 4013 }; 4014 4015 enum { 4016 MLX5_CQC_STATUS_OK = 0x0, 4017 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4018 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4019 }; 4020 4021 enum { 4022 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4023 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4024 }; 4025 4026 enum { 4027 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4028 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4029 MLX5_CQC_ST_FIRED = 0xa, 4030 }; 4031 4032 enum { 4033 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4034 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4035 MLX5_CQ_PERIOD_NUM_MODES 4036 }; 4037 4038 struct mlx5_ifc_cqc_bits { 4039 u8 status[0x4]; 4040 u8 reserved_at_4[0x2]; 4041 u8 dbr_umem_valid[0x1]; 4042 u8 apu_cq[0x1]; 4043 u8 cqe_sz[0x3]; 4044 u8 cc[0x1]; 4045 u8 reserved_at_c[0x1]; 4046 u8 scqe_break_moderation_en[0x1]; 4047 u8 oi[0x1]; 4048 u8 cq_period_mode[0x2]; 4049 u8 cqe_comp_en[0x1]; 4050 u8 mini_cqe_res_format[0x2]; 4051 u8 st[0x4]; 4052 u8 reserved_at_18[0x8]; 4053 4054 u8 reserved_at_20[0x20]; 4055 4056 u8 reserved_at_40[0x14]; 4057 u8 page_offset[0x6]; 4058 u8 reserved_at_5a[0x6]; 4059 4060 u8 reserved_at_60[0x3]; 4061 u8 log_cq_size[0x5]; 4062 u8 uar_page[0x18]; 4063 4064 u8 reserved_at_80[0x4]; 4065 u8 cq_period[0xc]; 4066 u8 cq_max_count[0x10]; 4067 4068 u8 c_eqn_or_apu_element[0x20]; 4069 4070 u8 reserved_at_c0[0x3]; 4071 u8 log_page_size[0x5]; 4072 u8 reserved_at_c8[0x18]; 4073 4074 u8 reserved_at_e0[0x20]; 4075 4076 u8 reserved_at_100[0x8]; 4077 u8 last_notified_index[0x18]; 4078 4079 u8 reserved_at_120[0x8]; 4080 u8 last_solicit_index[0x18]; 4081 4082 u8 reserved_at_140[0x8]; 4083 u8 consumer_counter[0x18]; 4084 4085 u8 reserved_at_160[0x8]; 4086 u8 producer_counter[0x18]; 4087 4088 u8 reserved_at_180[0x40]; 4089 4090 u8 dbr_addr[0x40]; 4091 }; 4092 4093 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4094 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4095 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4096 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4097 u8 reserved_at_0[0x800]; 4098 }; 4099 4100 struct mlx5_ifc_query_adapter_param_block_bits { 4101 u8 reserved_at_0[0xc0]; 4102 4103 u8 reserved_at_c0[0x8]; 4104 u8 ieee_vendor_id[0x18]; 4105 4106 u8 reserved_at_e0[0x10]; 4107 u8 vsd_vendor_id[0x10]; 4108 4109 u8 vsd[208][0x8]; 4110 4111 u8 vsd_contd_psid[16][0x8]; 4112 }; 4113 4114 enum { 4115 MLX5_XRQC_STATE_GOOD = 0x0, 4116 MLX5_XRQC_STATE_ERROR = 0x1, 4117 }; 4118 4119 enum { 4120 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4121 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4122 }; 4123 4124 enum { 4125 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4126 }; 4127 4128 struct mlx5_ifc_tag_matching_topology_context_bits { 4129 u8 log_matching_list_sz[0x4]; 4130 u8 reserved_at_4[0xc]; 4131 u8 append_next_index[0x10]; 4132 4133 u8 sw_phase_cnt[0x10]; 4134 u8 hw_phase_cnt[0x10]; 4135 4136 u8 reserved_at_40[0x40]; 4137 }; 4138 4139 struct mlx5_ifc_xrqc_bits { 4140 u8 state[0x4]; 4141 u8 rlkey[0x1]; 4142 u8 reserved_at_5[0xf]; 4143 u8 topology[0x4]; 4144 u8 reserved_at_18[0x4]; 4145 u8 offload[0x4]; 4146 4147 u8 reserved_at_20[0x8]; 4148 u8 user_index[0x18]; 4149 4150 u8 reserved_at_40[0x8]; 4151 u8 cqn[0x18]; 4152 4153 u8 reserved_at_60[0xa0]; 4154 4155 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4156 4157 u8 reserved_at_180[0x280]; 4158 4159 struct mlx5_ifc_wq_bits wq; 4160 }; 4161 4162 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4163 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4164 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4165 u8 reserved_at_0[0x20]; 4166 }; 4167 4168 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4169 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4170 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4171 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4172 u8 reserved_at_0[0x20]; 4173 }; 4174 4175 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4176 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4177 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4178 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4179 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4180 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4181 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4182 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4183 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4184 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4185 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4186 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4187 u8 reserved_at_0[0x7c0]; 4188 }; 4189 4190 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4191 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4192 u8 reserved_at_0[0x7c0]; 4193 }; 4194 4195 union mlx5_ifc_event_auto_bits { 4196 struct mlx5_ifc_comp_event_bits comp_event; 4197 struct mlx5_ifc_dct_events_bits dct_events; 4198 struct mlx5_ifc_qp_events_bits qp_events; 4199 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4200 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4201 struct mlx5_ifc_cq_error_bits cq_error; 4202 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4203 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4204 struct mlx5_ifc_gpio_event_bits gpio_event; 4205 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4206 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4207 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4208 u8 reserved_at_0[0xe0]; 4209 }; 4210 4211 struct mlx5_ifc_health_buffer_bits { 4212 u8 reserved_at_0[0x100]; 4213 4214 u8 assert_existptr[0x20]; 4215 4216 u8 assert_callra[0x20]; 4217 4218 u8 reserved_at_140[0x20]; 4219 4220 u8 time[0x20]; 4221 4222 u8 fw_version[0x20]; 4223 4224 u8 hw_id[0x20]; 4225 4226 u8 rfr[0x1]; 4227 u8 reserved_at_1c1[0x3]; 4228 u8 valid[0x1]; 4229 u8 severity[0x3]; 4230 u8 reserved_at_1c8[0x18]; 4231 4232 u8 irisc_index[0x8]; 4233 u8 synd[0x8]; 4234 u8 ext_synd[0x10]; 4235 }; 4236 4237 struct mlx5_ifc_register_loopback_control_bits { 4238 u8 no_lb[0x1]; 4239 u8 reserved_at_1[0x7]; 4240 u8 port[0x8]; 4241 u8 reserved_at_10[0x10]; 4242 4243 u8 reserved_at_20[0x60]; 4244 }; 4245 4246 struct mlx5_ifc_vport_tc_element_bits { 4247 u8 traffic_class[0x4]; 4248 u8 reserved_at_4[0xc]; 4249 u8 vport_number[0x10]; 4250 }; 4251 4252 struct mlx5_ifc_vport_element_bits { 4253 u8 reserved_at_0[0x10]; 4254 u8 vport_number[0x10]; 4255 }; 4256 4257 enum { 4258 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4259 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4260 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4261 }; 4262 4263 struct mlx5_ifc_tsar_element_bits { 4264 u8 reserved_at_0[0x8]; 4265 u8 tsar_type[0x8]; 4266 u8 reserved_at_10[0x10]; 4267 }; 4268 4269 enum { 4270 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4271 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4272 }; 4273 4274 struct mlx5_ifc_teardown_hca_out_bits { 4275 u8 status[0x8]; 4276 u8 reserved_at_8[0x18]; 4277 4278 u8 syndrome[0x20]; 4279 4280 u8 reserved_at_40[0x3f]; 4281 4282 u8 state[0x1]; 4283 }; 4284 4285 enum { 4286 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4287 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4288 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4289 }; 4290 4291 struct mlx5_ifc_teardown_hca_in_bits { 4292 u8 opcode[0x10]; 4293 u8 reserved_at_10[0x10]; 4294 4295 u8 reserved_at_20[0x10]; 4296 u8 op_mod[0x10]; 4297 4298 u8 reserved_at_40[0x10]; 4299 u8 profile[0x10]; 4300 4301 u8 reserved_at_60[0x20]; 4302 }; 4303 4304 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4305 u8 status[0x8]; 4306 u8 reserved_at_8[0x18]; 4307 4308 u8 syndrome[0x20]; 4309 4310 u8 reserved_at_40[0x40]; 4311 }; 4312 4313 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4314 u8 opcode[0x10]; 4315 u8 uid[0x10]; 4316 4317 u8 reserved_at_20[0x10]; 4318 u8 op_mod[0x10]; 4319 4320 u8 reserved_at_40[0x8]; 4321 u8 qpn[0x18]; 4322 4323 u8 reserved_at_60[0x20]; 4324 4325 u8 opt_param_mask[0x20]; 4326 4327 u8 reserved_at_a0[0x20]; 4328 4329 struct mlx5_ifc_qpc_bits qpc; 4330 4331 u8 reserved_at_800[0x80]; 4332 }; 4333 4334 struct mlx5_ifc_sqd2rts_qp_out_bits { 4335 u8 status[0x8]; 4336 u8 reserved_at_8[0x18]; 4337 4338 u8 syndrome[0x20]; 4339 4340 u8 reserved_at_40[0x40]; 4341 }; 4342 4343 struct mlx5_ifc_sqd2rts_qp_in_bits { 4344 u8 opcode[0x10]; 4345 u8 uid[0x10]; 4346 4347 u8 reserved_at_20[0x10]; 4348 u8 op_mod[0x10]; 4349 4350 u8 reserved_at_40[0x8]; 4351 u8 qpn[0x18]; 4352 4353 u8 reserved_at_60[0x20]; 4354 4355 u8 opt_param_mask[0x20]; 4356 4357 u8 reserved_at_a0[0x20]; 4358 4359 struct mlx5_ifc_qpc_bits qpc; 4360 4361 u8 reserved_at_800[0x80]; 4362 }; 4363 4364 struct mlx5_ifc_set_roce_address_out_bits { 4365 u8 status[0x8]; 4366 u8 reserved_at_8[0x18]; 4367 4368 u8 syndrome[0x20]; 4369 4370 u8 reserved_at_40[0x40]; 4371 }; 4372 4373 struct mlx5_ifc_set_roce_address_in_bits { 4374 u8 opcode[0x10]; 4375 u8 reserved_at_10[0x10]; 4376 4377 u8 reserved_at_20[0x10]; 4378 u8 op_mod[0x10]; 4379 4380 u8 roce_address_index[0x10]; 4381 u8 reserved_at_50[0xc]; 4382 u8 vhca_port_num[0x4]; 4383 4384 u8 reserved_at_60[0x20]; 4385 4386 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4387 }; 4388 4389 struct mlx5_ifc_set_mad_demux_out_bits { 4390 u8 status[0x8]; 4391 u8 reserved_at_8[0x18]; 4392 4393 u8 syndrome[0x20]; 4394 4395 u8 reserved_at_40[0x40]; 4396 }; 4397 4398 enum { 4399 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4400 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4401 }; 4402 4403 struct mlx5_ifc_set_mad_demux_in_bits { 4404 u8 opcode[0x10]; 4405 u8 reserved_at_10[0x10]; 4406 4407 u8 reserved_at_20[0x10]; 4408 u8 op_mod[0x10]; 4409 4410 u8 reserved_at_40[0x20]; 4411 4412 u8 reserved_at_60[0x6]; 4413 u8 demux_mode[0x2]; 4414 u8 reserved_at_68[0x18]; 4415 }; 4416 4417 struct mlx5_ifc_set_l2_table_entry_out_bits { 4418 u8 status[0x8]; 4419 u8 reserved_at_8[0x18]; 4420 4421 u8 syndrome[0x20]; 4422 4423 u8 reserved_at_40[0x40]; 4424 }; 4425 4426 struct mlx5_ifc_set_l2_table_entry_in_bits { 4427 u8 opcode[0x10]; 4428 u8 reserved_at_10[0x10]; 4429 4430 u8 reserved_at_20[0x10]; 4431 u8 op_mod[0x10]; 4432 4433 u8 reserved_at_40[0x60]; 4434 4435 u8 reserved_at_a0[0x8]; 4436 u8 table_index[0x18]; 4437 4438 u8 reserved_at_c0[0x20]; 4439 4440 u8 reserved_at_e0[0x13]; 4441 u8 vlan_valid[0x1]; 4442 u8 vlan[0xc]; 4443 4444 struct mlx5_ifc_mac_address_layout_bits mac_address; 4445 4446 u8 reserved_at_140[0xc0]; 4447 }; 4448 4449 struct mlx5_ifc_set_issi_out_bits { 4450 u8 status[0x8]; 4451 u8 reserved_at_8[0x18]; 4452 4453 u8 syndrome[0x20]; 4454 4455 u8 reserved_at_40[0x40]; 4456 }; 4457 4458 struct mlx5_ifc_set_issi_in_bits { 4459 u8 opcode[0x10]; 4460 u8 reserved_at_10[0x10]; 4461 4462 u8 reserved_at_20[0x10]; 4463 u8 op_mod[0x10]; 4464 4465 u8 reserved_at_40[0x10]; 4466 u8 current_issi[0x10]; 4467 4468 u8 reserved_at_60[0x20]; 4469 }; 4470 4471 struct mlx5_ifc_set_hca_cap_out_bits { 4472 u8 status[0x8]; 4473 u8 reserved_at_8[0x18]; 4474 4475 u8 syndrome[0x20]; 4476 4477 u8 reserved_at_40[0x40]; 4478 }; 4479 4480 struct mlx5_ifc_set_hca_cap_in_bits { 4481 u8 opcode[0x10]; 4482 u8 reserved_at_10[0x10]; 4483 4484 u8 reserved_at_20[0x10]; 4485 u8 op_mod[0x10]; 4486 4487 u8 other_function[0x1]; 4488 u8 reserved_at_41[0xf]; 4489 u8 function_id[0x10]; 4490 4491 u8 reserved_at_60[0x20]; 4492 4493 union mlx5_ifc_hca_cap_union_bits capability; 4494 }; 4495 4496 enum { 4497 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4498 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4499 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4500 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4501 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4502 }; 4503 4504 struct mlx5_ifc_set_fte_out_bits { 4505 u8 status[0x8]; 4506 u8 reserved_at_8[0x18]; 4507 4508 u8 syndrome[0x20]; 4509 4510 u8 reserved_at_40[0x40]; 4511 }; 4512 4513 struct mlx5_ifc_set_fte_in_bits { 4514 u8 opcode[0x10]; 4515 u8 reserved_at_10[0x10]; 4516 4517 u8 reserved_at_20[0x10]; 4518 u8 op_mod[0x10]; 4519 4520 u8 other_vport[0x1]; 4521 u8 reserved_at_41[0xf]; 4522 u8 vport_number[0x10]; 4523 4524 u8 reserved_at_60[0x20]; 4525 4526 u8 table_type[0x8]; 4527 u8 reserved_at_88[0x18]; 4528 4529 u8 reserved_at_a0[0x8]; 4530 u8 table_id[0x18]; 4531 4532 u8 ignore_flow_level[0x1]; 4533 u8 reserved_at_c1[0x17]; 4534 u8 modify_enable_mask[0x8]; 4535 4536 u8 reserved_at_e0[0x20]; 4537 4538 u8 flow_index[0x20]; 4539 4540 u8 reserved_at_120[0xe0]; 4541 4542 struct mlx5_ifc_flow_context_bits flow_context; 4543 }; 4544 4545 struct mlx5_ifc_rts2rts_qp_out_bits { 4546 u8 status[0x8]; 4547 u8 reserved_at_8[0x18]; 4548 4549 u8 syndrome[0x20]; 4550 4551 u8 reserved_at_40[0x20]; 4552 u8 ece[0x20]; 4553 }; 4554 4555 struct mlx5_ifc_rts2rts_qp_in_bits { 4556 u8 opcode[0x10]; 4557 u8 uid[0x10]; 4558 4559 u8 reserved_at_20[0x10]; 4560 u8 op_mod[0x10]; 4561 4562 u8 reserved_at_40[0x8]; 4563 u8 qpn[0x18]; 4564 4565 u8 reserved_at_60[0x20]; 4566 4567 u8 opt_param_mask[0x20]; 4568 4569 u8 ece[0x20]; 4570 4571 struct mlx5_ifc_qpc_bits qpc; 4572 4573 u8 reserved_at_800[0x80]; 4574 }; 4575 4576 struct mlx5_ifc_rtr2rts_qp_out_bits { 4577 u8 status[0x8]; 4578 u8 reserved_at_8[0x18]; 4579 4580 u8 syndrome[0x20]; 4581 4582 u8 reserved_at_40[0x20]; 4583 u8 ece[0x20]; 4584 }; 4585 4586 struct mlx5_ifc_rtr2rts_qp_in_bits { 4587 u8 opcode[0x10]; 4588 u8 uid[0x10]; 4589 4590 u8 reserved_at_20[0x10]; 4591 u8 op_mod[0x10]; 4592 4593 u8 reserved_at_40[0x8]; 4594 u8 qpn[0x18]; 4595 4596 u8 reserved_at_60[0x20]; 4597 4598 u8 opt_param_mask[0x20]; 4599 4600 u8 ece[0x20]; 4601 4602 struct mlx5_ifc_qpc_bits qpc; 4603 4604 u8 reserved_at_800[0x80]; 4605 }; 4606 4607 struct mlx5_ifc_rst2init_qp_out_bits { 4608 u8 status[0x8]; 4609 u8 reserved_at_8[0x18]; 4610 4611 u8 syndrome[0x20]; 4612 4613 u8 reserved_at_40[0x20]; 4614 u8 ece[0x20]; 4615 }; 4616 4617 struct mlx5_ifc_rst2init_qp_in_bits { 4618 u8 opcode[0x10]; 4619 u8 uid[0x10]; 4620 4621 u8 reserved_at_20[0x10]; 4622 u8 op_mod[0x10]; 4623 4624 u8 reserved_at_40[0x8]; 4625 u8 qpn[0x18]; 4626 4627 u8 reserved_at_60[0x20]; 4628 4629 u8 opt_param_mask[0x20]; 4630 4631 u8 ece[0x20]; 4632 4633 struct mlx5_ifc_qpc_bits qpc; 4634 4635 u8 reserved_at_800[0x80]; 4636 }; 4637 4638 struct mlx5_ifc_query_xrq_out_bits { 4639 u8 status[0x8]; 4640 u8 reserved_at_8[0x18]; 4641 4642 u8 syndrome[0x20]; 4643 4644 u8 reserved_at_40[0x40]; 4645 4646 struct mlx5_ifc_xrqc_bits xrq_context; 4647 }; 4648 4649 struct mlx5_ifc_query_xrq_in_bits { 4650 u8 opcode[0x10]; 4651 u8 reserved_at_10[0x10]; 4652 4653 u8 reserved_at_20[0x10]; 4654 u8 op_mod[0x10]; 4655 4656 u8 reserved_at_40[0x8]; 4657 u8 xrqn[0x18]; 4658 4659 u8 reserved_at_60[0x20]; 4660 }; 4661 4662 struct mlx5_ifc_query_xrc_srq_out_bits { 4663 u8 status[0x8]; 4664 u8 reserved_at_8[0x18]; 4665 4666 u8 syndrome[0x20]; 4667 4668 u8 reserved_at_40[0x40]; 4669 4670 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4671 4672 u8 reserved_at_280[0x600]; 4673 4674 u8 pas[][0x40]; 4675 }; 4676 4677 struct mlx5_ifc_query_xrc_srq_in_bits { 4678 u8 opcode[0x10]; 4679 u8 reserved_at_10[0x10]; 4680 4681 u8 reserved_at_20[0x10]; 4682 u8 op_mod[0x10]; 4683 4684 u8 reserved_at_40[0x8]; 4685 u8 xrc_srqn[0x18]; 4686 4687 u8 reserved_at_60[0x20]; 4688 }; 4689 4690 enum { 4691 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4692 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4693 }; 4694 4695 struct mlx5_ifc_query_vport_state_out_bits { 4696 u8 status[0x8]; 4697 u8 reserved_at_8[0x18]; 4698 4699 u8 syndrome[0x20]; 4700 4701 u8 reserved_at_40[0x20]; 4702 4703 u8 reserved_at_60[0x18]; 4704 u8 admin_state[0x4]; 4705 u8 state[0x4]; 4706 }; 4707 4708 enum { 4709 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4710 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4711 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4712 }; 4713 4714 struct mlx5_ifc_arm_monitor_counter_in_bits { 4715 u8 opcode[0x10]; 4716 u8 uid[0x10]; 4717 4718 u8 reserved_at_20[0x10]; 4719 u8 op_mod[0x10]; 4720 4721 u8 reserved_at_40[0x20]; 4722 4723 u8 reserved_at_60[0x20]; 4724 }; 4725 4726 struct mlx5_ifc_arm_monitor_counter_out_bits { 4727 u8 status[0x8]; 4728 u8 reserved_at_8[0x18]; 4729 4730 u8 syndrome[0x20]; 4731 4732 u8 reserved_at_40[0x40]; 4733 }; 4734 4735 enum { 4736 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4737 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4738 }; 4739 4740 enum mlx5_monitor_counter_ppcnt { 4741 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4742 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4743 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4744 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4745 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4746 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4747 }; 4748 4749 enum { 4750 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4751 }; 4752 4753 struct mlx5_ifc_monitor_counter_output_bits { 4754 u8 reserved_at_0[0x4]; 4755 u8 type[0x4]; 4756 u8 reserved_at_8[0x8]; 4757 u8 counter[0x10]; 4758 4759 u8 counter_group_id[0x20]; 4760 }; 4761 4762 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4763 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4764 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4765 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4766 4767 struct mlx5_ifc_set_monitor_counter_in_bits { 4768 u8 opcode[0x10]; 4769 u8 uid[0x10]; 4770 4771 u8 reserved_at_20[0x10]; 4772 u8 op_mod[0x10]; 4773 4774 u8 reserved_at_40[0x10]; 4775 u8 num_of_counters[0x10]; 4776 4777 u8 reserved_at_60[0x20]; 4778 4779 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4780 }; 4781 4782 struct mlx5_ifc_set_monitor_counter_out_bits { 4783 u8 status[0x8]; 4784 u8 reserved_at_8[0x18]; 4785 4786 u8 syndrome[0x20]; 4787 4788 u8 reserved_at_40[0x40]; 4789 }; 4790 4791 struct mlx5_ifc_query_vport_state_in_bits { 4792 u8 opcode[0x10]; 4793 u8 reserved_at_10[0x10]; 4794 4795 u8 reserved_at_20[0x10]; 4796 u8 op_mod[0x10]; 4797 4798 u8 other_vport[0x1]; 4799 u8 reserved_at_41[0xf]; 4800 u8 vport_number[0x10]; 4801 4802 u8 reserved_at_60[0x20]; 4803 }; 4804 4805 struct mlx5_ifc_query_vnic_env_out_bits { 4806 u8 status[0x8]; 4807 u8 reserved_at_8[0x18]; 4808 4809 u8 syndrome[0x20]; 4810 4811 u8 reserved_at_40[0x40]; 4812 4813 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4814 }; 4815 4816 enum { 4817 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4818 }; 4819 4820 struct mlx5_ifc_query_vnic_env_in_bits { 4821 u8 opcode[0x10]; 4822 u8 reserved_at_10[0x10]; 4823 4824 u8 reserved_at_20[0x10]; 4825 u8 op_mod[0x10]; 4826 4827 u8 other_vport[0x1]; 4828 u8 reserved_at_41[0xf]; 4829 u8 vport_number[0x10]; 4830 4831 u8 reserved_at_60[0x20]; 4832 }; 4833 4834 struct mlx5_ifc_query_vport_counter_out_bits { 4835 u8 status[0x8]; 4836 u8 reserved_at_8[0x18]; 4837 4838 u8 syndrome[0x20]; 4839 4840 u8 reserved_at_40[0x40]; 4841 4842 struct mlx5_ifc_traffic_counter_bits received_errors; 4843 4844 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4845 4846 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4847 4848 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4849 4850 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4851 4852 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4853 4854 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4855 4856 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4857 4858 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4859 4860 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4861 4862 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4863 4864 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4865 4866 u8 reserved_at_680[0xa00]; 4867 }; 4868 4869 enum { 4870 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4871 }; 4872 4873 struct mlx5_ifc_query_vport_counter_in_bits { 4874 u8 opcode[0x10]; 4875 u8 reserved_at_10[0x10]; 4876 4877 u8 reserved_at_20[0x10]; 4878 u8 op_mod[0x10]; 4879 4880 u8 other_vport[0x1]; 4881 u8 reserved_at_41[0xb]; 4882 u8 port_num[0x4]; 4883 u8 vport_number[0x10]; 4884 4885 u8 reserved_at_60[0x60]; 4886 4887 u8 clear[0x1]; 4888 u8 reserved_at_c1[0x1f]; 4889 4890 u8 reserved_at_e0[0x20]; 4891 }; 4892 4893 struct mlx5_ifc_query_tis_out_bits { 4894 u8 status[0x8]; 4895 u8 reserved_at_8[0x18]; 4896 4897 u8 syndrome[0x20]; 4898 4899 u8 reserved_at_40[0x40]; 4900 4901 struct mlx5_ifc_tisc_bits tis_context; 4902 }; 4903 4904 struct mlx5_ifc_query_tis_in_bits { 4905 u8 opcode[0x10]; 4906 u8 reserved_at_10[0x10]; 4907 4908 u8 reserved_at_20[0x10]; 4909 u8 op_mod[0x10]; 4910 4911 u8 reserved_at_40[0x8]; 4912 u8 tisn[0x18]; 4913 4914 u8 reserved_at_60[0x20]; 4915 }; 4916 4917 struct mlx5_ifc_query_tir_out_bits { 4918 u8 status[0x8]; 4919 u8 reserved_at_8[0x18]; 4920 4921 u8 syndrome[0x20]; 4922 4923 u8 reserved_at_40[0xc0]; 4924 4925 struct mlx5_ifc_tirc_bits tir_context; 4926 }; 4927 4928 struct mlx5_ifc_query_tir_in_bits { 4929 u8 opcode[0x10]; 4930 u8 reserved_at_10[0x10]; 4931 4932 u8 reserved_at_20[0x10]; 4933 u8 op_mod[0x10]; 4934 4935 u8 reserved_at_40[0x8]; 4936 u8 tirn[0x18]; 4937 4938 u8 reserved_at_60[0x20]; 4939 }; 4940 4941 struct mlx5_ifc_query_srq_out_bits { 4942 u8 status[0x8]; 4943 u8 reserved_at_8[0x18]; 4944 4945 u8 syndrome[0x20]; 4946 4947 u8 reserved_at_40[0x40]; 4948 4949 struct mlx5_ifc_srqc_bits srq_context_entry; 4950 4951 u8 reserved_at_280[0x600]; 4952 4953 u8 pas[][0x40]; 4954 }; 4955 4956 struct mlx5_ifc_query_srq_in_bits { 4957 u8 opcode[0x10]; 4958 u8 reserved_at_10[0x10]; 4959 4960 u8 reserved_at_20[0x10]; 4961 u8 op_mod[0x10]; 4962 4963 u8 reserved_at_40[0x8]; 4964 u8 srqn[0x18]; 4965 4966 u8 reserved_at_60[0x20]; 4967 }; 4968 4969 struct mlx5_ifc_query_sq_out_bits { 4970 u8 status[0x8]; 4971 u8 reserved_at_8[0x18]; 4972 4973 u8 syndrome[0x20]; 4974 4975 u8 reserved_at_40[0xc0]; 4976 4977 struct mlx5_ifc_sqc_bits sq_context; 4978 }; 4979 4980 struct mlx5_ifc_query_sq_in_bits { 4981 u8 opcode[0x10]; 4982 u8 reserved_at_10[0x10]; 4983 4984 u8 reserved_at_20[0x10]; 4985 u8 op_mod[0x10]; 4986 4987 u8 reserved_at_40[0x8]; 4988 u8 sqn[0x18]; 4989 4990 u8 reserved_at_60[0x20]; 4991 }; 4992 4993 struct mlx5_ifc_query_special_contexts_out_bits { 4994 u8 status[0x8]; 4995 u8 reserved_at_8[0x18]; 4996 4997 u8 syndrome[0x20]; 4998 4999 u8 dump_fill_mkey[0x20]; 5000 5001 u8 resd_lkey[0x20]; 5002 5003 u8 null_mkey[0x20]; 5004 5005 u8 reserved_at_a0[0x60]; 5006 }; 5007 5008 struct mlx5_ifc_query_special_contexts_in_bits { 5009 u8 opcode[0x10]; 5010 u8 reserved_at_10[0x10]; 5011 5012 u8 reserved_at_20[0x10]; 5013 u8 op_mod[0x10]; 5014 5015 u8 reserved_at_40[0x40]; 5016 }; 5017 5018 struct mlx5_ifc_query_scheduling_element_out_bits { 5019 u8 opcode[0x10]; 5020 u8 reserved_at_10[0x10]; 5021 5022 u8 reserved_at_20[0x10]; 5023 u8 op_mod[0x10]; 5024 5025 u8 reserved_at_40[0xc0]; 5026 5027 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5028 5029 u8 reserved_at_300[0x100]; 5030 }; 5031 5032 enum { 5033 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5034 SCHEDULING_HIERARCHY_NIC = 0x3, 5035 }; 5036 5037 struct mlx5_ifc_query_scheduling_element_in_bits { 5038 u8 opcode[0x10]; 5039 u8 reserved_at_10[0x10]; 5040 5041 u8 reserved_at_20[0x10]; 5042 u8 op_mod[0x10]; 5043 5044 u8 scheduling_hierarchy[0x8]; 5045 u8 reserved_at_48[0x18]; 5046 5047 u8 scheduling_element_id[0x20]; 5048 5049 u8 reserved_at_80[0x180]; 5050 }; 5051 5052 struct mlx5_ifc_query_rqt_out_bits { 5053 u8 status[0x8]; 5054 u8 reserved_at_8[0x18]; 5055 5056 u8 syndrome[0x20]; 5057 5058 u8 reserved_at_40[0xc0]; 5059 5060 struct mlx5_ifc_rqtc_bits rqt_context; 5061 }; 5062 5063 struct mlx5_ifc_query_rqt_in_bits { 5064 u8 opcode[0x10]; 5065 u8 reserved_at_10[0x10]; 5066 5067 u8 reserved_at_20[0x10]; 5068 u8 op_mod[0x10]; 5069 5070 u8 reserved_at_40[0x8]; 5071 u8 rqtn[0x18]; 5072 5073 u8 reserved_at_60[0x20]; 5074 }; 5075 5076 struct mlx5_ifc_query_rq_out_bits { 5077 u8 status[0x8]; 5078 u8 reserved_at_8[0x18]; 5079 5080 u8 syndrome[0x20]; 5081 5082 u8 reserved_at_40[0xc0]; 5083 5084 struct mlx5_ifc_rqc_bits rq_context; 5085 }; 5086 5087 struct mlx5_ifc_query_rq_in_bits { 5088 u8 opcode[0x10]; 5089 u8 reserved_at_10[0x10]; 5090 5091 u8 reserved_at_20[0x10]; 5092 u8 op_mod[0x10]; 5093 5094 u8 reserved_at_40[0x8]; 5095 u8 rqn[0x18]; 5096 5097 u8 reserved_at_60[0x20]; 5098 }; 5099 5100 struct mlx5_ifc_query_roce_address_out_bits { 5101 u8 status[0x8]; 5102 u8 reserved_at_8[0x18]; 5103 5104 u8 syndrome[0x20]; 5105 5106 u8 reserved_at_40[0x40]; 5107 5108 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5109 }; 5110 5111 struct mlx5_ifc_query_roce_address_in_bits { 5112 u8 opcode[0x10]; 5113 u8 reserved_at_10[0x10]; 5114 5115 u8 reserved_at_20[0x10]; 5116 u8 op_mod[0x10]; 5117 5118 u8 roce_address_index[0x10]; 5119 u8 reserved_at_50[0xc]; 5120 u8 vhca_port_num[0x4]; 5121 5122 u8 reserved_at_60[0x20]; 5123 }; 5124 5125 struct mlx5_ifc_query_rmp_out_bits { 5126 u8 status[0x8]; 5127 u8 reserved_at_8[0x18]; 5128 5129 u8 syndrome[0x20]; 5130 5131 u8 reserved_at_40[0xc0]; 5132 5133 struct mlx5_ifc_rmpc_bits rmp_context; 5134 }; 5135 5136 struct mlx5_ifc_query_rmp_in_bits { 5137 u8 opcode[0x10]; 5138 u8 reserved_at_10[0x10]; 5139 5140 u8 reserved_at_20[0x10]; 5141 u8 op_mod[0x10]; 5142 5143 u8 reserved_at_40[0x8]; 5144 u8 rmpn[0x18]; 5145 5146 u8 reserved_at_60[0x20]; 5147 }; 5148 5149 struct mlx5_ifc_query_qp_out_bits { 5150 u8 status[0x8]; 5151 u8 reserved_at_8[0x18]; 5152 5153 u8 syndrome[0x20]; 5154 5155 u8 reserved_at_40[0x20]; 5156 u8 ece[0x20]; 5157 5158 u8 opt_param_mask[0x20]; 5159 5160 u8 reserved_at_a0[0x20]; 5161 5162 struct mlx5_ifc_qpc_bits qpc; 5163 5164 u8 reserved_at_800[0x80]; 5165 5166 u8 pas[][0x40]; 5167 }; 5168 5169 struct mlx5_ifc_query_qp_in_bits { 5170 u8 opcode[0x10]; 5171 u8 reserved_at_10[0x10]; 5172 5173 u8 reserved_at_20[0x10]; 5174 u8 op_mod[0x10]; 5175 5176 u8 reserved_at_40[0x8]; 5177 u8 qpn[0x18]; 5178 5179 u8 reserved_at_60[0x20]; 5180 }; 5181 5182 struct mlx5_ifc_query_q_counter_out_bits { 5183 u8 status[0x8]; 5184 u8 reserved_at_8[0x18]; 5185 5186 u8 syndrome[0x20]; 5187 5188 u8 reserved_at_40[0x40]; 5189 5190 u8 rx_write_requests[0x20]; 5191 5192 u8 reserved_at_a0[0x20]; 5193 5194 u8 rx_read_requests[0x20]; 5195 5196 u8 reserved_at_e0[0x20]; 5197 5198 u8 rx_atomic_requests[0x20]; 5199 5200 u8 reserved_at_120[0x20]; 5201 5202 u8 rx_dct_connect[0x20]; 5203 5204 u8 reserved_at_160[0x20]; 5205 5206 u8 out_of_buffer[0x20]; 5207 5208 u8 reserved_at_1a0[0x20]; 5209 5210 u8 out_of_sequence[0x20]; 5211 5212 u8 reserved_at_1e0[0x20]; 5213 5214 u8 duplicate_request[0x20]; 5215 5216 u8 reserved_at_220[0x20]; 5217 5218 u8 rnr_nak_retry_err[0x20]; 5219 5220 u8 reserved_at_260[0x20]; 5221 5222 u8 packet_seq_err[0x20]; 5223 5224 u8 reserved_at_2a0[0x20]; 5225 5226 u8 implied_nak_seq_err[0x20]; 5227 5228 u8 reserved_at_2e0[0x20]; 5229 5230 u8 local_ack_timeout_err[0x20]; 5231 5232 u8 reserved_at_320[0xa0]; 5233 5234 u8 resp_local_length_error[0x20]; 5235 5236 u8 req_local_length_error[0x20]; 5237 5238 u8 resp_local_qp_error[0x20]; 5239 5240 u8 local_operation_error[0x20]; 5241 5242 u8 resp_local_protection[0x20]; 5243 5244 u8 req_local_protection[0x20]; 5245 5246 u8 resp_cqe_error[0x20]; 5247 5248 u8 req_cqe_error[0x20]; 5249 5250 u8 req_mw_binding[0x20]; 5251 5252 u8 req_bad_response[0x20]; 5253 5254 u8 req_remote_invalid_request[0x20]; 5255 5256 u8 resp_remote_invalid_request[0x20]; 5257 5258 u8 req_remote_access_errors[0x20]; 5259 5260 u8 resp_remote_access_errors[0x20]; 5261 5262 u8 req_remote_operation_errors[0x20]; 5263 5264 u8 req_transport_retries_exceeded[0x20]; 5265 5266 u8 cq_overflow[0x20]; 5267 5268 u8 resp_cqe_flush_error[0x20]; 5269 5270 u8 req_cqe_flush_error[0x20]; 5271 5272 u8 reserved_at_620[0x20]; 5273 5274 u8 roce_adp_retrans[0x20]; 5275 5276 u8 roce_adp_retrans_to[0x20]; 5277 5278 u8 roce_slow_restart[0x20]; 5279 5280 u8 roce_slow_restart_cnps[0x20]; 5281 5282 u8 roce_slow_restart_trans[0x20]; 5283 5284 u8 reserved_at_6e0[0x120]; 5285 }; 5286 5287 struct mlx5_ifc_query_q_counter_in_bits { 5288 u8 opcode[0x10]; 5289 u8 reserved_at_10[0x10]; 5290 5291 u8 reserved_at_20[0x10]; 5292 u8 op_mod[0x10]; 5293 5294 u8 reserved_at_40[0x80]; 5295 5296 u8 clear[0x1]; 5297 u8 reserved_at_c1[0x1f]; 5298 5299 u8 reserved_at_e0[0x18]; 5300 u8 counter_set_id[0x8]; 5301 }; 5302 5303 struct mlx5_ifc_query_pages_out_bits { 5304 u8 status[0x8]; 5305 u8 reserved_at_8[0x18]; 5306 5307 u8 syndrome[0x20]; 5308 5309 u8 embedded_cpu_function[0x1]; 5310 u8 reserved_at_41[0xf]; 5311 u8 function_id[0x10]; 5312 5313 u8 num_pages[0x20]; 5314 }; 5315 5316 enum { 5317 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5318 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5319 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5320 }; 5321 5322 struct mlx5_ifc_query_pages_in_bits { 5323 u8 opcode[0x10]; 5324 u8 reserved_at_10[0x10]; 5325 5326 u8 reserved_at_20[0x10]; 5327 u8 op_mod[0x10]; 5328 5329 u8 embedded_cpu_function[0x1]; 5330 u8 reserved_at_41[0xf]; 5331 u8 function_id[0x10]; 5332 5333 u8 reserved_at_60[0x20]; 5334 }; 5335 5336 struct mlx5_ifc_query_nic_vport_context_out_bits { 5337 u8 status[0x8]; 5338 u8 reserved_at_8[0x18]; 5339 5340 u8 syndrome[0x20]; 5341 5342 u8 reserved_at_40[0x40]; 5343 5344 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5345 }; 5346 5347 struct mlx5_ifc_query_nic_vport_context_in_bits { 5348 u8 opcode[0x10]; 5349 u8 reserved_at_10[0x10]; 5350 5351 u8 reserved_at_20[0x10]; 5352 u8 op_mod[0x10]; 5353 5354 u8 other_vport[0x1]; 5355 u8 reserved_at_41[0xf]; 5356 u8 vport_number[0x10]; 5357 5358 u8 reserved_at_60[0x5]; 5359 u8 allowed_list_type[0x3]; 5360 u8 reserved_at_68[0x18]; 5361 }; 5362 5363 struct mlx5_ifc_query_mkey_out_bits { 5364 u8 status[0x8]; 5365 u8 reserved_at_8[0x18]; 5366 5367 u8 syndrome[0x20]; 5368 5369 u8 reserved_at_40[0x40]; 5370 5371 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5372 5373 u8 reserved_at_280[0x600]; 5374 5375 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5376 5377 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5378 }; 5379 5380 struct mlx5_ifc_query_mkey_in_bits { 5381 u8 opcode[0x10]; 5382 u8 reserved_at_10[0x10]; 5383 5384 u8 reserved_at_20[0x10]; 5385 u8 op_mod[0x10]; 5386 5387 u8 reserved_at_40[0x8]; 5388 u8 mkey_index[0x18]; 5389 5390 u8 pg_access[0x1]; 5391 u8 reserved_at_61[0x1f]; 5392 }; 5393 5394 struct mlx5_ifc_query_mad_demux_out_bits { 5395 u8 status[0x8]; 5396 u8 reserved_at_8[0x18]; 5397 5398 u8 syndrome[0x20]; 5399 5400 u8 reserved_at_40[0x40]; 5401 5402 u8 mad_dumux_parameters_block[0x20]; 5403 }; 5404 5405 struct mlx5_ifc_query_mad_demux_in_bits { 5406 u8 opcode[0x10]; 5407 u8 reserved_at_10[0x10]; 5408 5409 u8 reserved_at_20[0x10]; 5410 u8 op_mod[0x10]; 5411 5412 u8 reserved_at_40[0x40]; 5413 }; 5414 5415 struct mlx5_ifc_query_l2_table_entry_out_bits { 5416 u8 status[0x8]; 5417 u8 reserved_at_8[0x18]; 5418 5419 u8 syndrome[0x20]; 5420 5421 u8 reserved_at_40[0xa0]; 5422 5423 u8 reserved_at_e0[0x13]; 5424 u8 vlan_valid[0x1]; 5425 u8 vlan[0xc]; 5426 5427 struct mlx5_ifc_mac_address_layout_bits mac_address; 5428 5429 u8 reserved_at_140[0xc0]; 5430 }; 5431 5432 struct mlx5_ifc_query_l2_table_entry_in_bits { 5433 u8 opcode[0x10]; 5434 u8 reserved_at_10[0x10]; 5435 5436 u8 reserved_at_20[0x10]; 5437 u8 op_mod[0x10]; 5438 5439 u8 reserved_at_40[0x60]; 5440 5441 u8 reserved_at_a0[0x8]; 5442 u8 table_index[0x18]; 5443 5444 u8 reserved_at_c0[0x140]; 5445 }; 5446 5447 struct mlx5_ifc_query_issi_out_bits { 5448 u8 status[0x8]; 5449 u8 reserved_at_8[0x18]; 5450 5451 u8 syndrome[0x20]; 5452 5453 u8 reserved_at_40[0x10]; 5454 u8 current_issi[0x10]; 5455 5456 u8 reserved_at_60[0xa0]; 5457 5458 u8 reserved_at_100[76][0x8]; 5459 u8 supported_issi_dw0[0x20]; 5460 }; 5461 5462 struct mlx5_ifc_query_issi_in_bits { 5463 u8 opcode[0x10]; 5464 u8 reserved_at_10[0x10]; 5465 5466 u8 reserved_at_20[0x10]; 5467 u8 op_mod[0x10]; 5468 5469 u8 reserved_at_40[0x40]; 5470 }; 5471 5472 struct mlx5_ifc_set_driver_version_out_bits { 5473 u8 status[0x8]; 5474 u8 reserved_0[0x18]; 5475 5476 u8 syndrome[0x20]; 5477 u8 reserved_1[0x40]; 5478 }; 5479 5480 struct mlx5_ifc_set_driver_version_in_bits { 5481 u8 opcode[0x10]; 5482 u8 reserved_0[0x10]; 5483 5484 u8 reserved_1[0x10]; 5485 u8 op_mod[0x10]; 5486 5487 u8 reserved_2[0x40]; 5488 u8 driver_version[64][0x8]; 5489 }; 5490 5491 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5492 u8 status[0x8]; 5493 u8 reserved_at_8[0x18]; 5494 5495 u8 syndrome[0x20]; 5496 5497 u8 reserved_at_40[0x40]; 5498 5499 struct mlx5_ifc_pkey_bits pkey[]; 5500 }; 5501 5502 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5503 u8 opcode[0x10]; 5504 u8 reserved_at_10[0x10]; 5505 5506 u8 reserved_at_20[0x10]; 5507 u8 op_mod[0x10]; 5508 5509 u8 other_vport[0x1]; 5510 u8 reserved_at_41[0xb]; 5511 u8 port_num[0x4]; 5512 u8 vport_number[0x10]; 5513 5514 u8 reserved_at_60[0x10]; 5515 u8 pkey_index[0x10]; 5516 }; 5517 5518 enum { 5519 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5520 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5521 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5522 }; 5523 5524 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5525 u8 status[0x8]; 5526 u8 reserved_at_8[0x18]; 5527 5528 u8 syndrome[0x20]; 5529 5530 u8 reserved_at_40[0x20]; 5531 5532 u8 gids_num[0x10]; 5533 u8 reserved_at_70[0x10]; 5534 5535 struct mlx5_ifc_array128_auto_bits gid[]; 5536 }; 5537 5538 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5539 u8 opcode[0x10]; 5540 u8 reserved_at_10[0x10]; 5541 5542 u8 reserved_at_20[0x10]; 5543 u8 op_mod[0x10]; 5544 5545 u8 other_vport[0x1]; 5546 u8 reserved_at_41[0xb]; 5547 u8 port_num[0x4]; 5548 u8 vport_number[0x10]; 5549 5550 u8 reserved_at_60[0x10]; 5551 u8 gid_index[0x10]; 5552 }; 5553 5554 struct mlx5_ifc_query_hca_vport_context_out_bits { 5555 u8 status[0x8]; 5556 u8 reserved_at_8[0x18]; 5557 5558 u8 syndrome[0x20]; 5559 5560 u8 reserved_at_40[0x40]; 5561 5562 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5563 }; 5564 5565 struct mlx5_ifc_query_hca_vport_context_in_bits { 5566 u8 opcode[0x10]; 5567 u8 reserved_at_10[0x10]; 5568 5569 u8 reserved_at_20[0x10]; 5570 u8 op_mod[0x10]; 5571 5572 u8 other_vport[0x1]; 5573 u8 reserved_at_41[0xb]; 5574 u8 port_num[0x4]; 5575 u8 vport_number[0x10]; 5576 5577 u8 reserved_at_60[0x20]; 5578 }; 5579 5580 struct mlx5_ifc_query_hca_cap_out_bits { 5581 u8 status[0x8]; 5582 u8 reserved_at_8[0x18]; 5583 5584 u8 syndrome[0x20]; 5585 5586 u8 reserved_at_40[0x40]; 5587 5588 union mlx5_ifc_hca_cap_union_bits capability; 5589 }; 5590 5591 struct mlx5_ifc_query_hca_cap_in_bits { 5592 u8 opcode[0x10]; 5593 u8 reserved_at_10[0x10]; 5594 5595 u8 reserved_at_20[0x10]; 5596 u8 op_mod[0x10]; 5597 5598 u8 other_function[0x1]; 5599 u8 reserved_at_41[0xf]; 5600 u8 function_id[0x10]; 5601 5602 u8 reserved_at_60[0x20]; 5603 }; 5604 5605 struct mlx5_ifc_other_hca_cap_bits { 5606 u8 roce[0x1]; 5607 u8 reserved_at_1[0x27f]; 5608 }; 5609 5610 struct mlx5_ifc_query_other_hca_cap_out_bits { 5611 u8 status[0x8]; 5612 u8 reserved_at_8[0x18]; 5613 5614 u8 syndrome[0x20]; 5615 5616 u8 reserved_at_40[0x40]; 5617 5618 struct mlx5_ifc_other_hca_cap_bits other_capability; 5619 }; 5620 5621 struct mlx5_ifc_query_other_hca_cap_in_bits { 5622 u8 opcode[0x10]; 5623 u8 reserved_at_10[0x10]; 5624 5625 u8 reserved_at_20[0x10]; 5626 u8 op_mod[0x10]; 5627 5628 u8 reserved_at_40[0x10]; 5629 u8 function_id[0x10]; 5630 5631 u8 reserved_at_60[0x20]; 5632 }; 5633 5634 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5635 u8 status[0x8]; 5636 u8 reserved_at_8[0x18]; 5637 5638 u8 syndrome[0x20]; 5639 5640 u8 reserved_at_40[0x40]; 5641 }; 5642 5643 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5644 u8 opcode[0x10]; 5645 u8 reserved_at_10[0x10]; 5646 5647 u8 reserved_at_20[0x10]; 5648 u8 op_mod[0x10]; 5649 5650 u8 reserved_at_40[0x10]; 5651 u8 function_id[0x10]; 5652 u8 field_select[0x20]; 5653 5654 struct mlx5_ifc_other_hca_cap_bits other_capability; 5655 }; 5656 5657 struct mlx5_ifc_flow_table_context_bits { 5658 u8 reformat_en[0x1]; 5659 u8 decap_en[0x1]; 5660 u8 sw_owner[0x1]; 5661 u8 termination_table[0x1]; 5662 u8 table_miss_action[0x4]; 5663 u8 level[0x8]; 5664 u8 reserved_at_10[0x8]; 5665 u8 log_size[0x8]; 5666 5667 u8 reserved_at_20[0x8]; 5668 u8 table_miss_id[0x18]; 5669 5670 u8 reserved_at_40[0x8]; 5671 u8 lag_master_next_table_id[0x18]; 5672 5673 u8 reserved_at_60[0x60]; 5674 5675 u8 sw_owner_icm_root_1[0x40]; 5676 5677 u8 sw_owner_icm_root_0[0x40]; 5678 5679 }; 5680 5681 struct mlx5_ifc_query_flow_table_out_bits { 5682 u8 status[0x8]; 5683 u8 reserved_at_8[0x18]; 5684 5685 u8 syndrome[0x20]; 5686 5687 u8 reserved_at_40[0x80]; 5688 5689 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5690 }; 5691 5692 struct mlx5_ifc_query_flow_table_in_bits { 5693 u8 opcode[0x10]; 5694 u8 reserved_at_10[0x10]; 5695 5696 u8 reserved_at_20[0x10]; 5697 u8 op_mod[0x10]; 5698 5699 u8 reserved_at_40[0x40]; 5700 5701 u8 table_type[0x8]; 5702 u8 reserved_at_88[0x18]; 5703 5704 u8 reserved_at_a0[0x8]; 5705 u8 table_id[0x18]; 5706 5707 u8 reserved_at_c0[0x140]; 5708 }; 5709 5710 struct mlx5_ifc_query_fte_out_bits { 5711 u8 status[0x8]; 5712 u8 reserved_at_8[0x18]; 5713 5714 u8 syndrome[0x20]; 5715 5716 u8 reserved_at_40[0x1c0]; 5717 5718 struct mlx5_ifc_flow_context_bits flow_context; 5719 }; 5720 5721 struct mlx5_ifc_query_fte_in_bits { 5722 u8 opcode[0x10]; 5723 u8 reserved_at_10[0x10]; 5724 5725 u8 reserved_at_20[0x10]; 5726 u8 op_mod[0x10]; 5727 5728 u8 reserved_at_40[0x40]; 5729 5730 u8 table_type[0x8]; 5731 u8 reserved_at_88[0x18]; 5732 5733 u8 reserved_at_a0[0x8]; 5734 u8 table_id[0x18]; 5735 5736 u8 reserved_at_c0[0x40]; 5737 5738 u8 flow_index[0x20]; 5739 5740 u8 reserved_at_120[0xe0]; 5741 }; 5742 5743 struct mlx5_ifc_match_definer_format_0_bits { 5744 u8 reserved_at_0[0x100]; 5745 5746 u8 metadata_reg_c_0[0x20]; 5747 5748 u8 metadata_reg_c_1[0x20]; 5749 5750 u8 outer_dmac_47_16[0x20]; 5751 5752 u8 outer_dmac_15_0[0x10]; 5753 u8 outer_ethertype[0x10]; 5754 5755 u8 reserved_at_180[0x1]; 5756 u8 sx_sniffer[0x1]; 5757 u8 functional_lb[0x1]; 5758 u8 outer_ip_frag[0x1]; 5759 u8 outer_qp_type[0x2]; 5760 u8 outer_encap_type[0x2]; 5761 u8 port_number[0x2]; 5762 u8 outer_l3_type[0x2]; 5763 u8 outer_l4_type[0x2]; 5764 u8 outer_first_vlan_type[0x2]; 5765 u8 outer_first_vlan_prio[0x3]; 5766 u8 outer_first_vlan_cfi[0x1]; 5767 u8 outer_first_vlan_vid[0xc]; 5768 5769 u8 outer_l4_type_ext[0x4]; 5770 u8 reserved_at_1a4[0x2]; 5771 u8 outer_ipsec_layer[0x2]; 5772 u8 outer_l2_type[0x2]; 5773 u8 force_lb[0x1]; 5774 u8 outer_l2_ok[0x1]; 5775 u8 outer_l3_ok[0x1]; 5776 u8 outer_l4_ok[0x1]; 5777 u8 outer_second_vlan_type[0x2]; 5778 u8 outer_second_vlan_prio[0x3]; 5779 u8 outer_second_vlan_cfi[0x1]; 5780 u8 outer_second_vlan_vid[0xc]; 5781 5782 u8 outer_smac_47_16[0x20]; 5783 5784 u8 outer_smac_15_0[0x10]; 5785 u8 inner_ipv4_checksum_ok[0x1]; 5786 u8 inner_l4_checksum_ok[0x1]; 5787 u8 outer_ipv4_checksum_ok[0x1]; 5788 u8 outer_l4_checksum_ok[0x1]; 5789 u8 inner_l3_ok[0x1]; 5790 u8 inner_l4_ok[0x1]; 5791 u8 outer_l3_ok_duplicate[0x1]; 5792 u8 outer_l4_ok_duplicate[0x1]; 5793 u8 outer_tcp_cwr[0x1]; 5794 u8 outer_tcp_ece[0x1]; 5795 u8 outer_tcp_urg[0x1]; 5796 u8 outer_tcp_ack[0x1]; 5797 u8 outer_tcp_psh[0x1]; 5798 u8 outer_tcp_rst[0x1]; 5799 u8 outer_tcp_syn[0x1]; 5800 u8 outer_tcp_fin[0x1]; 5801 }; 5802 5803 struct mlx5_ifc_match_definer_format_22_bits { 5804 u8 reserved_at_0[0x100]; 5805 5806 u8 outer_ip_src_addr[0x20]; 5807 5808 u8 outer_ip_dest_addr[0x20]; 5809 5810 u8 outer_l4_sport[0x10]; 5811 u8 outer_l4_dport[0x10]; 5812 5813 u8 reserved_at_160[0x1]; 5814 u8 sx_sniffer[0x1]; 5815 u8 functional_lb[0x1]; 5816 u8 outer_ip_frag[0x1]; 5817 u8 outer_qp_type[0x2]; 5818 u8 outer_encap_type[0x2]; 5819 u8 port_number[0x2]; 5820 u8 outer_l3_type[0x2]; 5821 u8 outer_l4_type[0x2]; 5822 u8 outer_first_vlan_type[0x2]; 5823 u8 outer_first_vlan_prio[0x3]; 5824 u8 outer_first_vlan_cfi[0x1]; 5825 u8 outer_first_vlan_vid[0xc]; 5826 5827 u8 metadata_reg_c_0[0x20]; 5828 5829 u8 outer_dmac_47_16[0x20]; 5830 5831 u8 outer_smac_47_16[0x20]; 5832 5833 u8 outer_smac_15_0[0x10]; 5834 u8 outer_dmac_15_0[0x10]; 5835 }; 5836 5837 struct mlx5_ifc_match_definer_format_23_bits { 5838 u8 reserved_at_0[0x100]; 5839 5840 u8 inner_ip_src_addr[0x20]; 5841 5842 u8 inner_ip_dest_addr[0x20]; 5843 5844 u8 inner_l4_sport[0x10]; 5845 u8 inner_l4_dport[0x10]; 5846 5847 u8 reserved_at_160[0x1]; 5848 u8 sx_sniffer[0x1]; 5849 u8 functional_lb[0x1]; 5850 u8 inner_ip_frag[0x1]; 5851 u8 inner_qp_type[0x2]; 5852 u8 inner_encap_type[0x2]; 5853 u8 port_number[0x2]; 5854 u8 inner_l3_type[0x2]; 5855 u8 inner_l4_type[0x2]; 5856 u8 inner_first_vlan_type[0x2]; 5857 u8 inner_first_vlan_prio[0x3]; 5858 u8 inner_first_vlan_cfi[0x1]; 5859 u8 inner_first_vlan_vid[0xc]; 5860 5861 u8 tunnel_header_0[0x20]; 5862 5863 u8 inner_dmac_47_16[0x20]; 5864 5865 u8 inner_smac_47_16[0x20]; 5866 5867 u8 inner_smac_15_0[0x10]; 5868 u8 inner_dmac_15_0[0x10]; 5869 }; 5870 5871 struct mlx5_ifc_match_definer_format_29_bits { 5872 u8 reserved_at_0[0xc0]; 5873 5874 u8 outer_ip_dest_addr[0x80]; 5875 5876 u8 outer_ip_src_addr[0x80]; 5877 5878 u8 outer_l4_sport[0x10]; 5879 u8 outer_l4_dport[0x10]; 5880 5881 u8 reserved_at_1e0[0x20]; 5882 }; 5883 5884 struct mlx5_ifc_match_definer_format_30_bits { 5885 u8 reserved_at_0[0xa0]; 5886 5887 u8 outer_ip_dest_addr[0x80]; 5888 5889 u8 outer_ip_src_addr[0x80]; 5890 5891 u8 outer_dmac_47_16[0x20]; 5892 5893 u8 outer_smac_47_16[0x20]; 5894 5895 u8 outer_smac_15_0[0x10]; 5896 u8 outer_dmac_15_0[0x10]; 5897 }; 5898 5899 struct mlx5_ifc_match_definer_format_31_bits { 5900 u8 reserved_at_0[0xc0]; 5901 5902 u8 inner_ip_dest_addr[0x80]; 5903 5904 u8 inner_ip_src_addr[0x80]; 5905 5906 u8 inner_l4_sport[0x10]; 5907 u8 inner_l4_dport[0x10]; 5908 5909 u8 reserved_at_1e0[0x20]; 5910 }; 5911 5912 struct mlx5_ifc_match_definer_format_32_bits { 5913 u8 reserved_at_0[0xa0]; 5914 5915 u8 inner_ip_dest_addr[0x80]; 5916 5917 u8 inner_ip_src_addr[0x80]; 5918 5919 u8 inner_dmac_47_16[0x20]; 5920 5921 u8 inner_smac_47_16[0x20]; 5922 5923 u8 inner_smac_15_0[0x10]; 5924 u8 inner_dmac_15_0[0x10]; 5925 }; 5926 5927 struct mlx5_ifc_match_definer_bits { 5928 u8 modify_field_select[0x40]; 5929 5930 u8 reserved_at_40[0x40]; 5931 5932 u8 reserved_at_80[0x10]; 5933 u8 format_id[0x10]; 5934 5935 u8 reserved_at_a0[0x160]; 5936 5937 u8 match_mask[16][0x20]; 5938 }; 5939 5940 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 5941 u8 opcode[0x10]; 5942 u8 uid[0x10]; 5943 5944 u8 vhca_tunnel_id[0x10]; 5945 u8 obj_type[0x10]; 5946 5947 u8 obj_id[0x20]; 5948 5949 u8 reserved_at_60[0x20]; 5950 }; 5951 5952 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 5953 u8 status[0x8]; 5954 u8 reserved_at_8[0x18]; 5955 5956 u8 syndrome[0x20]; 5957 5958 u8 obj_id[0x20]; 5959 5960 u8 reserved_at_60[0x20]; 5961 }; 5962 5963 struct mlx5_ifc_create_match_definer_in_bits { 5964 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 5965 5966 struct mlx5_ifc_match_definer_bits obj_context; 5967 }; 5968 5969 struct mlx5_ifc_create_match_definer_out_bits { 5970 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 5971 }; 5972 5973 enum { 5974 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5975 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5976 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5977 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5978 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5979 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 5980 }; 5981 5982 struct mlx5_ifc_query_flow_group_out_bits { 5983 u8 status[0x8]; 5984 u8 reserved_at_8[0x18]; 5985 5986 u8 syndrome[0x20]; 5987 5988 u8 reserved_at_40[0xa0]; 5989 5990 u8 start_flow_index[0x20]; 5991 5992 u8 reserved_at_100[0x20]; 5993 5994 u8 end_flow_index[0x20]; 5995 5996 u8 reserved_at_140[0xa0]; 5997 5998 u8 reserved_at_1e0[0x18]; 5999 u8 match_criteria_enable[0x8]; 6000 6001 struct mlx5_ifc_fte_match_param_bits match_criteria; 6002 6003 u8 reserved_at_1200[0xe00]; 6004 }; 6005 6006 struct mlx5_ifc_query_flow_group_in_bits { 6007 u8 opcode[0x10]; 6008 u8 reserved_at_10[0x10]; 6009 6010 u8 reserved_at_20[0x10]; 6011 u8 op_mod[0x10]; 6012 6013 u8 reserved_at_40[0x40]; 6014 6015 u8 table_type[0x8]; 6016 u8 reserved_at_88[0x18]; 6017 6018 u8 reserved_at_a0[0x8]; 6019 u8 table_id[0x18]; 6020 6021 u8 group_id[0x20]; 6022 6023 u8 reserved_at_e0[0x120]; 6024 }; 6025 6026 struct mlx5_ifc_query_flow_counter_out_bits { 6027 u8 status[0x8]; 6028 u8 reserved_at_8[0x18]; 6029 6030 u8 syndrome[0x20]; 6031 6032 u8 reserved_at_40[0x40]; 6033 6034 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6035 }; 6036 6037 struct mlx5_ifc_query_flow_counter_in_bits { 6038 u8 opcode[0x10]; 6039 u8 reserved_at_10[0x10]; 6040 6041 u8 reserved_at_20[0x10]; 6042 u8 op_mod[0x10]; 6043 6044 u8 reserved_at_40[0x80]; 6045 6046 u8 clear[0x1]; 6047 u8 reserved_at_c1[0xf]; 6048 u8 num_of_counters[0x10]; 6049 6050 u8 flow_counter_id[0x20]; 6051 }; 6052 6053 struct mlx5_ifc_query_esw_vport_context_out_bits { 6054 u8 status[0x8]; 6055 u8 reserved_at_8[0x18]; 6056 6057 u8 syndrome[0x20]; 6058 6059 u8 reserved_at_40[0x40]; 6060 6061 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6062 }; 6063 6064 struct mlx5_ifc_query_esw_vport_context_in_bits { 6065 u8 opcode[0x10]; 6066 u8 reserved_at_10[0x10]; 6067 6068 u8 reserved_at_20[0x10]; 6069 u8 op_mod[0x10]; 6070 6071 u8 other_vport[0x1]; 6072 u8 reserved_at_41[0xf]; 6073 u8 vport_number[0x10]; 6074 6075 u8 reserved_at_60[0x20]; 6076 }; 6077 6078 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6079 u8 status[0x8]; 6080 u8 reserved_at_8[0x18]; 6081 6082 u8 syndrome[0x20]; 6083 6084 u8 reserved_at_40[0x40]; 6085 }; 6086 6087 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6088 u8 reserved_at_0[0x1b]; 6089 u8 fdb_to_vport_reg_c_id[0x1]; 6090 u8 vport_cvlan_insert[0x1]; 6091 u8 vport_svlan_insert[0x1]; 6092 u8 vport_cvlan_strip[0x1]; 6093 u8 vport_svlan_strip[0x1]; 6094 }; 6095 6096 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6097 u8 opcode[0x10]; 6098 u8 reserved_at_10[0x10]; 6099 6100 u8 reserved_at_20[0x10]; 6101 u8 op_mod[0x10]; 6102 6103 u8 other_vport[0x1]; 6104 u8 reserved_at_41[0xf]; 6105 u8 vport_number[0x10]; 6106 6107 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6108 6109 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6110 }; 6111 6112 struct mlx5_ifc_query_eq_out_bits { 6113 u8 status[0x8]; 6114 u8 reserved_at_8[0x18]; 6115 6116 u8 syndrome[0x20]; 6117 6118 u8 reserved_at_40[0x40]; 6119 6120 struct mlx5_ifc_eqc_bits eq_context_entry; 6121 6122 u8 reserved_at_280[0x40]; 6123 6124 u8 event_bitmask[0x40]; 6125 6126 u8 reserved_at_300[0x580]; 6127 6128 u8 pas[][0x40]; 6129 }; 6130 6131 struct mlx5_ifc_query_eq_in_bits { 6132 u8 opcode[0x10]; 6133 u8 reserved_at_10[0x10]; 6134 6135 u8 reserved_at_20[0x10]; 6136 u8 op_mod[0x10]; 6137 6138 u8 reserved_at_40[0x18]; 6139 u8 eq_number[0x8]; 6140 6141 u8 reserved_at_60[0x20]; 6142 }; 6143 6144 struct mlx5_ifc_packet_reformat_context_in_bits { 6145 u8 reformat_type[0x8]; 6146 u8 reserved_at_8[0x4]; 6147 u8 reformat_param_0[0x4]; 6148 u8 reserved_at_10[0x6]; 6149 u8 reformat_data_size[0xa]; 6150 6151 u8 reformat_param_1[0x8]; 6152 u8 reserved_at_28[0x8]; 6153 u8 reformat_data[2][0x8]; 6154 6155 u8 more_reformat_data[][0x8]; 6156 }; 6157 6158 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6159 u8 status[0x8]; 6160 u8 reserved_at_8[0x18]; 6161 6162 u8 syndrome[0x20]; 6163 6164 u8 reserved_at_40[0xa0]; 6165 6166 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6167 }; 6168 6169 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6170 u8 opcode[0x10]; 6171 u8 reserved_at_10[0x10]; 6172 6173 u8 reserved_at_20[0x10]; 6174 u8 op_mod[0x10]; 6175 6176 u8 packet_reformat_id[0x20]; 6177 6178 u8 reserved_at_60[0xa0]; 6179 }; 6180 6181 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6182 u8 status[0x8]; 6183 u8 reserved_at_8[0x18]; 6184 6185 u8 syndrome[0x20]; 6186 6187 u8 packet_reformat_id[0x20]; 6188 6189 u8 reserved_at_60[0x20]; 6190 }; 6191 6192 enum { 6193 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6194 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6195 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6196 }; 6197 6198 enum mlx5_reformat_ctx_type { 6199 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6200 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6201 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6202 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6203 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6204 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6205 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6206 }; 6207 6208 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6209 u8 opcode[0x10]; 6210 u8 reserved_at_10[0x10]; 6211 6212 u8 reserved_at_20[0x10]; 6213 u8 op_mod[0x10]; 6214 6215 u8 reserved_at_40[0xa0]; 6216 6217 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6218 }; 6219 6220 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6221 u8 status[0x8]; 6222 u8 reserved_at_8[0x18]; 6223 6224 u8 syndrome[0x20]; 6225 6226 u8 reserved_at_40[0x40]; 6227 }; 6228 6229 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6230 u8 opcode[0x10]; 6231 u8 reserved_at_10[0x10]; 6232 6233 u8 reserved_20[0x10]; 6234 u8 op_mod[0x10]; 6235 6236 u8 packet_reformat_id[0x20]; 6237 6238 u8 reserved_60[0x20]; 6239 }; 6240 6241 struct mlx5_ifc_set_action_in_bits { 6242 u8 action_type[0x4]; 6243 u8 field[0xc]; 6244 u8 reserved_at_10[0x3]; 6245 u8 offset[0x5]; 6246 u8 reserved_at_18[0x3]; 6247 u8 length[0x5]; 6248 6249 u8 data[0x20]; 6250 }; 6251 6252 struct mlx5_ifc_add_action_in_bits { 6253 u8 action_type[0x4]; 6254 u8 field[0xc]; 6255 u8 reserved_at_10[0x10]; 6256 6257 u8 data[0x20]; 6258 }; 6259 6260 struct mlx5_ifc_copy_action_in_bits { 6261 u8 action_type[0x4]; 6262 u8 src_field[0xc]; 6263 u8 reserved_at_10[0x3]; 6264 u8 src_offset[0x5]; 6265 u8 reserved_at_18[0x3]; 6266 u8 length[0x5]; 6267 6268 u8 reserved_at_20[0x4]; 6269 u8 dst_field[0xc]; 6270 u8 reserved_at_30[0x3]; 6271 u8 dst_offset[0x5]; 6272 u8 reserved_at_38[0x8]; 6273 }; 6274 6275 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6276 struct mlx5_ifc_set_action_in_bits set_action_in; 6277 struct mlx5_ifc_add_action_in_bits add_action_in; 6278 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6279 u8 reserved_at_0[0x40]; 6280 }; 6281 6282 enum { 6283 MLX5_ACTION_TYPE_SET = 0x1, 6284 MLX5_ACTION_TYPE_ADD = 0x2, 6285 MLX5_ACTION_TYPE_COPY = 0x3, 6286 }; 6287 6288 enum { 6289 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6290 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6291 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6292 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6293 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6294 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6295 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6296 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6297 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6298 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6299 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6300 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6301 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6302 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6303 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6304 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6305 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6306 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6307 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6308 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6309 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6310 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6311 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6312 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6313 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6314 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6315 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6316 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6317 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6318 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6319 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6320 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6321 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6322 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6323 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6324 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6325 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6326 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6327 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6328 }; 6329 6330 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6331 u8 status[0x8]; 6332 u8 reserved_at_8[0x18]; 6333 6334 u8 syndrome[0x20]; 6335 6336 u8 modify_header_id[0x20]; 6337 6338 u8 reserved_at_60[0x20]; 6339 }; 6340 6341 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6342 u8 opcode[0x10]; 6343 u8 reserved_at_10[0x10]; 6344 6345 u8 reserved_at_20[0x10]; 6346 u8 op_mod[0x10]; 6347 6348 u8 reserved_at_40[0x20]; 6349 6350 u8 table_type[0x8]; 6351 u8 reserved_at_68[0x10]; 6352 u8 num_of_actions[0x8]; 6353 6354 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6355 }; 6356 6357 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6358 u8 status[0x8]; 6359 u8 reserved_at_8[0x18]; 6360 6361 u8 syndrome[0x20]; 6362 6363 u8 reserved_at_40[0x40]; 6364 }; 6365 6366 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6367 u8 opcode[0x10]; 6368 u8 reserved_at_10[0x10]; 6369 6370 u8 reserved_at_20[0x10]; 6371 u8 op_mod[0x10]; 6372 6373 u8 modify_header_id[0x20]; 6374 6375 u8 reserved_at_60[0x20]; 6376 }; 6377 6378 struct mlx5_ifc_query_modify_header_context_in_bits { 6379 u8 opcode[0x10]; 6380 u8 uid[0x10]; 6381 6382 u8 reserved_at_20[0x10]; 6383 u8 op_mod[0x10]; 6384 6385 u8 modify_header_id[0x20]; 6386 6387 u8 reserved_at_60[0xa0]; 6388 }; 6389 6390 struct mlx5_ifc_query_dct_out_bits { 6391 u8 status[0x8]; 6392 u8 reserved_at_8[0x18]; 6393 6394 u8 syndrome[0x20]; 6395 6396 u8 reserved_at_40[0x40]; 6397 6398 struct mlx5_ifc_dctc_bits dct_context_entry; 6399 6400 u8 reserved_at_280[0x180]; 6401 }; 6402 6403 struct mlx5_ifc_query_dct_in_bits { 6404 u8 opcode[0x10]; 6405 u8 reserved_at_10[0x10]; 6406 6407 u8 reserved_at_20[0x10]; 6408 u8 op_mod[0x10]; 6409 6410 u8 reserved_at_40[0x8]; 6411 u8 dctn[0x18]; 6412 6413 u8 reserved_at_60[0x20]; 6414 }; 6415 6416 struct mlx5_ifc_query_cq_out_bits { 6417 u8 status[0x8]; 6418 u8 reserved_at_8[0x18]; 6419 6420 u8 syndrome[0x20]; 6421 6422 u8 reserved_at_40[0x40]; 6423 6424 struct mlx5_ifc_cqc_bits cq_context; 6425 6426 u8 reserved_at_280[0x600]; 6427 6428 u8 pas[][0x40]; 6429 }; 6430 6431 struct mlx5_ifc_query_cq_in_bits { 6432 u8 opcode[0x10]; 6433 u8 reserved_at_10[0x10]; 6434 6435 u8 reserved_at_20[0x10]; 6436 u8 op_mod[0x10]; 6437 6438 u8 reserved_at_40[0x8]; 6439 u8 cqn[0x18]; 6440 6441 u8 reserved_at_60[0x20]; 6442 }; 6443 6444 struct mlx5_ifc_query_cong_status_out_bits { 6445 u8 status[0x8]; 6446 u8 reserved_at_8[0x18]; 6447 6448 u8 syndrome[0x20]; 6449 6450 u8 reserved_at_40[0x20]; 6451 6452 u8 enable[0x1]; 6453 u8 tag_enable[0x1]; 6454 u8 reserved_at_62[0x1e]; 6455 }; 6456 6457 struct mlx5_ifc_query_cong_status_in_bits { 6458 u8 opcode[0x10]; 6459 u8 reserved_at_10[0x10]; 6460 6461 u8 reserved_at_20[0x10]; 6462 u8 op_mod[0x10]; 6463 6464 u8 reserved_at_40[0x18]; 6465 u8 priority[0x4]; 6466 u8 cong_protocol[0x4]; 6467 6468 u8 reserved_at_60[0x20]; 6469 }; 6470 6471 struct mlx5_ifc_query_cong_statistics_out_bits { 6472 u8 status[0x8]; 6473 u8 reserved_at_8[0x18]; 6474 6475 u8 syndrome[0x20]; 6476 6477 u8 reserved_at_40[0x40]; 6478 6479 u8 rp_cur_flows[0x20]; 6480 6481 u8 sum_flows[0x20]; 6482 6483 u8 rp_cnp_ignored_high[0x20]; 6484 6485 u8 rp_cnp_ignored_low[0x20]; 6486 6487 u8 rp_cnp_handled_high[0x20]; 6488 6489 u8 rp_cnp_handled_low[0x20]; 6490 6491 u8 reserved_at_140[0x100]; 6492 6493 u8 time_stamp_high[0x20]; 6494 6495 u8 time_stamp_low[0x20]; 6496 6497 u8 accumulators_period[0x20]; 6498 6499 u8 np_ecn_marked_roce_packets_high[0x20]; 6500 6501 u8 np_ecn_marked_roce_packets_low[0x20]; 6502 6503 u8 np_cnp_sent_high[0x20]; 6504 6505 u8 np_cnp_sent_low[0x20]; 6506 6507 u8 reserved_at_320[0x560]; 6508 }; 6509 6510 struct mlx5_ifc_query_cong_statistics_in_bits { 6511 u8 opcode[0x10]; 6512 u8 reserved_at_10[0x10]; 6513 6514 u8 reserved_at_20[0x10]; 6515 u8 op_mod[0x10]; 6516 6517 u8 clear[0x1]; 6518 u8 reserved_at_41[0x1f]; 6519 6520 u8 reserved_at_60[0x20]; 6521 }; 6522 6523 struct mlx5_ifc_query_cong_params_out_bits { 6524 u8 status[0x8]; 6525 u8 reserved_at_8[0x18]; 6526 6527 u8 syndrome[0x20]; 6528 6529 u8 reserved_at_40[0x40]; 6530 6531 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6532 }; 6533 6534 struct mlx5_ifc_query_cong_params_in_bits { 6535 u8 opcode[0x10]; 6536 u8 reserved_at_10[0x10]; 6537 6538 u8 reserved_at_20[0x10]; 6539 u8 op_mod[0x10]; 6540 6541 u8 reserved_at_40[0x1c]; 6542 u8 cong_protocol[0x4]; 6543 6544 u8 reserved_at_60[0x20]; 6545 }; 6546 6547 struct mlx5_ifc_query_adapter_out_bits { 6548 u8 status[0x8]; 6549 u8 reserved_at_8[0x18]; 6550 6551 u8 syndrome[0x20]; 6552 6553 u8 reserved_at_40[0x40]; 6554 6555 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6556 }; 6557 6558 struct mlx5_ifc_query_adapter_in_bits { 6559 u8 opcode[0x10]; 6560 u8 reserved_at_10[0x10]; 6561 6562 u8 reserved_at_20[0x10]; 6563 u8 op_mod[0x10]; 6564 6565 u8 reserved_at_40[0x40]; 6566 }; 6567 6568 struct mlx5_ifc_qp_2rst_out_bits { 6569 u8 status[0x8]; 6570 u8 reserved_at_8[0x18]; 6571 6572 u8 syndrome[0x20]; 6573 6574 u8 reserved_at_40[0x40]; 6575 }; 6576 6577 struct mlx5_ifc_qp_2rst_in_bits { 6578 u8 opcode[0x10]; 6579 u8 uid[0x10]; 6580 6581 u8 reserved_at_20[0x10]; 6582 u8 op_mod[0x10]; 6583 6584 u8 reserved_at_40[0x8]; 6585 u8 qpn[0x18]; 6586 6587 u8 reserved_at_60[0x20]; 6588 }; 6589 6590 struct mlx5_ifc_qp_2err_out_bits { 6591 u8 status[0x8]; 6592 u8 reserved_at_8[0x18]; 6593 6594 u8 syndrome[0x20]; 6595 6596 u8 reserved_at_40[0x40]; 6597 }; 6598 6599 struct mlx5_ifc_qp_2err_in_bits { 6600 u8 opcode[0x10]; 6601 u8 uid[0x10]; 6602 6603 u8 reserved_at_20[0x10]; 6604 u8 op_mod[0x10]; 6605 6606 u8 reserved_at_40[0x8]; 6607 u8 qpn[0x18]; 6608 6609 u8 reserved_at_60[0x20]; 6610 }; 6611 6612 struct mlx5_ifc_page_fault_resume_out_bits { 6613 u8 status[0x8]; 6614 u8 reserved_at_8[0x18]; 6615 6616 u8 syndrome[0x20]; 6617 6618 u8 reserved_at_40[0x40]; 6619 }; 6620 6621 struct mlx5_ifc_page_fault_resume_in_bits { 6622 u8 opcode[0x10]; 6623 u8 reserved_at_10[0x10]; 6624 6625 u8 reserved_at_20[0x10]; 6626 u8 op_mod[0x10]; 6627 6628 u8 error[0x1]; 6629 u8 reserved_at_41[0x4]; 6630 u8 page_fault_type[0x3]; 6631 u8 wq_number[0x18]; 6632 6633 u8 reserved_at_60[0x8]; 6634 u8 token[0x18]; 6635 }; 6636 6637 struct mlx5_ifc_nop_out_bits { 6638 u8 status[0x8]; 6639 u8 reserved_at_8[0x18]; 6640 6641 u8 syndrome[0x20]; 6642 6643 u8 reserved_at_40[0x40]; 6644 }; 6645 6646 struct mlx5_ifc_nop_in_bits { 6647 u8 opcode[0x10]; 6648 u8 reserved_at_10[0x10]; 6649 6650 u8 reserved_at_20[0x10]; 6651 u8 op_mod[0x10]; 6652 6653 u8 reserved_at_40[0x40]; 6654 }; 6655 6656 struct mlx5_ifc_modify_vport_state_out_bits { 6657 u8 status[0x8]; 6658 u8 reserved_at_8[0x18]; 6659 6660 u8 syndrome[0x20]; 6661 6662 u8 reserved_at_40[0x40]; 6663 }; 6664 6665 struct mlx5_ifc_modify_vport_state_in_bits { 6666 u8 opcode[0x10]; 6667 u8 reserved_at_10[0x10]; 6668 6669 u8 reserved_at_20[0x10]; 6670 u8 op_mod[0x10]; 6671 6672 u8 other_vport[0x1]; 6673 u8 reserved_at_41[0xf]; 6674 u8 vport_number[0x10]; 6675 6676 u8 reserved_at_60[0x18]; 6677 u8 admin_state[0x4]; 6678 u8 reserved_at_7c[0x4]; 6679 }; 6680 6681 struct mlx5_ifc_modify_tis_out_bits { 6682 u8 status[0x8]; 6683 u8 reserved_at_8[0x18]; 6684 6685 u8 syndrome[0x20]; 6686 6687 u8 reserved_at_40[0x40]; 6688 }; 6689 6690 struct mlx5_ifc_modify_tis_bitmask_bits { 6691 u8 reserved_at_0[0x20]; 6692 6693 u8 reserved_at_20[0x1d]; 6694 u8 lag_tx_port_affinity[0x1]; 6695 u8 strict_lag_tx_port_affinity[0x1]; 6696 u8 prio[0x1]; 6697 }; 6698 6699 struct mlx5_ifc_modify_tis_in_bits { 6700 u8 opcode[0x10]; 6701 u8 uid[0x10]; 6702 6703 u8 reserved_at_20[0x10]; 6704 u8 op_mod[0x10]; 6705 6706 u8 reserved_at_40[0x8]; 6707 u8 tisn[0x18]; 6708 6709 u8 reserved_at_60[0x20]; 6710 6711 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6712 6713 u8 reserved_at_c0[0x40]; 6714 6715 struct mlx5_ifc_tisc_bits ctx; 6716 }; 6717 6718 struct mlx5_ifc_modify_tir_bitmask_bits { 6719 u8 reserved_at_0[0x20]; 6720 6721 u8 reserved_at_20[0x1b]; 6722 u8 self_lb_en[0x1]; 6723 u8 reserved_at_3c[0x1]; 6724 u8 hash[0x1]; 6725 u8 reserved_at_3e[0x1]; 6726 u8 packet_merge[0x1]; 6727 }; 6728 6729 struct mlx5_ifc_modify_tir_out_bits { 6730 u8 status[0x8]; 6731 u8 reserved_at_8[0x18]; 6732 6733 u8 syndrome[0x20]; 6734 6735 u8 reserved_at_40[0x40]; 6736 }; 6737 6738 struct mlx5_ifc_modify_tir_in_bits { 6739 u8 opcode[0x10]; 6740 u8 uid[0x10]; 6741 6742 u8 reserved_at_20[0x10]; 6743 u8 op_mod[0x10]; 6744 6745 u8 reserved_at_40[0x8]; 6746 u8 tirn[0x18]; 6747 6748 u8 reserved_at_60[0x20]; 6749 6750 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6751 6752 u8 reserved_at_c0[0x40]; 6753 6754 struct mlx5_ifc_tirc_bits ctx; 6755 }; 6756 6757 struct mlx5_ifc_modify_sq_out_bits { 6758 u8 status[0x8]; 6759 u8 reserved_at_8[0x18]; 6760 6761 u8 syndrome[0x20]; 6762 6763 u8 reserved_at_40[0x40]; 6764 }; 6765 6766 struct mlx5_ifc_modify_sq_in_bits { 6767 u8 opcode[0x10]; 6768 u8 uid[0x10]; 6769 6770 u8 reserved_at_20[0x10]; 6771 u8 op_mod[0x10]; 6772 6773 u8 sq_state[0x4]; 6774 u8 reserved_at_44[0x4]; 6775 u8 sqn[0x18]; 6776 6777 u8 reserved_at_60[0x20]; 6778 6779 u8 modify_bitmask[0x40]; 6780 6781 u8 reserved_at_c0[0x40]; 6782 6783 struct mlx5_ifc_sqc_bits ctx; 6784 }; 6785 6786 struct mlx5_ifc_modify_scheduling_element_out_bits { 6787 u8 status[0x8]; 6788 u8 reserved_at_8[0x18]; 6789 6790 u8 syndrome[0x20]; 6791 6792 u8 reserved_at_40[0x1c0]; 6793 }; 6794 6795 enum { 6796 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6797 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6798 }; 6799 6800 struct mlx5_ifc_modify_scheduling_element_in_bits { 6801 u8 opcode[0x10]; 6802 u8 reserved_at_10[0x10]; 6803 6804 u8 reserved_at_20[0x10]; 6805 u8 op_mod[0x10]; 6806 6807 u8 scheduling_hierarchy[0x8]; 6808 u8 reserved_at_48[0x18]; 6809 6810 u8 scheduling_element_id[0x20]; 6811 6812 u8 reserved_at_80[0x20]; 6813 6814 u8 modify_bitmask[0x20]; 6815 6816 u8 reserved_at_c0[0x40]; 6817 6818 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6819 6820 u8 reserved_at_300[0x100]; 6821 }; 6822 6823 struct mlx5_ifc_modify_rqt_out_bits { 6824 u8 status[0x8]; 6825 u8 reserved_at_8[0x18]; 6826 6827 u8 syndrome[0x20]; 6828 6829 u8 reserved_at_40[0x40]; 6830 }; 6831 6832 struct mlx5_ifc_rqt_bitmask_bits { 6833 u8 reserved_at_0[0x20]; 6834 6835 u8 reserved_at_20[0x1f]; 6836 u8 rqn_list[0x1]; 6837 }; 6838 6839 struct mlx5_ifc_modify_rqt_in_bits { 6840 u8 opcode[0x10]; 6841 u8 uid[0x10]; 6842 6843 u8 reserved_at_20[0x10]; 6844 u8 op_mod[0x10]; 6845 6846 u8 reserved_at_40[0x8]; 6847 u8 rqtn[0x18]; 6848 6849 u8 reserved_at_60[0x20]; 6850 6851 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6852 6853 u8 reserved_at_c0[0x40]; 6854 6855 struct mlx5_ifc_rqtc_bits ctx; 6856 }; 6857 6858 struct mlx5_ifc_modify_rq_out_bits { 6859 u8 status[0x8]; 6860 u8 reserved_at_8[0x18]; 6861 6862 u8 syndrome[0x20]; 6863 6864 u8 reserved_at_40[0x40]; 6865 }; 6866 6867 enum { 6868 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6869 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6870 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6871 }; 6872 6873 struct mlx5_ifc_modify_rq_in_bits { 6874 u8 opcode[0x10]; 6875 u8 uid[0x10]; 6876 6877 u8 reserved_at_20[0x10]; 6878 u8 op_mod[0x10]; 6879 6880 u8 rq_state[0x4]; 6881 u8 reserved_at_44[0x4]; 6882 u8 rqn[0x18]; 6883 6884 u8 reserved_at_60[0x20]; 6885 6886 u8 modify_bitmask[0x40]; 6887 6888 u8 reserved_at_c0[0x40]; 6889 6890 struct mlx5_ifc_rqc_bits ctx; 6891 }; 6892 6893 struct mlx5_ifc_modify_rmp_out_bits { 6894 u8 status[0x8]; 6895 u8 reserved_at_8[0x18]; 6896 6897 u8 syndrome[0x20]; 6898 6899 u8 reserved_at_40[0x40]; 6900 }; 6901 6902 struct mlx5_ifc_rmp_bitmask_bits { 6903 u8 reserved_at_0[0x20]; 6904 6905 u8 reserved_at_20[0x1f]; 6906 u8 lwm[0x1]; 6907 }; 6908 6909 struct mlx5_ifc_modify_rmp_in_bits { 6910 u8 opcode[0x10]; 6911 u8 uid[0x10]; 6912 6913 u8 reserved_at_20[0x10]; 6914 u8 op_mod[0x10]; 6915 6916 u8 rmp_state[0x4]; 6917 u8 reserved_at_44[0x4]; 6918 u8 rmpn[0x18]; 6919 6920 u8 reserved_at_60[0x20]; 6921 6922 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6923 6924 u8 reserved_at_c0[0x40]; 6925 6926 struct mlx5_ifc_rmpc_bits ctx; 6927 }; 6928 6929 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6930 u8 status[0x8]; 6931 u8 reserved_at_8[0x18]; 6932 6933 u8 syndrome[0x20]; 6934 6935 u8 reserved_at_40[0x40]; 6936 }; 6937 6938 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6939 u8 reserved_at_0[0x12]; 6940 u8 affiliation[0x1]; 6941 u8 reserved_at_13[0x1]; 6942 u8 disable_uc_local_lb[0x1]; 6943 u8 disable_mc_local_lb[0x1]; 6944 u8 node_guid[0x1]; 6945 u8 port_guid[0x1]; 6946 u8 min_inline[0x1]; 6947 u8 mtu[0x1]; 6948 u8 change_event[0x1]; 6949 u8 promisc[0x1]; 6950 u8 permanent_address[0x1]; 6951 u8 addresses_list[0x1]; 6952 u8 roce_en[0x1]; 6953 u8 reserved_at_1f[0x1]; 6954 }; 6955 6956 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6957 u8 opcode[0x10]; 6958 u8 reserved_at_10[0x10]; 6959 6960 u8 reserved_at_20[0x10]; 6961 u8 op_mod[0x10]; 6962 6963 u8 other_vport[0x1]; 6964 u8 reserved_at_41[0xf]; 6965 u8 vport_number[0x10]; 6966 6967 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6968 6969 u8 reserved_at_80[0x780]; 6970 6971 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6972 }; 6973 6974 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6975 u8 status[0x8]; 6976 u8 reserved_at_8[0x18]; 6977 6978 u8 syndrome[0x20]; 6979 6980 u8 reserved_at_40[0x40]; 6981 }; 6982 6983 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6984 u8 opcode[0x10]; 6985 u8 reserved_at_10[0x10]; 6986 6987 u8 reserved_at_20[0x10]; 6988 u8 op_mod[0x10]; 6989 6990 u8 other_vport[0x1]; 6991 u8 reserved_at_41[0xb]; 6992 u8 port_num[0x4]; 6993 u8 vport_number[0x10]; 6994 6995 u8 reserved_at_60[0x20]; 6996 6997 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6998 }; 6999 7000 struct mlx5_ifc_modify_cq_out_bits { 7001 u8 status[0x8]; 7002 u8 reserved_at_8[0x18]; 7003 7004 u8 syndrome[0x20]; 7005 7006 u8 reserved_at_40[0x40]; 7007 }; 7008 7009 enum { 7010 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7011 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7012 }; 7013 7014 struct mlx5_ifc_modify_cq_in_bits { 7015 u8 opcode[0x10]; 7016 u8 uid[0x10]; 7017 7018 u8 reserved_at_20[0x10]; 7019 u8 op_mod[0x10]; 7020 7021 u8 reserved_at_40[0x8]; 7022 u8 cqn[0x18]; 7023 7024 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7025 7026 struct mlx5_ifc_cqc_bits cq_context; 7027 7028 u8 reserved_at_280[0x60]; 7029 7030 u8 cq_umem_valid[0x1]; 7031 u8 reserved_at_2e1[0x1f]; 7032 7033 u8 reserved_at_300[0x580]; 7034 7035 u8 pas[][0x40]; 7036 }; 7037 7038 struct mlx5_ifc_modify_cong_status_out_bits { 7039 u8 status[0x8]; 7040 u8 reserved_at_8[0x18]; 7041 7042 u8 syndrome[0x20]; 7043 7044 u8 reserved_at_40[0x40]; 7045 }; 7046 7047 struct mlx5_ifc_modify_cong_status_in_bits { 7048 u8 opcode[0x10]; 7049 u8 reserved_at_10[0x10]; 7050 7051 u8 reserved_at_20[0x10]; 7052 u8 op_mod[0x10]; 7053 7054 u8 reserved_at_40[0x18]; 7055 u8 priority[0x4]; 7056 u8 cong_protocol[0x4]; 7057 7058 u8 enable[0x1]; 7059 u8 tag_enable[0x1]; 7060 u8 reserved_at_62[0x1e]; 7061 }; 7062 7063 struct mlx5_ifc_modify_cong_params_out_bits { 7064 u8 status[0x8]; 7065 u8 reserved_at_8[0x18]; 7066 7067 u8 syndrome[0x20]; 7068 7069 u8 reserved_at_40[0x40]; 7070 }; 7071 7072 struct mlx5_ifc_modify_cong_params_in_bits { 7073 u8 opcode[0x10]; 7074 u8 reserved_at_10[0x10]; 7075 7076 u8 reserved_at_20[0x10]; 7077 u8 op_mod[0x10]; 7078 7079 u8 reserved_at_40[0x1c]; 7080 u8 cong_protocol[0x4]; 7081 7082 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7083 7084 u8 reserved_at_80[0x80]; 7085 7086 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7087 }; 7088 7089 struct mlx5_ifc_manage_pages_out_bits { 7090 u8 status[0x8]; 7091 u8 reserved_at_8[0x18]; 7092 7093 u8 syndrome[0x20]; 7094 7095 u8 output_num_entries[0x20]; 7096 7097 u8 reserved_at_60[0x20]; 7098 7099 u8 pas[][0x40]; 7100 }; 7101 7102 enum { 7103 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7104 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7105 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7106 }; 7107 7108 struct mlx5_ifc_manage_pages_in_bits { 7109 u8 opcode[0x10]; 7110 u8 reserved_at_10[0x10]; 7111 7112 u8 reserved_at_20[0x10]; 7113 u8 op_mod[0x10]; 7114 7115 u8 embedded_cpu_function[0x1]; 7116 u8 reserved_at_41[0xf]; 7117 u8 function_id[0x10]; 7118 7119 u8 input_num_entries[0x20]; 7120 7121 u8 pas[][0x40]; 7122 }; 7123 7124 struct mlx5_ifc_mad_ifc_out_bits { 7125 u8 status[0x8]; 7126 u8 reserved_at_8[0x18]; 7127 7128 u8 syndrome[0x20]; 7129 7130 u8 reserved_at_40[0x40]; 7131 7132 u8 response_mad_packet[256][0x8]; 7133 }; 7134 7135 struct mlx5_ifc_mad_ifc_in_bits { 7136 u8 opcode[0x10]; 7137 u8 reserved_at_10[0x10]; 7138 7139 u8 reserved_at_20[0x10]; 7140 u8 op_mod[0x10]; 7141 7142 u8 remote_lid[0x10]; 7143 u8 reserved_at_50[0x8]; 7144 u8 port[0x8]; 7145 7146 u8 reserved_at_60[0x20]; 7147 7148 u8 mad[256][0x8]; 7149 }; 7150 7151 struct mlx5_ifc_init_hca_out_bits { 7152 u8 status[0x8]; 7153 u8 reserved_at_8[0x18]; 7154 7155 u8 syndrome[0x20]; 7156 7157 u8 reserved_at_40[0x40]; 7158 }; 7159 7160 struct mlx5_ifc_init_hca_in_bits { 7161 u8 opcode[0x10]; 7162 u8 reserved_at_10[0x10]; 7163 7164 u8 reserved_at_20[0x10]; 7165 u8 op_mod[0x10]; 7166 7167 u8 reserved_at_40[0x40]; 7168 u8 sw_owner_id[4][0x20]; 7169 }; 7170 7171 struct mlx5_ifc_init2rtr_qp_out_bits { 7172 u8 status[0x8]; 7173 u8 reserved_at_8[0x18]; 7174 7175 u8 syndrome[0x20]; 7176 7177 u8 reserved_at_40[0x20]; 7178 u8 ece[0x20]; 7179 }; 7180 7181 struct mlx5_ifc_init2rtr_qp_in_bits { 7182 u8 opcode[0x10]; 7183 u8 uid[0x10]; 7184 7185 u8 reserved_at_20[0x10]; 7186 u8 op_mod[0x10]; 7187 7188 u8 reserved_at_40[0x8]; 7189 u8 qpn[0x18]; 7190 7191 u8 reserved_at_60[0x20]; 7192 7193 u8 opt_param_mask[0x20]; 7194 7195 u8 ece[0x20]; 7196 7197 struct mlx5_ifc_qpc_bits qpc; 7198 7199 u8 reserved_at_800[0x80]; 7200 }; 7201 7202 struct mlx5_ifc_init2init_qp_out_bits { 7203 u8 status[0x8]; 7204 u8 reserved_at_8[0x18]; 7205 7206 u8 syndrome[0x20]; 7207 7208 u8 reserved_at_40[0x20]; 7209 u8 ece[0x20]; 7210 }; 7211 7212 struct mlx5_ifc_init2init_qp_in_bits { 7213 u8 opcode[0x10]; 7214 u8 uid[0x10]; 7215 7216 u8 reserved_at_20[0x10]; 7217 u8 op_mod[0x10]; 7218 7219 u8 reserved_at_40[0x8]; 7220 u8 qpn[0x18]; 7221 7222 u8 reserved_at_60[0x20]; 7223 7224 u8 opt_param_mask[0x20]; 7225 7226 u8 ece[0x20]; 7227 7228 struct mlx5_ifc_qpc_bits qpc; 7229 7230 u8 reserved_at_800[0x80]; 7231 }; 7232 7233 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7234 u8 status[0x8]; 7235 u8 reserved_at_8[0x18]; 7236 7237 u8 syndrome[0x20]; 7238 7239 u8 reserved_at_40[0x40]; 7240 7241 u8 packet_headers_log[128][0x8]; 7242 7243 u8 packet_syndrome[64][0x8]; 7244 }; 7245 7246 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7247 u8 opcode[0x10]; 7248 u8 reserved_at_10[0x10]; 7249 7250 u8 reserved_at_20[0x10]; 7251 u8 op_mod[0x10]; 7252 7253 u8 reserved_at_40[0x40]; 7254 }; 7255 7256 struct mlx5_ifc_gen_eqe_in_bits { 7257 u8 opcode[0x10]; 7258 u8 reserved_at_10[0x10]; 7259 7260 u8 reserved_at_20[0x10]; 7261 u8 op_mod[0x10]; 7262 7263 u8 reserved_at_40[0x18]; 7264 u8 eq_number[0x8]; 7265 7266 u8 reserved_at_60[0x20]; 7267 7268 u8 eqe[64][0x8]; 7269 }; 7270 7271 struct mlx5_ifc_gen_eq_out_bits { 7272 u8 status[0x8]; 7273 u8 reserved_at_8[0x18]; 7274 7275 u8 syndrome[0x20]; 7276 7277 u8 reserved_at_40[0x40]; 7278 }; 7279 7280 struct mlx5_ifc_enable_hca_out_bits { 7281 u8 status[0x8]; 7282 u8 reserved_at_8[0x18]; 7283 7284 u8 syndrome[0x20]; 7285 7286 u8 reserved_at_40[0x20]; 7287 }; 7288 7289 struct mlx5_ifc_enable_hca_in_bits { 7290 u8 opcode[0x10]; 7291 u8 reserved_at_10[0x10]; 7292 7293 u8 reserved_at_20[0x10]; 7294 u8 op_mod[0x10]; 7295 7296 u8 embedded_cpu_function[0x1]; 7297 u8 reserved_at_41[0xf]; 7298 u8 function_id[0x10]; 7299 7300 u8 reserved_at_60[0x20]; 7301 }; 7302 7303 struct mlx5_ifc_drain_dct_out_bits { 7304 u8 status[0x8]; 7305 u8 reserved_at_8[0x18]; 7306 7307 u8 syndrome[0x20]; 7308 7309 u8 reserved_at_40[0x40]; 7310 }; 7311 7312 struct mlx5_ifc_drain_dct_in_bits { 7313 u8 opcode[0x10]; 7314 u8 uid[0x10]; 7315 7316 u8 reserved_at_20[0x10]; 7317 u8 op_mod[0x10]; 7318 7319 u8 reserved_at_40[0x8]; 7320 u8 dctn[0x18]; 7321 7322 u8 reserved_at_60[0x20]; 7323 }; 7324 7325 struct mlx5_ifc_disable_hca_out_bits { 7326 u8 status[0x8]; 7327 u8 reserved_at_8[0x18]; 7328 7329 u8 syndrome[0x20]; 7330 7331 u8 reserved_at_40[0x20]; 7332 }; 7333 7334 struct mlx5_ifc_disable_hca_in_bits { 7335 u8 opcode[0x10]; 7336 u8 reserved_at_10[0x10]; 7337 7338 u8 reserved_at_20[0x10]; 7339 u8 op_mod[0x10]; 7340 7341 u8 embedded_cpu_function[0x1]; 7342 u8 reserved_at_41[0xf]; 7343 u8 function_id[0x10]; 7344 7345 u8 reserved_at_60[0x20]; 7346 }; 7347 7348 struct mlx5_ifc_detach_from_mcg_out_bits { 7349 u8 status[0x8]; 7350 u8 reserved_at_8[0x18]; 7351 7352 u8 syndrome[0x20]; 7353 7354 u8 reserved_at_40[0x40]; 7355 }; 7356 7357 struct mlx5_ifc_detach_from_mcg_in_bits { 7358 u8 opcode[0x10]; 7359 u8 uid[0x10]; 7360 7361 u8 reserved_at_20[0x10]; 7362 u8 op_mod[0x10]; 7363 7364 u8 reserved_at_40[0x8]; 7365 u8 qpn[0x18]; 7366 7367 u8 reserved_at_60[0x20]; 7368 7369 u8 multicast_gid[16][0x8]; 7370 }; 7371 7372 struct mlx5_ifc_destroy_xrq_out_bits { 7373 u8 status[0x8]; 7374 u8 reserved_at_8[0x18]; 7375 7376 u8 syndrome[0x20]; 7377 7378 u8 reserved_at_40[0x40]; 7379 }; 7380 7381 struct mlx5_ifc_destroy_xrq_in_bits { 7382 u8 opcode[0x10]; 7383 u8 uid[0x10]; 7384 7385 u8 reserved_at_20[0x10]; 7386 u8 op_mod[0x10]; 7387 7388 u8 reserved_at_40[0x8]; 7389 u8 xrqn[0x18]; 7390 7391 u8 reserved_at_60[0x20]; 7392 }; 7393 7394 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7395 u8 status[0x8]; 7396 u8 reserved_at_8[0x18]; 7397 7398 u8 syndrome[0x20]; 7399 7400 u8 reserved_at_40[0x40]; 7401 }; 7402 7403 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7404 u8 opcode[0x10]; 7405 u8 uid[0x10]; 7406 7407 u8 reserved_at_20[0x10]; 7408 u8 op_mod[0x10]; 7409 7410 u8 reserved_at_40[0x8]; 7411 u8 xrc_srqn[0x18]; 7412 7413 u8 reserved_at_60[0x20]; 7414 }; 7415 7416 struct mlx5_ifc_destroy_tis_out_bits { 7417 u8 status[0x8]; 7418 u8 reserved_at_8[0x18]; 7419 7420 u8 syndrome[0x20]; 7421 7422 u8 reserved_at_40[0x40]; 7423 }; 7424 7425 struct mlx5_ifc_destroy_tis_in_bits { 7426 u8 opcode[0x10]; 7427 u8 uid[0x10]; 7428 7429 u8 reserved_at_20[0x10]; 7430 u8 op_mod[0x10]; 7431 7432 u8 reserved_at_40[0x8]; 7433 u8 tisn[0x18]; 7434 7435 u8 reserved_at_60[0x20]; 7436 }; 7437 7438 struct mlx5_ifc_destroy_tir_out_bits { 7439 u8 status[0x8]; 7440 u8 reserved_at_8[0x18]; 7441 7442 u8 syndrome[0x20]; 7443 7444 u8 reserved_at_40[0x40]; 7445 }; 7446 7447 struct mlx5_ifc_destroy_tir_in_bits { 7448 u8 opcode[0x10]; 7449 u8 uid[0x10]; 7450 7451 u8 reserved_at_20[0x10]; 7452 u8 op_mod[0x10]; 7453 7454 u8 reserved_at_40[0x8]; 7455 u8 tirn[0x18]; 7456 7457 u8 reserved_at_60[0x20]; 7458 }; 7459 7460 struct mlx5_ifc_destroy_srq_out_bits { 7461 u8 status[0x8]; 7462 u8 reserved_at_8[0x18]; 7463 7464 u8 syndrome[0x20]; 7465 7466 u8 reserved_at_40[0x40]; 7467 }; 7468 7469 struct mlx5_ifc_destroy_srq_in_bits { 7470 u8 opcode[0x10]; 7471 u8 uid[0x10]; 7472 7473 u8 reserved_at_20[0x10]; 7474 u8 op_mod[0x10]; 7475 7476 u8 reserved_at_40[0x8]; 7477 u8 srqn[0x18]; 7478 7479 u8 reserved_at_60[0x20]; 7480 }; 7481 7482 struct mlx5_ifc_destroy_sq_out_bits { 7483 u8 status[0x8]; 7484 u8 reserved_at_8[0x18]; 7485 7486 u8 syndrome[0x20]; 7487 7488 u8 reserved_at_40[0x40]; 7489 }; 7490 7491 struct mlx5_ifc_destroy_sq_in_bits { 7492 u8 opcode[0x10]; 7493 u8 uid[0x10]; 7494 7495 u8 reserved_at_20[0x10]; 7496 u8 op_mod[0x10]; 7497 7498 u8 reserved_at_40[0x8]; 7499 u8 sqn[0x18]; 7500 7501 u8 reserved_at_60[0x20]; 7502 }; 7503 7504 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7505 u8 status[0x8]; 7506 u8 reserved_at_8[0x18]; 7507 7508 u8 syndrome[0x20]; 7509 7510 u8 reserved_at_40[0x1c0]; 7511 }; 7512 7513 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7514 u8 opcode[0x10]; 7515 u8 reserved_at_10[0x10]; 7516 7517 u8 reserved_at_20[0x10]; 7518 u8 op_mod[0x10]; 7519 7520 u8 scheduling_hierarchy[0x8]; 7521 u8 reserved_at_48[0x18]; 7522 7523 u8 scheduling_element_id[0x20]; 7524 7525 u8 reserved_at_80[0x180]; 7526 }; 7527 7528 struct mlx5_ifc_destroy_rqt_out_bits { 7529 u8 status[0x8]; 7530 u8 reserved_at_8[0x18]; 7531 7532 u8 syndrome[0x20]; 7533 7534 u8 reserved_at_40[0x40]; 7535 }; 7536 7537 struct mlx5_ifc_destroy_rqt_in_bits { 7538 u8 opcode[0x10]; 7539 u8 uid[0x10]; 7540 7541 u8 reserved_at_20[0x10]; 7542 u8 op_mod[0x10]; 7543 7544 u8 reserved_at_40[0x8]; 7545 u8 rqtn[0x18]; 7546 7547 u8 reserved_at_60[0x20]; 7548 }; 7549 7550 struct mlx5_ifc_destroy_rq_out_bits { 7551 u8 status[0x8]; 7552 u8 reserved_at_8[0x18]; 7553 7554 u8 syndrome[0x20]; 7555 7556 u8 reserved_at_40[0x40]; 7557 }; 7558 7559 struct mlx5_ifc_destroy_rq_in_bits { 7560 u8 opcode[0x10]; 7561 u8 uid[0x10]; 7562 7563 u8 reserved_at_20[0x10]; 7564 u8 op_mod[0x10]; 7565 7566 u8 reserved_at_40[0x8]; 7567 u8 rqn[0x18]; 7568 7569 u8 reserved_at_60[0x20]; 7570 }; 7571 7572 struct mlx5_ifc_set_delay_drop_params_in_bits { 7573 u8 opcode[0x10]; 7574 u8 reserved_at_10[0x10]; 7575 7576 u8 reserved_at_20[0x10]; 7577 u8 op_mod[0x10]; 7578 7579 u8 reserved_at_40[0x20]; 7580 7581 u8 reserved_at_60[0x10]; 7582 u8 delay_drop_timeout[0x10]; 7583 }; 7584 7585 struct mlx5_ifc_set_delay_drop_params_out_bits { 7586 u8 status[0x8]; 7587 u8 reserved_at_8[0x18]; 7588 7589 u8 syndrome[0x20]; 7590 7591 u8 reserved_at_40[0x40]; 7592 }; 7593 7594 struct mlx5_ifc_destroy_rmp_out_bits { 7595 u8 status[0x8]; 7596 u8 reserved_at_8[0x18]; 7597 7598 u8 syndrome[0x20]; 7599 7600 u8 reserved_at_40[0x40]; 7601 }; 7602 7603 struct mlx5_ifc_destroy_rmp_in_bits { 7604 u8 opcode[0x10]; 7605 u8 uid[0x10]; 7606 7607 u8 reserved_at_20[0x10]; 7608 u8 op_mod[0x10]; 7609 7610 u8 reserved_at_40[0x8]; 7611 u8 rmpn[0x18]; 7612 7613 u8 reserved_at_60[0x20]; 7614 }; 7615 7616 struct mlx5_ifc_destroy_qp_out_bits { 7617 u8 status[0x8]; 7618 u8 reserved_at_8[0x18]; 7619 7620 u8 syndrome[0x20]; 7621 7622 u8 reserved_at_40[0x40]; 7623 }; 7624 7625 struct mlx5_ifc_destroy_qp_in_bits { 7626 u8 opcode[0x10]; 7627 u8 uid[0x10]; 7628 7629 u8 reserved_at_20[0x10]; 7630 u8 op_mod[0x10]; 7631 7632 u8 reserved_at_40[0x8]; 7633 u8 qpn[0x18]; 7634 7635 u8 reserved_at_60[0x20]; 7636 }; 7637 7638 struct mlx5_ifc_destroy_psv_out_bits { 7639 u8 status[0x8]; 7640 u8 reserved_at_8[0x18]; 7641 7642 u8 syndrome[0x20]; 7643 7644 u8 reserved_at_40[0x40]; 7645 }; 7646 7647 struct mlx5_ifc_destroy_psv_in_bits { 7648 u8 opcode[0x10]; 7649 u8 reserved_at_10[0x10]; 7650 7651 u8 reserved_at_20[0x10]; 7652 u8 op_mod[0x10]; 7653 7654 u8 reserved_at_40[0x8]; 7655 u8 psvn[0x18]; 7656 7657 u8 reserved_at_60[0x20]; 7658 }; 7659 7660 struct mlx5_ifc_destroy_mkey_out_bits { 7661 u8 status[0x8]; 7662 u8 reserved_at_8[0x18]; 7663 7664 u8 syndrome[0x20]; 7665 7666 u8 reserved_at_40[0x40]; 7667 }; 7668 7669 struct mlx5_ifc_destroy_mkey_in_bits { 7670 u8 opcode[0x10]; 7671 u8 uid[0x10]; 7672 7673 u8 reserved_at_20[0x10]; 7674 u8 op_mod[0x10]; 7675 7676 u8 reserved_at_40[0x8]; 7677 u8 mkey_index[0x18]; 7678 7679 u8 reserved_at_60[0x20]; 7680 }; 7681 7682 struct mlx5_ifc_destroy_flow_table_out_bits { 7683 u8 status[0x8]; 7684 u8 reserved_at_8[0x18]; 7685 7686 u8 syndrome[0x20]; 7687 7688 u8 reserved_at_40[0x40]; 7689 }; 7690 7691 struct mlx5_ifc_destroy_flow_table_in_bits { 7692 u8 opcode[0x10]; 7693 u8 reserved_at_10[0x10]; 7694 7695 u8 reserved_at_20[0x10]; 7696 u8 op_mod[0x10]; 7697 7698 u8 other_vport[0x1]; 7699 u8 reserved_at_41[0xf]; 7700 u8 vport_number[0x10]; 7701 7702 u8 reserved_at_60[0x20]; 7703 7704 u8 table_type[0x8]; 7705 u8 reserved_at_88[0x18]; 7706 7707 u8 reserved_at_a0[0x8]; 7708 u8 table_id[0x18]; 7709 7710 u8 reserved_at_c0[0x140]; 7711 }; 7712 7713 struct mlx5_ifc_destroy_flow_group_out_bits { 7714 u8 status[0x8]; 7715 u8 reserved_at_8[0x18]; 7716 7717 u8 syndrome[0x20]; 7718 7719 u8 reserved_at_40[0x40]; 7720 }; 7721 7722 struct mlx5_ifc_destroy_flow_group_in_bits { 7723 u8 opcode[0x10]; 7724 u8 reserved_at_10[0x10]; 7725 7726 u8 reserved_at_20[0x10]; 7727 u8 op_mod[0x10]; 7728 7729 u8 other_vport[0x1]; 7730 u8 reserved_at_41[0xf]; 7731 u8 vport_number[0x10]; 7732 7733 u8 reserved_at_60[0x20]; 7734 7735 u8 table_type[0x8]; 7736 u8 reserved_at_88[0x18]; 7737 7738 u8 reserved_at_a0[0x8]; 7739 u8 table_id[0x18]; 7740 7741 u8 group_id[0x20]; 7742 7743 u8 reserved_at_e0[0x120]; 7744 }; 7745 7746 struct mlx5_ifc_destroy_eq_out_bits { 7747 u8 status[0x8]; 7748 u8 reserved_at_8[0x18]; 7749 7750 u8 syndrome[0x20]; 7751 7752 u8 reserved_at_40[0x40]; 7753 }; 7754 7755 struct mlx5_ifc_destroy_eq_in_bits { 7756 u8 opcode[0x10]; 7757 u8 reserved_at_10[0x10]; 7758 7759 u8 reserved_at_20[0x10]; 7760 u8 op_mod[0x10]; 7761 7762 u8 reserved_at_40[0x18]; 7763 u8 eq_number[0x8]; 7764 7765 u8 reserved_at_60[0x20]; 7766 }; 7767 7768 struct mlx5_ifc_destroy_dct_out_bits { 7769 u8 status[0x8]; 7770 u8 reserved_at_8[0x18]; 7771 7772 u8 syndrome[0x20]; 7773 7774 u8 reserved_at_40[0x40]; 7775 }; 7776 7777 struct mlx5_ifc_destroy_dct_in_bits { 7778 u8 opcode[0x10]; 7779 u8 uid[0x10]; 7780 7781 u8 reserved_at_20[0x10]; 7782 u8 op_mod[0x10]; 7783 7784 u8 reserved_at_40[0x8]; 7785 u8 dctn[0x18]; 7786 7787 u8 reserved_at_60[0x20]; 7788 }; 7789 7790 struct mlx5_ifc_destroy_cq_out_bits { 7791 u8 status[0x8]; 7792 u8 reserved_at_8[0x18]; 7793 7794 u8 syndrome[0x20]; 7795 7796 u8 reserved_at_40[0x40]; 7797 }; 7798 7799 struct mlx5_ifc_destroy_cq_in_bits { 7800 u8 opcode[0x10]; 7801 u8 uid[0x10]; 7802 7803 u8 reserved_at_20[0x10]; 7804 u8 op_mod[0x10]; 7805 7806 u8 reserved_at_40[0x8]; 7807 u8 cqn[0x18]; 7808 7809 u8 reserved_at_60[0x20]; 7810 }; 7811 7812 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7813 u8 status[0x8]; 7814 u8 reserved_at_8[0x18]; 7815 7816 u8 syndrome[0x20]; 7817 7818 u8 reserved_at_40[0x40]; 7819 }; 7820 7821 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7822 u8 opcode[0x10]; 7823 u8 reserved_at_10[0x10]; 7824 7825 u8 reserved_at_20[0x10]; 7826 u8 op_mod[0x10]; 7827 7828 u8 reserved_at_40[0x20]; 7829 7830 u8 reserved_at_60[0x10]; 7831 u8 vxlan_udp_port[0x10]; 7832 }; 7833 7834 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7835 u8 status[0x8]; 7836 u8 reserved_at_8[0x18]; 7837 7838 u8 syndrome[0x20]; 7839 7840 u8 reserved_at_40[0x40]; 7841 }; 7842 7843 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7844 u8 opcode[0x10]; 7845 u8 reserved_at_10[0x10]; 7846 7847 u8 reserved_at_20[0x10]; 7848 u8 op_mod[0x10]; 7849 7850 u8 reserved_at_40[0x60]; 7851 7852 u8 reserved_at_a0[0x8]; 7853 u8 table_index[0x18]; 7854 7855 u8 reserved_at_c0[0x140]; 7856 }; 7857 7858 struct mlx5_ifc_delete_fte_out_bits { 7859 u8 status[0x8]; 7860 u8 reserved_at_8[0x18]; 7861 7862 u8 syndrome[0x20]; 7863 7864 u8 reserved_at_40[0x40]; 7865 }; 7866 7867 struct mlx5_ifc_delete_fte_in_bits { 7868 u8 opcode[0x10]; 7869 u8 reserved_at_10[0x10]; 7870 7871 u8 reserved_at_20[0x10]; 7872 u8 op_mod[0x10]; 7873 7874 u8 other_vport[0x1]; 7875 u8 reserved_at_41[0xf]; 7876 u8 vport_number[0x10]; 7877 7878 u8 reserved_at_60[0x20]; 7879 7880 u8 table_type[0x8]; 7881 u8 reserved_at_88[0x18]; 7882 7883 u8 reserved_at_a0[0x8]; 7884 u8 table_id[0x18]; 7885 7886 u8 reserved_at_c0[0x40]; 7887 7888 u8 flow_index[0x20]; 7889 7890 u8 reserved_at_120[0xe0]; 7891 }; 7892 7893 struct mlx5_ifc_dealloc_xrcd_out_bits { 7894 u8 status[0x8]; 7895 u8 reserved_at_8[0x18]; 7896 7897 u8 syndrome[0x20]; 7898 7899 u8 reserved_at_40[0x40]; 7900 }; 7901 7902 struct mlx5_ifc_dealloc_xrcd_in_bits { 7903 u8 opcode[0x10]; 7904 u8 uid[0x10]; 7905 7906 u8 reserved_at_20[0x10]; 7907 u8 op_mod[0x10]; 7908 7909 u8 reserved_at_40[0x8]; 7910 u8 xrcd[0x18]; 7911 7912 u8 reserved_at_60[0x20]; 7913 }; 7914 7915 struct mlx5_ifc_dealloc_uar_out_bits { 7916 u8 status[0x8]; 7917 u8 reserved_at_8[0x18]; 7918 7919 u8 syndrome[0x20]; 7920 7921 u8 reserved_at_40[0x40]; 7922 }; 7923 7924 struct mlx5_ifc_dealloc_uar_in_bits { 7925 u8 opcode[0x10]; 7926 u8 uid[0x10]; 7927 7928 u8 reserved_at_20[0x10]; 7929 u8 op_mod[0x10]; 7930 7931 u8 reserved_at_40[0x8]; 7932 u8 uar[0x18]; 7933 7934 u8 reserved_at_60[0x20]; 7935 }; 7936 7937 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7938 u8 status[0x8]; 7939 u8 reserved_at_8[0x18]; 7940 7941 u8 syndrome[0x20]; 7942 7943 u8 reserved_at_40[0x40]; 7944 }; 7945 7946 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7947 u8 opcode[0x10]; 7948 u8 uid[0x10]; 7949 7950 u8 reserved_at_20[0x10]; 7951 u8 op_mod[0x10]; 7952 7953 u8 reserved_at_40[0x8]; 7954 u8 transport_domain[0x18]; 7955 7956 u8 reserved_at_60[0x20]; 7957 }; 7958 7959 struct mlx5_ifc_dealloc_q_counter_out_bits { 7960 u8 status[0x8]; 7961 u8 reserved_at_8[0x18]; 7962 7963 u8 syndrome[0x20]; 7964 7965 u8 reserved_at_40[0x40]; 7966 }; 7967 7968 struct mlx5_ifc_dealloc_q_counter_in_bits { 7969 u8 opcode[0x10]; 7970 u8 reserved_at_10[0x10]; 7971 7972 u8 reserved_at_20[0x10]; 7973 u8 op_mod[0x10]; 7974 7975 u8 reserved_at_40[0x18]; 7976 u8 counter_set_id[0x8]; 7977 7978 u8 reserved_at_60[0x20]; 7979 }; 7980 7981 struct mlx5_ifc_dealloc_pd_out_bits { 7982 u8 status[0x8]; 7983 u8 reserved_at_8[0x18]; 7984 7985 u8 syndrome[0x20]; 7986 7987 u8 reserved_at_40[0x40]; 7988 }; 7989 7990 struct mlx5_ifc_dealloc_pd_in_bits { 7991 u8 opcode[0x10]; 7992 u8 uid[0x10]; 7993 7994 u8 reserved_at_20[0x10]; 7995 u8 op_mod[0x10]; 7996 7997 u8 reserved_at_40[0x8]; 7998 u8 pd[0x18]; 7999 8000 u8 reserved_at_60[0x20]; 8001 }; 8002 8003 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8004 u8 status[0x8]; 8005 u8 reserved_at_8[0x18]; 8006 8007 u8 syndrome[0x20]; 8008 8009 u8 reserved_at_40[0x40]; 8010 }; 8011 8012 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8013 u8 opcode[0x10]; 8014 u8 reserved_at_10[0x10]; 8015 8016 u8 reserved_at_20[0x10]; 8017 u8 op_mod[0x10]; 8018 8019 u8 flow_counter_id[0x20]; 8020 8021 u8 reserved_at_60[0x20]; 8022 }; 8023 8024 struct mlx5_ifc_create_xrq_out_bits { 8025 u8 status[0x8]; 8026 u8 reserved_at_8[0x18]; 8027 8028 u8 syndrome[0x20]; 8029 8030 u8 reserved_at_40[0x8]; 8031 u8 xrqn[0x18]; 8032 8033 u8 reserved_at_60[0x20]; 8034 }; 8035 8036 struct mlx5_ifc_create_xrq_in_bits { 8037 u8 opcode[0x10]; 8038 u8 uid[0x10]; 8039 8040 u8 reserved_at_20[0x10]; 8041 u8 op_mod[0x10]; 8042 8043 u8 reserved_at_40[0x40]; 8044 8045 struct mlx5_ifc_xrqc_bits xrq_context; 8046 }; 8047 8048 struct mlx5_ifc_create_xrc_srq_out_bits { 8049 u8 status[0x8]; 8050 u8 reserved_at_8[0x18]; 8051 8052 u8 syndrome[0x20]; 8053 8054 u8 reserved_at_40[0x8]; 8055 u8 xrc_srqn[0x18]; 8056 8057 u8 reserved_at_60[0x20]; 8058 }; 8059 8060 struct mlx5_ifc_create_xrc_srq_in_bits { 8061 u8 opcode[0x10]; 8062 u8 uid[0x10]; 8063 8064 u8 reserved_at_20[0x10]; 8065 u8 op_mod[0x10]; 8066 8067 u8 reserved_at_40[0x40]; 8068 8069 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8070 8071 u8 reserved_at_280[0x60]; 8072 8073 u8 xrc_srq_umem_valid[0x1]; 8074 u8 reserved_at_2e1[0x1f]; 8075 8076 u8 reserved_at_300[0x580]; 8077 8078 u8 pas[][0x40]; 8079 }; 8080 8081 struct mlx5_ifc_create_tis_out_bits { 8082 u8 status[0x8]; 8083 u8 reserved_at_8[0x18]; 8084 8085 u8 syndrome[0x20]; 8086 8087 u8 reserved_at_40[0x8]; 8088 u8 tisn[0x18]; 8089 8090 u8 reserved_at_60[0x20]; 8091 }; 8092 8093 struct mlx5_ifc_create_tis_in_bits { 8094 u8 opcode[0x10]; 8095 u8 uid[0x10]; 8096 8097 u8 reserved_at_20[0x10]; 8098 u8 op_mod[0x10]; 8099 8100 u8 reserved_at_40[0xc0]; 8101 8102 struct mlx5_ifc_tisc_bits ctx; 8103 }; 8104 8105 struct mlx5_ifc_create_tir_out_bits { 8106 u8 status[0x8]; 8107 u8 icm_address_63_40[0x18]; 8108 8109 u8 syndrome[0x20]; 8110 8111 u8 icm_address_39_32[0x8]; 8112 u8 tirn[0x18]; 8113 8114 u8 icm_address_31_0[0x20]; 8115 }; 8116 8117 struct mlx5_ifc_create_tir_in_bits { 8118 u8 opcode[0x10]; 8119 u8 uid[0x10]; 8120 8121 u8 reserved_at_20[0x10]; 8122 u8 op_mod[0x10]; 8123 8124 u8 reserved_at_40[0xc0]; 8125 8126 struct mlx5_ifc_tirc_bits ctx; 8127 }; 8128 8129 struct mlx5_ifc_create_srq_out_bits { 8130 u8 status[0x8]; 8131 u8 reserved_at_8[0x18]; 8132 8133 u8 syndrome[0x20]; 8134 8135 u8 reserved_at_40[0x8]; 8136 u8 srqn[0x18]; 8137 8138 u8 reserved_at_60[0x20]; 8139 }; 8140 8141 struct mlx5_ifc_create_srq_in_bits { 8142 u8 opcode[0x10]; 8143 u8 uid[0x10]; 8144 8145 u8 reserved_at_20[0x10]; 8146 u8 op_mod[0x10]; 8147 8148 u8 reserved_at_40[0x40]; 8149 8150 struct mlx5_ifc_srqc_bits srq_context_entry; 8151 8152 u8 reserved_at_280[0x600]; 8153 8154 u8 pas[][0x40]; 8155 }; 8156 8157 struct mlx5_ifc_create_sq_out_bits { 8158 u8 status[0x8]; 8159 u8 reserved_at_8[0x18]; 8160 8161 u8 syndrome[0x20]; 8162 8163 u8 reserved_at_40[0x8]; 8164 u8 sqn[0x18]; 8165 8166 u8 reserved_at_60[0x20]; 8167 }; 8168 8169 struct mlx5_ifc_create_sq_in_bits { 8170 u8 opcode[0x10]; 8171 u8 uid[0x10]; 8172 8173 u8 reserved_at_20[0x10]; 8174 u8 op_mod[0x10]; 8175 8176 u8 reserved_at_40[0xc0]; 8177 8178 struct mlx5_ifc_sqc_bits ctx; 8179 }; 8180 8181 struct mlx5_ifc_create_scheduling_element_out_bits { 8182 u8 status[0x8]; 8183 u8 reserved_at_8[0x18]; 8184 8185 u8 syndrome[0x20]; 8186 8187 u8 reserved_at_40[0x40]; 8188 8189 u8 scheduling_element_id[0x20]; 8190 8191 u8 reserved_at_a0[0x160]; 8192 }; 8193 8194 struct mlx5_ifc_create_scheduling_element_in_bits { 8195 u8 opcode[0x10]; 8196 u8 reserved_at_10[0x10]; 8197 8198 u8 reserved_at_20[0x10]; 8199 u8 op_mod[0x10]; 8200 8201 u8 scheduling_hierarchy[0x8]; 8202 u8 reserved_at_48[0x18]; 8203 8204 u8 reserved_at_60[0xa0]; 8205 8206 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8207 8208 u8 reserved_at_300[0x100]; 8209 }; 8210 8211 struct mlx5_ifc_create_rqt_out_bits { 8212 u8 status[0x8]; 8213 u8 reserved_at_8[0x18]; 8214 8215 u8 syndrome[0x20]; 8216 8217 u8 reserved_at_40[0x8]; 8218 u8 rqtn[0x18]; 8219 8220 u8 reserved_at_60[0x20]; 8221 }; 8222 8223 struct mlx5_ifc_create_rqt_in_bits { 8224 u8 opcode[0x10]; 8225 u8 uid[0x10]; 8226 8227 u8 reserved_at_20[0x10]; 8228 u8 op_mod[0x10]; 8229 8230 u8 reserved_at_40[0xc0]; 8231 8232 struct mlx5_ifc_rqtc_bits rqt_context; 8233 }; 8234 8235 struct mlx5_ifc_create_rq_out_bits { 8236 u8 status[0x8]; 8237 u8 reserved_at_8[0x18]; 8238 8239 u8 syndrome[0x20]; 8240 8241 u8 reserved_at_40[0x8]; 8242 u8 rqn[0x18]; 8243 8244 u8 reserved_at_60[0x20]; 8245 }; 8246 8247 struct mlx5_ifc_create_rq_in_bits { 8248 u8 opcode[0x10]; 8249 u8 uid[0x10]; 8250 8251 u8 reserved_at_20[0x10]; 8252 u8 op_mod[0x10]; 8253 8254 u8 reserved_at_40[0xc0]; 8255 8256 struct mlx5_ifc_rqc_bits ctx; 8257 }; 8258 8259 struct mlx5_ifc_create_rmp_out_bits { 8260 u8 status[0x8]; 8261 u8 reserved_at_8[0x18]; 8262 8263 u8 syndrome[0x20]; 8264 8265 u8 reserved_at_40[0x8]; 8266 u8 rmpn[0x18]; 8267 8268 u8 reserved_at_60[0x20]; 8269 }; 8270 8271 struct mlx5_ifc_create_rmp_in_bits { 8272 u8 opcode[0x10]; 8273 u8 uid[0x10]; 8274 8275 u8 reserved_at_20[0x10]; 8276 u8 op_mod[0x10]; 8277 8278 u8 reserved_at_40[0xc0]; 8279 8280 struct mlx5_ifc_rmpc_bits ctx; 8281 }; 8282 8283 struct mlx5_ifc_create_qp_out_bits { 8284 u8 status[0x8]; 8285 u8 reserved_at_8[0x18]; 8286 8287 u8 syndrome[0x20]; 8288 8289 u8 reserved_at_40[0x8]; 8290 u8 qpn[0x18]; 8291 8292 u8 ece[0x20]; 8293 }; 8294 8295 struct mlx5_ifc_create_qp_in_bits { 8296 u8 opcode[0x10]; 8297 u8 uid[0x10]; 8298 8299 u8 reserved_at_20[0x10]; 8300 u8 op_mod[0x10]; 8301 8302 u8 reserved_at_40[0x8]; 8303 u8 input_qpn[0x18]; 8304 8305 u8 reserved_at_60[0x20]; 8306 u8 opt_param_mask[0x20]; 8307 8308 u8 ece[0x20]; 8309 8310 struct mlx5_ifc_qpc_bits qpc; 8311 8312 u8 reserved_at_800[0x60]; 8313 8314 u8 wq_umem_valid[0x1]; 8315 u8 reserved_at_861[0x1f]; 8316 8317 u8 pas[][0x40]; 8318 }; 8319 8320 struct mlx5_ifc_create_psv_out_bits { 8321 u8 status[0x8]; 8322 u8 reserved_at_8[0x18]; 8323 8324 u8 syndrome[0x20]; 8325 8326 u8 reserved_at_40[0x40]; 8327 8328 u8 reserved_at_80[0x8]; 8329 u8 psv0_index[0x18]; 8330 8331 u8 reserved_at_a0[0x8]; 8332 u8 psv1_index[0x18]; 8333 8334 u8 reserved_at_c0[0x8]; 8335 u8 psv2_index[0x18]; 8336 8337 u8 reserved_at_e0[0x8]; 8338 u8 psv3_index[0x18]; 8339 }; 8340 8341 struct mlx5_ifc_create_psv_in_bits { 8342 u8 opcode[0x10]; 8343 u8 reserved_at_10[0x10]; 8344 8345 u8 reserved_at_20[0x10]; 8346 u8 op_mod[0x10]; 8347 8348 u8 num_psv[0x4]; 8349 u8 reserved_at_44[0x4]; 8350 u8 pd[0x18]; 8351 8352 u8 reserved_at_60[0x20]; 8353 }; 8354 8355 struct mlx5_ifc_create_mkey_out_bits { 8356 u8 status[0x8]; 8357 u8 reserved_at_8[0x18]; 8358 8359 u8 syndrome[0x20]; 8360 8361 u8 reserved_at_40[0x8]; 8362 u8 mkey_index[0x18]; 8363 8364 u8 reserved_at_60[0x20]; 8365 }; 8366 8367 struct mlx5_ifc_create_mkey_in_bits { 8368 u8 opcode[0x10]; 8369 u8 uid[0x10]; 8370 8371 u8 reserved_at_20[0x10]; 8372 u8 op_mod[0x10]; 8373 8374 u8 reserved_at_40[0x20]; 8375 8376 u8 pg_access[0x1]; 8377 u8 mkey_umem_valid[0x1]; 8378 u8 reserved_at_62[0x1e]; 8379 8380 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8381 8382 u8 reserved_at_280[0x80]; 8383 8384 u8 translations_octword_actual_size[0x20]; 8385 8386 u8 reserved_at_320[0x560]; 8387 8388 u8 klm_pas_mtt[][0x20]; 8389 }; 8390 8391 enum { 8392 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8393 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8394 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8395 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8396 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8397 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8398 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8399 }; 8400 8401 struct mlx5_ifc_create_flow_table_out_bits { 8402 u8 status[0x8]; 8403 u8 icm_address_63_40[0x18]; 8404 8405 u8 syndrome[0x20]; 8406 8407 u8 icm_address_39_32[0x8]; 8408 u8 table_id[0x18]; 8409 8410 u8 icm_address_31_0[0x20]; 8411 }; 8412 8413 struct mlx5_ifc_create_flow_table_in_bits { 8414 u8 opcode[0x10]; 8415 u8 reserved_at_10[0x10]; 8416 8417 u8 reserved_at_20[0x10]; 8418 u8 op_mod[0x10]; 8419 8420 u8 other_vport[0x1]; 8421 u8 reserved_at_41[0xf]; 8422 u8 vport_number[0x10]; 8423 8424 u8 reserved_at_60[0x20]; 8425 8426 u8 table_type[0x8]; 8427 u8 reserved_at_88[0x18]; 8428 8429 u8 reserved_at_a0[0x20]; 8430 8431 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8432 }; 8433 8434 struct mlx5_ifc_create_flow_group_out_bits { 8435 u8 status[0x8]; 8436 u8 reserved_at_8[0x18]; 8437 8438 u8 syndrome[0x20]; 8439 8440 u8 reserved_at_40[0x8]; 8441 u8 group_id[0x18]; 8442 8443 u8 reserved_at_60[0x20]; 8444 }; 8445 8446 enum { 8447 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8448 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8449 }; 8450 8451 enum { 8452 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8453 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8454 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8455 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8456 }; 8457 8458 struct mlx5_ifc_create_flow_group_in_bits { 8459 u8 opcode[0x10]; 8460 u8 reserved_at_10[0x10]; 8461 8462 u8 reserved_at_20[0x10]; 8463 u8 op_mod[0x10]; 8464 8465 u8 other_vport[0x1]; 8466 u8 reserved_at_41[0xf]; 8467 u8 vport_number[0x10]; 8468 8469 u8 reserved_at_60[0x20]; 8470 8471 u8 table_type[0x8]; 8472 u8 reserved_at_88[0x4]; 8473 u8 group_type[0x4]; 8474 u8 reserved_at_90[0x10]; 8475 8476 u8 reserved_at_a0[0x8]; 8477 u8 table_id[0x18]; 8478 8479 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8480 8481 u8 reserved_at_c1[0x1f]; 8482 8483 u8 start_flow_index[0x20]; 8484 8485 u8 reserved_at_100[0x20]; 8486 8487 u8 end_flow_index[0x20]; 8488 8489 u8 reserved_at_140[0x10]; 8490 u8 match_definer_id[0x10]; 8491 8492 u8 reserved_at_160[0x80]; 8493 8494 u8 reserved_at_1e0[0x18]; 8495 u8 match_criteria_enable[0x8]; 8496 8497 struct mlx5_ifc_fte_match_param_bits match_criteria; 8498 8499 u8 reserved_at_1200[0xe00]; 8500 }; 8501 8502 struct mlx5_ifc_create_eq_out_bits { 8503 u8 status[0x8]; 8504 u8 reserved_at_8[0x18]; 8505 8506 u8 syndrome[0x20]; 8507 8508 u8 reserved_at_40[0x18]; 8509 u8 eq_number[0x8]; 8510 8511 u8 reserved_at_60[0x20]; 8512 }; 8513 8514 struct mlx5_ifc_create_eq_in_bits { 8515 u8 opcode[0x10]; 8516 u8 uid[0x10]; 8517 8518 u8 reserved_at_20[0x10]; 8519 u8 op_mod[0x10]; 8520 8521 u8 reserved_at_40[0x40]; 8522 8523 struct mlx5_ifc_eqc_bits eq_context_entry; 8524 8525 u8 reserved_at_280[0x40]; 8526 8527 u8 event_bitmask[4][0x40]; 8528 8529 u8 reserved_at_3c0[0x4c0]; 8530 8531 u8 pas[][0x40]; 8532 }; 8533 8534 struct mlx5_ifc_create_dct_out_bits { 8535 u8 status[0x8]; 8536 u8 reserved_at_8[0x18]; 8537 8538 u8 syndrome[0x20]; 8539 8540 u8 reserved_at_40[0x8]; 8541 u8 dctn[0x18]; 8542 8543 u8 ece[0x20]; 8544 }; 8545 8546 struct mlx5_ifc_create_dct_in_bits { 8547 u8 opcode[0x10]; 8548 u8 uid[0x10]; 8549 8550 u8 reserved_at_20[0x10]; 8551 u8 op_mod[0x10]; 8552 8553 u8 reserved_at_40[0x40]; 8554 8555 struct mlx5_ifc_dctc_bits dct_context_entry; 8556 8557 u8 reserved_at_280[0x180]; 8558 }; 8559 8560 struct mlx5_ifc_create_cq_out_bits { 8561 u8 status[0x8]; 8562 u8 reserved_at_8[0x18]; 8563 8564 u8 syndrome[0x20]; 8565 8566 u8 reserved_at_40[0x8]; 8567 u8 cqn[0x18]; 8568 8569 u8 reserved_at_60[0x20]; 8570 }; 8571 8572 struct mlx5_ifc_create_cq_in_bits { 8573 u8 opcode[0x10]; 8574 u8 uid[0x10]; 8575 8576 u8 reserved_at_20[0x10]; 8577 u8 op_mod[0x10]; 8578 8579 u8 reserved_at_40[0x40]; 8580 8581 struct mlx5_ifc_cqc_bits cq_context; 8582 8583 u8 reserved_at_280[0x60]; 8584 8585 u8 cq_umem_valid[0x1]; 8586 u8 reserved_at_2e1[0x59f]; 8587 8588 u8 pas[][0x40]; 8589 }; 8590 8591 struct mlx5_ifc_config_int_moderation_out_bits { 8592 u8 status[0x8]; 8593 u8 reserved_at_8[0x18]; 8594 8595 u8 syndrome[0x20]; 8596 8597 u8 reserved_at_40[0x4]; 8598 u8 min_delay[0xc]; 8599 u8 int_vector[0x10]; 8600 8601 u8 reserved_at_60[0x20]; 8602 }; 8603 8604 enum { 8605 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8606 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8607 }; 8608 8609 struct mlx5_ifc_config_int_moderation_in_bits { 8610 u8 opcode[0x10]; 8611 u8 reserved_at_10[0x10]; 8612 8613 u8 reserved_at_20[0x10]; 8614 u8 op_mod[0x10]; 8615 8616 u8 reserved_at_40[0x4]; 8617 u8 min_delay[0xc]; 8618 u8 int_vector[0x10]; 8619 8620 u8 reserved_at_60[0x20]; 8621 }; 8622 8623 struct mlx5_ifc_attach_to_mcg_out_bits { 8624 u8 status[0x8]; 8625 u8 reserved_at_8[0x18]; 8626 8627 u8 syndrome[0x20]; 8628 8629 u8 reserved_at_40[0x40]; 8630 }; 8631 8632 struct mlx5_ifc_attach_to_mcg_in_bits { 8633 u8 opcode[0x10]; 8634 u8 uid[0x10]; 8635 8636 u8 reserved_at_20[0x10]; 8637 u8 op_mod[0x10]; 8638 8639 u8 reserved_at_40[0x8]; 8640 u8 qpn[0x18]; 8641 8642 u8 reserved_at_60[0x20]; 8643 8644 u8 multicast_gid[16][0x8]; 8645 }; 8646 8647 struct mlx5_ifc_arm_xrq_out_bits { 8648 u8 status[0x8]; 8649 u8 reserved_at_8[0x18]; 8650 8651 u8 syndrome[0x20]; 8652 8653 u8 reserved_at_40[0x40]; 8654 }; 8655 8656 struct mlx5_ifc_arm_xrq_in_bits { 8657 u8 opcode[0x10]; 8658 u8 reserved_at_10[0x10]; 8659 8660 u8 reserved_at_20[0x10]; 8661 u8 op_mod[0x10]; 8662 8663 u8 reserved_at_40[0x8]; 8664 u8 xrqn[0x18]; 8665 8666 u8 reserved_at_60[0x10]; 8667 u8 lwm[0x10]; 8668 }; 8669 8670 struct mlx5_ifc_arm_xrc_srq_out_bits { 8671 u8 status[0x8]; 8672 u8 reserved_at_8[0x18]; 8673 8674 u8 syndrome[0x20]; 8675 8676 u8 reserved_at_40[0x40]; 8677 }; 8678 8679 enum { 8680 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8681 }; 8682 8683 struct mlx5_ifc_arm_xrc_srq_in_bits { 8684 u8 opcode[0x10]; 8685 u8 uid[0x10]; 8686 8687 u8 reserved_at_20[0x10]; 8688 u8 op_mod[0x10]; 8689 8690 u8 reserved_at_40[0x8]; 8691 u8 xrc_srqn[0x18]; 8692 8693 u8 reserved_at_60[0x10]; 8694 u8 lwm[0x10]; 8695 }; 8696 8697 struct mlx5_ifc_arm_rq_out_bits { 8698 u8 status[0x8]; 8699 u8 reserved_at_8[0x18]; 8700 8701 u8 syndrome[0x20]; 8702 8703 u8 reserved_at_40[0x40]; 8704 }; 8705 8706 enum { 8707 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8708 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8709 }; 8710 8711 struct mlx5_ifc_arm_rq_in_bits { 8712 u8 opcode[0x10]; 8713 u8 uid[0x10]; 8714 8715 u8 reserved_at_20[0x10]; 8716 u8 op_mod[0x10]; 8717 8718 u8 reserved_at_40[0x8]; 8719 u8 srq_number[0x18]; 8720 8721 u8 reserved_at_60[0x10]; 8722 u8 lwm[0x10]; 8723 }; 8724 8725 struct mlx5_ifc_arm_dct_out_bits { 8726 u8 status[0x8]; 8727 u8 reserved_at_8[0x18]; 8728 8729 u8 syndrome[0x20]; 8730 8731 u8 reserved_at_40[0x40]; 8732 }; 8733 8734 struct mlx5_ifc_arm_dct_in_bits { 8735 u8 opcode[0x10]; 8736 u8 reserved_at_10[0x10]; 8737 8738 u8 reserved_at_20[0x10]; 8739 u8 op_mod[0x10]; 8740 8741 u8 reserved_at_40[0x8]; 8742 u8 dct_number[0x18]; 8743 8744 u8 reserved_at_60[0x20]; 8745 }; 8746 8747 struct mlx5_ifc_alloc_xrcd_out_bits { 8748 u8 status[0x8]; 8749 u8 reserved_at_8[0x18]; 8750 8751 u8 syndrome[0x20]; 8752 8753 u8 reserved_at_40[0x8]; 8754 u8 xrcd[0x18]; 8755 8756 u8 reserved_at_60[0x20]; 8757 }; 8758 8759 struct mlx5_ifc_alloc_xrcd_in_bits { 8760 u8 opcode[0x10]; 8761 u8 uid[0x10]; 8762 8763 u8 reserved_at_20[0x10]; 8764 u8 op_mod[0x10]; 8765 8766 u8 reserved_at_40[0x40]; 8767 }; 8768 8769 struct mlx5_ifc_alloc_uar_out_bits { 8770 u8 status[0x8]; 8771 u8 reserved_at_8[0x18]; 8772 8773 u8 syndrome[0x20]; 8774 8775 u8 reserved_at_40[0x8]; 8776 u8 uar[0x18]; 8777 8778 u8 reserved_at_60[0x20]; 8779 }; 8780 8781 struct mlx5_ifc_alloc_uar_in_bits { 8782 u8 opcode[0x10]; 8783 u8 uid[0x10]; 8784 8785 u8 reserved_at_20[0x10]; 8786 u8 op_mod[0x10]; 8787 8788 u8 reserved_at_40[0x40]; 8789 }; 8790 8791 struct mlx5_ifc_alloc_transport_domain_out_bits { 8792 u8 status[0x8]; 8793 u8 reserved_at_8[0x18]; 8794 8795 u8 syndrome[0x20]; 8796 8797 u8 reserved_at_40[0x8]; 8798 u8 transport_domain[0x18]; 8799 8800 u8 reserved_at_60[0x20]; 8801 }; 8802 8803 struct mlx5_ifc_alloc_transport_domain_in_bits { 8804 u8 opcode[0x10]; 8805 u8 uid[0x10]; 8806 8807 u8 reserved_at_20[0x10]; 8808 u8 op_mod[0x10]; 8809 8810 u8 reserved_at_40[0x40]; 8811 }; 8812 8813 struct mlx5_ifc_alloc_q_counter_out_bits { 8814 u8 status[0x8]; 8815 u8 reserved_at_8[0x18]; 8816 8817 u8 syndrome[0x20]; 8818 8819 u8 reserved_at_40[0x18]; 8820 u8 counter_set_id[0x8]; 8821 8822 u8 reserved_at_60[0x20]; 8823 }; 8824 8825 struct mlx5_ifc_alloc_q_counter_in_bits { 8826 u8 opcode[0x10]; 8827 u8 uid[0x10]; 8828 8829 u8 reserved_at_20[0x10]; 8830 u8 op_mod[0x10]; 8831 8832 u8 reserved_at_40[0x40]; 8833 }; 8834 8835 struct mlx5_ifc_alloc_pd_out_bits { 8836 u8 status[0x8]; 8837 u8 reserved_at_8[0x18]; 8838 8839 u8 syndrome[0x20]; 8840 8841 u8 reserved_at_40[0x8]; 8842 u8 pd[0x18]; 8843 8844 u8 reserved_at_60[0x20]; 8845 }; 8846 8847 struct mlx5_ifc_alloc_pd_in_bits { 8848 u8 opcode[0x10]; 8849 u8 uid[0x10]; 8850 8851 u8 reserved_at_20[0x10]; 8852 u8 op_mod[0x10]; 8853 8854 u8 reserved_at_40[0x40]; 8855 }; 8856 8857 struct mlx5_ifc_alloc_flow_counter_out_bits { 8858 u8 status[0x8]; 8859 u8 reserved_at_8[0x18]; 8860 8861 u8 syndrome[0x20]; 8862 8863 u8 flow_counter_id[0x20]; 8864 8865 u8 reserved_at_60[0x20]; 8866 }; 8867 8868 struct mlx5_ifc_alloc_flow_counter_in_bits { 8869 u8 opcode[0x10]; 8870 u8 reserved_at_10[0x10]; 8871 8872 u8 reserved_at_20[0x10]; 8873 u8 op_mod[0x10]; 8874 8875 u8 reserved_at_40[0x38]; 8876 u8 flow_counter_bulk[0x8]; 8877 }; 8878 8879 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8880 u8 status[0x8]; 8881 u8 reserved_at_8[0x18]; 8882 8883 u8 syndrome[0x20]; 8884 8885 u8 reserved_at_40[0x40]; 8886 }; 8887 8888 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8889 u8 opcode[0x10]; 8890 u8 reserved_at_10[0x10]; 8891 8892 u8 reserved_at_20[0x10]; 8893 u8 op_mod[0x10]; 8894 8895 u8 reserved_at_40[0x20]; 8896 8897 u8 reserved_at_60[0x10]; 8898 u8 vxlan_udp_port[0x10]; 8899 }; 8900 8901 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8902 u8 status[0x8]; 8903 u8 reserved_at_8[0x18]; 8904 8905 u8 syndrome[0x20]; 8906 8907 u8 reserved_at_40[0x40]; 8908 }; 8909 8910 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8911 u8 rate_limit[0x20]; 8912 8913 u8 burst_upper_bound[0x20]; 8914 8915 u8 reserved_at_40[0x10]; 8916 u8 typical_packet_size[0x10]; 8917 8918 u8 reserved_at_60[0x120]; 8919 }; 8920 8921 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8922 u8 opcode[0x10]; 8923 u8 uid[0x10]; 8924 8925 u8 reserved_at_20[0x10]; 8926 u8 op_mod[0x10]; 8927 8928 u8 reserved_at_40[0x10]; 8929 u8 rate_limit_index[0x10]; 8930 8931 u8 reserved_at_60[0x20]; 8932 8933 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8934 }; 8935 8936 struct mlx5_ifc_access_register_out_bits { 8937 u8 status[0x8]; 8938 u8 reserved_at_8[0x18]; 8939 8940 u8 syndrome[0x20]; 8941 8942 u8 reserved_at_40[0x40]; 8943 8944 u8 register_data[][0x20]; 8945 }; 8946 8947 enum { 8948 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8949 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8950 }; 8951 8952 struct mlx5_ifc_access_register_in_bits { 8953 u8 opcode[0x10]; 8954 u8 reserved_at_10[0x10]; 8955 8956 u8 reserved_at_20[0x10]; 8957 u8 op_mod[0x10]; 8958 8959 u8 reserved_at_40[0x10]; 8960 u8 register_id[0x10]; 8961 8962 u8 argument[0x20]; 8963 8964 u8 register_data[][0x20]; 8965 }; 8966 8967 struct mlx5_ifc_sltp_reg_bits { 8968 u8 status[0x4]; 8969 u8 version[0x4]; 8970 u8 local_port[0x8]; 8971 u8 pnat[0x2]; 8972 u8 reserved_at_12[0x2]; 8973 u8 lane[0x4]; 8974 u8 reserved_at_18[0x8]; 8975 8976 u8 reserved_at_20[0x20]; 8977 8978 u8 reserved_at_40[0x7]; 8979 u8 polarity[0x1]; 8980 u8 ob_tap0[0x8]; 8981 u8 ob_tap1[0x8]; 8982 u8 ob_tap2[0x8]; 8983 8984 u8 reserved_at_60[0xc]; 8985 u8 ob_preemp_mode[0x4]; 8986 u8 ob_reg[0x8]; 8987 u8 ob_bias[0x8]; 8988 8989 u8 reserved_at_80[0x20]; 8990 }; 8991 8992 struct mlx5_ifc_slrg_reg_bits { 8993 u8 status[0x4]; 8994 u8 version[0x4]; 8995 u8 local_port[0x8]; 8996 u8 pnat[0x2]; 8997 u8 reserved_at_12[0x2]; 8998 u8 lane[0x4]; 8999 u8 reserved_at_18[0x8]; 9000 9001 u8 time_to_link_up[0x10]; 9002 u8 reserved_at_30[0xc]; 9003 u8 grade_lane_speed[0x4]; 9004 9005 u8 grade_version[0x8]; 9006 u8 grade[0x18]; 9007 9008 u8 reserved_at_60[0x4]; 9009 u8 height_grade_type[0x4]; 9010 u8 height_grade[0x18]; 9011 9012 u8 height_dz[0x10]; 9013 u8 height_dv[0x10]; 9014 9015 u8 reserved_at_a0[0x10]; 9016 u8 height_sigma[0x10]; 9017 9018 u8 reserved_at_c0[0x20]; 9019 9020 u8 reserved_at_e0[0x4]; 9021 u8 phase_grade_type[0x4]; 9022 u8 phase_grade[0x18]; 9023 9024 u8 reserved_at_100[0x8]; 9025 u8 phase_eo_pos[0x8]; 9026 u8 reserved_at_110[0x8]; 9027 u8 phase_eo_neg[0x8]; 9028 9029 u8 ffe_set_tested[0x10]; 9030 u8 test_errors_per_lane[0x10]; 9031 }; 9032 9033 struct mlx5_ifc_pvlc_reg_bits { 9034 u8 reserved_at_0[0x8]; 9035 u8 local_port[0x8]; 9036 u8 reserved_at_10[0x10]; 9037 9038 u8 reserved_at_20[0x1c]; 9039 u8 vl_hw_cap[0x4]; 9040 9041 u8 reserved_at_40[0x1c]; 9042 u8 vl_admin[0x4]; 9043 9044 u8 reserved_at_60[0x1c]; 9045 u8 vl_operational[0x4]; 9046 }; 9047 9048 struct mlx5_ifc_pude_reg_bits { 9049 u8 swid[0x8]; 9050 u8 local_port[0x8]; 9051 u8 reserved_at_10[0x4]; 9052 u8 admin_status[0x4]; 9053 u8 reserved_at_18[0x4]; 9054 u8 oper_status[0x4]; 9055 9056 u8 reserved_at_20[0x60]; 9057 }; 9058 9059 struct mlx5_ifc_ptys_reg_bits { 9060 u8 reserved_at_0[0x1]; 9061 u8 an_disable_admin[0x1]; 9062 u8 an_disable_cap[0x1]; 9063 u8 reserved_at_3[0x5]; 9064 u8 local_port[0x8]; 9065 u8 reserved_at_10[0xd]; 9066 u8 proto_mask[0x3]; 9067 9068 u8 an_status[0x4]; 9069 u8 reserved_at_24[0xc]; 9070 u8 data_rate_oper[0x10]; 9071 9072 u8 ext_eth_proto_capability[0x20]; 9073 9074 u8 eth_proto_capability[0x20]; 9075 9076 u8 ib_link_width_capability[0x10]; 9077 u8 ib_proto_capability[0x10]; 9078 9079 u8 ext_eth_proto_admin[0x20]; 9080 9081 u8 eth_proto_admin[0x20]; 9082 9083 u8 ib_link_width_admin[0x10]; 9084 u8 ib_proto_admin[0x10]; 9085 9086 u8 ext_eth_proto_oper[0x20]; 9087 9088 u8 eth_proto_oper[0x20]; 9089 9090 u8 ib_link_width_oper[0x10]; 9091 u8 ib_proto_oper[0x10]; 9092 9093 u8 reserved_at_160[0x1c]; 9094 u8 connector_type[0x4]; 9095 9096 u8 eth_proto_lp_advertise[0x20]; 9097 9098 u8 reserved_at_1a0[0x60]; 9099 }; 9100 9101 struct mlx5_ifc_mlcr_reg_bits { 9102 u8 reserved_at_0[0x8]; 9103 u8 local_port[0x8]; 9104 u8 reserved_at_10[0x20]; 9105 9106 u8 beacon_duration[0x10]; 9107 u8 reserved_at_40[0x10]; 9108 9109 u8 beacon_remain[0x10]; 9110 }; 9111 9112 struct mlx5_ifc_ptas_reg_bits { 9113 u8 reserved_at_0[0x20]; 9114 9115 u8 algorithm_options[0x10]; 9116 u8 reserved_at_30[0x4]; 9117 u8 repetitions_mode[0x4]; 9118 u8 num_of_repetitions[0x8]; 9119 9120 u8 grade_version[0x8]; 9121 u8 height_grade_type[0x4]; 9122 u8 phase_grade_type[0x4]; 9123 u8 height_grade_weight[0x8]; 9124 u8 phase_grade_weight[0x8]; 9125 9126 u8 gisim_measure_bits[0x10]; 9127 u8 adaptive_tap_measure_bits[0x10]; 9128 9129 u8 ber_bath_high_error_threshold[0x10]; 9130 u8 ber_bath_mid_error_threshold[0x10]; 9131 9132 u8 ber_bath_low_error_threshold[0x10]; 9133 u8 one_ratio_high_threshold[0x10]; 9134 9135 u8 one_ratio_high_mid_threshold[0x10]; 9136 u8 one_ratio_low_mid_threshold[0x10]; 9137 9138 u8 one_ratio_low_threshold[0x10]; 9139 u8 ndeo_error_threshold[0x10]; 9140 9141 u8 mixer_offset_step_size[0x10]; 9142 u8 reserved_at_110[0x8]; 9143 u8 mix90_phase_for_voltage_bath[0x8]; 9144 9145 u8 mixer_offset_start[0x10]; 9146 u8 mixer_offset_end[0x10]; 9147 9148 u8 reserved_at_140[0x15]; 9149 u8 ber_test_time[0xb]; 9150 }; 9151 9152 struct mlx5_ifc_pspa_reg_bits { 9153 u8 swid[0x8]; 9154 u8 local_port[0x8]; 9155 u8 sub_port[0x8]; 9156 u8 reserved_at_18[0x8]; 9157 9158 u8 reserved_at_20[0x20]; 9159 }; 9160 9161 struct mlx5_ifc_pqdr_reg_bits { 9162 u8 reserved_at_0[0x8]; 9163 u8 local_port[0x8]; 9164 u8 reserved_at_10[0x5]; 9165 u8 prio[0x3]; 9166 u8 reserved_at_18[0x6]; 9167 u8 mode[0x2]; 9168 9169 u8 reserved_at_20[0x20]; 9170 9171 u8 reserved_at_40[0x10]; 9172 u8 min_threshold[0x10]; 9173 9174 u8 reserved_at_60[0x10]; 9175 u8 max_threshold[0x10]; 9176 9177 u8 reserved_at_80[0x10]; 9178 u8 mark_probability_denominator[0x10]; 9179 9180 u8 reserved_at_a0[0x60]; 9181 }; 9182 9183 struct mlx5_ifc_ppsc_reg_bits { 9184 u8 reserved_at_0[0x8]; 9185 u8 local_port[0x8]; 9186 u8 reserved_at_10[0x10]; 9187 9188 u8 reserved_at_20[0x60]; 9189 9190 u8 reserved_at_80[0x1c]; 9191 u8 wrps_admin[0x4]; 9192 9193 u8 reserved_at_a0[0x1c]; 9194 u8 wrps_status[0x4]; 9195 9196 u8 reserved_at_c0[0x8]; 9197 u8 up_threshold[0x8]; 9198 u8 reserved_at_d0[0x8]; 9199 u8 down_threshold[0x8]; 9200 9201 u8 reserved_at_e0[0x20]; 9202 9203 u8 reserved_at_100[0x1c]; 9204 u8 srps_admin[0x4]; 9205 9206 u8 reserved_at_120[0x1c]; 9207 u8 srps_status[0x4]; 9208 9209 u8 reserved_at_140[0x40]; 9210 }; 9211 9212 struct mlx5_ifc_pplr_reg_bits { 9213 u8 reserved_at_0[0x8]; 9214 u8 local_port[0x8]; 9215 u8 reserved_at_10[0x10]; 9216 9217 u8 reserved_at_20[0x8]; 9218 u8 lb_cap[0x8]; 9219 u8 reserved_at_30[0x8]; 9220 u8 lb_en[0x8]; 9221 }; 9222 9223 struct mlx5_ifc_pplm_reg_bits { 9224 u8 reserved_at_0[0x8]; 9225 u8 local_port[0x8]; 9226 u8 reserved_at_10[0x10]; 9227 9228 u8 reserved_at_20[0x20]; 9229 9230 u8 port_profile_mode[0x8]; 9231 u8 static_port_profile[0x8]; 9232 u8 active_port_profile[0x8]; 9233 u8 reserved_at_58[0x8]; 9234 9235 u8 retransmission_active[0x8]; 9236 u8 fec_mode_active[0x18]; 9237 9238 u8 rs_fec_correction_bypass_cap[0x4]; 9239 u8 reserved_at_84[0x8]; 9240 u8 fec_override_cap_56g[0x4]; 9241 u8 fec_override_cap_100g[0x4]; 9242 u8 fec_override_cap_50g[0x4]; 9243 u8 fec_override_cap_25g[0x4]; 9244 u8 fec_override_cap_10g_40g[0x4]; 9245 9246 u8 rs_fec_correction_bypass_admin[0x4]; 9247 u8 reserved_at_a4[0x8]; 9248 u8 fec_override_admin_56g[0x4]; 9249 u8 fec_override_admin_100g[0x4]; 9250 u8 fec_override_admin_50g[0x4]; 9251 u8 fec_override_admin_25g[0x4]; 9252 u8 fec_override_admin_10g_40g[0x4]; 9253 9254 u8 fec_override_cap_400g_8x[0x10]; 9255 u8 fec_override_cap_200g_4x[0x10]; 9256 9257 u8 fec_override_cap_100g_2x[0x10]; 9258 u8 fec_override_cap_50g_1x[0x10]; 9259 9260 u8 fec_override_admin_400g_8x[0x10]; 9261 u8 fec_override_admin_200g_4x[0x10]; 9262 9263 u8 fec_override_admin_100g_2x[0x10]; 9264 u8 fec_override_admin_50g_1x[0x10]; 9265 9266 u8 reserved_at_140[0x140]; 9267 }; 9268 9269 struct mlx5_ifc_ppcnt_reg_bits { 9270 u8 swid[0x8]; 9271 u8 local_port[0x8]; 9272 u8 pnat[0x2]; 9273 u8 reserved_at_12[0x8]; 9274 u8 grp[0x6]; 9275 9276 u8 clr[0x1]; 9277 u8 reserved_at_21[0x1c]; 9278 u8 prio_tc[0x3]; 9279 9280 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9281 }; 9282 9283 struct mlx5_ifc_mpein_reg_bits { 9284 u8 reserved_at_0[0x2]; 9285 u8 depth[0x6]; 9286 u8 pcie_index[0x8]; 9287 u8 node[0x8]; 9288 u8 reserved_at_18[0x8]; 9289 9290 u8 capability_mask[0x20]; 9291 9292 u8 reserved_at_40[0x8]; 9293 u8 link_width_enabled[0x8]; 9294 u8 link_speed_enabled[0x10]; 9295 9296 u8 lane0_physical_position[0x8]; 9297 u8 link_width_active[0x8]; 9298 u8 link_speed_active[0x10]; 9299 9300 u8 num_of_pfs[0x10]; 9301 u8 num_of_vfs[0x10]; 9302 9303 u8 bdf0[0x10]; 9304 u8 reserved_at_b0[0x10]; 9305 9306 u8 max_read_request_size[0x4]; 9307 u8 max_payload_size[0x4]; 9308 u8 reserved_at_c8[0x5]; 9309 u8 pwr_status[0x3]; 9310 u8 port_type[0x4]; 9311 u8 reserved_at_d4[0xb]; 9312 u8 lane_reversal[0x1]; 9313 9314 u8 reserved_at_e0[0x14]; 9315 u8 pci_power[0xc]; 9316 9317 u8 reserved_at_100[0x20]; 9318 9319 u8 device_status[0x10]; 9320 u8 port_state[0x8]; 9321 u8 reserved_at_138[0x8]; 9322 9323 u8 reserved_at_140[0x10]; 9324 u8 receiver_detect_result[0x10]; 9325 9326 u8 reserved_at_160[0x20]; 9327 }; 9328 9329 struct mlx5_ifc_mpcnt_reg_bits { 9330 u8 reserved_at_0[0x8]; 9331 u8 pcie_index[0x8]; 9332 u8 reserved_at_10[0xa]; 9333 u8 grp[0x6]; 9334 9335 u8 clr[0x1]; 9336 u8 reserved_at_21[0x1f]; 9337 9338 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9339 }; 9340 9341 struct mlx5_ifc_ppad_reg_bits { 9342 u8 reserved_at_0[0x3]; 9343 u8 single_mac[0x1]; 9344 u8 reserved_at_4[0x4]; 9345 u8 local_port[0x8]; 9346 u8 mac_47_32[0x10]; 9347 9348 u8 mac_31_0[0x20]; 9349 9350 u8 reserved_at_40[0x40]; 9351 }; 9352 9353 struct mlx5_ifc_pmtu_reg_bits { 9354 u8 reserved_at_0[0x8]; 9355 u8 local_port[0x8]; 9356 u8 reserved_at_10[0x10]; 9357 9358 u8 max_mtu[0x10]; 9359 u8 reserved_at_30[0x10]; 9360 9361 u8 admin_mtu[0x10]; 9362 u8 reserved_at_50[0x10]; 9363 9364 u8 oper_mtu[0x10]; 9365 u8 reserved_at_70[0x10]; 9366 }; 9367 9368 struct mlx5_ifc_pmpr_reg_bits { 9369 u8 reserved_at_0[0x8]; 9370 u8 module[0x8]; 9371 u8 reserved_at_10[0x10]; 9372 9373 u8 reserved_at_20[0x18]; 9374 u8 attenuation_5g[0x8]; 9375 9376 u8 reserved_at_40[0x18]; 9377 u8 attenuation_7g[0x8]; 9378 9379 u8 reserved_at_60[0x18]; 9380 u8 attenuation_12g[0x8]; 9381 }; 9382 9383 struct mlx5_ifc_pmpe_reg_bits { 9384 u8 reserved_at_0[0x8]; 9385 u8 module[0x8]; 9386 u8 reserved_at_10[0xc]; 9387 u8 module_status[0x4]; 9388 9389 u8 reserved_at_20[0x60]; 9390 }; 9391 9392 struct mlx5_ifc_pmpc_reg_bits { 9393 u8 module_state_updated[32][0x8]; 9394 }; 9395 9396 struct mlx5_ifc_pmlpn_reg_bits { 9397 u8 reserved_at_0[0x4]; 9398 u8 mlpn_status[0x4]; 9399 u8 local_port[0x8]; 9400 u8 reserved_at_10[0x10]; 9401 9402 u8 e[0x1]; 9403 u8 reserved_at_21[0x1f]; 9404 }; 9405 9406 struct mlx5_ifc_pmlp_reg_bits { 9407 u8 rxtx[0x1]; 9408 u8 reserved_at_1[0x7]; 9409 u8 local_port[0x8]; 9410 u8 reserved_at_10[0x8]; 9411 u8 width[0x8]; 9412 9413 u8 lane0_module_mapping[0x20]; 9414 9415 u8 lane1_module_mapping[0x20]; 9416 9417 u8 lane2_module_mapping[0x20]; 9418 9419 u8 lane3_module_mapping[0x20]; 9420 9421 u8 reserved_at_a0[0x160]; 9422 }; 9423 9424 struct mlx5_ifc_pmaos_reg_bits { 9425 u8 reserved_at_0[0x8]; 9426 u8 module[0x8]; 9427 u8 reserved_at_10[0x4]; 9428 u8 admin_status[0x4]; 9429 u8 reserved_at_18[0x4]; 9430 u8 oper_status[0x4]; 9431 9432 u8 ase[0x1]; 9433 u8 ee[0x1]; 9434 u8 reserved_at_22[0x1c]; 9435 u8 e[0x2]; 9436 9437 u8 reserved_at_40[0x40]; 9438 }; 9439 9440 struct mlx5_ifc_plpc_reg_bits { 9441 u8 reserved_at_0[0x4]; 9442 u8 profile_id[0xc]; 9443 u8 reserved_at_10[0x4]; 9444 u8 proto_mask[0x4]; 9445 u8 reserved_at_18[0x8]; 9446 9447 u8 reserved_at_20[0x10]; 9448 u8 lane_speed[0x10]; 9449 9450 u8 reserved_at_40[0x17]; 9451 u8 lpbf[0x1]; 9452 u8 fec_mode_policy[0x8]; 9453 9454 u8 retransmission_capability[0x8]; 9455 u8 fec_mode_capability[0x18]; 9456 9457 u8 retransmission_support_admin[0x8]; 9458 u8 fec_mode_support_admin[0x18]; 9459 9460 u8 retransmission_request_admin[0x8]; 9461 u8 fec_mode_request_admin[0x18]; 9462 9463 u8 reserved_at_c0[0x80]; 9464 }; 9465 9466 struct mlx5_ifc_plib_reg_bits { 9467 u8 reserved_at_0[0x8]; 9468 u8 local_port[0x8]; 9469 u8 reserved_at_10[0x8]; 9470 u8 ib_port[0x8]; 9471 9472 u8 reserved_at_20[0x60]; 9473 }; 9474 9475 struct mlx5_ifc_plbf_reg_bits { 9476 u8 reserved_at_0[0x8]; 9477 u8 local_port[0x8]; 9478 u8 reserved_at_10[0xd]; 9479 u8 lbf_mode[0x3]; 9480 9481 u8 reserved_at_20[0x20]; 9482 }; 9483 9484 struct mlx5_ifc_pipg_reg_bits { 9485 u8 reserved_at_0[0x8]; 9486 u8 local_port[0x8]; 9487 u8 reserved_at_10[0x10]; 9488 9489 u8 dic[0x1]; 9490 u8 reserved_at_21[0x19]; 9491 u8 ipg[0x4]; 9492 u8 reserved_at_3e[0x2]; 9493 }; 9494 9495 struct mlx5_ifc_pifr_reg_bits { 9496 u8 reserved_at_0[0x8]; 9497 u8 local_port[0x8]; 9498 u8 reserved_at_10[0x10]; 9499 9500 u8 reserved_at_20[0xe0]; 9501 9502 u8 port_filter[8][0x20]; 9503 9504 u8 port_filter_update_en[8][0x20]; 9505 }; 9506 9507 struct mlx5_ifc_pfcc_reg_bits { 9508 u8 reserved_at_0[0x8]; 9509 u8 local_port[0x8]; 9510 u8 reserved_at_10[0xb]; 9511 u8 ppan_mask_n[0x1]; 9512 u8 minor_stall_mask[0x1]; 9513 u8 critical_stall_mask[0x1]; 9514 u8 reserved_at_1e[0x2]; 9515 9516 u8 ppan[0x4]; 9517 u8 reserved_at_24[0x4]; 9518 u8 prio_mask_tx[0x8]; 9519 u8 reserved_at_30[0x8]; 9520 u8 prio_mask_rx[0x8]; 9521 9522 u8 pptx[0x1]; 9523 u8 aptx[0x1]; 9524 u8 pptx_mask_n[0x1]; 9525 u8 reserved_at_43[0x5]; 9526 u8 pfctx[0x8]; 9527 u8 reserved_at_50[0x10]; 9528 9529 u8 pprx[0x1]; 9530 u8 aprx[0x1]; 9531 u8 pprx_mask_n[0x1]; 9532 u8 reserved_at_63[0x5]; 9533 u8 pfcrx[0x8]; 9534 u8 reserved_at_70[0x10]; 9535 9536 u8 device_stall_minor_watermark[0x10]; 9537 u8 device_stall_critical_watermark[0x10]; 9538 9539 u8 reserved_at_a0[0x60]; 9540 }; 9541 9542 struct mlx5_ifc_pelc_reg_bits { 9543 u8 op[0x4]; 9544 u8 reserved_at_4[0x4]; 9545 u8 local_port[0x8]; 9546 u8 reserved_at_10[0x10]; 9547 9548 u8 op_admin[0x8]; 9549 u8 op_capability[0x8]; 9550 u8 op_request[0x8]; 9551 u8 op_active[0x8]; 9552 9553 u8 admin[0x40]; 9554 9555 u8 capability[0x40]; 9556 9557 u8 request[0x40]; 9558 9559 u8 active[0x40]; 9560 9561 u8 reserved_at_140[0x80]; 9562 }; 9563 9564 struct mlx5_ifc_peir_reg_bits { 9565 u8 reserved_at_0[0x8]; 9566 u8 local_port[0x8]; 9567 u8 reserved_at_10[0x10]; 9568 9569 u8 reserved_at_20[0xc]; 9570 u8 error_count[0x4]; 9571 u8 reserved_at_30[0x10]; 9572 9573 u8 reserved_at_40[0xc]; 9574 u8 lane[0x4]; 9575 u8 reserved_at_50[0x8]; 9576 u8 error_type[0x8]; 9577 }; 9578 9579 struct mlx5_ifc_mpegc_reg_bits { 9580 u8 reserved_at_0[0x30]; 9581 u8 field_select[0x10]; 9582 9583 u8 tx_overflow_sense[0x1]; 9584 u8 mark_cqe[0x1]; 9585 u8 mark_cnp[0x1]; 9586 u8 reserved_at_43[0x1b]; 9587 u8 tx_lossy_overflow_oper[0x2]; 9588 9589 u8 reserved_at_60[0x100]; 9590 }; 9591 9592 enum { 9593 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9594 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9595 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9596 }; 9597 9598 struct mlx5_ifc_mtutc_reg_bits { 9599 u8 reserved_at_0[0x1c]; 9600 u8 operation[0x4]; 9601 9602 u8 freq_adjustment[0x20]; 9603 9604 u8 reserved_at_40[0x40]; 9605 9606 u8 utc_sec[0x20]; 9607 9608 u8 reserved_at_a0[0x2]; 9609 u8 utc_nsec[0x1e]; 9610 9611 u8 time_adjustment[0x20]; 9612 }; 9613 9614 struct mlx5_ifc_pcam_enhanced_features_bits { 9615 u8 reserved_at_0[0x68]; 9616 u8 fec_50G_per_lane_in_pplm[0x1]; 9617 u8 reserved_at_69[0x4]; 9618 u8 rx_icrc_encapsulated_counter[0x1]; 9619 u8 reserved_at_6e[0x4]; 9620 u8 ptys_extended_ethernet[0x1]; 9621 u8 reserved_at_73[0x3]; 9622 u8 pfcc_mask[0x1]; 9623 u8 reserved_at_77[0x3]; 9624 u8 per_lane_error_counters[0x1]; 9625 u8 rx_buffer_fullness_counters[0x1]; 9626 u8 ptys_connector_type[0x1]; 9627 u8 reserved_at_7d[0x1]; 9628 u8 ppcnt_discard_group[0x1]; 9629 u8 ppcnt_statistical_group[0x1]; 9630 }; 9631 9632 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9633 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9634 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9635 9636 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9637 u8 pplm[0x1]; 9638 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9639 9640 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9641 u8 pbmc[0x1]; 9642 u8 pptb[0x1]; 9643 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9644 u8 ppcnt[0x1]; 9645 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9646 }; 9647 9648 struct mlx5_ifc_pcam_reg_bits { 9649 u8 reserved_at_0[0x8]; 9650 u8 feature_group[0x8]; 9651 u8 reserved_at_10[0x8]; 9652 u8 access_reg_group[0x8]; 9653 9654 u8 reserved_at_20[0x20]; 9655 9656 union { 9657 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9658 u8 reserved_at_0[0x80]; 9659 } port_access_reg_cap_mask; 9660 9661 u8 reserved_at_c0[0x80]; 9662 9663 union { 9664 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9665 u8 reserved_at_0[0x80]; 9666 } feature_cap_mask; 9667 9668 u8 reserved_at_1c0[0xc0]; 9669 }; 9670 9671 struct mlx5_ifc_mcam_enhanced_features_bits { 9672 u8 reserved_at_0[0x6b]; 9673 u8 ptpcyc2realtime_modify[0x1]; 9674 u8 reserved_at_6c[0x2]; 9675 u8 pci_status_and_power[0x1]; 9676 u8 reserved_at_6f[0x5]; 9677 u8 mark_tx_action_cnp[0x1]; 9678 u8 mark_tx_action_cqe[0x1]; 9679 u8 dynamic_tx_overflow[0x1]; 9680 u8 reserved_at_77[0x4]; 9681 u8 pcie_outbound_stalled[0x1]; 9682 u8 tx_overflow_buffer_pkt[0x1]; 9683 u8 mtpps_enh_out_per_adj[0x1]; 9684 u8 mtpps_fs[0x1]; 9685 u8 pcie_performance_group[0x1]; 9686 }; 9687 9688 struct mlx5_ifc_mcam_access_reg_bits { 9689 u8 reserved_at_0[0x1c]; 9690 u8 mcda[0x1]; 9691 u8 mcc[0x1]; 9692 u8 mcqi[0x1]; 9693 u8 mcqs[0x1]; 9694 9695 u8 regs_95_to_87[0x9]; 9696 u8 mpegc[0x1]; 9697 u8 mtutc[0x1]; 9698 u8 regs_84_to_68[0x11]; 9699 u8 tracer_registers[0x4]; 9700 9701 u8 regs_63_to_32[0x20]; 9702 u8 regs_31_to_0[0x20]; 9703 }; 9704 9705 struct mlx5_ifc_mcam_access_reg_bits1 { 9706 u8 regs_127_to_96[0x20]; 9707 9708 u8 regs_95_to_64[0x20]; 9709 9710 u8 regs_63_to_32[0x20]; 9711 9712 u8 regs_31_to_0[0x20]; 9713 }; 9714 9715 struct mlx5_ifc_mcam_access_reg_bits2 { 9716 u8 regs_127_to_99[0x1d]; 9717 u8 mirc[0x1]; 9718 u8 regs_97_to_96[0x2]; 9719 9720 u8 regs_95_to_64[0x20]; 9721 9722 u8 regs_63_to_32[0x20]; 9723 9724 u8 regs_31_to_0[0x20]; 9725 }; 9726 9727 struct mlx5_ifc_mcam_reg_bits { 9728 u8 reserved_at_0[0x8]; 9729 u8 feature_group[0x8]; 9730 u8 reserved_at_10[0x8]; 9731 u8 access_reg_group[0x8]; 9732 9733 u8 reserved_at_20[0x20]; 9734 9735 union { 9736 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9737 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9738 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9739 u8 reserved_at_0[0x80]; 9740 } mng_access_reg_cap_mask; 9741 9742 u8 reserved_at_c0[0x80]; 9743 9744 union { 9745 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9746 u8 reserved_at_0[0x80]; 9747 } mng_feature_cap_mask; 9748 9749 u8 reserved_at_1c0[0x80]; 9750 }; 9751 9752 struct mlx5_ifc_qcam_access_reg_cap_mask { 9753 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9754 u8 qpdpm[0x1]; 9755 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9756 u8 qdpm[0x1]; 9757 u8 qpts[0x1]; 9758 u8 qcap[0x1]; 9759 u8 qcam_access_reg_cap_mask_0[0x1]; 9760 }; 9761 9762 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9763 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9764 u8 qpts_trust_both[0x1]; 9765 }; 9766 9767 struct mlx5_ifc_qcam_reg_bits { 9768 u8 reserved_at_0[0x8]; 9769 u8 feature_group[0x8]; 9770 u8 reserved_at_10[0x8]; 9771 u8 access_reg_group[0x8]; 9772 u8 reserved_at_20[0x20]; 9773 9774 union { 9775 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9776 u8 reserved_at_0[0x80]; 9777 } qos_access_reg_cap_mask; 9778 9779 u8 reserved_at_c0[0x80]; 9780 9781 union { 9782 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9783 u8 reserved_at_0[0x80]; 9784 } qos_feature_cap_mask; 9785 9786 u8 reserved_at_1c0[0x80]; 9787 }; 9788 9789 struct mlx5_ifc_core_dump_reg_bits { 9790 u8 reserved_at_0[0x18]; 9791 u8 core_dump_type[0x8]; 9792 9793 u8 reserved_at_20[0x30]; 9794 u8 vhca_id[0x10]; 9795 9796 u8 reserved_at_60[0x8]; 9797 u8 qpn[0x18]; 9798 u8 reserved_at_80[0x180]; 9799 }; 9800 9801 struct mlx5_ifc_pcap_reg_bits { 9802 u8 reserved_at_0[0x8]; 9803 u8 local_port[0x8]; 9804 u8 reserved_at_10[0x10]; 9805 9806 u8 port_capability_mask[4][0x20]; 9807 }; 9808 9809 struct mlx5_ifc_paos_reg_bits { 9810 u8 swid[0x8]; 9811 u8 local_port[0x8]; 9812 u8 reserved_at_10[0x4]; 9813 u8 admin_status[0x4]; 9814 u8 reserved_at_18[0x4]; 9815 u8 oper_status[0x4]; 9816 9817 u8 ase[0x1]; 9818 u8 ee[0x1]; 9819 u8 reserved_at_22[0x1c]; 9820 u8 e[0x2]; 9821 9822 u8 reserved_at_40[0x40]; 9823 }; 9824 9825 struct mlx5_ifc_pamp_reg_bits { 9826 u8 reserved_at_0[0x8]; 9827 u8 opamp_group[0x8]; 9828 u8 reserved_at_10[0xc]; 9829 u8 opamp_group_type[0x4]; 9830 9831 u8 start_index[0x10]; 9832 u8 reserved_at_30[0x4]; 9833 u8 num_of_indices[0xc]; 9834 9835 u8 index_data[18][0x10]; 9836 }; 9837 9838 struct mlx5_ifc_pcmr_reg_bits { 9839 u8 reserved_at_0[0x8]; 9840 u8 local_port[0x8]; 9841 u8 reserved_at_10[0x10]; 9842 9843 u8 entropy_force_cap[0x1]; 9844 u8 entropy_calc_cap[0x1]; 9845 u8 entropy_gre_calc_cap[0x1]; 9846 u8 reserved_at_23[0xf]; 9847 u8 rx_ts_over_crc_cap[0x1]; 9848 u8 reserved_at_33[0xb]; 9849 u8 fcs_cap[0x1]; 9850 u8 reserved_at_3f[0x1]; 9851 9852 u8 entropy_force[0x1]; 9853 u8 entropy_calc[0x1]; 9854 u8 entropy_gre_calc[0x1]; 9855 u8 reserved_at_43[0xf]; 9856 u8 rx_ts_over_crc[0x1]; 9857 u8 reserved_at_53[0xb]; 9858 u8 fcs_chk[0x1]; 9859 u8 reserved_at_5f[0x1]; 9860 }; 9861 9862 struct mlx5_ifc_lane_2_module_mapping_bits { 9863 u8 reserved_at_0[0x6]; 9864 u8 rx_lane[0x2]; 9865 u8 reserved_at_8[0x6]; 9866 u8 tx_lane[0x2]; 9867 u8 reserved_at_10[0x8]; 9868 u8 module[0x8]; 9869 }; 9870 9871 struct mlx5_ifc_bufferx_reg_bits { 9872 u8 reserved_at_0[0x6]; 9873 u8 lossy[0x1]; 9874 u8 epsb[0x1]; 9875 u8 reserved_at_8[0xc]; 9876 u8 size[0xc]; 9877 9878 u8 xoff_threshold[0x10]; 9879 u8 xon_threshold[0x10]; 9880 }; 9881 9882 struct mlx5_ifc_set_node_in_bits { 9883 u8 node_description[64][0x8]; 9884 }; 9885 9886 struct mlx5_ifc_register_power_settings_bits { 9887 u8 reserved_at_0[0x18]; 9888 u8 power_settings_level[0x8]; 9889 9890 u8 reserved_at_20[0x60]; 9891 }; 9892 9893 struct mlx5_ifc_register_host_endianness_bits { 9894 u8 he[0x1]; 9895 u8 reserved_at_1[0x1f]; 9896 9897 u8 reserved_at_20[0x60]; 9898 }; 9899 9900 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9901 u8 reserved_at_0[0x20]; 9902 9903 u8 mkey[0x20]; 9904 9905 u8 addressh_63_32[0x20]; 9906 9907 u8 addressl_31_0[0x20]; 9908 }; 9909 9910 struct mlx5_ifc_ud_adrs_vector_bits { 9911 u8 dc_key[0x40]; 9912 9913 u8 ext[0x1]; 9914 u8 reserved_at_41[0x7]; 9915 u8 destination_qp_dct[0x18]; 9916 9917 u8 static_rate[0x4]; 9918 u8 sl_eth_prio[0x4]; 9919 u8 fl[0x1]; 9920 u8 mlid[0x7]; 9921 u8 rlid_udp_sport[0x10]; 9922 9923 u8 reserved_at_80[0x20]; 9924 9925 u8 rmac_47_16[0x20]; 9926 9927 u8 rmac_15_0[0x10]; 9928 u8 tclass[0x8]; 9929 u8 hop_limit[0x8]; 9930 9931 u8 reserved_at_e0[0x1]; 9932 u8 grh[0x1]; 9933 u8 reserved_at_e2[0x2]; 9934 u8 src_addr_index[0x8]; 9935 u8 flow_label[0x14]; 9936 9937 u8 rgid_rip[16][0x8]; 9938 }; 9939 9940 struct mlx5_ifc_pages_req_event_bits { 9941 u8 reserved_at_0[0x10]; 9942 u8 function_id[0x10]; 9943 9944 u8 num_pages[0x20]; 9945 9946 u8 reserved_at_40[0xa0]; 9947 }; 9948 9949 struct mlx5_ifc_eqe_bits { 9950 u8 reserved_at_0[0x8]; 9951 u8 event_type[0x8]; 9952 u8 reserved_at_10[0x8]; 9953 u8 event_sub_type[0x8]; 9954 9955 u8 reserved_at_20[0xe0]; 9956 9957 union mlx5_ifc_event_auto_bits event_data; 9958 9959 u8 reserved_at_1e0[0x10]; 9960 u8 signature[0x8]; 9961 u8 reserved_at_1f8[0x7]; 9962 u8 owner[0x1]; 9963 }; 9964 9965 enum { 9966 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9967 }; 9968 9969 struct mlx5_ifc_cmd_queue_entry_bits { 9970 u8 type[0x8]; 9971 u8 reserved_at_8[0x18]; 9972 9973 u8 input_length[0x20]; 9974 9975 u8 input_mailbox_pointer_63_32[0x20]; 9976 9977 u8 input_mailbox_pointer_31_9[0x17]; 9978 u8 reserved_at_77[0x9]; 9979 9980 u8 command_input_inline_data[16][0x8]; 9981 9982 u8 command_output_inline_data[16][0x8]; 9983 9984 u8 output_mailbox_pointer_63_32[0x20]; 9985 9986 u8 output_mailbox_pointer_31_9[0x17]; 9987 u8 reserved_at_1b7[0x9]; 9988 9989 u8 output_length[0x20]; 9990 9991 u8 token[0x8]; 9992 u8 signature[0x8]; 9993 u8 reserved_at_1f0[0x8]; 9994 u8 status[0x7]; 9995 u8 ownership[0x1]; 9996 }; 9997 9998 struct mlx5_ifc_cmd_out_bits { 9999 u8 status[0x8]; 10000 u8 reserved_at_8[0x18]; 10001 10002 u8 syndrome[0x20]; 10003 10004 u8 command_output[0x20]; 10005 }; 10006 10007 struct mlx5_ifc_cmd_in_bits { 10008 u8 opcode[0x10]; 10009 u8 reserved_at_10[0x10]; 10010 10011 u8 reserved_at_20[0x10]; 10012 u8 op_mod[0x10]; 10013 10014 u8 command[][0x20]; 10015 }; 10016 10017 struct mlx5_ifc_cmd_if_box_bits { 10018 u8 mailbox_data[512][0x8]; 10019 10020 u8 reserved_at_1000[0x180]; 10021 10022 u8 next_pointer_63_32[0x20]; 10023 10024 u8 next_pointer_31_10[0x16]; 10025 u8 reserved_at_11b6[0xa]; 10026 10027 u8 block_number[0x20]; 10028 10029 u8 reserved_at_11e0[0x8]; 10030 u8 token[0x8]; 10031 u8 ctrl_signature[0x8]; 10032 u8 signature[0x8]; 10033 }; 10034 10035 struct mlx5_ifc_mtt_bits { 10036 u8 ptag_63_32[0x20]; 10037 10038 u8 ptag_31_8[0x18]; 10039 u8 reserved_at_38[0x6]; 10040 u8 wr_en[0x1]; 10041 u8 rd_en[0x1]; 10042 }; 10043 10044 struct mlx5_ifc_query_wol_rol_out_bits { 10045 u8 status[0x8]; 10046 u8 reserved_at_8[0x18]; 10047 10048 u8 syndrome[0x20]; 10049 10050 u8 reserved_at_40[0x10]; 10051 u8 rol_mode[0x8]; 10052 u8 wol_mode[0x8]; 10053 10054 u8 reserved_at_60[0x20]; 10055 }; 10056 10057 struct mlx5_ifc_query_wol_rol_in_bits { 10058 u8 opcode[0x10]; 10059 u8 reserved_at_10[0x10]; 10060 10061 u8 reserved_at_20[0x10]; 10062 u8 op_mod[0x10]; 10063 10064 u8 reserved_at_40[0x40]; 10065 }; 10066 10067 struct mlx5_ifc_set_wol_rol_out_bits { 10068 u8 status[0x8]; 10069 u8 reserved_at_8[0x18]; 10070 10071 u8 syndrome[0x20]; 10072 10073 u8 reserved_at_40[0x40]; 10074 }; 10075 10076 struct mlx5_ifc_set_wol_rol_in_bits { 10077 u8 opcode[0x10]; 10078 u8 reserved_at_10[0x10]; 10079 10080 u8 reserved_at_20[0x10]; 10081 u8 op_mod[0x10]; 10082 10083 u8 rol_mode_valid[0x1]; 10084 u8 wol_mode_valid[0x1]; 10085 u8 reserved_at_42[0xe]; 10086 u8 rol_mode[0x8]; 10087 u8 wol_mode[0x8]; 10088 10089 u8 reserved_at_60[0x20]; 10090 }; 10091 10092 enum { 10093 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10094 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10095 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10096 }; 10097 10098 enum { 10099 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10100 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10101 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10102 }; 10103 10104 enum { 10105 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10106 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10107 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10108 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10109 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10110 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10111 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10112 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10113 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10114 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10115 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10116 }; 10117 10118 struct mlx5_ifc_initial_seg_bits { 10119 u8 fw_rev_minor[0x10]; 10120 u8 fw_rev_major[0x10]; 10121 10122 u8 cmd_interface_rev[0x10]; 10123 u8 fw_rev_subminor[0x10]; 10124 10125 u8 reserved_at_40[0x40]; 10126 10127 u8 cmdq_phy_addr_63_32[0x20]; 10128 10129 u8 cmdq_phy_addr_31_12[0x14]; 10130 u8 reserved_at_b4[0x2]; 10131 u8 nic_interface[0x2]; 10132 u8 log_cmdq_size[0x4]; 10133 u8 log_cmdq_stride[0x4]; 10134 10135 u8 command_doorbell_vector[0x20]; 10136 10137 u8 reserved_at_e0[0xf00]; 10138 10139 u8 initializing[0x1]; 10140 u8 reserved_at_fe1[0x4]; 10141 u8 nic_interface_supported[0x3]; 10142 u8 embedded_cpu[0x1]; 10143 u8 reserved_at_fe9[0x17]; 10144 10145 struct mlx5_ifc_health_buffer_bits health_buffer; 10146 10147 u8 no_dram_nic_offset[0x20]; 10148 10149 u8 reserved_at_1220[0x6e40]; 10150 10151 u8 reserved_at_8060[0x1f]; 10152 u8 clear_int[0x1]; 10153 10154 u8 health_syndrome[0x8]; 10155 u8 health_counter[0x18]; 10156 10157 u8 reserved_at_80a0[0x17fc0]; 10158 }; 10159 10160 struct mlx5_ifc_mtpps_reg_bits { 10161 u8 reserved_at_0[0xc]; 10162 u8 cap_number_of_pps_pins[0x4]; 10163 u8 reserved_at_10[0x4]; 10164 u8 cap_max_num_of_pps_in_pins[0x4]; 10165 u8 reserved_at_18[0x4]; 10166 u8 cap_max_num_of_pps_out_pins[0x4]; 10167 10168 u8 reserved_at_20[0x24]; 10169 u8 cap_pin_3_mode[0x4]; 10170 u8 reserved_at_48[0x4]; 10171 u8 cap_pin_2_mode[0x4]; 10172 u8 reserved_at_50[0x4]; 10173 u8 cap_pin_1_mode[0x4]; 10174 u8 reserved_at_58[0x4]; 10175 u8 cap_pin_0_mode[0x4]; 10176 10177 u8 reserved_at_60[0x4]; 10178 u8 cap_pin_7_mode[0x4]; 10179 u8 reserved_at_68[0x4]; 10180 u8 cap_pin_6_mode[0x4]; 10181 u8 reserved_at_70[0x4]; 10182 u8 cap_pin_5_mode[0x4]; 10183 u8 reserved_at_78[0x4]; 10184 u8 cap_pin_4_mode[0x4]; 10185 10186 u8 field_select[0x20]; 10187 u8 reserved_at_a0[0x60]; 10188 10189 u8 enable[0x1]; 10190 u8 reserved_at_101[0xb]; 10191 u8 pattern[0x4]; 10192 u8 reserved_at_110[0x4]; 10193 u8 pin_mode[0x4]; 10194 u8 pin[0x8]; 10195 10196 u8 reserved_at_120[0x20]; 10197 10198 u8 time_stamp[0x40]; 10199 10200 u8 out_pulse_duration[0x10]; 10201 u8 out_periodic_adjustment[0x10]; 10202 u8 enhanced_out_periodic_adjustment[0x20]; 10203 10204 u8 reserved_at_1c0[0x20]; 10205 }; 10206 10207 struct mlx5_ifc_mtppse_reg_bits { 10208 u8 reserved_at_0[0x18]; 10209 u8 pin[0x8]; 10210 u8 event_arm[0x1]; 10211 u8 reserved_at_21[0x1b]; 10212 u8 event_generation_mode[0x4]; 10213 u8 reserved_at_40[0x40]; 10214 }; 10215 10216 struct mlx5_ifc_mcqs_reg_bits { 10217 u8 last_index_flag[0x1]; 10218 u8 reserved_at_1[0x7]; 10219 u8 fw_device[0x8]; 10220 u8 component_index[0x10]; 10221 10222 u8 reserved_at_20[0x10]; 10223 u8 identifier[0x10]; 10224 10225 u8 reserved_at_40[0x17]; 10226 u8 component_status[0x5]; 10227 u8 component_update_state[0x4]; 10228 10229 u8 last_update_state_changer_type[0x4]; 10230 u8 last_update_state_changer_host_id[0x4]; 10231 u8 reserved_at_68[0x18]; 10232 }; 10233 10234 struct mlx5_ifc_mcqi_cap_bits { 10235 u8 supported_info_bitmask[0x20]; 10236 10237 u8 component_size[0x20]; 10238 10239 u8 max_component_size[0x20]; 10240 10241 u8 log_mcda_word_size[0x4]; 10242 u8 reserved_at_64[0xc]; 10243 u8 mcda_max_write_size[0x10]; 10244 10245 u8 rd_en[0x1]; 10246 u8 reserved_at_81[0x1]; 10247 u8 match_chip_id[0x1]; 10248 u8 match_psid[0x1]; 10249 u8 check_user_timestamp[0x1]; 10250 u8 match_base_guid_mac[0x1]; 10251 u8 reserved_at_86[0x1a]; 10252 }; 10253 10254 struct mlx5_ifc_mcqi_version_bits { 10255 u8 reserved_at_0[0x2]; 10256 u8 build_time_valid[0x1]; 10257 u8 user_defined_time_valid[0x1]; 10258 u8 reserved_at_4[0x14]; 10259 u8 version_string_length[0x8]; 10260 10261 u8 version[0x20]; 10262 10263 u8 build_time[0x40]; 10264 10265 u8 user_defined_time[0x40]; 10266 10267 u8 build_tool_version[0x20]; 10268 10269 u8 reserved_at_e0[0x20]; 10270 10271 u8 version_string[92][0x8]; 10272 }; 10273 10274 struct mlx5_ifc_mcqi_activation_method_bits { 10275 u8 pending_server_ac_power_cycle[0x1]; 10276 u8 pending_server_dc_power_cycle[0x1]; 10277 u8 pending_server_reboot[0x1]; 10278 u8 pending_fw_reset[0x1]; 10279 u8 auto_activate[0x1]; 10280 u8 all_hosts_sync[0x1]; 10281 u8 device_hw_reset[0x1]; 10282 u8 reserved_at_7[0x19]; 10283 }; 10284 10285 union mlx5_ifc_mcqi_reg_data_bits { 10286 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10287 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10288 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10289 }; 10290 10291 struct mlx5_ifc_mcqi_reg_bits { 10292 u8 read_pending_component[0x1]; 10293 u8 reserved_at_1[0xf]; 10294 u8 component_index[0x10]; 10295 10296 u8 reserved_at_20[0x20]; 10297 10298 u8 reserved_at_40[0x1b]; 10299 u8 info_type[0x5]; 10300 10301 u8 info_size[0x20]; 10302 10303 u8 offset[0x20]; 10304 10305 u8 reserved_at_a0[0x10]; 10306 u8 data_size[0x10]; 10307 10308 union mlx5_ifc_mcqi_reg_data_bits data[]; 10309 }; 10310 10311 struct mlx5_ifc_mcc_reg_bits { 10312 u8 reserved_at_0[0x4]; 10313 u8 time_elapsed_since_last_cmd[0xc]; 10314 u8 reserved_at_10[0x8]; 10315 u8 instruction[0x8]; 10316 10317 u8 reserved_at_20[0x10]; 10318 u8 component_index[0x10]; 10319 10320 u8 reserved_at_40[0x8]; 10321 u8 update_handle[0x18]; 10322 10323 u8 handle_owner_type[0x4]; 10324 u8 handle_owner_host_id[0x4]; 10325 u8 reserved_at_68[0x1]; 10326 u8 control_progress[0x7]; 10327 u8 error_code[0x8]; 10328 u8 reserved_at_78[0x4]; 10329 u8 control_state[0x4]; 10330 10331 u8 component_size[0x20]; 10332 10333 u8 reserved_at_a0[0x60]; 10334 }; 10335 10336 struct mlx5_ifc_mcda_reg_bits { 10337 u8 reserved_at_0[0x8]; 10338 u8 update_handle[0x18]; 10339 10340 u8 offset[0x20]; 10341 10342 u8 reserved_at_40[0x10]; 10343 u8 size[0x10]; 10344 10345 u8 reserved_at_60[0x20]; 10346 10347 u8 data[][0x20]; 10348 }; 10349 10350 enum { 10351 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10352 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10353 }; 10354 10355 enum { 10356 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10357 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10358 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10359 }; 10360 10361 struct mlx5_ifc_mfrl_reg_bits { 10362 u8 reserved_at_0[0x20]; 10363 10364 u8 reserved_at_20[0x2]; 10365 u8 pci_sync_for_fw_update_start[0x1]; 10366 u8 pci_sync_for_fw_update_resp[0x2]; 10367 u8 rst_type_sel[0x3]; 10368 u8 reserved_at_28[0x8]; 10369 u8 reset_type[0x8]; 10370 u8 reset_level[0x8]; 10371 }; 10372 10373 struct mlx5_ifc_mirc_reg_bits { 10374 u8 reserved_at_0[0x18]; 10375 u8 status_code[0x8]; 10376 10377 u8 reserved_at_20[0x20]; 10378 }; 10379 10380 struct mlx5_ifc_pddr_monitor_opcode_bits { 10381 u8 reserved_at_0[0x10]; 10382 u8 monitor_opcode[0x10]; 10383 }; 10384 10385 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10386 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10387 u8 reserved_at_0[0x20]; 10388 }; 10389 10390 enum { 10391 /* Monitor opcodes */ 10392 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10393 }; 10394 10395 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10396 u8 reserved_at_0[0x10]; 10397 u8 group_opcode[0x10]; 10398 10399 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10400 10401 u8 reserved_at_40[0x20]; 10402 10403 u8 status_message[59][0x20]; 10404 }; 10405 10406 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10407 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10408 u8 reserved_at_0[0x7c0]; 10409 }; 10410 10411 enum { 10412 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10413 }; 10414 10415 struct mlx5_ifc_pddr_reg_bits { 10416 u8 reserved_at_0[0x8]; 10417 u8 local_port[0x8]; 10418 u8 pnat[0x2]; 10419 u8 reserved_at_12[0xe]; 10420 10421 u8 reserved_at_20[0x18]; 10422 u8 page_select[0x8]; 10423 10424 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10425 }; 10426 10427 struct mlx5_ifc_mrtc_reg_bits { 10428 u8 time_synced[0x1]; 10429 u8 reserved_at_1[0x1f]; 10430 10431 u8 reserved_at_20[0x20]; 10432 10433 u8 time_h[0x20]; 10434 10435 u8 time_l[0x20]; 10436 }; 10437 10438 union mlx5_ifc_ports_control_registers_document_bits { 10439 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10440 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10441 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10442 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10443 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10444 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10445 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10446 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10447 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10448 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10449 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10450 struct mlx5_ifc_paos_reg_bits paos_reg; 10451 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10452 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10453 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10454 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10455 struct mlx5_ifc_peir_reg_bits peir_reg; 10456 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10457 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10458 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10459 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10460 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10461 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10462 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10463 struct mlx5_ifc_plib_reg_bits plib_reg; 10464 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10465 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10466 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10467 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10468 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10469 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10470 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10471 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10472 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10473 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10474 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10475 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10476 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10477 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10478 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10479 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10480 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10481 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10482 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10483 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10484 struct mlx5_ifc_pude_reg_bits pude_reg; 10485 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10486 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10487 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10488 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10489 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10490 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10491 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10492 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10493 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10494 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10495 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10496 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10497 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10498 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10499 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10500 u8 reserved_at_0[0x60e0]; 10501 }; 10502 10503 union mlx5_ifc_debug_enhancements_document_bits { 10504 struct mlx5_ifc_health_buffer_bits health_buffer; 10505 u8 reserved_at_0[0x200]; 10506 }; 10507 10508 union mlx5_ifc_uplink_pci_interface_document_bits { 10509 struct mlx5_ifc_initial_seg_bits initial_seg; 10510 u8 reserved_at_0[0x20060]; 10511 }; 10512 10513 struct mlx5_ifc_set_flow_table_root_out_bits { 10514 u8 status[0x8]; 10515 u8 reserved_at_8[0x18]; 10516 10517 u8 syndrome[0x20]; 10518 10519 u8 reserved_at_40[0x40]; 10520 }; 10521 10522 struct mlx5_ifc_set_flow_table_root_in_bits { 10523 u8 opcode[0x10]; 10524 u8 reserved_at_10[0x10]; 10525 10526 u8 reserved_at_20[0x10]; 10527 u8 op_mod[0x10]; 10528 10529 u8 other_vport[0x1]; 10530 u8 reserved_at_41[0xf]; 10531 u8 vport_number[0x10]; 10532 10533 u8 reserved_at_60[0x20]; 10534 10535 u8 table_type[0x8]; 10536 u8 reserved_at_88[0x7]; 10537 u8 table_of_other_vport[0x1]; 10538 u8 table_vport_number[0x10]; 10539 10540 u8 reserved_at_a0[0x8]; 10541 u8 table_id[0x18]; 10542 10543 u8 reserved_at_c0[0x8]; 10544 u8 underlay_qpn[0x18]; 10545 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10546 u8 reserved_at_e1[0xf]; 10547 u8 table_eswitch_owner_vhca_id[0x10]; 10548 u8 reserved_at_100[0x100]; 10549 }; 10550 10551 enum { 10552 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10553 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10554 }; 10555 10556 struct mlx5_ifc_modify_flow_table_out_bits { 10557 u8 status[0x8]; 10558 u8 reserved_at_8[0x18]; 10559 10560 u8 syndrome[0x20]; 10561 10562 u8 reserved_at_40[0x40]; 10563 }; 10564 10565 struct mlx5_ifc_modify_flow_table_in_bits { 10566 u8 opcode[0x10]; 10567 u8 reserved_at_10[0x10]; 10568 10569 u8 reserved_at_20[0x10]; 10570 u8 op_mod[0x10]; 10571 10572 u8 other_vport[0x1]; 10573 u8 reserved_at_41[0xf]; 10574 u8 vport_number[0x10]; 10575 10576 u8 reserved_at_60[0x10]; 10577 u8 modify_field_select[0x10]; 10578 10579 u8 table_type[0x8]; 10580 u8 reserved_at_88[0x18]; 10581 10582 u8 reserved_at_a0[0x8]; 10583 u8 table_id[0x18]; 10584 10585 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10586 }; 10587 10588 struct mlx5_ifc_ets_tcn_config_reg_bits { 10589 u8 g[0x1]; 10590 u8 b[0x1]; 10591 u8 r[0x1]; 10592 u8 reserved_at_3[0x9]; 10593 u8 group[0x4]; 10594 u8 reserved_at_10[0x9]; 10595 u8 bw_allocation[0x7]; 10596 10597 u8 reserved_at_20[0xc]; 10598 u8 max_bw_units[0x4]; 10599 u8 reserved_at_30[0x8]; 10600 u8 max_bw_value[0x8]; 10601 }; 10602 10603 struct mlx5_ifc_ets_global_config_reg_bits { 10604 u8 reserved_at_0[0x2]; 10605 u8 r[0x1]; 10606 u8 reserved_at_3[0x1d]; 10607 10608 u8 reserved_at_20[0xc]; 10609 u8 max_bw_units[0x4]; 10610 u8 reserved_at_30[0x8]; 10611 u8 max_bw_value[0x8]; 10612 }; 10613 10614 struct mlx5_ifc_qetc_reg_bits { 10615 u8 reserved_at_0[0x8]; 10616 u8 port_number[0x8]; 10617 u8 reserved_at_10[0x30]; 10618 10619 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10620 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10621 }; 10622 10623 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10624 u8 e[0x1]; 10625 u8 reserved_at_01[0x0b]; 10626 u8 prio[0x04]; 10627 }; 10628 10629 struct mlx5_ifc_qpdpm_reg_bits { 10630 u8 reserved_at_0[0x8]; 10631 u8 local_port[0x8]; 10632 u8 reserved_at_10[0x10]; 10633 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10634 }; 10635 10636 struct mlx5_ifc_qpts_reg_bits { 10637 u8 reserved_at_0[0x8]; 10638 u8 local_port[0x8]; 10639 u8 reserved_at_10[0x2d]; 10640 u8 trust_state[0x3]; 10641 }; 10642 10643 struct mlx5_ifc_pptb_reg_bits { 10644 u8 reserved_at_0[0x2]; 10645 u8 mm[0x2]; 10646 u8 reserved_at_4[0x4]; 10647 u8 local_port[0x8]; 10648 u8 reserved_at_10[0x6]; 10649 u8 cm[0x1]; 10650 u8 um[0x1]; 10651 u8 pm[0x8]; 10652 10653 u8 prio_x_buff[0x20]; 10654 10655 u8 pm_msb[0x8]; 10656 u8 reserved_at_48[0x10]; 10657 u8 ctrl_buff[0x4]; 10658 u8 untagged_buff[0x4]; 10659 }; 10660 10661 struct mlx5_ifc_sbcam_reg_bits { 10662 u8 reserved_at_0[0x8]; 10663 u8 feature_group[0x8]; 10664 u8 reserved_at_10[0x8]; 10665 u8 access_reg_group[0x8]; 10666 10667 u8 reserved_at_20[0x20]; 10668 10669 u8 sb_access_reg_cap_mask[4][0x20]; 10670 10671 u8 reserved_at_c0[0x80]; 10672 10673 u8 sb_feature_cap_mask[4][0x20]; 10674 10675 u8 reserved_at_1c0[0x40]; 10676 10677 u8 cap_total_buffer_size[0x20]; 10678 10679 u8 cap_cell_size[0x10]; 10680 u8 cap_max_pg_buffers[0x8]; 10681 u8 cap_num_pool_supported[0x8]; 10682 10683 u8 reserved_at_240[0x8]; 10684 u8 cap_sbsr_stat_size[0x8]; 10685 u8 cap_max_tclass_data[0x8]; 10686 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10687 }; 10688 10689 struct mlx5_ifc_pbmc_reg_bits { 10690 u8 reserved_at_0[0x8]; 10691 u8 local_port[0x8]; 10692 u8 reserved_at_10[0x10]; 10693 10694 u8 xoff_timer_value[0x10]; 10695 u8 xoff_refresh[0x10]; 10696 10697 u8 reserved_at_40[0x9]; 10698 u8 fullness_threshold[0x7]; 10699 u8 port_buffer_size[0x10]; 10700 10701 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10702 10703 u8 reserved_at_2e0[0x80]; 10704 }; 10705 10706 struct mlx5_ifc_qtct_reg_bits { 10707 u8 reserved_at_0[0x8]; 10708 u8 port_number[0x8]; 10709 u8 reserved_at_10[0xd]; 10710 u8 prio[0x3]; 10711 10712 u8 reserved_at_20[0x1d]; 10713 u8 tclass[0x3]; 10714 }; 10715 10716 struct mlx5_ifc_mcia_reg_bits { 10717 u8 l[0x1]; 10718 u8 reserved_at_1[0x7]; 10719 u8 module[0x8]; 10720 u8 reserved_at_10[0x8]; 10721 u8 status[0x8]; 10722 10723 u8 i2c_device_address[0x8]; 10724 u8 page_number[0x8]; 10725 u8 device_address[0x10]; 10726 10727 u8 reserved_at_40[0x10]; 10728 u8 size[0x10]; 10729 10730 u8 reserved_at_60[0x20]; 10731 10732 u8 dword_0[0x20]; 10733 u8 dword_1[0x20]; 10734 u8 dword_2[0x20]; 10735 u8 dword_3[0x20]; 10736 u8 dword_4[0x20]; 10737 u8 dword_5[0x20]; 10738 u8 dword_6[0x20]; 10739 u8 dword_7[0x20]; 10740 u8 dword_8[0x20]; 10741 u8 dword_9[0x20]; 10742 u8 dword_10[0x20]; 10743 u8 dword_11[0x20]; 10744 }; 10745 10746 struct mlx5_ifc_dcbx_param_bits { 10747 u8 dcbx_cee_cap[0x1]; 10748 u8 dcbx_ieee_cap[0x1]; 10749 u8 dcbx_standby_cap[0x1]; 10750 u8 reserved_at_3[0x5]; 10751 u8 port_number[0x8]; 10752 u8 reserved_at_10[0xa]; 10753 u8 max_application_table_size[6]; 10754 u8 reserved_at_20[0x15]; 10755 u8 version_oper[0x3]; 10756 u8 reserved_at_38[5]; 10757 u8 version_admin[0x3]; 10758 u8 willing_admin[0x1]; 10759 u8 reserved_at_41[0x3]; 10760 u8 pfc_cap_oper[0x4]; 10761 u8 reserved_at_48[0x4]; 10762 u8 pfc_cap_admin[0x4]; 10763 u8 reserved_at_50[0x4]; 10764 u8 num_of_tc_oper[0x4]; 10765 u8 reserved_at_58[0x4]; 10766 u8 num_of_tc_admin[0x4]; 10767 u8 remote_willing[0x1]; 10768 u8 reserved_at_61[3]; 10769 u8 remote_pfc_cap[4]; 10770 u8 reserved_at_68[0x14]; 10771 u8 remote_num_of_tc[0x4]; 10772 u8 reserved_at_80[0x18]; 10773 u8 error[0x8]; 10774 u8 reserved_at_a0[0x160]; 10775 }; 10776 10777 enum { 10778 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10779 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT, 10780 }; 10781 10782 struct mlx5_ifc_lagc_bits { 10783 u8 fdb_selection_mode[0x1]; 10784 u8 reserved_at_1[0x14]; 10785 u8 port_select_mode[0x3]; 10786 u8 reserved_at_18[0x5]; 10787 u8 lag_state[0x3]; 10788 10789 u8 reserved_at_20[0x14]; 10790 u8 tx_remap_affinity_2[0x4]; 10791 u8 reserved_at_38[0x4]; 10792 u8 tx_remap_affinity_1[0x4]; 10793 }; 10794 10795 struct mlx5_ifc_create_lag_out_bits { 10796 u8 status[0x8]; 10797 u8 reserved_at_8[0x18]; 10798 10799 u8 syndrome[0x20]; 10800 10801 u8 reserved_at_40[0x40]; 10802 }; 10803 10804 struct mlx5_ifc_create_lag_in_bits { 10805 u8 opcode[0x10]; 10806 u8 reserved_at_10[0x10]; 10807 10808 u8 reserved_at_20[0x10]; 10809 u8 op_mod[0x10]; 10810 10811 struct mlx5_ifc_lagc_bits ctx; 10812 }; 10813 10814 struct mlx5_ifc_modify_lag_out_bits { 10815 u8 status[0x8]; 10816 u8 reserved_at_8[0x18]; 10817 10818 u8 syndrome[0x20]; 10819 10820 u8 reserved_at_40[0x40]; 10821 }; 10822 10823 struct mlx5_ifc_modify_lag_in_bits { 10824 u8 opcode[0x10]; 10825 u8 reserved_at_10[0x10]; 10826 10827 u8 reserved_at_20[0x10]; 10828 u8 op_mod[0x10]; 10829 10830 u8 reserved_at_40[0x20]; 10831 u8 field_select[0x20]; 10832 10833 struct mlx5_ifc_lagc_bits ctx; 10834 }; 10835 10836 struct mlx5_ifc_query_lag_out_bits { 10837 u8 status[0x8]; 10838 u8 reserved_at_8[0x18]; 10839 10840 u8 syndrome[0x20]; 10841 10842 struct mlx5_ifc_lagc_bits ctx; 10843 }; 10844 10845 struct mlx5_ifc_query_lag_in_bits { 10846 u8 opcode[0x10]; 10847 u8 reserved_at_10[0x10]; 10848 10849 u8 reserved_at_20[0x10]; 10850 u8 op_mod[0x10]; 10851 10852 u8 reserved_at_40[0x40]; 10853 }; 10854 10855 struct mlx5_ifc_destroy_lag_out_bits { 10856 u8 status[0x8]; 10857 u8 reserved_at_8[0x18]; 10858 10859 u8 syndrome[0x20]; 10860 10861 u8 reserved_at_40[0x40]; 10862 }; 10863 10864 struct mlx5_ifc_destroy_lag_in_bits { 10865 u8 opcode[0x10]; 10866 u8 reserved_at_10[0x10]; 10867 10868 u8 reserved_at_20[0x10]; 10869 u8 op_mod[0x10]; 10870 10871 u8 reserved_at_40[0x40]; 10872 }; 10873 10874 struct mlx5_ifc_create_vport_lag_out_bits { 10875 u8 status[0x8]; 10876 u8 reserved_at_8[0x18]; 10877 10878 u8 syndrome[0x20]; 10879 10880 u8 reserved_at_40[0x40]; 10881 }; 10882 10883 struct mlx5_ifc_create_vport_lag_in_bits { 10884 u8 opcode[0x10]; 10885 u8 reserved_at_10[0x10]; 10886 10887 u8 reserved_at_20[0x10]; 10888 u8 op_mod[0x10]; 10889 10890 u8 reserved_at_40[0x40]; 10891 }; 10892 10893 struct mlx5_ifc_destroy_vport_lag_out_bits { 10894 u8 status[0x8]; 10895 u8 reserved_at_8[0x18]; 10896 10897 u8 syndrome[0x20]; 10898 10899 u8 reserved_at_40[0x40]; 10900 }; 10901 10902 struct mlx5_ifc_destroy_vport_lag_in_bits { 10903 u8 opcode[0x10]; 10904 u8 reserved_at_10[0x10]; 10905 10906 u8 reserved_at_20[0x10]; 10907 u8 op_mod[0x10]; 10908 10909 u8 reserved_at_40[0x40]; 10910 }; 10911 10912 enum { 10913 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 10914 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 10915 }; 10916 10917 struct mlx5_ifc_modify_memic_in_bits { 10918 u8 opcode[0x10]; 10919 u8 uid[0x10]; 10920 10921 u8 reserved_at_20[0x10]; 10922 u8 op_mod[0x10]; 10923 10924 u8 reserved_at_40[0x20]; 10925 10926 u8 reserved_at_60[0x18]; 10927 u8 memic_operation_type[0x8]; 10928 10929 u8 memic_start_addr[0x40]; 10930 10931 u8 reserved_at_c0[0x140]; 10932 }; 10933 10934 struct mlx5_ifc_modify_memic_out_bits { 10935 u8 status[0x8]; 10936 u8 reserved_at_8[0x18]; 10937 10938 u8 syndrome[0x20]; 10939 10940 u8 reserved_at_40[0x40]; 10941 10942 u8 memic_operation_addr[0x40]; 10943 10944 u8 reserved_at_c0[0x140]; 10945 }; 10946 10947 struct mlx5_ifc_alloc_memic_in_bits { 10948 u8 opcode[0x10]; 10949 u8 reserved_at_10[0x10]; 10950 10951 u8 reserved_at_20[0x10]; 10952 u8 op_mod[0x10]; 10953 10954 u8 reserved_at_30[0x20]; 10955 10956 u8 reserved_at_40[0x18]; 10957 u8 log_memic_addr_alignment[0x8]; 10958 10959 u8 range_start_addr[0x40]; 10960 10961 u8 range_size[0x20]; 10962 10963 u8 memic_size[0x20]; 10964 }; 10965 10966 struct mlx5_ifc_alloc_memic_out_bits { 10967 u8 status[0x8]; 10968 u8 reserved_at_8[0x18]; 10969 10970 u8 syndrome[0x20]; 10971 10972 u8 memic_start_addr[0x40]; 10973 }; 10974 10975 struct mlx5_ifc_dealloc_memic_in_bits { 10976 u8 opcode[0x10]; 10977 u8 reserved_at_10[0x10]; 10978 10979 u8 reserved_at_20[0x10]; 10980 u8 op_mod[0x10]; 10981 10982 u8 reserved_at_40[0x40]; 10983 10984 u8 memic_start_addr[0x40]; 10985 10986 u8 memic_size[0x20]; 10987 10988 u8 reserved_at_e0[0x20]; 10989 }; 10990 10991 struct mlx5_ifc_dealloc_memic_out_bits { 10992 u8 status[0x8]; 10993 u8 reserved_at_8[0x18]; 10994 10995 u8 syndrome[0x20]; 10996 10997 u8 reserved_at_40[0x40]; 10998 }; 10999 11000 struct mlx5_ifc_umem_bits { 11001 u8 reserved_at_0[0x80]; 11002 11003 u8 reserved_at_80[0x1b]; 11004 u8 log_page_size[0x5]; 11005 11006 u8 page_offset[0x20]; 11007 11008 u8 num_of_mtt[0x40]; 11009 11010 struct mlx5_ifc_mtt_bits mtt[]; 11011 }; 11012 11013 struct mlx5_ifc_uctx_bits { 11014 u8 cap[0x20]; 11015 11016 u8 reserved_at_20[0x160]; 11017 }; 11018 11019 struct mlx5_ifc_sw_icm_bits { 11020 u8 modify_field_select[0x40]; 11021 11022 u8 reserved_at_40[0x18]; 11023 u8 log_sw_icm_size[0x8]; 11024 11025 u8 reserved_at_60[0x20]; 11026 11027 u8 sw_icm_start_addr[0x40]; 11028 11029 u8 reserved_at_c0[0x140]; 11030 }; 11031 11032 struct mlx5_ifc_geneve_tlv_option_bits { 11033 u8 modify_field_select[0x40]; 11034 11035 u8 reserved_at_40[0x18]; 11036 u8 geneve_option_fte_index[0x8]; 11037 11038 u8 option_class[0x10]; 11039 u8 option_type[0x8]; 11040 u8 reserved_at_78[0x3]; 11041 u8 option_data_length[0x5]; 11042 11043 u8 reserved_at_80[0x180]; 11044 }; 11045 11046 struct mlx5_ifc_create_umem_in_bits { 11047 u8 opcode[0x10]; 11048 u8 uid[0x10]; 11049 11050 u8 reserved_at_20[0x10]; 11051 u8 op_mod[0x10]; 11052 11053 u8 reserved_at_40[0x40]; 11054 11055 struct mlx5_ifc_umem_bits umem; 11056 }; 11057 11058 struct mlx5_ifc_create_umem_out_bits { 11059 u8 status[0x8]; 11060 u8 reserved_at_8[0x18]; 11061 11062 u8 syndrome[0x20]; 11063 11064 u8 reserved_at_40[0x8]; 11065 u8 umem_id[0x18]; 11066 11067 u8 reserved_at_60[0x20]; 11068 }; 11069 11070 struct mlx5_ifc_destroy_umem_in_bits { 11071 u8 opcode[0x10]; 11072 u8 uid[0x10]; 11073 11074 u8 reserved_at_20[0x10]; 11075 u8 op_mod[0x10]; 11076 11077 u8 reserved_at_40[0x8]; 11078 u8 umem_id[0x18]; 11079 11080 u8 reserved_at_60[0x20]; 11081 }; 11082 11083 struct mlx5_ifc_destroy_umem_out_bits { 11084 u8 status[0x8]; 11085 u8 reserved_at_8[0x18]; 11086 11087 u8 syndrome[0x20]; 11088 11089 u8 reserved_at_40[0x40]; 11090 }; 11091 11092 struct mlx5_ifc_create_uctx_in_bits { 11093 u8 opcode[0x10]; 11094 u8 reserved_at_10[0x10]; 11095 11096 u8 reserved_at_20[0x10]; 11097 u8 op_mod[0x10]; 11098 11099 u8 reserved_at_40[0x40]; 11100 11101 struct mlx5_ifc_uctx_bits uctx; 11102 }; 11103 11104 struct mlx5_ifc_create_uctx_out_bits { 11105 u8 status[0x8]; 11106 u8 reserved_at_8[0x18]; 11107 11108 u8 syndrome[0x20]; 11109 11110 u8 reserved_at_40[0x10]; 11111 u8 uid[0x10]; 11112 11113 u8 reserved_at_60[0x20]; 11114 }; 11115 11116 struct mlx5_ifc_destroy_uctx_in_bits { 11117 u8 opcode[0x10]; 11118 u8 reserved_at_10[0x10]; 11119 11120 u8 reserved_at_20[0x10]; 11121 u8 op_mod[0x10]; 11122 11123 u8 reserved_at_40[0x10]; 11124 u8 uid[0x10]; 11125 11126 u8 reserved_at_60[0x20]; 11127 }; 11128 11129 struct mlx5_ifc_destroy_uctx_out_bits { 11130 u8 status[0x8]; 11131 u8 reserved_at_8[0x18]; 11132 11133 u8 syndrome[0x20]; 11134 11135 u8 reserved_at_40[0x40]; 11136 }; 11137 11138 struct mlx5_ifc_create_sw_icm_in_bits { 11139 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11140 struct mlx5_ifc_sw_icm_bits sw_icm; 11141 }; 11142 11143 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11144 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11145 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11146 }; 11147 11148 struct mlx5_ifc_mtrc_string_db_param_bits { 11149 u8 string_db_base_address[0x20]; 11150 11151 u8 reserved_at_20[0x8]; 11152 u8 string_db_size[0x18]; 11153 }; 11154 11155 struct mlx5_ifc_mtrc_cap_bits { 11156 u8 trace_owner[0x1]; 11157 u8 trace_to_memory[0x1]; 11158 u8 reserved_at_2[0x4]; 11159 u8 trc_ver[0x2]; 11160 u8 reserved_at_8[0x14]; 11161 u8 num_string_db[0x4]; 11162 11163 u8 first_string_trace[0x8]; 11164 u8 num_string_trace[0x8]; 11165 u8 reserved_at_30[0x28]; 11166 11167 u8 log_max_trace_buffer_size[0x8]; 11168 11169 u8 reserved_at_60[0x20]; 11170 11171 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11172 11173 u8 reserved_at_280[0x180]; 11174 }; 11175 11176 struct mlx5_ifc_mtrc_conf_bits { 11177 u8 reserved_at_0[0x1c]; 11178 u8 trace_mode[0x4]; 11179 u8 reserved_at_20[0x18]; 11180 u8 log_trace_buffer_size[0x8]; 11181 u8 trace_mkey[0x20]; 11182 u8 reserved_at_60[0x3a0]; 11183 }; 11184 11185 struct mlx5_ifc_mtrc_stdb_bits { 11186 u8 string_db_index[0x4]; 11187 u8 reserved_at_4[0x4]; 11188 u8 read_size[0x18]; 11189 u8 start_offset[0x20]; 11190 u8 string_db_data[]; 11191 }; 11192 11193 struct mlx5_ifc_mtrc_ctrl_bits { 11194 u8 trace_status[0x2]; 11195 u8 reserved_at_2[0x2]; 11196 u8 arm_event[0x1]; 11197 u8 reserved_at_5[0xb]; 11198 u8 modify_field_select[0x10]; 11199 u8 reserved_at_20[0x2b]; 11200 u8 current_timestamp52_32[0x15]; 11201 u8 current_timestamp31_0[0x20]; 11202 u8 reserved_at_80[0x180]; 11203 }; 11204 11205 struct mlx5_ifc_host_params_context_bits { 11206 u8 host_number[0x8]; 11207 u8 reserved_at_8[0x7]; 11208 u8 host_pf_disabled[0x1]; 11209 u8 host_num_of_vfs[0x10]; 11210 11211 u8 host_total_vfs[0x10]; 11212 u8 host_pci_bus[0x10]; 11213 11214 u8 reserved_at_40[0x10]; 11215 u8 host_pci_device[0x10]; 11216 11217 u8 reserved_at_60[0x10]; 11218 u8 host_pci_function[0x10]; 11219 11220 u8 reserved_at_80[0x180]; 11221 }; 11222 11223 struct mlx5_ifc_query_esw_functions_in_bits { 11224 u8 opcode[0x10]; 11225 u8 reserved_at_10[0x10]; 11226 11227 u8 reserved_at_20[0x10]; 11228 u8 op_mod[0x10]; 11229 11230 u8 reserved_at_40[0x40]; 11231 }; 11232 11233 struct mlx5_ifc_query_esw_functions_out_bits { 11234 u8 status[0x8]; 11235 u8 reserved_at_8[0x18]; 11236 11237 u8 syndrome[0x20]; 11238 11239 u8 reserved_at_40[0x40]; 11240 11241 struct mlx5_ifc_host_params_context_bits host_params_context; 11242 11243 u8 reserved_at_280[0x180]; 11244 u8 host_sf_enable[][0x40]; 11245 }; 11246 11247 struct mlx5_ifc_sf_partition_bits { 11248 u8 reserved_at_0[0x10]; 11249 u8 log_num_sf[0x8]; 11250 u8 log_sf_bar_size[0x8]; 11251 }; 11252 11253 struct mlx5_ifc_query_sf_partitions_out_bits { 11254 u8 status[0x8]; 11255 u8 reserved_at_8[0x18]; 11256 11257 u8 syndrome[0x20]; 11258 11259 u8 reserved_at_40[0x18]; 11260 u8 num_sf_partitions[0x8]; 11261 11262 u8 reserved_at_60[0x20]; 11263 11264 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11265 }; 11266 11267 struct mlx5_ifc_query_sf_partitions_in_bits { 11268 u8 opcode[0x10]; 11269 u8 reserved_at_10[0x10]; 11270 11271 u8 reserved_at_20[0x10]; 11272 u8 op_mod[0x10]; 11273 11274 u8 reserved_at_40[0x40]; 11275 }; 11276 11277 struct mlx5_ifc_dealloc_sf_out_bits { 11278 u8 status[0x8]; 11279 u8 reserved_at_8[0x18]; 11280 11281 u8 syndrome[0x20]; 11282 11283 u8 reserved_at_40[0x40]; 11284 }; 11285 11286 struct mlx5_ifc_dealloc_sf_in_bits { 11287 u8 opcode[0x10]; 11288 u8 reserved_at_10[0x10]; 11289 11290 u8 reserved_at_20[0x10]; 11291 u8 op_mod[0x10]; 11292 11293 u8 reserved_at_40[0x10]; 11294 u8 function_id[0x10]; 11295 11296 u8 reserved_at_60[0x20]; 11297 }; 11298 11299 struct mlx5_ifc_alloc_sf_out_bits { 11300 u8 status[0x8]; 11301 u8 reserved_at_8[0x18]; 11302 11303 u8 syndrome[0x20]; 11304 11305 u8 reserved_at_40[0x40]; 11306 }; 11307 11308 struct mlx5_ifc_alloc_sf_in_bits { 11309 u8 opcode[0x10]; 11310 u8 reserved_at_10[0x10]; 11311 11312 u8 reserved_at_20[0x10]; 11313 u8 op_mod[0x10]; 11314 11315 u8 reserved_at_40[0x10]; 11316 u8 function_id[0x10]; 11317 11318 u8 reserved_at_60[0x20]; 11319 }; 11320 11321 struct mlx5_ifc_affiliated_event_header_bits { 11322 u8 reserved_at_0[0x10]; 11323 u8 obj_type[0x10]; 11324 11325 u8 obj_id[0x20]; 11326 }; 11327 11328 enum { 11329 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11330 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11331 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11332 }; 11333 11334 enum { 11335 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11336 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11337 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11338 }; 11339 11340 enum { 11341 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11342 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 11343 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 11344 }; 11345 11346 struct mlx5_ifc_ipsec_obj_bits { 11347 u8 modify_field_select[0x40]; 11348 u8 full_offload[0x1]; 11349 u8 reserved_at_41[0x1]; 11350 u8 esn_en[0x1]; 11351 u8 esn_overlap[0x1]; 11352 u8 reserved_at_44[0x2]; 11353 u8 icv_length[0x2]; 11354 u8 reserved_at_48[0x4]; 11355 u8 aso_return_reg[0x4]; 11356 u8 reserved_at_50[0x10]; 11357 11358 u8 esn_msb[0x20]; 11359 11360 u8 reserved_at_80[0x8]; 11361 u8 dekn[0x18]; 11362 11363 u8 salt[0x20]; 11364 11365 u8 implicit_iv[0x40]; 11366 11367 u8 reserved_at_100[0x700]; 11368 }; 11369 11370 struct mlx5_ifc_create_ipsec_obj_in_bits { 11371 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11372 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11373 }; 11374 11375 enum { 11376 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11377 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11378 }; 11379 11380 struct mlx5_ifc_query_ipsec_obj_out_bits { 11381 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11382 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11383 }; 11384 11385 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11386 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11387 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11388 }; 11389 11390 struct mlx5_ifc_encryption_key_obj_bits { 11391 u8 modify_field_select[0x40]; 11392 11393 u8 reserved_at_40[0x14]; 11394 u8 key_size[0x4]; 11395 u8 reserved_at_58[0x4]; 11396 u8 key_type[0x4]; 11397 11398 u8 reserved_at_60[0x8]; 11399 u8 pd[0x18]; 11400 11401 u8 reserved_at_80[0x180]; 11402 u8 key[8][0x20]; 11403 11404 u8 reserved_at_300[0x500]; 11405 }; 11406 11407 struct mlx5_ifc_create_encryption_key_in_bits { 11408 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11409 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11410 }; 11411 11412 struct mlx5_ifc_sampler_obj_bits { 11413 u8 modify_field_select[0x40]; 11414 11415 u8 table_type[0x8]; 11416 u8 level[0x8]; 11417 u8 reserved_at_50[0xf]; 11418 u8 ignore_flow_level[0x1]; 11419 11420 u8 sample_ratio[0x20]; 11421 11422 u8 reserved_at_80[0x8]; 11423 u8 sample_table_id[0x18]; 11424 11425 u8 reserved_at_a0[0x8]; 11426 u8 default_table_id[0x18]; 11427 11428 u8 sw_steering_icm_address_rx[0x40]; 11429 u8 sw_steering_icm_address_tx[0x40]; 11430 11431 u8 reserved_at_140[0xa0]; 11432 }; 11433 11434 struct mlx5_ifc_create_sampler_obj_in_bits { 11435 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11436 struct mlx5_ifc_sampler_obj_bits sampler_object; 11437 }; 11438 11439 struct mlx5_ifc_query_sampler_obj_out_bits { 11440 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11441 struct mlx5_ifc_sampler_obj_bits sampler_object; 11442 }; 11443 11444 enum { 11445 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11446 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11447 }; 11448 11449 enum { 11450 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11451 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11452 }; 11453 11454 struct mlx5_ifc_tls_static_params_bits { 11455 u8 const_2[0x2]; 11456 u8 tls_version[0x4]; 11457 u8 const_1[0x2]; 11458 u8 reserved_at_8[0x14]; 11459 u8 encryption_standard[0x4]; 11460 11461 u8 reserved_at_20[0x20]; 11462 11463 u8 initial_record_number[0x40]; 11464 11465 u8 resync_tcp_sn[0x20]; 11466 11467 u8 gcm_iv[0x20]; 11468 11469 u8 implicit_iv[0x40]; 11470 11471 u8 reserved_at_100[0x8]; 11472 u8 dek_index[0x18]; 11473 11474 u8 reserved_at_120[0xe0]; 11475 }; 11476 11477 struct mlx5_ifc_tls_progress_params_bits { 11478 u8 next_record_tcp_sn[0x20]; 11479 11480 u8 hw_resync_tcp_sn[0x20]; 11481 11482 u8 record_tracker_state[0x2]; 11483 u8 auth_state[0x2]; 11484 u8 reserved_at_44[0x4]; 11485 u8 hw_offset_record_number[0x18]; 11486 }; 11487 11488 enum { 11489 MLX5_MTT_PERM_READ = 1 << 0, 11490 MLX5_MTT_PERM_WRITE = 1 << 1, 11491 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11492 }; 11493 11494 #endif /* MLX5_IFC_H */ 11495