1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 72 MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION = 0x25, 73 }; 74 75 enum { 76 MLX5_SHARED_RESOURCE_UID = 0xffff, 77 }; 78 79 enum { 80 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 81 }; 82 83 enum { 84 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 85 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 86 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 87 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 88 }; 89 90 enum { 91 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 92 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 93 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 94 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 95 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 96 MLX5_OBJ_TYPE_MKEY = 0xff01, 97 MLX5_OBJ_TYPE_QP = 0xff02, 98 MLX5_OBJ_TYPE_PSV = 0xff03, 99 MLX5_OBJ_TYPE_RMP = 0xff04, 100 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 101 MLX5_OBJ_TYPE_RQ = 0xff06, 102 MLX5_OBJ_TYPE_SQ = 0xff07, 103 MLX5_OBJ_TYPE_TIR = 0xff08, 104 MLX5_OBJ_TYPE_TIS = 0xff09, 105 MLX5_OBJ_TYPE_DCT = 0xff0a, 106 MLX5_OBJ_TYPE_XRQ = 0xff0b, 107 MLX5_OBJ_TYPE_RQT = 0xff0e, 108 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 109 MLX5_OBJ_TYPE_CQ = 0xff10, 110 }; 111 112 enum { 113 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 114 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 115 MLX5_CMD_OP_INIT_HCA = 0x102, 116 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 117 MLX5_CMD_OP_ENABLE_HCA = 0x104, 118 MLX5_CMD_OP_DISABLE_HCA = 0x105, 119 MLX5_CMD_OP_QUERY_PAGES = 0x107, 120 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 121 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 122 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 123 MLX5_CMD_OP_SET_ISSI = 0x10b, 124 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 125 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 126 MLX5_CMD_OP_ALLOC_SF = 0x113, 127 MLX5_CMD_OP_DEALLOC_SF = 0x114, 128 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 129 MLX5_CMD_OP_RESUME_VHCA = 0x116, 130 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 131 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 132 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 133 MLX5_CMD_OP_CREATE_MKEY = 0x200, 134 MLX5_CMD_OP_QUERY_MKEY = 0x201, 135 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 136 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 137 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 138 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 139 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 140 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 141 MLX5_CMD_OP_CREATE_EQ = 0x301, 142 MLX5_CMD_OP_DESTROY_EQ = 0x302, 143 MLX5_CMD_OP_QUERY_EQ = 0x303, 144 MLX5_CMD_OP_GEN_EQE = 0x304, 145 MLX5_CMD_OP_CREATE_CQ = 0x400, 146 MLX5_CMD_OP_DESTROY_CQ = 0x401, 147 MLX5_CMD_OP_QUERY_CQ = 0x402, 148 MLX5_CMD_OP_MODIFY_CQ = 0x403, 149 MLX5_CMD_OP_CREATE_QP = 0x500, 150 MLX5_CMD_OP_DESTROY_QP = 0x501, 151 MLX5_CMD_OP_RST2INIT_QP = 0x502, 152 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 153 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 154 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 155 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 156 MLX5_CMD_OP_2ERR_QP = 0x507, 157 MLX5_CMD_OP_2RST_QP = 0x50a, 158 MLX5_CMD_OP_QUERY_QP = 0x50b, 159 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 160 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 161 MLX5_CMD_OP_CREATE_PSV = 0x600, 162 MLX5_CMD_OP_DESTROY_PSV = 0x601, 163 MLX5_CMD_OP_CREATE_SRQ = 0x700, 164 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 165 MLX5_CMD_OP_QUERY_SRQ = 0x702, 166 MLX5_CMD_OP_ARM_RQ = 0x703, 167 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 168 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 169 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 170 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 171 MLX5_CMD_OP_CREATE_DCT = 0x710, 172 MLX5_CMD_OP_DESTROY_DCT = 0x711, 173 MLX5_CMD_OP_DRAIN_DCT = 0x712, 174 MLX5_CMD_OP_QUERY_DCT = 0x713, 175 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 176 MLX5_CMD_OP_CREATE_XRQ = 0x717, 177 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 178 MLX5_CMD_OP_QUERY_XRQ = 0x719, 179 MLX5_CMD_OP_ARM_XRQ = 0x71a, 180 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 181 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 182 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 183 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 184 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 185 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 186 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 187 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 188 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 189 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 190 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 191 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 192 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 193 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 194 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 195 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 196 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 197 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 198 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 199 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 200 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 201 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 202 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 203 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 204 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 205 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 206 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 207 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 208 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 209 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 210 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 211 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 212 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 213 MLX5_CMD_OP_ALLOC_PD = 0x800, 214 MLX5_CMD_OP_DEALLOC_PD = 0x801, 215 MLX5_CMD_OP_ALLOC_UAR = 0x802, 216 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 217 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 218 MLX5_CMD_OP_ACCESS_REG = 0x805, 219 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 220 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 221 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 222 MLX5_CMD_OP_MAD_IFC = 0x50d, 223 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 224 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 225 MLX5_CMD_OP_NOP = 0x80d, 226 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 227 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 228 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 229 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 230 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 231 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 232 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 233 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 234 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 235 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 236 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 237 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 238 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 239 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 240 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 241 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 242 MLX5_CMD_OP_CREATE_LAG = 0x840, 243 MLX5_CMD_OP_MODIFY_LAG = 0x841, 244 MLX5_CMD_OP_QUERY_LAG = 0x842, 245 MLX5_CMD_OP_DESTROY_LAG = 0x843, 246 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 247 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 248 MLX5_CMD_OP_CREATE_TIR = 0x900, 249 MLX5_CMD_OP_MODIFY_TIR = 0x901, 250 MLX5_CMD_OP_DESTROY_TIR = 0x902, 251 MLX5_CMD_OP_QUERY_TIR = 0x903, 252 MLX5_CMD_OP_CREATE_SQ = 0x904, 253 MLX5_CMD_OP_MODIFY_SQ = 0x905, 254 MLX5_CMD_OP_DESTROY_SQ = 0x906, 255 MLX5_CMD_OP_QUERY_SQ = 0x907, 256 MLX5_CMD_OP_CREATE_RQ = 0x908, 257 MLX5_CMD_OP_MODIFY_RQ = 0x909, 258 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 259 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 260 MLX5_CMD_OP_QUERY_RQ = 0x90b, 261 MLX5_CMD_OP_CREATE_RMP = 0x90c, 262 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 263 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 264 MLX5_CMD_OP_QUERY_RMP = 0x90f, 265 MLX5_CMD_OP_CREATE_TIS = 0x912, 266 MLX5_CMD_OP_MODIFY_TIS = 0x913, 267 MLX5_CMD_OP_DESTROY_TIS = 0x914, 268 MLX5_CMD_OP_QUERY_TIS = 0x915, 269 MLX5_CMD_OP_CREATE_RQT = 0x916, 270 MLX5_CMD_OP_MODIFY_RQT = 0x917, 271 MLX5_CMD_OP_DESTROY_RQT = 0x918, 272 MLX5_CMD_OP_QUERY_RQT = 0x919, 273 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 274 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 275 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 276 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 277 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 278 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 279 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 280 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 282 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 283 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 284 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 285 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 286 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 287 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 288 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 289 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 290 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 291 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 292 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 293 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 294 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 295 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 296 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 297 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 298 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 299 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 300 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 301 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 302 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 303 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 304 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 305 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 306 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 307 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 308 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 309 MLX5_CMD_OP_MAX 310 }; 311 312 /* Valid range for general commands that don't work over an object */ 313 enum { 314 MLX5_CMD_OP_GENERAL_START = 0xb00, 315 MLX5_CMD_OP_GENERAL_END = 0xd00, 316 }; 317 318 struct mlx5_ifc_flow_table_fields_supported_bits { 319 u8 outer_dmac[0x1]; 320 u8 outer_smac[0x1]; 321 u8 outer_ether_type[0x1]; 322 u8 outer_ip_version[0x1]; 323 u8 outer_first_prio[0x1]; 324 u8 outer_first_cfi[0x1]; 325 u8 outer_first_vid[0x1]; 326 u8 outer_ipv4_ttl[0x1]; 327 u8 outer_second_prio[0x1]; 328 u8 outer_second_cfi[0x1]; 329 u8 outer_second_vid[0x1]; 330 u8 reserved_at_b[0x1]; 331 u8 outer_sip[0x1]; 332 u8 outer_dip[0x1]; 333 u8 outer_frag[0x1]; 334 u8 outer_ip_protocol[0x1]; 335 u8 outer_ip_ecn[0x1]; 336 u8 outer_ip_dscp[0x1]; 337 u8 outer_udp_sport[0x1]; 338 u8 outer_udp_dport[0x1]; 339 u8 outer_tcp_sport[0x1]; 340 u8 outer_tcp_dport[0x1]; 341 u8 outer_tcp_flags[0x1]; 342 u8 outer_gre_protocol[0x1]; 343 u8 outer_gre_key[0x1]; 344 u8 outer_vxlan_vni[0x1]; 345 u8 outer_geneve_vni[0x1]; 346 u8 outer_geneve_oam[0x1]; 347 u8 outer_geneve_protocol_type[0x1]; 348 u8 outer_geneve_opt_len[0x1]; 349 u8 source_vhca_port[0x1]; 350 u8 source_eswitch_port[0x1]; 351 352 u8 inner_dmac[0x1]; 353 u8 inner_smac[0x1]; 354 u8 inner_ether_type[0x1]; 355 u8 inner_ip_version[0x1]; 356 u8 inner_first_prio[0x1]; 357 u8 inner_first_cfi[0x1]; 358 u8 inner_first_vid[0x1]; 359 u8 reserved_at_27[0x1]; 360 u8 inner_second_prio[0x1]; 361 u8 inner_second_cfi[0x1]; 362 u8 inner_second_vid[0x1]; 363 u8 reserved_at_2b[0x1]; 364 u8 inner_sip[0x1]; 365 u8 inner_dip[0x1]; 366 u8 inner_frag[0x1]; 367 u8 inner_ip_protocol[0x1]; 368 u8 inner_ip_ecn[0x1]; 369 u8 inner_ip_dscp[0x1]; 370 u8 inner_udp_sport[0x1]; 371 u8 inner_udp_dport[0x1]; 372 u8 inner_tcp_sport[0x1]; 373 u8 inner_tcp_dport[0x1]; 374 u8 inner_tcp_flags[0x1]; 375 u8 reserved_at_37[0x9]; 376 377 u8 geneve_tlv_option_0_data[0x1]; 378 u8 geneve_tlv_option_0_exist[0x1]; 379 u8 reserved_at_42[0x3]; 380 u8 outer_first_mpls_over_udp[0x4]; 381 u8 outer_first_mpls_over_gre[0x4]; 382 u8 inner_first_mpls[0x4]; 383 u8 outer_first_mpls[0x4]; 384 u8 reserved_at_55[0x2]; 385 u8 outer_esp_spi[0x1]; 386 u8 reserved_at_58[0x2]; 387 u8 bth_dst_qp[0x1]; 388 u8 reserved_at_5b[0x5]; 389 390 u8 reserved_at_60[0x18]; 391 u8 metadata_reg_c_7[0x1]; 392 u8 metadata_reg_c_6[0x1]; 393 u8 metadata_reg_c_5[0x1]; 394 u8 metadata_reg_c_4[0x1]; 395 u8 metadata_reg_c_3[0x1]; 396 u8 metadata_reg_c_2[0x1]; 397 u8 metadata_reg_c_1[0x1]; 398 u8 metadata_reg_c_0[0x1]; 399 }; 400 401 struct mlx5_ifc_flow_table_fields_supported_2_bits { 402 u8 reserved_at_0[0xe]; 403 u8 bth_opcode[0x1]; 404 u8 reserved_at_f[0x11]; 405 406 u8 reserved_at_20[0x60]; 407 }; 408 409 struct mlx5_ifc_flow_table_prop_layout_bits { 410 u8 ft_support[0x1]; 411 u8 reserved_at_1[0x1]; 412 u8 flow_counter[0x1]; 413 u8 flow_modify_en[0x1]; 414 u8 modify_root[0x1]; 415 u8 identified_miss_table_mode[0x1]; 416 u8 flow_table_modify[0x1]; 417 u8 reformat[0x1]; 418 u8 decap[0x1]; 419 u8 reserved_at_9[0x1]; 420 u8 pop_vlan[0x1]; 421 u8 push_vlan[0x1]; 422 u8 reserved_at_c[0x1]; 423 u8 pop_vlan_2[0x1]; 424 u8 push_vlan_2[0x1]; 425 u8 reformat_and_vlan_action[0x1]; 426 u8 reserved_at_10[0x1]; 427 u8 sw_owner[0x1]; 428 u8 reformat_l3_tunnel_to_l2[0x1]; 429 u8 reformat_l2_to_l3_tunnel[0x1]; 430 u8 reformat_and_modify_action[0x1]; 431 u8 ignore_flow_level[0x1]; 432 u8 reserved_at_16[0x1]; 433 u8 table_miss_action_domain[0x1]; 434 u8 termination_table[0x1]; 435 u8 reformat_and_fwd_to_table[0x1]; 436 u8 reserved_at_1a[0x2]; 437 u8 ipsec_encrypt[0x1]; 438 u8 ipsec_decrypt[0x1]; 439 u8 sw_owner_v2[0x1]; 440 u8 reserved_at_1f[0x1]; 441 442 u8 termination_table_raw_traffic[0x1]; 443 u8 reserved_at_21[0x1]; 444 u8 log_max_ft_size[0x6]; 445 u8 log_max_modify_header_context[0x8]; 446 u8 max_modify_header_actions[0x8]; 447 u8 max_ft_level[0x8]; 448 449 u8 reformat_add_esp_trasport[0x1]; 450 u8 reserved_at_41[0x2]; 451 u8 reformat_del_esp_trasport[0x1]; 452 u8 reserved_at_44[0x2]; 453 u8 execute_aso[0x1]; 454 u8 reserved_at_47[0x19]; 455 456 u8 reserved_at_60[0x2]; 457 u8 reformat_insert[0x1]; 458 u8 reformat_remove[0x1]; 459 u8 macsec_encrypt[0x1]; 460 u8 macsec_decrypt[0x1]; 461 u8 reserved_at_66[0x2]; 462 u8 reformat_add_macsec[0x1]; 463 u8 reformat_remove_macsec[0x1]; 464 u8 reserved_at_6a[0xe]; 465 u8 log_max_ft_num[0x8]; 466 467 u8 reserved_at_80[0x10]; 468 u8 log_max_flow_counter[0x8]; 469 u8 log_max_destination[0x8]; 470 471 u8 reserved_at_a0[0x18]; 472 u8 log_max_flow[0x8]; 473 474 u8 reserved_at_c0[0x40]; 475 476 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 477 478 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 479 }; 480 481 struct mlx5_ifc_odp_per_transport_service_cap_bits { 482 u8 send[0x1]; 483 u8 receive[0x1]; 484 u8 write[0x1]; 485 u8 read[0x1]; 486 u8 atomic[0x1]; 487 u8 srq_receive[0x1]; 488 u8 reserved_at_6[0x1a]; 489 }; 490 491 struct mlx5_ifc_ipv4_layout_bits { 492 u8 reserved_at_0[0x60]; 493 494 u8 ipv4[0x20]; 495 }; 496 497 struct mlx5_ifc_ipv6_layout_bits { 498 u8 ipv6[16][0x8]; 499 }; 500 501 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 502 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 503 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 504 u8 reserved_at_0[0x80]; 505 }; 506 507 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 508 u8 smac_47_16[0x20]; 509 510 u8 smac_15_0[0x10]; 511 u8 ethertype[0x10]; 512 513 u8 dmac_47_16[0x20]; 514 515 u8 dmac_15_0[0x10]; 516 u8 first_prio[0x3]; 517 u8 first_cfi[0x1]; 518 u8 first_vid[0xc]; 519 520 u8 ip_protocol[0x8]; 521 u8 ip_dscp[0x6]; 522 u8 ip_ecn[0x2]; 523 u8 cvlan_tag[0x1]; 524 u8 svlan_tag[0x1]; 525 u8 frag[0x1]; 526 u8 ip_version[0x4]; 527 u8 tcp_flags[0x9]; 528 529 u8 tcp_sport[0x10]; 530 u8 tcp_dport[0x10]; 531 532 u8 reserved_at_c0[0x10]; 533 u8 ipv4_ihl[0x4]; 534 u8 reserved_at_c4[0x4]; 535 536 u8 ttl_hoplimit[0x8]; 537 538 u8 udp_sport[0x10]; 539 u8 udp_dport[0x10]; 540 541 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 542 543 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 544 }; 545 546 struct mlx5_ifc_nvgre_key_bits { 547 u8 hi[0x18]; 548 u8 lo[0x8]; 549 }; 550 551 union mlx5_ifc_gre_key_bits { 552 struct mlx5_ifc_nvgre_key_bits nvgre; 553 u8 key[0x20]; 554 }; 555 556 struct mlx5_ifc_fte_match_set_misc_bits { 557 u8 gre_c_present[0x1]; 558 u8 reserved_at_1[0x1]; 559 u8 gre_k_present[0x1]; 560 u8 gre_s_present[0x1]; 561 u8 source_vhca_port[0x4]; 562 u8 source_sqn[0x18]; 563 564 u8 source_eswitch_owner_vhca_id[0x10]; 565 u8 source_port[0x10]; 566 567 u8 outer_second_prio[0x3]; 568 u8 outer_second_cfi[0x1]; 569 u8 outer_second_vid[0xc]; 570 u8 inner_second_prio[0x3]; 571 u8 inner_second_cfi[0x1]; 572 u8 inner_second_vid[0xc]; 573 574 u8 outer_second_cvlan_tag[0x1]; 575 u8 inner_second_cvlan_tag[0x1]; 576 u8 outer_second_svlan_tag[0x1]; 577 u8 inner_second_svlan_tag[0x1]; 578 u8 reserved_at_64[0xc]; 579 u8 gre_protocol[0x10]; 580 581 union mlx5_ifc_gre_key_bits gre_key; 582 583 u8 vxlan_vni[0x18]; 584 u8 bth_opcode[0x8]; 585 586 u8 geneve_vni[0x18]; 587 u8 reserved_at_d8[0x6]; 588 u8 geneve_tlv_option_0_exist[0x1]; 589 u8 geneve_oam[0x1]; 590 591 u8 reserved_at_e0[0xc]; 592 u8 outer_ipv6_flow_label[0x14]; 593 594 u8 reserved_at_100[0xc]; 595 u8 inner_ipv6_flow_label[0x14]; 596 597 u8 reserved_at_120[0xa]; 598 u8 geneve_opt_len[0x6]; 599 u8 geneve_protocol_type[0x10]; 600 601 u8 reserved_at_140[0x8]; 602 u8 bth_dst_qp[0x18]; 603 u8 reserved_at_160[0x20]; 604 u8 outer_esp_spi[0x20]; 605 u8 reserved_at_1a0[0x60]; 606 }; 607 608 struct mlx5_ifc_fte_match_mpls_bits { 609 u8 mpls_label[0x14]; 610 u8 mpls_exp[0x3]; 611 u8 mpls_s_bos[0x1]; 612 u8 mpls_ttl[0x8]; 613 }; 614 615 struct mlx5_ifc_fte_match_set_misc2_bits { 616 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 617 618 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 619 620 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 621 622 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 623 624 u8 metadata_reg_c_7[0x20]; 625 626 u8 metadata_reg_c_6[0x20]; 627 628 u8 metadata_reg_c_5[0x20]; 629 630 u8 metadata_reg_c_4[0x20]; 631 632 u8 metadata_reg_c_3[0x20]; 633 634 u8 metadata_reg_c_2[0x20]; 635 636 u8 metadata_reg_c_1[0x20]; 637 638 u8 metadata_reg_c_0[0x20]; 639 640 u8 metadata_reg_a[0x20]; 641 642 u8 reserved_at_1a0[0x8]; 643 644 u8 macsec_syndrome[0x8]; 645 u8 ipsec_syndrome[0x8]; 646 u8 reserved_at_1b8[0x8]; 647 648 u8 reserved_at_1c0[0x40]; 649 }; 650 651 struct mlx5_ifc_fte_match_set_misc3_bits { 652 u8 inner_tcp_seq_num[0x20]; 653 654 u8 outer_tcp_seq_num[0x20]; 655 656 u8 inner_tcp_ack_num[0x20]; 657 658 u8 outer_tcp_ack_num[0x20]; 659 660 u8 reserved_at_80[0x8]; 661 u8 outer_vxlan_gpe_vni[0x18]; 662 663 u8 outer_vxlan_gpe_next_protocol[0x8]; 664 u8 outer_vxlan_gpe_flags[0x8]; 665 u8 reserved_at_b0[0x10]; 666 667 u8 icmp_header_data[0x20]; 668 669 u8 icmpv6_header_data[0x20]; 670 671 u8 icmp_type[0x8]; 672 u8 icmp_code[0x8]; 673 u8 icmpv6_type[0x8]; 674 u8 icmpv6_code[0x8]; 675 676 u8 geneve_tlv_option_0_data[0x20]; 677 678 u8 gtpu_teid[0x20]; 679 680 u8 gtpu_msg_type[0x8]; 681 u8 gtpu_msg_flags[0x8]; 682 u8 reserved_at_170[0x10]; 683 684 u8 gtpu_dw_2[0x20]; 685 686 u8 gtpu_first_ext_dw_0[0x20]; 687 688 u8 gtpu_dw_0[0x20]; 689 690 u8 reserved_at_1e0[0x20]; 691 }; 692 693 struct mlx5_ifc_fte_match_set_misc4_bits { 694 u8 prog_sample_field_value_0[0x20]; 695 696 u8 prog_sample_field_id_0[0x20]; 697 698 u8 prog_sample_field_value_1[0x20]; 699 700 u8 prog_sample_field_id_1[0x20]; 701 702 u8 prog_sample_field_value_2[0x20]; 703 704 u8 prog_sample_field_id_2[0x20]; 705 706 u8 prog_sample_field_value_3[0x20]; 707 708 u8 prog_sample_field_id_3[0x20]; 709 710 u8 reserved_at_100[0x100]; 711 }; 712 713 struct mlx5_ifc_fte_match_set_misc5_bits { 714 u8 macsec_tag_0[0x20]; 715 716 u8 macsec_tag_1[0x20]; 717 718 u8 macsec_tag_2[0x20]; 719 720 u8 macsec_tag_3[0x20]; 721 722 u8 tunnel_header_0[0x20]; 723 724 u8 tunnel_header_1[0x20]; 725 726 u8 tunnel_header_2[0x20]; 727 728 u8 tunnel_header_3[0x20]; 729 730 u8 reserved_at_100[0x100]; 731 }; 732 733 struct mlx5_ifc_cmd_pas_bits { 734 u8 pa_h[0x20]; 735 736 u8 pa_l[0x14]; 737 u8 reserved_at_34[0xc]; 738 }; 739 740 struct mlx5_ifc_uint64_bits { 741 u8 hi[0x20]; 742 743 u8 lo[0x20]; 744 }; 745 746 enum { 747 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 748 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 749 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 750 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 751 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 752 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 753 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 754 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 755 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 756 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 757 }; 758 759 struct mlx5_ifc_ads_bits { 760 u8 fl[0x1]; 761 u8 free_ar[0x1]; 762 u8 reserved_at_2[0xe]; 763 u8 pkey_index[0x10]; 764 765 u8 reserved_at_20[0x8]; 766 u8 grh[0x1]; 767 u8 mlid[0x7]; 768 u8 rlid[0x10]; 769 770 u8 ack_timeout[0x5]; 771 u8 reserved_at_45[0x3]; 772 u8 src_addr_index[0x8]; 773 u8 reserved_at_50[0x4]; 774 u8 stat_rate[0x4]; 775 u8 hop_limit[0x8]; 776 777 u8 reserved_at_60[0x4]; 778 u8 tclass[0x8]; 779 u8 flow_label[0x14]; 780 781 u8 rgid_rip[16][0x8]; 782 783 u8 reserved_at_100[0x4]; 784 u8 f_dscp[0x1]; 785 u8 f_ecn[0x1]; 786 u8 reserved_at_106[0x1]; 787 u8 f_eth_prio[0x1]; 788 u8 ecn[0x2]; 789 u8 dscp[0x6]; 790 u8 udp_sport[0x10]; 791 792 u8 dei_cfi[0x1]; 793 u8 eth_prio[0x3]; 794 u8 sl[0x4]; 795 u8 vhca_port_num[0x8]; 796 u8 rmac_47_32[0x10]; 797 798 u8 rmac_31_0[0x20]; 799 }; 800 801 struct mlx5_ifc_flow_table_nic_cap_bits { 802 u8 nic_rx_multi_path_tirs[0x1]; 803 u8 nic_rx_multi_path_tirs_fts[0x1]; 804 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 805 u8 reserved_at_3[0x4]; 806 u8 sw_owner_reformat_supported[0x1]; 807 u8 reserved_at_8[0x18]; 808 809 u8 encap_general_header[0x1]; 810 u8 reserved_at_21[0xa]; 811 u8 log_max_packet_reformat_context[0x5]; 812 u8 reserved_at_30[0x6]; 813 u8 max_encap_header_size[0xa]; 814 u8 reserved_at_40[0x1c0]; 815 816 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 817 818 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 819 820 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 821 822 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 823 824 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 825 826 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 827 828 u8 reserved_at_e00[0x700]; 829 830 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 831 832 u8 reserved_at_1580[0x280]; 833 834 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 835 836 u8 reserved_at_1880[0x780]; 837 838 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 839 840 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 841 842 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 843 844 u8 reserved_at_20c0[0x5f40]; 845 }; 846 847 struct mlx5_ifc_port_selection_cap_bits { 848 u8 reserved_at_0[0x10]; 849 u8 port_select_flow_table[0x1]; 850 u8 reserved_at_11[0x1]; 851 u8 port_select_flow_table_bypass[0x1]; 852 u8 reserved_at_13[0xd]; 853 854 u8 reserved_at_20[0x1e0]; 855 856 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 857 858 u8 reserved_at_400[0x7c00]; 859 }; 860 861 enum { 862 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 863 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 864 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 865 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 866 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 867 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 868 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 869 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 870 }; 871 872 struct mlx5_ifc_flow_table_eswitch_cap_bits { 873 u8 fdb_to_vport_reg_c_id[0x8]; 874 u8 reserved_at_8[0xd]; 875 u8 fdb_modify_header_fwd_to_table[0x1]; 876 u8 fdb_ipv4_ttl_modify[0x1]; 877 u8 flow_source[0x1]; 878 u8 reserved_at_18[0x2]; 879 u8 multi_fdb_encap[0x1]; 880 u8 egress_acl_forward_to_vport[0x1]; 881 u8 fdb_multi_path_to_table[0x1]; 882 u8 reserved_at_1d[0x3]; 883 884 u8 reserved_at_20[0x1e0]; 885 886 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 887 888 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 889 890 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 891 892 u8 reserved_at_800[0x1000]; 893 894 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 895 896 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 897 898 u8 sw_steering_uplink_icm_address_rx[0x40]; 899 900 u8 sw_steering_uplink_icm_address_tx[0x40]; 901 902 u8 reserved_at_1900[0x6700]; 903 }; 904 905 enum { 906 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 907 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 908 }; 909 910 struct mlx5_ifc_e_switch_cap_bits { 911 u8 vport_svlan_strip[0x1]; 912 u8 vport_cvlan_strip[0x1]; 913 u8 vport_svlan_insert[0x1]; 914 u8 vport_cvlan_insert_if_not_exist[0x1]; 915 u8 vport_cvlan_insert_overwrite[0x1]; 916 u8 reserved_at_5[0x2]; 917 u8 esw_shared_ingress_acl[0x1]; 918 u8 esw_uplink_ingress_acl[0x1]; 919 u8 root_ft_on_other_esw[0x1]; 920 u8 reserved_at_a[0xf]; 921 u8 esw_functions_changed[0x1]; 922 u8 reserved_at_1a[0x1]; 923 u8 ecpf_vport_exists[0x1]; 924 u8 counter_eswitch_affinity[0x1]; 925 u8 merged_eswitch[0x1]; 926 u8 nic_vport_node_guid_modify[0x1]; 927 u8 nic_vport_port_guid_modify[0x1]; 928 929 u8 vxlan_encap_decap[0x1]; 930 u8 nvgre_encap_decap[0x1]; 931 u8 reserved_at_22[0x1]; 932 u8 log_max_fdb_encap_uplink[0x5]; 933 u8 reserved_at_21[0x3]; 934 u8 log_max_packet_reformat_context[0x5]; 935 u8 reserved_2b[0x6]; 936 u8 max_encap_header_size[0xa]; 937 938 u8 reserved_at_40[0xb]; 939 u8 log_max_esw_sf[0x5]; 940 u8 esw_sf_base_id[0x10]; 941 942 u8 reserved_at_60[0x7a0]; 943 944 }; 945 946 struct mlx5_ifc_qos_cap_bits { 947 u8 packet_pacing[0x1]; 948 u8 esw_scheduling[0x1]; 949 u8 esw_bw_share[0x1]; 950 u8 esw_rate_limit[0x1]; 951 u8 reserved_at_4[0x1]; 952 u8 packet_pacing_burst_bound[0x1]; 953 u8 packet_pacing_typical_size[0x1]; 954 u8 reserved_at_7[0x1]; 955 u8 nic_sq_scheduling[0x1]; 956 u8 nic_bw_share[0x1]; 957 u8 nic_rate_limit[0x1]; 958 u8 packet_pacing_uid[0x1]; 959 u8 log_esw_max_sched_depth[0x4]; 960 u8 reserved_at_10[0x10]; 961 962 u8 reserved_at_20[0xb]; 963 u8 log_max_qos_nic_queue_group[0x5]; 964 u8 reserved_at_30[0x10]; 965 966 u8 packet_pacing_max_rate[0x20]; 967 968 u8 packet_pacing_min_rate[0x20]; 969 970 u8 reserved_at_80[0x10]; 971 u8 packet_pacing_rate_table_size[0x10]; 972 973 u8 esw_element_type[0x10]; 974 u8 esw_tsar_type[0x10]; 975 976 u8 reserved_at_c0[0x10]; 977 u8 max_qos_para_vport[0x10]; 978 979 u8 max_tsar_bw_share[0x20]; 980 981 u8 reserved_at_100[0x20]; 982 983 u8 reserved_at_120[0x3]; 984 u8 log_meter_aso_granularity[0x5]; 985 u8 reserved_at_128[0x3]; 986 u8 log_meter_aso_max_alloc[0x5]; 987 u8 reserved_at_130[0x3]; 988 u8 log_max_num_meter_aso[0x5]; 989 u8 reserved_at_138[0x8]; 990 991 u8 reserved_at_140[0x6c0]; 992 }; 993 994 struct mlx5_ifc_debug_cap_bits { 995 u8 core_dump_general[0x1]; 996 u8 core_dump_qp[0x1]; 997 u8 reserved_at_2[0x7]; 998 u8 resource_dump[0x1]; 999 u8 reserved_at_a[0x16]; 1000 1001 u8 reserved_at_20[0x2]; 1002 u8 stall_detect[0x1]; 1003 u8 reserved_at_23[0x1d]; 1004 1005 u8 reserved_at_40[0x7c0]; 1006 }; 1007 1008 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1009 u8 csum_cap[0x1]; 1010 u8 vlan_cap[0x1]; 1011 u8 lro_cap[0x1]; 1012 u8 lro_psh_flag[0x1]; 1013 u8 lro_time_stamp[0x1]; 1014 u8 reserved_at_5[0x2]; 1015 u8 wqe_vlan_insert[0x1]; 1016 u8 self_lb_en_modifiable[0x1]; 1017 u8 reserved_at_9[0x2]; 1018 u8 max_lso_cap[0x5]; 1019 u8 multi_pkt_send_wqe[0x2]; 1020 u8 wqe_inline_mode[0x2]; 1021 u8 rss_ind_tbl_cap[0x4]; 1022 u8 reg_umr_sq[0x1]; 1023 u8 scatter_fcs[0x1]; 1024 u8 enhanced_multi_pkt_send_wqe[0x1]; 1025 u8 tunnel_lso_const_out_ip_id[0x1]; 1026 u8 tunnel_lro_gre[0x1]; 1027 u8 tunnel_lro_vxlan[0x1]; 1028 u8 tunnel_stateless_gre[0x1]; 1029 u8 tunnel_stateless_vxlan[0x1]; 1030 1031 u8 swp[0x1]; 1032 u8 swp_csum[0x1]; 1033 u8 swp_lso[0x1]; 1034 u8 cqe_checksum_full[0x1]; 1035 u8 tunnel_stateless_geneve_tx[0x1]; 1036 u8 tunnel_stateless_mpls_over_udp[0x1]; 1037 u8 tunnel_stateless_mpls_over_gre[0x1]; 1038 u8 tunnel_stateless_vxlan_gpe[0x1]; 1039 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1040 u8 tunnel_stateless_ip_over_ip[0x1]; 1041 u8 insert_trailer[0x1]; 1042 u8 reserved_at_2b[0x1]; 1043 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1044 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1045 u8 reserved_at_2e[0x2]; 1046 u8 max_vxlan_udp_ports[0x8]; 1047 u8 reserved_at_38[0x6]; 1048 u8 max_geneve_opt_len[0x1]; 1049 u8 tunnel_stateless_geneve_rx[0x1]; 1050 1051 u8 reserved_at_40[0x10]; 1052 u8 lro_min_mss_size[0x10]; 1053 1054 u8 reserved_at_60[0x120]; 1055 1056 u8 lro_timer_supported_periods[4][0x20]; 1057 1058 u8 reserved_at_200[0x600]; 1059 }; 1060 1061 enum { 1062 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1063 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1064 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1065 }; 1066 1067 struct mlx5_ifc_roce_cap_bits { 1068 u8 roce_apm[0x1]; 1069 u8 reserved_at_1[0x3]; 1070 u8 sw_r_roce_src_udp_port[0x1]; 1071 u8 fl_rc_qp_when_roce_disabled[0x1]; 1072 u8 fl_rc_qp_when_roce_enabled[0x1]; 1073 u8 reserved_at_7[0x17]; 1074 u8 qp_ts_format[0x2]; 1075 1076 u8 reserved_at_20[0x60]; 1077 1078 u8 reserved_at_80[0xc]; 1079 u8 l3_type[0x4]; 1080 u8 reserved_at_90[0x8]; 1081 u8 roce_version[0x8]; 1082 1083 u8 reserved_at_a0[0x10]; 1084 u8 r_roce_dest_udp_port[0x10]; 1085 1086 u8 r_roce_max_src_udp_port[0x10]; 1087 u8 r_roce_min_src_udp_port[0x10]; 1088 1089 u8 reserved_at_e0[0x10]; 1090 u8 roce_address_table_size[0x10]; 1091 1092 u8 reserved_at_100[0x700]; 1093 }; 1094 1095 struct mlx5_ifc_sync_steering_in_bits { 1096 u8 opcode[0x10]; 1097 u8 uid[0x10]; 1098 1099 u8 reserved_at_20[0x10]; 1100 u8 op_mod[0x10]; 1101 1102 u8 reserved_at_40[0xc0]; 1103 }; 1104 1105 struct mlx5_ifc_sync_steering_out_bits { 1106 u8 status[0x8]; 1107 u8 reserved_at_8[0x18]; 1108 1109 u8 syndrome[0x20]; 1110 1111 u8 reserved_at_40[0x40]; 1112 }; 1113 1114 struct mlx5_ifc_device_mem_cap_bits { 1115 u8 memic[0x1]; 1116 u8 reserved_at_1[0x1f]; 1117 1118 u8 reserved_at_20[0xb]; 1119 u8 log_min_memic_alloc_size[0x5]; 1120 u8 reserved_at_30[0x8]; 1121 u8 log_max_memic_addr_alignment[0x8]; 1122 1123 u8 memic_bar_start_addr[0x40]; 1124 1125 u8 memic_bar_size[0x20]; 1126 1127 u8 max_memic_size[0x20]; 1128 1129 u8 steering_sw_icm_start_address[0x40]; 1130 1131 u8 reserved_at_100[0x8]; 1132 u8 log_header_modify_sw_icm_size[0x8]; 1133 u8 reserved_at_110[0x2]; 1134 u8 log_sw_icm_alloc_granularity[0x6]; 1135 u8 log_steering_sw_icm_size[0x8]; 1136 1137 u8 reserved_at_120[0x18]; 1138 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1139 1140 u8 header_modify_sw_icm_start_address[0x40]; 1141 1142 u8 reserved_at_180[0x40]; 1143 1144 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1145 1146 u8 memic_operations[0x20]; 1147 1148 u8 reserved_at_220[0x5e0]; 1149 }; 1150 1151 struct mlx5_ifc_device_event_cap_bits { 1152 u8 user_affiliated_events[4][0x40]; 1153 1154 u8 user_unaffiliated_events[4][0x40]; 1155 }; 1156 1157 struct mlx5_ifc_virtio_emulation_cap_bits { 1158 u8 desc_tunnel_offload_type[0x1]; 1159 u8 eth_frame_offload_type[0x1]; 1160 u8 virtio_version_1_0[0x1]; 1161 u8 device_features_bits_mask[0xd]; 1162 u8 event_mode[0x8]; 1163 u8 virtio_queue_type[0x8]; 1164 1165 u8 max_tunnel_desc[0x10]; 1166 u8 reserved_at_30[0x3]; 1167 u8 log_doorbell_stride[0x5]; 1168 u8 reserved_at_38[0x3]; 1169 u8 log_doorbell_bar_size[0x5]; 1170 1171 u8 doorbell_bar_offset[0x40]; 1172 1173 u8 max_emulated_devices[0x8]; 1174 u8 max_num_virtio_queues[0x18]; 1175 1176 u8 reserved_at_a0[0x60]; 1177 1178 u8 umem_1_buffer_param_a[0x20]; 1179 1180 u8 umem_1_buffer_param_b[0x20]; 1181 1182 u8 umem_2_buffer_param_a[0x20]; 1183 1184 u8 umem_2_buffer_param_b[0x20]; 1185 1186 u8 umem_3_buffer_param_a[0x20]; 1187 1188 u8 umem_3_buffer_param_b[0x20]; 1189 1190 u8 reserved_at_1c0[0x640]; 1191 }; 1192 1193 enum { 1194 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1195 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1196 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1197 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1198 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1199 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1200 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1201 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1202 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1203 }; 1204 1205 enum { 1206 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1207 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1208 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1209 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1210 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1211 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1212 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1213 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1214 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1215 }; 1216 1217 struct mlx5_ifc_atomic_caps_bits { 1218 u8 reserved_at_0[0x40]; 1219 1220 u8 atomic_req_8B_endianness_mode[0x2]; 1221 u8 reserved_at_42[0x4]; 1222 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1223 1224 u8 reserved_at_47[0x19]; 1225 1226 u8 reserved_at_60[0x20]; 1227 1228 u8 reserved_at_80[0x10]; 1229 u8 atomic_operations[0x10]; 1230 1231 u8 reserved_at_a0[0x10]; 1232 u8 atomic_size_qp[0x10]; 1233 1234 u8 reserved_at_c0[0x10]; 1235 u8 atomic_size_dc[0x10]; 1236 1237 u8 reserved_at_e0[0x720]; 1238 }; 1239 1240 struct mlx5_ifc_odp_cap_bits { 1241 u8 reserved_at_0[0x40]; 1242 1243 u8 sig[0x1]; 1244 u8 reserved_at_41[0x1f]; 1245 1246 u8 reserved_at_60[0x20]; 1247 1248 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1249 1250 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1251 1252 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1253 1254 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1255 1256 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1257 1258 u8 reserved_at_120[0x6E0]; 1259 }; 1260 1261 struct mlx5_ifc_calc_op { 1262 u8 reserved_at_0[0x10]; 1263 u8 reserved_at_10[0x9]; 1264 u8 op_swap_endianness[0x1]; 1265 u8 op_min[0x1]; 1266 u8 op_xor[0x1]; 1267 u8 op_or[0x1]; 1268 u8 op_and[0x1]; 1269 u8 op_max[0x1]; 1270 u8 op_add[0x1]; 1271 }; 1272 1273 struct mlx5_ifc_vector_calc_cap_bits { 1274 u8 calc_matrix[0x1]; 1275 u8 reserved_at_1[0x1f]; 1276 u8 reserved_at_20[0x8]; 1277 u8 max_vec_count[0x8]; 1278 u8 reserved_at_30[0xd]; 1279 u8 max_chunk_size[0x3]; 1280 struct mlx5_ifc_calc_op calc0; 1281 struct mlx5_ifc_calc_op calc1; 1282 struct mlx5_ifc_calc_op calc2; 1283 struct mlx5_ifc_calc_op calc3; 1284 1285 u8 reserved_at_c0[0x720]; 1286 }; 1287 1288 struct mlx5_ifc_tls_cap_bits { 1289 u8 tls_1_2_aes_gcm_128[0x1]; 1290 u8 tls_1_3_aes_gcm_128[0x1]; 1291 u8 tls_1_2_aes_gcm_256[0x1]; 1292 u8 tls_1_3_aes_gcm_256[0x1]; 1293 u8 reserved_at_4[0x1c]; 1294 1295 u8 reserved_at_20[0x7e0]; 1296 }; 1297 1298 struct mlx5_ifc_ipsec_cap_bits { 1299 u8 ipsec_full_offload[0x1]; 1300 u8 ipsec_crypto_offload[0x1]; 1301 u8 ipsec_esn[0x1]; 1302 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1303 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1304 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1305 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1306 u8 reserved_at_7[0x4]; 1307 u8 log_max_ipsec_offload[0x5]; 1308 u8 reserved_at_10[0x10]; 1309 1310 u8 min_log_ipsec_full_replay_window[0x8]; 1311 u8 max_log_ipsec_full_replay_window[0x8]; 1312 u8 reserved_at_30[0x7d0]; 1313 }; 1314 1315 struct mlx5_ifc_macsec_cap_bits { 1316 u8 macsec_epn[0x1]; 1317 u8 reserved_at_1[0x2]; 1318 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1319 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1320 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1321 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1322 u8 reserved_at_7[0x4]; 1323 u8 log_max_macsec_offload[0x5]; 1324 u8 reserved_at_10[0x10]; 1325 1326 u8 min_log_macsec_full_replay_window[0x8]; 1327 u8 max_log_macsec_full_replay_window[0x8]; 1328 u8 reserved_at_30[0x10]; 1329 1330 u8 reserved_at_40[0x7c0]; 1331 }; 1332 1333 enum { 1334 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1335 MLX5_WQ_TYPE_CYCLIC = 0x1, 1336 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1337 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1338 }; 1339 1340 enum { 1341 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1342 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1343 }; 1344 1345 enum { 1346 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1347 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1348 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1349 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1350 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1351 }; 1352 1353 enum { 1354 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1355 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1356 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1357 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1358 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1359 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1360 }; 1361 1362 enum { 1363 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1364 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1365 }; 1366 1367 enum { 1368 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1369 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1370 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1371 }; 1372 1373 enum { 1374 MLX5_CAP_PORT_TYPE_IB = 0x0, 1375 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1376 }; 1377 1378 enum { 1379 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1380 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1381 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1382 }; 1383 1384 enum { 1385 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1386 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1387 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1388 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1389 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1390 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1391 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1392 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1393 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1394 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1395 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1396 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1397 }; 1398 1399 enum { 1400 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1401 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1402 }; 1403 1404 #define MLX5_FC_BULK_SIZE_FACTOR 128 1405 1406 enum mlx5_fc_bulk_alloc_bitmask { 1407 MLX5_FC_BULK_128 = (1 << 0), 1408 MLX5_FC_BULK_256 = (1 << 1), 1409 MLX5_FC_BULK_512 = (1 << 2), 1410 MLX5_FC_BULK_1024 = (1 << 3), 1411 MLX5_FC_BULK_2048 = (1 << 4), 1412 MLX5_FC_BULK_4096 = (1 << 5), 1413 MLX5_FC_BULK_8192 = (1 << 6), 1414 MLX5_FC_BULK_16384 = (1 << 7), 1415 }; 1416 1417 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1418 1419 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1420 1421 enum { 1422 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1423 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1424 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1425 }; 1426 1427 struct mlx5_ifc_cmd_hca_cap_bits { 1428 u8 reserved_at_0[0x10]; 1429 u8 shared_object_to_user_object_allowed[0x1]; 1430 u8 reserved_at_13[0xe]; 1431 u8 vhca_resource_manager[0x1]; 1432 1433 u8 hca_cap_2[0x1]; 1434 u8 create_lag_when_not_master_up[0x1]; 1435 u8 dtor[0x1]; 1436 u8 event_on_vhca_state_teardown_request[0x1]; 1437 u8 event_on_vhca_state_in_use[0x1]; 1438 u8 event_on_vhca_state_active[0x1]; 1439 u8 event_on_vhca_state_allocated[0x1]; 1440 u8 event_on_vhca_state_invalid[0x1]; 1441 u8 reserved_at_28[0x8]; 1442 u8 vhca_id[0x10]; 1443 1444 u8 reserved_at_40[0x40]; 1445 1446 u8 log_max_srq_sz[0x8]; 1447 u8 log_max_qp_sz[0x8]; 1448 u8 event_cap[0x1]; 1449 u8 reserved_at_91[0x2]; 1450 u8 isolate_vl_tc_new[0x1]; 1451 u8 reserved_at_94[0x4]; 1452 u8 prio_tag_required[0x1]; 1453 u8 reserved_at_99[0x2]; 1454 u8 log_max_qp[0x5]; 1455 1456 u8 reserved_at_a0[0x3]; 1457 u8 ece_support[0x1]; 1458 u8 reserved_at_a4[0x5]; 1459 u8 reg_c_preserve[0x1]; 1460 u8 reserved_at_aa[0x1]; 1461 u8 log_max_srq[0x5]; 1462 u8 reserved_at_b0[0x1]; 1463 u8 uplink_follow[0x1]; 1464 u8 ts_cqe_to_dest_cqn[0x1]; 1465 u8 reserved_at_b3[0x7]; 1466 u8 shampo[0x1]; 1467 u8 reserved_at_bb[0x5]; 1468 1469 u8 max_sgl_for_optimized_performance[0x8]; 1470 u8 log_max_cq_sz[0x8]; 1471 u8 relaxed_ordering_write_umr[0x1]; 1472 u8 relaxed_ordering_read_umr[0x1]; 1473 u8 reserved_at_d2[0x7]; 1474 u8 virtio_net_device_emualtion_manager[0x1]; 1475 u8 virtio_blk_device_emualtion_manager[0x1]; 1476 u8 log_max_cq[0x5]; 1477 1478 u8 log_max_eq_sz[0x8]; 1479 u8 relaxed_ordering_write[0x1]; 1480 u8 relaxed_ordering_read[0x1]; 1481 u8 log_max_mkey[0x6]; 1482 u8 reserved_at_f0[0x8]; 1483 u8 dump_fill_mkey[0x1]; 1484 u8 reserved_at_f9[0x2]; 1485 u8 fast_teardown[0x1]; 1486 u8 log_max_eq[0x4]; 1487 1488 u8 max_indirection[0x8]; 1489 u8 fixed_buffer_size[0x1]; 1490 u8 log_max_mrw_sz[0x7]; 1491 u8 force_teardown[0x1]; 1492 u8 reserved_at_111[0x1]; 1493 u8 log_max_bsf_list_size[0x6]; 1494 u8 umr_extended_translation_offset[0x1]; 1495 u8 null_mkey[0x1]; 1496 u8 log_max_klm_list_size[0x6]; 1497 1498 u8 reserved_at_120[0xa]; 1499 u8 log_max_ra_req_dc[0x6]; 1500 u8 reserved_at_130[0x2]; 1501 u8 eth_wqe_too_small[0x1]; 1502 u8 reserved_at_133[0x6]; 1503 u8 vnic_env_cq_overrun[0x1]; 1504 u8 log_max_ra_res_dc[0x6]; 1505 1506 u8 reserved_at_140[0x5]; 1507 u8 release_all_pages[0x1]; 1508 u8 must_not_use[0x1]; 1509 u8 reserved_at_147[0x2]; 1510 u8 roce_accl[0x1]; 1511 u8 log_max_ra_req_qp[0x6]; 1512 u8 reserved_at_150[0xa]; 1513 u8 log_max_ra_res_qp[0x6]; 1514 1515 u8 end_pad[0x1]; 1516 u8 cc_query_allowed[0x1]; 1517 u8 cc_modify_allowed[0x1]; 1518 u8 start_pad[0x1]; 1519 u8 cache_line_128byte[0x1]; 1520 u8 reserved_at_165[0x4]; 1521 u8 rts2rts_qp_counters_set_id[0x1]; 1522 u8 reserved_at_16a[0x2]; 1523 u8 vnic_env_int_rq_oob[0x1]; 1524 u8 sbcam_reg[0x1]; 1525 u8 reserved_at_16e[0x1]; 1526 u8 qcam_reg[0x1]; 1527 u8 gid_table_size[0x10]; 1528 1529 u8 out_of_seq_cnt[0x1]; 1530 u8 vport_counters[0x1]; 1531 u8 retransmission_q_counters[0x1]; 1532 u8 debug[0x1]; 1533 u8 modify_rq_counter_set_id[0x1]; 1534 u8 rq_delay_drop[0x1]; 1535 u8 max_qp_cnt[0xa]; 1536 u8 pkey_table_size[0x10]; 1537 1538 u8 vport_group_manager[0x1]; 1539 u8 vhca_group_manager[0x1]; 1540 u8 ib_virt[0x1]; 1541 u8 eth_virt[0x1]; 1542 u8 vnic_env_queue_counters[0x1]; 1543 u8 ets[0x1]; 1544 u8 nic_flow_table[0x1]; 1545 u8 eswitch_manager[0x1]; 1546 u8 device_memory[0x1]; 1547 u8 mcam_reg[0x1]; 1548 u8 pcam_reg[0x1]; 1549 u8 local_ca_ack_delay[0x5]; 1550 u8 port_module_event[0x1]; 1551 u8 enhanced_error_q_counters[0x1]; 1552 u8 ports_check[0x1]; 1553 u8 reserved_at_1b3[0x1]; 1554 u8 disable_link_up[0x1]; 1555 u8 beacon_led[0x1]; 1556 u8 port_type[0x2]; 1557 u8 num_ports[0x8]; 1558 1559 u8 reserved_at_1c0[0x1]; 1560 u8 pps[0x1]; 1561 u8 pps_modify[0x1]; 1562 u8 log_max_msg[0x5]; 1563 u8 reserved_at_1c8[0x4]; 1564 u8 max_tc[0x4]; 1565 u8 temp_warn_event[0x1]; 1566 u8 dcbx[0x1]; 1567 u8 general_notification_event[0x1]; 1568 u8 reserved_at_1d3[0x2]; 1569 u8 fpga[0x1]; 1570 u8 rol_s[0x1]; 1571 u8 rol_g[0x1]; 1572 u8 reserved_at_1d8[0x1]; 1573 u8 wol_s[0x1]; 1574 u8 wol_g[0x1]; 1575 u8 wol_a[0x1]; 1576 u8 wol_b[0x1]; 1577 u8 wol_m[0x1]; 1578 u8 wol_u[0x1]; 1579 u8 wol_p[0x1]; 1580 1581 u8 stat_rate_support[0x10]; 1582 u8 reserved_at_1f0[0x1]; 1583 u8 pci_sync_for_fw_update_event[0x1]; 1584 u8 reserved_at_1f2[0x6]; 1585 u8 init2_lag_tx_port_affinity[0x1]; 1586 u8 reserved_at_1fa[0x3]; 1587 u8 cqe_version[0x4]; 1588 1589 u8 compact_address_vector[0x1]; 1590 u8 striding_rq[0x1]; 1591 u8 reserved_at_202[0x1]; 1592 u8 ipoib_enhanced_offloads[0x1]; 1593 u8 ipoib_basic_offloads[0x1]; 1594 u8 reserved_at_205[0x1]; 1595 u8 repeated_block_disabled[0x1]; 1596 u8 umr_modify_entity_size_disabled[0x1]; 1597 u8 umr_modify_atomic_disabled[0x1]; 1598 u8 umr_indirect_mkey_disabled[0x1]; 1599 u8 umr_fence[0x2]; 1600 u8 dc_req_scat_data_cqe[0x1]; 1601 u8 reserved_at_20d[0x2]; 1602 u8 drain_sigerr[0x1]; 1603 u8 cmdif_checksum[0x2]; 1604 u8 sigerr_cqe[0x1]; 1605 u8 reserved_at_213[0x1]; 1606 u8 wq_signature[0x1]; 1607 u8 sctr_data_cqe[0x1]; 1608 u8 reserved_at_216[0x1]; 1609 u8 sho[0x1]; 1610 u8 tph[0x1]; 1611 u8 rf[0x1]; 1612 u8 dct[0x1]; 1613 u8 qos[0x1]; 1614 u8 eth_net_offloads[0x1]; 1615 u8 roce[0x1]; 1616 u8 atomic[0x1]; 1617 u8 reserved_at_21f[0x1]; 1618 1619 u8 cq_oi[0x1]; 1620 u8 cq_resize[0x1]; 1621 u8 cq_moderation[0x1]; 1622 u8 reserved_at_223[0x3]; 1623 u8 cq_eq_remap[0x1]; 1624 u8 pg[0x1]; 1625 u8 block_lb_mc[0x1]; 1626 u8 reserved_at_229[0x1]; 1627 u8 scqe_break_moderation[0x1]; 1628 u8 cq_period_start_from_cqe[0x1]; 1629 u8 cd[0x1]; 1630 u8 reserved_at_22d[0x1]; 1631 u8 apm[0x1]; 1632 u8 vector_calc[0x1]; 1633 u8 umr_ptr_rlky[0x1]; 1634 u8 imaicl[0x1]; 1635 u8 qp_packet_based[0x1]; 1636 u8 reserved_at_233[0x3]; 1637 u8 qkv[0x1]; 1638 u8 pkv[0x1]; 1639 u8 set_deth_sqpn[0x1]; 1640 u8 reserved_at_239[0x3]; 1641 u8 xrc[0x1]; 1642 u8 ud[0x1]; 1643 u8 uc[0x1]; 1644 u8 rc[0x1]; 1645 1646 u8 uar_4k[0x1]; 1647 u8 reserved_at_241[0x9]; 1648 u8 uar_sz[0x6]; 1649 u8 port_selection_cap[0x1]; 1650 u8 reserved_at_248[0x1]; 1651 u8 umem_uid_0[0x1]; 1652 u8 reserved_at_250[0x5]; 1653 u8 log_pg_sz[0x8]; 1654 1655 u8 bf[0x1]; 1656 u8 driver_version[0x1]; 1657 u8 pad_tx_eth_packet[0x1]; 1658 u8 reserved_at_263[0x3]; 1659 u8 mkey_by_name[0x1]; 1660 u8 reserved_at_267[0x4]; 1661 1662 u8 log_bf_reg_size[0x5]; 1663 1664 u8 reserved_at_270[0x6]; 1665 u8 lag_dct[0x2]; 1666 u8 lag_tx_port_affinity[0x1]; 1667 u8 lag_native_fdb_selection[0x1]; 1668 u8 reserved_at_27a[0x1]; 1669 u8 lag_master[0x1]; 1670 u8 num_lag_ports[0x4]; 1671 1672 u8 reserved_at_280[0x10]; 1673 u8 max_wqe_sz_sq[0x10]; 1674 1675 u8 reserved_at_2a0[0x10]; 1676 u8 max_wqe_sz_rq[0x10]; 1677 1678 u8 max_flow_counter_31_16[0x10]; 1679 u8 max_wqe_sz_sq_dc[0x10]; 1680 1681 u8 reserved_at_2e0[0x7]; 1682 u8 max_qp_mcg[0x19]; 1683 1684 u8 reserved_at_300[0x10]; 1685 u8 flow_counter_bulk_alloc[0x8]; 1686 u8 log_max_mcg[0x8]; 1687 1688 u8 reserved_at_320[0x3]; 1689 u8 log_max_transport_domain[0x5]; 1690 u8 reserved_at_328[0x3]; 1691 u8 log_max_pd[0x5]; 1692 u8 reserved_at_330[0xb]; 1693 u8 log_max_xrcd[0x5]; 1694 1695 u8 nic_receive_steering_discard[0x1]; 1696 u8 receive_discard_vport_down[0x1]; 1697 u8 transmit_discard_vport_down[0x1]; 1698 u8 eq_overrun_count[0x1]; 1699 u8 reserved_at_344[0x1]; 1700 u8 invalid_command_count[0x1]; 1701 u8 quota_exceeded_count[0x1]; 1702 u8 reserved_at_347[0x1]; 1703 u8 log_max_flow_counter_bulk[0x8]; 1704 u8 max_flow_counter_15_0[0x10]; 1705 1706 1707 u8 reserved_at_360[0x3]; 1708 u8 log_max_rq[0x5]; 1709 u8 reserved_at_368[0x3]; 1710 u8 log_max_sq[0x5]; 1711 u8 reserved_at_370[0x3]; 1712 u8 log_max_tir[0x5]; 1713 u8 reserved_at_378[0x3]; 1714 u8 log_max_tis[0x5]; 1715 1716 u8 basic_cyclic_rcv_wqe[0x1]; 1717 u8 reserved_at_381[0x2]; 1718 u8 log_max_rmp[0x5]; 1719 u8 reserved_at_388[0x3]; 1720 u8 log_max_rqt[0x5]; 1721 u8 reserved_at_390[0x3]; 1722 u8 log_max_rqt_size[0x5]; 1723 u8 reserved_at_398[0x3]; 1724 u8 log_max_tis_per_sq[0x5]; 1725 1726 u8 ext_stride_num_range[0x1]; 1727 u8 roce_rw_supported[0x1]; 1728 u8 log_max_current_uc_list_wr_supported[0x1]; 1729 u8 log_max_stride_sz_rq[0x5]; 1730 u8 reserved_at_3a8[0x3]; 1731 u8 log_min_stride_sz_rq[0x5]; 1732 u8 reserved_at_3b0[0x3]; 1733 u8 log_max_stride_sz_sq[0x5]; 1734 u8 reserved_at_3b8[0x3]; 1735 u8 log_min_stride_sz_sq[0x5]; 1736 1737 u8 hairpin[0x1]; 1738 u8 reserved_at_3c1[0x2]; 1739 u8 log_max_hairpin_queues[0x5]; 1740 u8 reserved_at_3c8[0x3]; 1741 u8 log_max_hairpin_wq_data_sz[0x5]; 1742 u8 reserved_at_3d0[0x3]; 1743 u8 log_max_hairpin_num_packets[0x5]; 1744 u8 reserved_at_3d8[0x3]; 1745 u8 log_max_wq_sz[0x5]; 1746 1747 u8 nic_vport_change_event[0x1]; 1748 u8 disable_local_lb_uc[0x1]; 1749 u8 disable_local_lb_mc[0x1]; 1750 u8 log_min_hairpin_wq_data_sz[0x5]; 1751 u8 reserved_at_3e8[0x2]; 1752 u8 vhca_state[0x1]; 1753 u8 log_max_vlan_list[0x5]; 1754 u8 reserved_at_3f0[0x3]; 1755 u8 log_max_current_mc_list[0x5]; 1756 u8 reserved_at_3f8[0x3]; 1757 u8 log_max_current_uc_list[0x5]; 1758 1759 u8 general_obj_types[0x40]; 1760 1761 u8 sq_ts_format[0x2]; 1762 u8 rq_ts_format[0x2]; 1763 u8 steering_format_version[0x4]; 1764 u8 create_qp_start_hint[0x18]; 1765 1766 u8 reserved_at_460[0x1]; 1767 u8 ats[0x1]; 1768 u8 reserved_at_462[0x1]; 1769 u8 log_max_uctx[0x5]; 1770 u8 reserved_at_468[0x2]; 1771 u8 ipsec_offload[0x1]; 1772 u8 log_max_umem[0x5]; 1773 u8 max_num_eqs[0x10]; 1774 1775 u8 reserved_at_480[0x1]; 1776 u8 tls_tx[0x1]; 1777 u8 tls_rx[0x1]; 1778 u8 log_max_l2_table[0x5]; 1779 u8 reserved_at_488[0x8]; 1780 u8 log_uar_page_sz[0x10]; 1781 1782 u8 reserved_at_4a0[0x20]; 1783 u8 device_frequency_mhz[0x20]; 1784 u8 device_frequency_khz[0x20]; 1785 1786 u8 reserved_at_500[0x20]; 1787 u8 num_of_uars_per_page[0x20]; 1788 1789 u8 flex_parser_protocols[0x20]; 1790 1791 u8 max_geneve_tlv_options[0x8]; 1792 u8 reserved_at_568[0x3]; 1793 u8 max_geneve_tlv_option_data_len[0x5]; 1794 u8 reserved_at_570[0x9]; 1795 u8 adv_virtualization[0x1]; 1796 u8 reserved_at_57a[0x6]; 1797 1798 u8 reserved_at_580[0xb]; 1799 u8 log_max_dci_stream_channels[0x5]; 1800 u8 reserved_at_590[0x3]; 1801 u8 log_max_dci_errored_streams[0x5]; 1802 u8 reserved_at_598[0x8]; 1803 1804 u8 reserved_at_5a0[0x10]; 1805 u8 enhanced_cqe_compression[0x1]; 1806 u8 reserved_at_5b1[0x2]; 1807 u8 log_max_dek[0x5]; 1808 u8 reserved_at_5b8[0x4]; 1809 u8 mini_cqe_resp_stride_index[0x1]; 1810 u8 cqe_128_always[0x1]; 1811 u8 cqe_compression_128[0x1]; 1812 u8 cqe_compression[0x1]; 1813 1814 u8 cqe_compression_timeout[0x10]; 1815 u8 cqe_compression_max_num[0x10]; 1816 1817 u8 reserved_at_5e0[0x8]; 1818 u8 flex_parser_id_gtpu_dw_0[0x4]; 1819 u8 reserved_at_5ec[0x4]; 1820 u8 tag_matching[0x1]; 1821 u8 rndv_offload_rc[0x1]; 1822 u8 rndv_offload_dc[0x1]; 1823 u8 log_tag_matching_list_sz[0x5]; 1824 u8 reserved_at_5f8[0x3]; 1825 u8 log_max_xrq[0x5]; 1826 1827 u8 affiliate_nic_vport_criteria[0x8]; 1828 u8 native_port_num[0x8]; 1829 u8 num_vhca_ports[0x8]; 1830 u8 flex_parser_id_gtpu_teid[0x4]; 1831 u8 reserved_at_61c[0x2]; 1832 u8 sw_owner_id[0x1]; 1833 u8 reserved_at_61f[0x1]; 1834 1835 u8 max_num_of_monitor_counters[0x10]; 1836 u8 num_ppcnt_monitor_counters[0x10]; 1837 1838 u8 max_num_sf[0x10]; 1839 u8 num_q_monitor_counters[0x10]; 1840 1841 u8 reserved_at_660[0x20]; 1842 1843 u8 sf[0x1]; 1844 u8 sf_set_partition[0x1]; 1845 u8 reserved_at_682[0x1]; 1846 u8 log_max_sf[0x5]; 1847 u8 apu[0x1]; 1848 u8 reserved_at_689[0x4]; 1849 u8 migration[0x1]; 1850 u8 reserved_at_68e[0x2]; 1851 u8 log_min_sf_size[0x8]; 1852 u8 max_num_sf_partitions[0x8]; 1853 1854 u8 uctx_cap[0x20]; 1855 1856 u8 reserved_at_6c0[0x4]; 1857 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1858 u8 flex_parser_id_icmp_dw1[0x4]; 1859 u8 flex_parser_id_icmp_dw0[0x4]; 1860 u8 flex_parser_id_icmpv6_dw1[0x4]; 1861 u8 flex_parser_id_icmpv6_dw0[0x4]; 1862 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1863 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1864 1865 u8 max_num_match_definer[0x10]; 1866 u8 sf_base_id[0x10]; 1867 1868 u8 flex_parser_id_gtpu_dw_2[0x4]; 1869 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1870 u8 num_total_dynamic_vf_msix[0x18]; 1871 u8 reserved_at_720[0x14]; 1872 u8 dynamic_msix_table_size[0xc]; 1873 u8 reserved_at_740[0xc]; 1874 u8 min_dynamic_vf_msix_table_size[0x4]; 1875 u8 reserved_at_750[0x4]; 1876 u8 max_dynamic_vf_msix_table_size[0xc]; 1877 1878 u8 reserved_at_760[0x20]; 1879 u8 vhca_tunnel_commands[0x40]; 1880 u8 match_definer_format_supported[0x40]; 1881 }; 1882 1883 struct mlx5_ifc_cmd_hca_cap_2_bits { 1884 u8 reserved_at_0[0x80]; 1885 1886 u8 migratable[0x1]; 1887 u8 reserved_at_81[0x1f]; 1888 1889 u8 max_reformat_insert_size[0x8]; 1890 u8 max_reformat_insert_offset[0x8]; 1891 u8 max_reformat_remove_size[0x8]; 1892 u8 max_reformat_remove_offset[0x8]; 1893 1894 u8 reserved_at_c0[0x8]; 1895 u8 migration_multi_load[0x1]; 1896 u8 migration_tracking_state[0x1]; 1897 u8 reserved_at_ca[0x16]; 1898 1899 u8 reserved_at_e0[0xc0]; 1900 1901 u8 reserved_at_1a0[0xb]; 1902 u8 log_min_mkey_entity_size[0x5]; 1903 u8 reserved_at_1b0[0x10]; 1904 1905 u8 reserved_at_1c0[0x60]; 1906 1907 u8 reserved_at_220[0x1]; 1908 u8 sw_vhca_id_valid[0x1]; 1909 u8 sw_vhca_id[0xe]; 1910 u8 reserved_at_230[0x10]; 1911 1912 u8 reserved_at_240[0xb]; 1913 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1914 u8 reserved_at_250[0x10]; 1915 1916 u8 reserved_at_260[0x5a0]; 1917 }; 1918 1919 enum mlx5_ifc_flow_destination_type { 1920 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1921 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1922 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1923 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1924 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1925 }; 1926 1927 enum mlx5_flow_table_miss_action { 1928 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1929 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1930 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1931 }; 1932 1933 struct mlx5_ifc_dest_format_struct_bits { 1934 u8 destination_type[0x8]; 1935 u8 destination_id[0x18]; 1936 1937 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1938 u8 packet_reformat[0x1]; 1939 u8 reserved_at_22[0xe]; 1940 u8 destination_eswitch_owner_vhca_id[0x10]; 1941 }; 1942 1943 struct mlx5_ifc_flow_counter_list_bits { 1944 u8 flow_counter_id[0x20]; 1945 1946 u8 reserved_at_20[0x20]; 1947 }; 1948 1949 struct mlx5_ifc_extended_dest_format_bits { 1950 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1951 1952 u8 packet_reformat_id[0x20]; 1953 1954 u8 reserved_at_60[0x20]; 1955 }; 1956 1957 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1958 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1959 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1960 }; 1961 1962 struct mlx5_ifc_fte_match_param_bits { 1963 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1964 1965 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1966 1967 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1968 1969 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1970 1971 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1972 1973 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1974 1975 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1976 1977 u8 reserved_at_e00[0x200]; 1978 }; 1979 1980 enum { 1981 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1982 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1983 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1984 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1985 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1986 }; 1987 1988 struct mlx5_ifc_rx_hash_field_select_bits { 1989 u8 l3_prot_type[0x1]; 1990 u8 l4_prot_type[0x1]; 1991 u8 selected_fields[0x1e]; 1992 }; 1993 1994 enum { 1995 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1996 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1997 }; 1998 1999 enum { 2000 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2001 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2002 }; 2003 2004 struct mlx5_ifc_wq_bits { 2005 u8 wq_type[0x4]; 2006 u8 wq_signature[0x1]; 2007 u8 end_padding_mode[0x2]; 2008 u8 cd_slave[0x1]; 2009 u8 reserved_at_8[0x18]; 2010 2011 u8 hds_skip_first_sge[0x1]; 2012 u8 log2_hds_buf_size[0x3]; 2013 u8 reserved_at_24[0x7]; 2014 u8 page_offset[0x5]; 2015 u8 lwm[0x10]; 2016 2017 u8 reserved_at_40[0x8]; 2018 u8 pd[0x18]; 2019 2020 u8 reserved_at_60[0x8]; 2021 u8 uar_page[0x18]; 2022 2023 u8 dbr_addr[0x40]; 2024 2025 u8 hw_counter[0x20]; 2026 2027 u8 sw_counter[0x20]; 2028 2029 u8 reserved_at_100[0xc]; 2030 u8 log_wq_stride[0x4]; 2031 u8 reserved_at_110[0x3]; 2032 u8 log_wq_pg_sz[0x5]; 2033 u8 reserved_at_118[0x3]; 2034 u8 log_wq_sz[0x5]; 2035 2036 u8 dbr_umem_valid[0x1]; 2037 u8 wq_umem_valid[0x1]; 2038 u8 reserved_at_122[0x1]; 2039 u8 log_hairpin_num_packets[0x5]; 2040 u8 reserved_at_128[0x3]; 2041 u8 log_hairpin_data_sz[0x5]; 2042 2043 u8 reserved_at_130[0x4]; 2044 u8 log_wqe_num_of_strides[0x4]; 2045 u8 two_byte_shift_en[0x1]; 2046 u8 reserved_at_139[0x4]; 2047 u8 log_wqe_stride_size[0x3]; 2048 2049 u8 reserved_at_140[0x80]; 2050 2051 u8 headers_mkey[0x20]; 2052 2053 u8 shampo_enable[0x1]; 2054 u8 reserved_at_1e1[0x4]; 2055 u8 log_reservation_size[0x3]; 2056 u8 reserved_at_1e8[0x5]; 2057 u8 log_max_num_of_packets_per_reservation[0x3]; 2058 u8 reserved_at_1f0[0x6]; 2059 u8 log_headers_entry_size[0x2]; 2060 u8 reserved_at_1f8[0x4]; 2061 u8 log_headers_buffer_entry_num[0x4]; 2062 2063 u8 reserved_at_200[0x400]; 2064 2065 struct mlx5_ifc_cmd_pas_bits pas[]; 2066 }; 2067 2068 struct mlx5_ifc_rq_num_bits { 2069 u8 reserved_at_0[0x8]; 2070 u8 rq_num[0x18]; 2071 }; 2072 2073 struct mlx5_ifc_mac_address_layout_bits { 2074 u8 reserved_at_0[0x10]; 2075 u8 mac_addr_47_32[0x10]; 2076 2077 u8 mac_addr_31_0[0x20]; 2078 }; 2079 2080 struct mlx5_ifc_vlan_layout_bits { 2081 u8 reserved_at_0[0x14]; 2082 u8 vlan[0x0c]; 2083 2084 u8 reserved_at_20[0x20]; 2085 }; 2086 2087 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2088 u8 reserved_at_0[0xa0]; 2089 2090 u8 min_time_between_cnps[0x20]; 2091 2092 u8 reserved_at_c0[0x12]; 2093 u8 cnp_dscp[0x6]; 2094 u8 reserved_at_d8[0x4]; 2095 u8 cnp_prio_mode[0x1]; 2096 u8 cnp_802p_prio[0x3]; 2097 2098 u8 reserved_at_e0[0x720]; 2099 }; 2100 2101 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2102 u8 reserved_at_0[0x60]; 2103 2104 u8 reserved_at_60[0x4]; 2105 u8 clamp_tgt_rate[0x1]; 2106 u8 reserved_at_65[0x3]; 2107 u8 clamp_tgt_rate_after_time_inc[0x1]; 2108 u8 reserved_at_69[0x17]; 2109 2110 u8 reserved_at_80[0x20]; 2111 2112 u8 rpg_time_reset[0x20]; 2113 2114 u8 rpg_byte_reset[0x20]; 2115 2116 u8 rpg_threshold[0x20]; 2117 2118 u8 rpg_max_rate[0x20]; 2119 2120 u8 rpg_ai_rate[0x20]; 2121 2122 u8 rpg_hai_rate[0x20]; 2123 2124 u8 rpg_gd[0x20]; 2125 2126 u8 rpg_min_dec_fac[0x20]; 2127 2128 u8 rpg_min_rate[0x20]; 2129 2130 u8 reserved_at_1c0[0xe0]; 2131 2132 u8 rate_to_set_on_first_cnp[0x20]; 2133 2134 u8 dce_tcp_g[0x20]; 2135 2136 u8 dce_tcp_rtt[0x20]; 2137 2138 u8 rate_reduce_monitor_period[0x20]; 2139 2140 u8 reserved_at_320[0x20]; 2141 2142 u8 initial_alpha_value[0x20]; 2143 2144 u8 reserved_at_360[0x4a0]; 2145 }; 2146 2147 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2148 u8 reserved_at_0[0x80]; 2149 2150 u8 rppp_max_rps[0x20]; 2151 2152 u8 rpg_time_reset[0x20]; 2153 2154 u8 rpg_byte_reset[0x20]; 2155 2156 u8 rpg_threshold[0x20]; 2157 2158 u8 rpg_max_rate[0x20]; 2159 2160 u8 rpg_ai_rate[0x20]; 2161 2162 u8 rpg_hai_rate[0x20]; 2163 2164 u8 rpg_gd[0x20]; 2165 2166 u8 rpg_min_dec_fac[0x20]; 2167 2168 u8 rpg_min_rate[0x20]; 2169 2170 u8 reserved_at_1c0[0x640]; 2171 }; 2172 2173 enum { 2174 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2175 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2176 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2177 }; 2178 2179 struct mlx5_ifc_resize_field_select_bits { 2180 u8 resize_field_select[0x20]; 2181 }; 2182 2183 struct mlx5_ifc_resource_dump_bits { 2184 u8 more_dump[0x1]; 2185 u8 inline_dump[0x1]; 2186 u8 reserved_at_2[0xa]; 2187 u8 seq_num[0x4]; 2188 u8 segment_type[0x10]; 2189 2190 u8 reserved_at_20[0x10]; 2191 u8 vhca_id[0x10]; 2192 2193 u8 index1[0x20]; 2194 2195 u8 index2[0x20]; 2196 2197 u8 num_of_obj1[0x10]; 2198 u8 num_of_obj2[0x10]; 2199 2200 u8 reserved_at_a0[0x20]; 2201 2202 u8 device_opaque[0x40]; 2203 2204 u8 mkey[0x20]; 2205 2206 u8 size[0x20]; 2207 2208 u8 address[0x40]; 2209 2210 u8 inline_data[52][0x20]; 2211 }; 2212 2213 struct mlx5_ifc_resource_dump_menu_record_bits { 2214 u8 reserved_at_0[0x4]; 2215 u8 num_of_obj2_supports_active[0x1]; 2216 u8 num_of_obj2_supports_all[0x1]; 2217 u8 must_have_num_of_obj2[0x1]; 2218 u8 support_num_of_obj2[0x1]; 2219 u8 num_of_obj1_supports_active[0x1]; 2220 u8 num_of_obj1_supports_all[0x1]; 2221 u8 must_have_num_of_obj1[0x1]; 2222 u8 support_num_of_obj1[0x1]; 2223 u8 must_have_index2[0x1]; 2224 u8 support_index2[0x1]; 2225 u8 must_have_index1[0x1]; 2226 u8 support_index1[0x1]; 2227 u8 segment_type[0x10]; 2228 2229 u8 segment_name[4][0x20]; 2230 2231 u8 index1_name[4][0x20]; 2232 2233 u8 index2_name[4][0x20]; 2234 }; 2235 2236 struct mlx5_ifc_resource_dump_segment_header_bits { 2237 u8 length_dw[0x10]; 2238 u8 segment_type[0x10]; 2239 }; 2240 2241 struct mlx5_ifc_resource_dump_command_segment_bits { 2242 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2243 2244 u8 segment_called[0x10]; 2245 u8 vhca_id[0x10]; 2246 2247 u8 index1[0x20]; 2248 2249 u8 index2[0x20]; 2250 2251 u8 num_of_obj1[0x10]; 2252 u8 num_of_obj2[0x10]; 2253 }; 2254 2255 struct mlx5_ifc_resource_dump_error_segment_bits { 2256 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2257 2258 u8 reserved_at_20[0x10]; 2259 u8 syndrome_id[0x10]; 2260 2261 u8 reserved_at_40[0x40]; 2262 2263 u8 error[8][0x20]; 2264 }; 2265 2266 struct mlx5_ifc_resource_dump_info_segment_bits { 2267 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2268 2269 u8 reserved_at_20[0x18]; 2270 u8 dump_version[0x8]; 2271 2272 u8 hw_version[0x20]; 2273 2274 u8 fw_version[0x20]; 2275 }; 2276 2277 struct mlx5_ifc_resource_dump_menu_segment_bits { 2278 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2279 2280 u8 reserved_at_20[0x10]; 2281 u8 num_of_records[0x10]; 2282 2283 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2284 }; 2285 2286 struct mlx5_ifc_resource_dump_resource_segment_bits { 2287 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2288 2289 u8 reserved_at_20[0x20]; 2290 2291 u8 index1[0x20]; 2292 2293 u8 index2[0x20]; 2294 2295 u8 payload[][0x20]; 2296 }; 2297 2298 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2299 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2300 }; 2301 2302 struct mlx5_ifc_menu_resource_dump_response_bits { 2303 struct mlx5_ifc_resource_dump_info_segment_bits info; 2304 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2305 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2306 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2307 }; 2308 2309 enum { 2310 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2311 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2312 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2313 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2314 }; 2315 2316 struct mlx5_ifc_modify_field_select_bits { 2317 u8 modify_field_select[0x20]; 2318 }; 2319 2320 struct mlx5_ifc_field_select_r_roce_np_bits { 2321 u8 field_select_r_roce_np[0x20]; 2322 }; 2323 2324 struct mlx5_ifc_field_select_r_roce_rp_bits { 2325 u8 field_select_r_roce_rp[0x20]; 2326 }; 2327 2328 enum { 2329 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2330 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2331 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2332 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2333 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2334 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2335 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2336 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2337 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2338 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2339 }; 2340 2341 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2342 u8 field_select_8021qaurp[0x20]; 2343 }; 2344 2345 struct mlx5_ifc_phys_layer_cntrs_bits { 2346 u8 time_since_last_clear_high[0x20]; 2347 2348 u8 time_since_last_clear_low[0x20]; 2349 2350 u8 symbol_errors_high[0x20]; 2351 2352 u8 symbol_errors_low[0x20]; 2353 2354 u8 sync_headers_errors_high[0x20]; 2355 2356 u8 sync_headers_errors_low[0x20]; 2357 2358 u8 edpl_bip_errors_lane0_high[0x20]; 2359 2360 u8 edpl_bip_errors_lane0_low[0x20]; 2361 2362 u8 edpl_bip_errors_lane1_high[0x20]; 2363 2364 u8 edpl_bip_errors_lane1_low[0x20]; 2365 2366 u8 edpl_bip_errors_lane2_high[0x20]; 2367 2368 u8 edpl_bip_errors_lane2_low[0x20]; 2369 2370 u8 edpl_bip_errors_lane3_high[0x20]; 2371 2372 u8 edpl_bip_errors_lane3_low[0x20]; 2373 2374 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2375 2376 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2377 2378 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2379 2380 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2381 2382 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2383 2384 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2385 2386 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2387 2388 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2389 2390 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2391 2392 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2393 2394 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2395 2396 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2397 2398 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2399 2400 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2401 2402 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2403 2404 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2405 2406 u8 rs_fec_corrected_blocks_high[0x20]; 2407 2408 u8 rs_fec_corrected_blocks_low[0x20]; 2409 2410 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2411 2412 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2413 2414 u8 rs_fec_no_errors_blocks_high[0x20]; 2415 2416 u8 rs_fec_no_errors_blocks_low[0x20]; 2417 2418 u8 rs_fec_single_error_blocks_high[0x20]; 2419 2420 u8 rs_fec_single_error_blocks_low[0x20]; 2421 2422 u8 rs_fec_corrected_symbols_total_high[0x20]; 2423 2424 u8 rs_fec_corrected_symbols_total_low[0x20]; 2425 2426 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2427 2428 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2429 2430 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2431 2432 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2433 2434 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2435 2436 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2437 2438 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2439 2440 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2441 2442 u8 link_down_events[0x20]; 2443 2444 u8 successful_recovery_events[0x20]; 2445 2446 u8 reserved_at_640[0x180]; 2447 }; 2448 2449 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2450 u8 time_since_last_clear_high[0x20]; 2451 2452 u8 time_since_last_clear_low[0x20]; 2453 2454 u8 phy_received_bits_high[0x20]; 2455 2456 u8 phy_received_bits_low[0x20]; 2457 2458 u8 phy_symbol_errors_high[0x20]; 2459 2460 u8 phy_symbol_errors_low[0x20]; 2461 2462 u8 phy_corrected_bits_high[0x20]; 2463 2464 u8 phy_corrected_bits_low[0x20]; 2465 2466 u8 phy_corrected_bits_lane0_high[0x20]; 2467 2468 u8 phy_corrected_bits_lane0_low[0x20]; 2469 2470 u8 phy_corrected_bits_lane1_high[0x20]; 2471 2472 u8 phy_corrected_bits_lane1_low[0x20]; 2473 2474 u8 phy_corrected_bits_lane2_high[0x20]; 2475 2476 u8 phy_corrected_bits_lane2_low[0x20]; 2477 2478 u8 phy_corrected_bits_lane3_high[0x20]; 2479 2480 u8 phy_corrected_bits_lane3_low[0x20]; 2481 2482 u8 reserved_at_200[0x5c0]; 2483 }; 2484 2485 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2486 u8 symbol_error_counter[0x10]; 2487 2488 u8 link_error_recovery_counter[0x8]; 2489 2490 u8 link_downed_counter[0x8]; 2491 2492 u8 port_rcv_errors[0x10]; 2493 2494 u8 port_rcv_remote_physical_errors[0x10]; 2495 2496 u8 port_rcv_switch_relay_errors[0x10]; 2497 2498 u8 port_xmit_discards[0x10]; 2499 2500 u8 port_xmit_constraint_errors[0x8]; 2501 2502 u8 port_rcv_constraint_errors[0x8]; 2503 2504 u8 reserved_at_70[0x8]; 2505 2506 u8 link_overrun_errors[0x8]; 2507 2508 u8 reserved_at_80[0x10]; 2509 2510 u8 vl_15_dropped[0x10]; 2511 2512 u8 reserved_at_a0[0x80]; 2513 2514 u8 port_xmit_wait[0x20]; 2515 }; 2516 2517 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2518 u8 transmit_queue_high[0x20]; 2519 2520 u8 transmit_queue_low[0x20]; 2521 2522 u8 no_buffer_discard_uc_high[0x20]; 2523 2524 u8 no_buffer_discard_uc_low[0x20]; 2525 2526 u8 reserved_at_80[0x740]; 2527 }; 2528 2529 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2530 u8 wred_discard_high[0x20]; 2531 2532 u8 wred_discard_low[0x20]; 2533 2534 u8 ecn_marked_tc_high[0x20]; 2535 2536 u8 ecn_marked_tc_low[0x20]; 2537 2538 u8 reserved_at_80[0x740]; 2539 }; 2540 2541 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2542 u8 rx_octets_high[0x20]; 2543 2544 u8 rx_octets_low[0x20]; 2545 2546 u8 reserved_at_40[0xc0]; 2547 2548 u8 rx_frames_high[0x20]; 2549 2550 u8 rx_frames_low[0x20]; 2551 2552 u8 tx_octets_high[0x20]; 2553 2554 u8 tx_octets_low[0x20]; 2555 2556 u8 reserved_at_180[0xc0]; 2557 2558 u8 tx_frames_high[0x20]; 2559 2560 u8 tx_frames_low[0x20]; 2561 2562 u8 rx_pause_high[0x20]; 2563 2564 u8 rx_pause_low[0x20]; 2565 2566 u8 rx_pause_duration_high[0x20]; 2567 2568 u8 rx_pause_duration_low[0x20]; 2569 2570 u8 tx_pause_high[0x20]; 2571 2572 u8 tx_pause_low[0x20]; 2573 2574 u8 tx_pause_duration_high[0x20]; 2575 2576 u8 tx_pause_duration_low[0x20]; 2577 2578 u8 rx_pause_transition_high[0x20]; 2579 2580 u8 rx_pause_transition_low[0x20]; 2581 2582 u8 rx_discards_high[0x20]; 2583 2584 u8 rx_discards_low[0x20]; 2585 2586 u8 device_stall_minor_watermark_cnt_high[0x20]; 2587 2588 u8 device_stall_minor_watermark_cnt_low[0x20]; 2589 2590 u8 device_stall_critical_watermark_cnt_high[0x20]; 2591 2592 u8 device_stall_critical_watermark_cnt_low[0x20]; 2593 2594 u8 reserved_at_480[0x340]; 2595 }; 2596 2597 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2598 u8 port_transmit_wait_high[0x20]; 2599 2600 u8 port_transmit_wait_low[0x20]; 2601 2602 u8 reserved_at_40[0x100]; 2603 2604 u8 rx_buffer_almost_full_high[0x20]; 2605 2606 u8 rx_buffer_almost_full_low[0x20]; 2607 2608 u8 rx_buffer_full_high[0x20]; 2609 2610 u8 rx_buffer_full_low[0x20]; 2611 2612 u8 rx_icrc_encapsulated_high[0x20]; 2613 2614 u8 rx_icrc_encapsulated_low[0x20]; 2615 2616 u8 reserved_at_200[0x5c0]; 2617 }; 2618 2619 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2620 u8 dot3stats_alignment_errors_high[0x20]; 2621 2622 u8 dot3stats_alignment_errors_low[0x20]; 2623 2624 u8 dot3stats_fcs_errors_high[0x20]; 2625 2626 u8 dot3stats_fcs_errors_low[0x20]; 2627 2628 u8 dot3stats_single_collision_frames_high[0x20]; 2629 2630 u8 dot3stats_single_collision_frames_low[0x20]; 2631 2632 u8 dot3stats_multiple_collision_frames_high[0x20]; 2633 2634 u8 dot3stats_multiple_collision_frames_low[0x20]; 2635 2636 u8 dot3stats_sqe_test_errors_high[0x20]; 2637 2638 u8 dot3stats_sqe_test_errors_low[0x20]; 2639 2640 u8 dot3stats_deferred_transmissions_high[0x20]; 2641 2642 u8 dot3stats_deferred_transmissions_low[0x20]; 2643 2644 u8 dot3stats_late_collisions_high[0x20]; 2645 2646 u8 dot3stats_late_collisions_low[0x20]; 2647 2648 u8 dot3stats_excessive_collisions_high[0x20]; 2649 2650 u8 dot3stats_excessive_collisions_low[0x20]; 2651 2652 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2653 2654 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2655 2656 u8 dot3stats_carrier_sense_errors_high[0x20]; 2657 2658 u8 dot3stats_carrier_sense_errors_low[0x20]; 2659 2660 u8 dot3stats_frame_too_longs_high[0x20]; 2661 2662 u8 dot3stats_frame_too_longs_low[0x20]; 2663 2664 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2665 2666 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2667 2668 u8 dot3stats_symbol_errors_high[0x20]; 2669 2670 u8 dot3stats_symbol_errors_low[0x20]; 2671 2672 u8 dot3control_in_unknown_opcodes_high[0x20]; 2673 2674 u8 dot3control_in_unknown_opcodes_low[0x20]; 2675 2676 u8 dot3in_pause_frames_high[0x20]; 2677 2678 u8 dot3in_pause_frames_low[0x20]; 2679 2680 u8 dot3out_pause_frames_high[0x20]; 2681 2682 u8 dot3out_pause_frames_low[0x20]; 2683 2684 u8 reserved_at_400[0x3c0]; 2685 }; 2686 2687 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2688 u8 ether_stats_drop_events_high[0x20]; 2689 2690 u8 ether_stats_drop_events_low[0x20]; 2691 2692 u8 ether_stats_octets_high[0x20]; 2693 2694 u8 ether_stats_octets_low[0x20]; 2695 2696 u8 ether_stats_pkts_high[0x20]; 2697 2698 u8 ether_stats_pkts_low[0x20]; 2699 2700 u8 ether_stats_broadcast_pkts_high[0x20]; 2701 2702 u8 ether_stats_broadcast_pkts_low[0x20]; 2703 2704 u8 ether_stats_multicast_pkts_high[0x20]; 2705 2706 u8 ether_stats_multicast_pkts_low[0x20]; 2707 2708 u8 ether_stats_crc_align_errors_high[0x20]; 2709 2710 u8 ether_stats_crc_align_errors_low[0x20]; 2711 2712 u8 ether_stats_undersize_pkts_high[0x20]; 2713 2714 u8 ether_stats_undersize_pkts_low[0x20]; 2715 2716 u8 ether_stats_oversize_pkts_high[0x20]; 2717 2718 u8 ether_stats_oversize_pkts_low[0x20]; 2719 2720 u8 ether_stats_fragments_high[0x20]; 2721 2722 u8 ether_stats_fragments_low[0x20]; 2723 2724 u8 ether_stats_jabbers_high[0x20]; 2725 2726 u8 ether_stats_jabbers_low[0x20]; 2727 2728 u8 ether_stats_collisions_high[0x20]; 2729 2730 u8 ether_stats_collisions_low[0x20]; 2731 2732 u8 ether_stats_pkts64octets_high[0x20]; 2733 2734 u8 ether_stats_pkts64octets_low[0x20]; 2735 2736 u8 ether_stats_pkts65to127octets_high[0x20]; 2737 2738 u8 ether_stats_pkts65to127octets_low[0x20]; 2739 2740 u8 ether_stats_pkts128to255octets_high[0x20]; 2741 2742 u8 ether_stats_pkts128to255octets_low[0x20]; 2743 2744 u8 ether_stats_pkts256to511octets_high[0x20]; 2745 2746 u8 ether_stats_pkts256to511octets_low[0x20]; 2747 2748 u8 ether_stats_pkts512to1023octets_high[0x20]; 2749 2750 u8 ether_stats_pkts512to1023octets_low[0x20]; 2751 2752 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2753 2754 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2755 2756 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2757 2758 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2759 2760 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2761 2762 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2763 2764 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2765 2766 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2767 2768 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2769 2770 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2771 2772 u8 reserved_at_540[0x280]; 2773 }; 2774 2775 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2776 u8 if_in_octets_high[0x20]; 2777 2778 u8 if_in_octets_low[0x20]; 2779 2780 u8 if_in_ucast_pkts_high[0x20]; 2781 2782 u8 if_in_ucast_pkts_low[0x20]; 2783 2784 u8 if_in_discards_high[0x20]; 2785 2786 u8 if_in_discards_low[0x20]; 2787 2788 u8 if_in_errors_high[0x20]; 2789 2790 u8 if_in_errors_low[0x20]; 2791 2792 u8 if_in_unknown_protos_high[0x20]; 2793 2794 u8 if_in_unknown_protos_low[0x20]; 2795 2796 u8 if_out_octets_high[0x20]; 2797 2798 u8 if_out_octets_low[0x20]; 2799 2800 u8 if_out_ucast_pkts_high[0x20]; 2801 2802 u8 if_out_ucast_pkts_low[0x20]; 2803 2804 u8 if_out_discards_high[0x20]; 2805 2806 u8 if_out_discards_low[0x20]; 2807 2808 u8 if_out_errors_high[0x20]; 2809 2810 u8 if_out_errors_low[0x20]; 2811 2812 u8 if_in_multicast_pkts_high[0x20]; 2813 2814 u8 if_in_multicast_pkts_low[0x20]; 2815 2816 u8 if_in_broadcast_pkts_high[0x20]; 2817 2818 u8 if_in_broadcast_pkts_low[0x20]; 2819 2820 u8 if_out_multicast_pkts_high[0x20]; 2821 2822 u8 if_out_multicast_pkts_low[0x20]; 2823 2824 u8 if_out_broadcast_pkts_high[0x20]; 2825 2826 u8 if_out_broadcast_pkts_low[0x20]; 2827 2828 u8 reserved_at_340[0x480]; 2829 }; 2830 2831 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2832 u8 a_frames_transmitted_ok_high[0x20]; 2833 2834 u8 a_frames_transmitted_ok_low[0x20]; 2835 2836 u8 a_frames_received_ok_high[0x20]; 2837 2838 u8 a_frames_received_ok_low[0x20]; 2839 2840 u8 a_frame_check_sequence_errors_high[0x20]; 2841 2842 u8 a_frame_check_sequence_errors_low[0x20]; 2843 2844 u8 a_alignment_errors_high[0x20]; 2845 2846 u8 a_alignment_errors_low[0x20]; 2847 2848 u8 a_octets_transmitted_ok_high[0x20]; 2849 2850 u8 a_octets_transmitted_ok_low[0x20]; 2851 2852 u8 a_octets_received_ok_high[0x20]; 2853 2854 u8 a_octets_received_ok_low[0x20]; 2855 2856 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2857 2858 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2859 2860 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2861 2862 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2863 2864 u8 a_multicast_frames_received_ok_high[0x20]; 2865 2866 u8 a_multicast_frames_received_ok_low[0x20]; 2867 2868 u8 a_broadcast_frames_received_ok_high[0x20]; 2869 2870 u8 a_broadcast_frames_received_ok_low[0x20]; 2871 2872 u8 a_in_range_length_errors_high[0x20]; 2873 2874 u8 a_in_range_length_errors_low[0x20]; 2875 2876 u8 a_out_of_range_length_field_high[0x20]; 2877 2878 u8 a_out_of_range_length_field_low[0x20]; 2879 2880 u8 a_frame_too_long_errors_high[0x20]; 2881 2882 u8 a_frame_too_long_errors_low[0x20]; 2883 2884 u8 a_symbol_error_during_carrier_high[0x20]; 2885 2886 u8 a_symbol_error_during_carrier_low[0x20]; 2887 2888 u8 a_mac_control_frames_transmitted_high[0x20]; 2889 2890 u8 a_mac_control_frames_transmitted_low[0x20]; 2891 2892 u8 a_mac_control_frames_received_high[0x20]; 2893 2894 u8 a_mac_control_frames_received_low[0x20]; 2895 2896 u8 a_unsupported_opcodes_received_high[0x20]; 2897 2898 u8 a_unsupported_opcodes_received_low[0x20]; 2899 2900 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2901 2902 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2903 2904 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2905 2906 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2907 2908 u8 reserved_at_4c0[0x300]; 2909 }; 2910 2911 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2912 u8 life_time_counter_high[0x20]; 2913 2914 u8 life_time_counter_low[0x20]; 2915 2916 u8 rx_errors[0x20]; 2917 2918 u8 tx_errors[0x20]; 2919 2920 u8 l0_to_recovery_eieos[0x20]; 2921 2922 u8 l0_to_recovery_ts[0x20]; 2923 2924 u8 l0_to_recovery_framing[0x20]; 2925 2926 u8 l0_to_recovery_retrain[0x20]; 2927 2928 u8 crc_error_dllp[0x20]; 2929 2930 u8 crc_error_tlp[0x20]; 2931 2932 u8 tx_overflow_buffer_pkt_high[0x20]; 2933 2934 u8 tx_overflow_buffer_pkt_low[0x20]; 2935 2936 u8 outbound_stalled_reads[0x20]; 2937 2938 u8 outbound_stalled_writes[0x20]; 2939 2940 u8 outbound_stalled_reads_events[0x20]; 2941 2942 u8 outbound_stalled_writes_events[0x20]; 2943 2944 u8 reserved_at_200[0x5c0]; 2945 }; 2946 2947 struct mlx5_ifc_cmd_inter_comp_event_bits { 2948 u8 command_completion_vector[0x20]; 2949 2950 u8 reserved_at_20[0xc0]; 2951 }; 2952 2953 struct mlx5_ifc_stall_vl_event_bits { 2954 u8 reserved_at_0[0x18]; 2955 u8 port_num[0x1]; 2956 u8 reserved_at_19[0x3]; 2957 u8 vl[0x4]; 2958 2959 u8 reserved_at_20[0xa0]; 2960 }; 2961 2962 struct mlx5_ifc_db_bf_congestion_event_bits { 2963 u8 event_subtype[0x8]; 2964 u8 reserved_at_8[0x8]; 2965 u8 congestion_level[0x8]; 2966 u8 reserved_at_18[0x8]; 2967 2968 u8 reserved_at_20[0xa0]; 2969 }; 2970 2971 struct mlx5_ifc_gpio_event_bits { 2972 u8 reserved_at_0[0x60]; 2973 2974 u8 gpio_event_hi[0x20]; 2975 2976 u8 gpio_event_lo[0x20]; 2977 2978 u8 reserved_at_a0[0x40]; 2979 }; 2980 2981 struct mlx5_ifc_port_state_change_event_bits { 2982 u8 reserved_at_0[0x40]; 2983 2984 u8 port_num[0x4]; 2985 u8 reserved_at_44[0x1c]; 2986 2987 u8 reserved_at_60[0x80]; 2988 }; 2989 2990 struct mlx5_ifc_dropped_packet_logged_bits { 2991 u8 reserved_at_0[0xe0]; 2992 }; 2993 2994 struct mlx5_ifc_default_timeout_bits { 2995 u8 to_multiplier[0x3]; 2996 u8 reserved_at_3[0x9]; 2997 u8 to_value[0x14]; 2998 }; 2999 3000 struct mlx5_ifc_dtor_reg_bits { 3001 u8 reserved_at_0[0x20]; 3002 3003 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3004 3005 u8 reserved_at_40[0x60]; 3006 3007 struct mlx5_ifc_default_timeout_bits health_poll_to; 3008 3009 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3010 3011 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3012 3013 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3014 3015 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3016 3017 struct mlx5_ifc_default_timeout_bits tear_down_to; 3018 3019 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3020 3021 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3022 3023 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3024 3025 u8 reserved_at_1c0[0x40]; 3026 }; 3027 3028 enum { 3029 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3030 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3031 }; 3032 3033 struct mlx5_ifc_cq_error_bits { 3034 u8 reserved_at_0[0x8]; 3035 u8 cqn[0x18]; 3036 3037 u8 reserved_at_20[0x20]; 3038 3039 u8 reserved_at_40[0x18]; 3040 u8 syndrome[0x8]; 3041 3042 u8 reserved_at_60[0x80]; 3043 }; 3044 3045 struct mlx5_ifc_rdma_page_fault_event_bits { 3046 u8 bytes_committed[0x20]; 3047 3048 u8 r_key[0x20]; 3049 3050 u8 reserved_at_40[0x10]; 3051 u8 packet_len[0x10]; 3052 3053 u8 rdma_op_len[0x20]; 3054 3055 u8 rdma_va[0x40]; 3056 3057 u8 reserved_at_c0[0x5]; 3058 u8 rdma[0x1]; 3059 u8 write[0x1]; 3060 u8 requestor[0x1]; 3061 u8 qp_number[0x18]; 3062 }; 3063 3064 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3065 u8 bytes_committed[0x20]; 3066 3067 u8 reserved_at_20[0x10]; 3068 u8 wqe_index[0x10]; 3069 3070 u8 reserved_at_40[0x10]; 3071 u8 len[0x10]; 3072 3073 u8 reserved_at_60[0x60]; 3074 3075 u8 reserved_at_c0[0x5]; 3076 u8 rdma[0x1]; 3077 u8 write_read[0x1]; 3078 u8 requestor[0x1]; 3079 u8 qpn[0x18]; 3080 }; 3081 3082 struct mlx5_ifc_qp_events_bits { 3083 u8 reserved_at_0[0xa0]; 3084 3085 u8 type[0x8]; 3086 u8 reserved_at_a8[0x18]; 3087 3088 u8 reserved_at_c0[0x8]; 3089 u8 qpn_rqn_sqn[0x18]; 3090 }; 3091 3092 struct mlx5_ifc_dct_events_bits { 3093 u8 reserved_at_0[0xc0]; 3094 3095 u8 reserved_at_c0[0x8]; 3096 u8 dct_number[0x18]; 3097 }; 3098 3099 struct mlx5_ifc_comp_event_bits { 3100 u8 reserved_at_0[0xc0]; 3101 3102 u8 reserved_at_c0[0x8]; 3103 u8 cq_number[0x18]; 3104 }; 3105 3106 enum { 3107 MLX5_QPC_STATE_RST = 0x0, 3108 MLX5_QPC_STATE_INIT = 0x1, 3109 MLX5_QPC_STATE_RTR = 0x2, 3110 MLX5_QPC_STATE_RTS = 0x3, 3111 MLX5_QPC_STATE_SQER = 0x4, 3112 MLX5_QPC_STATE_ERR = 0x6, 3113 MLX5_QPC_STATE_SQD = 0x7, 3114 MLX5_QPC_STATE_SUSPENDED = 0x9, 3115 }; 3116 3117 enum { 3118 MLX5_QPC_ST_RC = 0x0, 3119 MLX5_QPC_ST_UC = 0x1, 3120 MLX5_QPC_ST_UD = 0x2, 3121 MLX5_QPC_ST_XRC = 0x3, 3122 MLX5_QPC_ST_DCI = 0x5, 3123 MLX5_QPC_ST_QP0 = 0x7, 3124 MLX5_QPC_ST_QP1 = 0x8, 3125 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3126 MLX5_QPC_ST_REG_UMR = 0xc, 3127 }; 3128 3129 enum { 3130 MLX5_QPC_PM_STATE_ARMED = 0x0, 3131 MLX5_QPC_PM_STATE_REARM = 0x1, 3132 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3133 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3134 }; 3135 3136 enum { 3137 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3138 }; 3139 3140 enum { 3141 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3142 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3143 }; 3144 3145 enum { 3146 MLX5_QPC_MTU_256_BYTES = 0x1, 3147 MLX5_QPC_MTU_512_BYTES = 0x2, 3148 MLX5_QPC_MTU_1K_BYTES = 0x3, 3149 MLX5_QPC_MTU_2K_BYTES = 0x4, 3150 MLX5_QPC_MTU_4K_BYTES = 0x5, 3151 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3152 }; 3153 3154 enum { 3155 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3156 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3157 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3158 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3159 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3160 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3161 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3162 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3163 }; 3164 3165 enum { 3166 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3167 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3168 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3169 }; 3170 3171 enum { 3172 MLX5_QPC_CS_RES_DISABLE = 0x0, 3173 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3174 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3175 }; 3176 3177 enum { 3178 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3179 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3180 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3181 }; 3182 3183 struct mlx5_ifc_qpc_bits { 3184 u8 state[0x4]; 3185 u8 lag_tx_port_affinity[0x4]; 3186 u8 st[0x8]; 3187 u8 reserved_at_10[0x2]; 3188 u8 isolate_vl_tc[0x1]; 3189 u8 pm_state[0x2]; 3190 u8 reserved_at_15[0x1]; 3191 u8 req_e2e_credit_mode[0x2]; 3192 u8 offload_type[0x4]; 3193 u8 end_padding_mode[0x2]; 3194 u8 reserved_at_1e[0x2]; 3195 3196 u8 wq_signature[0x1]; 3197 u8 block_lb_mc[0x1]; 3198 u8 atomic_like_write_en[0x1]; 3199 u8 latency_sensitive[0x1]; 3200 u8 reserved_at_24[0x1]; 3201 u8 drain_sigerr[0x1]; 3202 u8 reserved_at_26[0x2]; 3203 u8 pd[0x18]; 3204 3205 u8 mtu[0x3]; 3206 u8 log_msg_max[0x5]; 3207 u8 reserved_at_48[0x1]; 3208 u8 log_rq_size[0x4]; 3209 u8 log_rq_stride[0x3]; 3210 u8 no_sq[0x1]; 3211 u8 log_sq_size[0x4]; 3212 u8 reserved_at_55[0x3]; 3213 u8 ts_format[0x2]; 3214 u8 reserved_at_5a[0x1]; 3215 u8 rlky[0x1]; 3216 u8 ulp_stateless_offload_mode[0x4]; 3217 3218 u8 counter_set_id[0x8]; 3219 u8 uar_page[0x18]; 3220 3221 u8 reserved_at_80[0x8]; 3222 u8 user_index[0x18]; 3223 3224 u8 reserved_at_a0[0x3]; 3225 u8 log_page_size[0x5]; 3226 u8 remote_qpn[0x18]; 3227 3228 struct mlx5_ifc_ads_bits primary_address_path; 3229 3230 struct mlx5_ifc_ads_bits secondary_address_path; 3231 3232 u8 log_ack_req_freq[0x4]; 3233 u8 reserved_at_384[0x4]; 3234 u8 log_sra_max[0x3]; 3235 u8 reserved_at_38b[0x2]; 3236 u8 retry_count[0x3]; 3237 u8 rnr_retry[0x3]; 3238 u8 reserved_at_393[0x1]; 3239 u8 fre[0x1]; 3240 u8 cur_rnr_retry[0x3]; 3241 u8 cur_retry_count[0x3]; 3242 u8 reserved_at_39b[0x5]; 3243 3244 u8 reserved_at_3a0[0x20]; 3245 3246 u8 reserved_at_3c0[0x8]; 3247 u8 next_send_psn[0x18]; 3248 3249 u8 reserved_at_3e0[0x3]; 3250 u8 log_num_dci_stream_channels[0x5]; 3251 u8 cqn_snd[0x18]; 3252 3253 u8 reserved_at_400[0x3]; 3254 u8 log_num_dci_errored_streams[0x5]; 3255 u8 deth_sqpn[0x18]; 3256 3257 u8 reserved_at_420[0x20]; 3258 3259 u8 reserved_at_440[0x8]; 3260 u8 last_acked_psn[0x18]; 3261 3262 u8 reserved_at_460[0x8]; 3263 u8 ssn[0x18]; 3264 3265 u8 reserved_at_480[0x8]; 3266 u8 log_rra_max[0x3]; 3267 u8 reserved_at_48b[0x1]; 3268 u8 atomic_mode[0x4]; 3269 u8 rre[0x1]; 3270 u8 rwe[0x1]; 3271 u8 rae[0x1]; 3272 u8 reserved_at_493[0x1]; 3273 u8 page_offset[0x6]; 3274 u8 reserved_at_49a[0x3]; 3275 u8 cd_slave_receive[0x1]; 3276 u8 cd_slave_send[0x1]; 3277 u8 cd_master[0x1]; 3278 3279 u8 reserved_at_4a0[0x3]; 3280 u8 min_rnr_nak[0x5]; 3281 u8 next_rcv_psn[0x18]; 3282 3283 u8 reserved_at_4c0[0x8]; 3284 u8 xrcd[0x18]; 3285 3286 u8 reserved_at_4e0[0x8]; 3287 u8 cqn_rcv[0x18]; 3288 3289 u8 dbr_addr[0x40]; 3290 3291 u8 q_key[0x20]; 3292 3293 u8 reserved_at_560[0x5]; 3294 u8 rq_type[0x3]; 3295 u8 srqn_rmpn_xrqn[0x18]; 3296 3297 u8 reserved_at_580[0x8]; 3298 u8 rmsn[0x18]; 3299 3300 u8 hw_sq_wqebb_counter[0x10]; 3301 u8 sw_sq_wqebb_counter[0x10]; 3302 3303 u8 hw_rq_counter[0x20]; 3304 3305 u8 sw_rq_counter[0x20]; 3306 3307 u8 reserved_at_600[0x20]; 3308 3309 u8 reserved_at_620[0xf]; 3310 u8 cgs[0x1]; 3311 u8 cs_req[0x8]; 3312 u8 cs_res[0x8]; 3313 3314 u8 dc_access_key[0x40]; 3315 3316 u8 reserved_at_680[0x3]; 3317 u8 dbr_umem_valid[0x1]; 3318 3319 u8 reserved_at_684[0xbc]; 3320 }; 3321 3322 struct mlx5_ifc_roce_addr_layout_bits { 3323 u8 source_l3_address[16][0x8]; 3324 3325 u8 reserved_at_80[0x3]; 3326 u8 vlan_valid[0x1]; 3327 u8 vlan_id[0xc]; 3328 u8 source_mac_47_32[0x10]; 3329 3330 u8 source_mac_31_0[0x20]; 3331 3332 u8 reserved_at_c0[0x14]; 3333 u8 roce_l3_type[0x4]; 3334 u8 roce_version[0x8]; 3335 3336 u8 reserved_at_e0[0x20]; 3337 }; 3338 3339 struct mlx5_ifc_shampo_cap_bits { 3340 u8 reserved_at_0[0x3]; 3341 u8 shampo_log_max_reservation_size[0x5]; 3342 u8 reserved_at_8[0x3]; 3343 u8 shampo_log_min_reservation_size[0x5]; 3344 u8 shampo_min_mss_size[0x10]; 3345 3346 u8 reserved_at_20[0x3]; 3347 u8 shampo_max_log_headers_entry_size[0x5]; 3348 u8 reserved_at_28[0x18]; 3349 3350 u8 reserved_at_40[0x7c0]; 3351 }; 3352 3353 union mlx5_ifc_hca_cap_union_bits { 3354 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3355 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3356 struct mlx5_ifc_odp_cap_bits odp_cap; 3357 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3358 struct mlx5_ifc_roce_cap_bits roce_cap; 3359 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3360 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3361 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3362 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3363 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3364 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3365 struct mlx5_ifc_qos_cap_bits qos_cap; 3366 struct mlx5_ifc_debug_cap_bits debug_cap; 3367 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3368 struct mlx5_ifc_tls_cap_bits tls_cap; 3369 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3370 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3371 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3372 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3373 u8 reserved_at_0[0x8000]; 3374 }; 3375 3376 enum { 3377 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3378 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3379 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3380 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3381 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3382 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3383 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3384 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3385 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3386 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3387 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3388 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3389 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3390 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3391 }; 3392 3393 enum { 3394 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3395 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3396 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3397 }; 3398 3399 enum { 3400 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3401 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3402 }; 3403 3404 struct mlx5_ifc_vlan_bits { 3405 u8 ethtype[0x10]; 3406 u8 prio[0x3]; 3407 u8 cfi[0x1]; 3408 u8 vid[0xc]; 3409 }; 3410 3411 enum { 3412 MLX5_FLOW_METER_COLOR_RED = 0x0, 3413 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3414 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3415 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3416 }; 3417 3418 enum { 3419 MLX5_EXE_ASO_FLOW_METER = 0x2, 3420 }; 3421 3422 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3423 u8 return_reg_id[0x4]; 3424 u8 aso_type[0x4]; 3425 u8 reserved_at_8[0x14]; 3426 u8 action[0x1]; 3427 u8 init_color[0x2]; 3428 u8 meter_id[0x1]; 3429 }; 3430 3431 union mlx5_ifc_exe_aso_ctrl { 3432 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3433 }; 3434 3435 struct mlx5_ifc_execute_aso_bits { 3436 u8 valid[0x1]; 3437 u8 reserved_at_1[0x7]; 3438 u8 aso_object_id[0x18]; 3439 3440 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3441 }; 3442 3443 struct mlx5_ifc_flow_context_bits { 3444 struct mlx5_ifc_vlan_bits push_vlan; 3445 3446 u8 group_id[0x20]; 3447 3448 u8 reserved_at_40[0x8]; 3449 u8 flow_tag[0x18]; 3450 3451 u8 reserved_at_60[0x10]; 3452 u8 action[0x10]; 3453 3454 u8 extended_destination[0x1]; 3455 u8 reserved_at_81[0x1]; 3456 u8 flow_source[0x2]; 3457 u8 encrypt_decrypt_type[0x4]; 3458 u8 destination_list_size[0x18]; 3459 3460 u8 reserved_at_a0[0x8]; 3461 u8 flow_counter_list_size[0x18]; 3462 3463 u8 packet_reformat_id[0x20]; 3464 3465 u8 modify_header_id[0x20]; 3466 3467 struct mlx5_ifc_vlan_bits push_vlan_2; 3468 3469 u8 encrypt_decrypt_obj_id[0x20]; 3470 u8 reserved_at_140[0xc0]; 3471 3472 struct mlx5_ifc_fte_match_param_bits match_value; 3473 3474 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3475 3476 u8 reserved_at_1300[0x500]; 3477 3478 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3479 }; 3480 3481 enum { 3482 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3483 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3484 }; 3485 3486 struct mlx5_ifc_xrc_srqc_bits { 3487 u8 state[0x4]; 3488 u8 log_xrc_srq_size[0x4]; 3489 u8 reserved_at_8[0x18]; 3490 3491 u8 wq_signature[0x1]; 3492 u8 cont_srq[0x1]; 3493 u8 reserved_at_22[0x1]; 3494 u8 rlky[0x1]; 3495 u8 basic_cyclic_rcv_wqe[0x1]; 3496 u8 log_rq_stride[0x3]; 3497 u8 xrcd[0x18]; 3498 3499 u8 page_offset[0x6]; 3500 u8 reserved_at_46[0x1]; 3501 u8 dbr_umem_valid[0x1]; 3502 u8 cqn[0x18]; 3503 3504 u8 reserved_at_60[0x20]; 3505 3506 u8 user_index_equal_xrc_srqn[0x1]; 3507 u8 reserved_at_81[0x1]; 3508 u8 log_page_size[0x6]; 3509 u8 user_index[0x18]; 3510 3511 u8 reserved_at_a0[0x20]; 3512 3513 u8 reserved_at_c0[0x8]; 3514 u8 pd[0x18]; 3515 3516 u8 lwm[0x10]; 3517 u8 wqe_cnt[0x10]; 3518 3519 u8 reserved_at_100[0x40]; 3520 3521 u8 db_record_addr_h[0x20]; 3522 3523 u8 db_record_addr_l[0x1e]; 3524 u8 reserved_at_17e[0x2]; 3525 3526 u8 reserved_at_180[0x80]; 3527 }; 3528 3529 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3530 u8 counter_error_queues[0x20]; 3531 3532 u8 total_error_queues[0x20]; 3533 3534 u8 send_queue_priority_update_flow[0x20]; 3535 3536 u8 reserved_at_60[0x20]; 3537 3538 u8 nic_receive_steering_discard[0x40]; 3539 3540 u8 receive_discard_vport_down[0x40]; 3541 3542 u8 transmit_discard_vport_down[0x40]; 3543 3544 u8 async_eq_overrun[0x20]; 3545 3546 u8 comp_eq_overrun[0x20]; 3547 3548 u8 reserved_at_180[0x20]; 3549 3550 u8 invalid_command[0x20]; 3551 3552 u8 quota_exceeded_command[0x20]; 3553 3554 u8 internal_rq_out_of_buffer[0x20]; 3555 3556 u8 cq_overrun[0x20]; 3557 3558 u8 eth_wqe_too_small[0x20]; 3559 3560 u8 reserved_at_220[0xdc0]; 3561 }; 3562 3563 struct mlx5_ifc_traffic_counter_bits { 3564 u8 packets[0x40]; 3565 3566 u8 octets[0x40]; 3567 }; 3568 3569 struct mlx5_ifc_tisc_bits { 3570 u8 strict_lag_tx_port_affinity[0x1]; 3571 u8 tls_en[0x1]; 3572 u8 reserved_at_2[0x2]; 3573 u8 lag_tx_port_affinity[0x04]; 3574 3575 u8 reserved_at_8[0x4]; 3576 u8 prio[0x4]; 3577 u8 reserved_at_10[0x10]; 3578 3579 u8 reserved_at_20[0x100]; 3580 3581 u8 reserved_at_120[0x8]; 3582 u8 transport_domain[0x18]; 3583 3584 u8 reserved_at_140[0x8]; 3585 u8 underlay_qpn[0x18]; 3586 3587 u8 reserved_at_160[0x8]; 3588 u8 pd[0x18]; 3589 3590 u8 reserved_at_180[0x380]; 3591 }; 3592 3593 enum { 3594 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3595 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3596 }; 3597 3598 enum { 3599 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3600 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3601 }; 3602 3603 enum { 3604 MLX5_RX_HASH_FN_NONE = 0x0, 3605 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3606 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3607 }; 3608 3609 enum { 3610 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3611 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3612 }; 3613 3614 struct mlx5_ifc_tirc_bits { 3615 u8 reserved_at_0[0x20]; 3616 3617 u8 disp_type[0x4]; 3618 u8 tls_en[0x1]; 3619 u8 reserved_at_25[0x1b]; 3620 3621 u8 reserved_at_40[0x40]; 3622 3623 u8 reserved_at_80[0x4]; 3624 u8 lro_timeout_period_usecs[0x10]; 3625 u8 packet_merge_mask[0x4]; 3626 u8 lro_max_ip_payload_size[0x8]; 3627 3628 u8 reserved_at_a0[0x40]; 3629 3630 u8 reserved_at_e0[0x8]; 3631 u8 inline_rqn[0x18]; 3632 3633 u8 rx_hash_symmetric[0x1]; 3634 u8 reserved_at_101[0x1]; 3635 u8 tunneled_offload_en[0x1]; 3636 u8 reserved_at_103[0x5]; 3637 u8 indirect_table[0x18]; 3638 3639 u8 rx_hash_fn[0x4]; 3640 u8 reserved_at_124[0x2]; 3641 u8 self_lb_block[0x2]; 3642 u8 transport_domain[0x18]; 3643 3644 u8 rx_hash_toeplitz_key[10][0x20]; 3645 3646 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3647 3648 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3649 3650 u8 reserved_at_2c0[0x4c0]; 3651 }; 3652 3653 enum { 3654 MLX5_SRQC_STATE_GOOD = 0x0, 3655 MLX5_SRQC_STATE_ERROR = 0x1, 3656 }; 3657 3658 struct mlx5_ifc_srqc_bits { 3659 u8 state[0x4]; 3660 u8 log_srq_size[0x4]; 3661 u8 reserved_at_8[0x18]; 3662 3663 u8 wq_signature[0x1]; 3664 u8 cont_srq[0x1]; 3665 u8 reserved_at_22[0x1]; 3666 u8 rlky[0x1]; 3667 u8 reserved_at_24[0x1]; 3668 u8 log_rq_stride[0x3]; 3669 u8 xrcd[0x18]; 3670 3671 u8 page_offset[0x6]; 3672 u8 reserved_at_46[0x2]; 3673 u8 cqn[0x18]; 3674 3675 u8 reserved_at_60[0x20]; 3676 3677 u8 reserved_at_80[0x2]; 3678 u8 log_page_size[0x6]; 3679 u8 reserved_at_88[0x18]; 3680 3681 u8 reserved_at_a0[0x20]; 3682 3683 u8 reserved_at_c0[0x8]; 3684 u8 pd[0x18]; 3685 3686 u8 lwm[0x10]; 3687 u8 wqe_cnt[0x10]; 3688 3689 u8 reserved_at_100[0x40]; 3690 3691 u8 dbr_addr[0x40]; 3692 3693 u8 reserved_at_180[0x80]; 3694 }; 3695 3696 enum { 3697 MLX5_SQC_STATE_RST = 0x0, 3698 MLX5_SQC_STATE_RDY = 0x1, 3699 MLX5_SQC_STATE_ERR = 0x3, 3700 }; 3701 3702 struct mlx5_ifc_sqc_bits { 3703 u8 rlky[0x1]; 3704 u8 cd_master[0x1]; 3705 u8 fre[0x1]; 3706 u8 flush_in_error_en[0x1]; 3707 u8 allow_multi_pkt_send_wqe[0x1]; 3708 u8 min_wqe_inline_mode[0x3]; 3709 u8 state[0x4]; 3710 u8 reg_umr[0x1]; 3711 u8 allow_swp[0x1]; 3712 u8 hairpin[0x1]; 3713 u8 reserved_at_f[0xb]; 3714 u8 ts_format[0x2]; 3715 u8 reserved_at_1c[0x4]; 3716 3717 u8 reserved_at_20[0x8]; 3718 u8 user_index[0x18]; 3719 3720 u8 reserved_at_40[0x8]; 3721 u8 cqn[0x18]; 3722 3723 u8 reserved_at_60[0x8]; 3724 u8 hairpin_peer_rq[0x18]; 3725 3726 u8 reserved_at_80[0x10]; 3727 u8 hairpin_peer_vhca[0x10]; 3728 3729 u8 reserved_at_a0[0x20]; 3730 3731 u8 reserved_at_c0[0x8]; 3732 u8 ts_cqe_to_dest_cqn[0x18]; 3733 3734 u8 reserved_at_e0[0x10]; 3735 u8 packet_pacing_rate_limit_index[0x10]; 3736 u8 tis_lst_sz[0x10]; 3737 u8 qos_queue_group_id[0x10]; 3738 3739 u8 reserved_at_120[0x40]; 3740 3741 u8 reserved_at_160[0x8]; 3742 u8 tis_num_0[0x18]; 3743 3744 struct mlx5_ifc_wq_bits wq; 3745 }; 3746 3747 enum { 3748 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3749 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3750 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3751 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3752 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3753 }; 3754 3755 enum { 3756 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3757 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3758 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3759 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3760 }; 3761 3762 struct mlx5_ifc_scheduling_context_bits { 3763 u8 element_type[0x8]; 3764 u8 reserved_at_8[0x18]; 3765 3766 u8 element_attributes[0x20]; 3767 3768 u8 parent_element_id[0x20]; 3769 3770 u8 reserved_at_60[0x40]; 3771 3772 u8 bw_share[0x20]; 3773 3774 u8 max_average_bw[0x20]; 3775 3776 u8 reserved_at_e0[0x120]; 3777 }; 3778 3779 struct mlx5_ifc_rqtc_bits { 3780 u8 reserved_at_0[0xa0]; 3781 3782 u8 reserved_at_a0[0x5]; 3783 u8 list_q_type[0x3]; 3784 u8 reserved_at_a8[0x8]; 3785 u8 rqt_max_size[0x10]; 3786 3787 u8 rq_vhca_id_format[0x1]; 3788 u8 reserved_at_c1[0xf]; 3789 u8 rqt_actual_size[0x10]; 3790 3791 u8 reserved_at_e0[0x6a0]; 3792 3793 struct mlx5_ifc_rq_num_bits rq_num[]; 3794 }; 3795 3796 enum { 3797 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3798 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3799 }; 3800 3801 enum { 3802 MLX5_RQC_STATE_RST = 0x0, 3803 MLX5_RQC_STATE_RDY = 0x1, 3804 MLX5_RQC_STATE_ERR = 0x3, 3805 }; 3806 3807 enum { 3808 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3809 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3810 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3811 }; 3812 3813 enum { 3814 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3815 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3816 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3817 }; 3818 3819 struct mlx5_ifc_rqc_bits { 3820 u8 rlky[0x1]; 3821 u8 delay_drop_en[0x1]; 3822 u8 scatter_fcs[0x1]; 3823 u8 vsd[0x1]; 3824 u8 mem_rq_type[0x4]; 3825 u8 state[0x4]; 3826 u8 reserved_at_c[0x1]; 3827 u8 flush_in_error_en[0x1]; 3828 u8 hairpin[0x1]; 3829 u8 reserved_at_f[0xb]; 3830 u8 ts_format[0x2]; 3831 u8 reserved_at_1c[0x4]; 3832 3833 u8 reserved_at_20[0x8]; 3834 u8 user_index[0x18]; 3835 3836 u8 reserved_at_40[0x8]; 3837 u8 cqn[0x18]; 3838 3839 u8 counter_set_id[0x8]; 3840 u8 reserved_at_68[0x18]; 3841 3842 u8 reserved_at_80[0x8]; 3843 u8 rmpn[0x18]; 3844 3845 u8 reserved_at_a0[0x8]; 3846 u8 hairpin_peer_sq[0x18]; 3847 3848 u8 reserved_at_c0[0x10]; 3849 u8 hairpin_peer_vhca[0x10]; 3850 3851 u8 reserved_at_e0[0x46]; 3852 u8 shampo_no_match_alignment_granularity[0x2]; 3853 u8 reserved_at_128[0x6]; 3854 u8 shampo_match_criteria_type[0x2]; 3855 u8 reservation_timeout[0x10]; 3856 3857 u8 reserved_at_140[0x40]; 3858 3859 struct mlx5_ifc_wq_bits wq; 3860 }; 3861 3862 enum { 3863 MLX5_RMPC_STATE_RDY = 0x1, 3864 MLX5_RMPC_STATE_ERR = 0x3, 3865 }; 3866 3867 struct mlx5_ifc_rmpc_bits { 3868 u8 reserved_at_0[0x8]; 3869 u8 state[0x4]; 3870 u8 reserved_at_c[0x14]; 3871 3872 u8 basic_cyclic_rcv_wqe[0x1]; 3873 u8 reserved_at_21[0x1f]; 3874 3875 u8 reserved_at_40[0x140]; 3876 3877 struct mlx5_ifc_wq_bits wq; 3878 }; 3879 3880 enum { 3881 VHCA_ID_TYPE_HW = 0, 3882 VHCA_ID_TYPE_SW = 1, 3883 }; 3884 3885 struct mlx5_ifc_nic_vport_context_bits { 3886 u8 reserved_at_0[0x5]; 3887 u8 min_wqe_inline_mode[0x3]; 3888 u8 reserved_at_8[0x15]; 3889 u8 disable_mc_local_lb[0x1]; 3890 u8 disable_uc_local_lb[0x1]; 3891 u8 roce_en[0x1]; 3892 3893 u8 arm_change_event[0x1]; 3894 u8 reserved_at_21[0x1a]; 3895 u8 event_on_mtu[0x1]; 3896 u8 event_on_promisc_change[0x1]; 3897 u8 event_on_vlan_change[0x1]; 3898 u8 event_on_mc_address_change[0x1]; 3899 u8 event_on_uc_address_change[0x1]; 3900 3901 u8 vhca_id_type[0x1]; 3902 u8 reserved_at_41[0xb]; 3903 u8 affiliation_criteria[0x4]; 3904 u8 affiliated_vhca_id[0x10]; 3905 3906 u8 reserved_at_60[0xd0]; 3907 3908 u8 mtu[0x10]; 3909 3910 u8 system_image_guid[0x40]; 3911 u8 port_guid[0x40]; 3912 u8 node_guid[0x40]; 3913 3914 u8 reserved_at_200[0x140]; 3915 u8 qkey_violation_counter[0x10]; 3916 u8 reserved_at_350[0x430]; 3917 3918 u8 promisc_uc[0x1]; 3919 u8 promisc_mc[0x1]; 3920 u8 promisc_all[0x1]; 3921 u8 reserved_at_783[0x2]; 3922 u8 allowed_list_type[0x3]; 3923 u8 reserved_at_788[0xc]; 3924 u8 allowed_list_size[0xc]; 3925 3926 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3927 3928 u8 reserved_at_7e0[0x20]; 3929 3930 u8 current_uc_mac_address[][0x40]; 3931 }; 3932 3933 enum { 3934 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3935 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3936 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3937 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3938 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3939 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3940 }; 3941 3942 struct mlx5_ifc_mkc_bits { 3943 u8 reserved_at_0[0x1]; 3944 u8 free[0x1]; 3945 u8 reserved_at_2[0x1]; 3946 u8 access_mode_4_2[0x3]; 3947 u8 reserved_at_6[0x7]; 3948 u8 relaxed_ordering_write[0x1]; 3949 u8 reserved_at_e[0x1]; 3950 u8 small_fence_on_rdma_read_response[0x1]; 3951 u8 umr_en[0x1]; 3952 u8 a[0x1]; 3953 u8 rw[0x1]; 3954 u8 rr[0x1]; 3955 u8 lw[0x1]; 3956 u8 lr[0x1]; 3957 u8 access_mode_1_0[0x2]; 3958 u8 reserved_at_18[0x2]; 3959 u8 ma_translation_mode[0x2]; 3960 u8 reserved_at_1c[0x4]; 3961 3962 u8 qpn[0x18]; 3963 u8 mkey_7_0[0x8]; 3964 3965 u8 reserved_at_40[0x20]; 3966 3967 u8 length64[0x1]; 3968 u8 bsf_en[0x1]; 3969 u8 sync_umr[0x1]; 3970 u8 reserved_at_63[0x2]; 3971 u8 expected_sigerr_count[0x1]; 3972 u8 reserved_at_66[0x1]; 3973 u8 en_rinval[0x1]; 3974 u8 pd[0x18]; 3975 3976 u8 start_addr[0x40]; 3977 3978 u8 len[0x40]; 3979 3980 u8 bsf_octword_size[0x20]; 3981 3982 u8 reserved_at_120[0x80]; 3983 3984 u8 translations_octword_size[0x20]; 3985 3986 u8 reserved_at_1c0[0x19]; 3987 u8 relaxed_ordering_read[0x1]; 3988 u8 reserved_at_1d9[0x1]; 3989 u8 log_page_size[0x5]; 3990 3991 u8 reserved_at_1e0[0x20]; 3992 }; 3993 3994 struct mlx5_ifc_pkey_bits { 3995 u8 reserved_at_0[0x10]; 3996 u8 pkey[0x10]; 3997 }; 3998 3999 struct mlx5_ifc_array128_auto_bits { 4000 u8 array128_auto[16][0x8]; 4001 }; 4002 4003 struct mlx5_ifc_hca_vport_context_bits { 4004 u8 field_select[0x20]; 4005 4006 u8 reserved_at_20[0xe0]; 4007 4008 u8 sm_virt_aware[0x1]; 4009 u8 has_smi[0x1]; 4010 u8 has_raw[0x1]; 4011 u8 grh_required[0x1]; 4012 u8 reserved_at_104[0xc]; 4013 u8 port_physical_state[0x4]; 4014 u8 vport_state_policy[0x4]; 4015 u8 port_state[0x4]; 4016 u8 vport_state[0x4]; 4017 4018 u8 reserved_at_120[0x20]; 4019 4020 u8 system_image_guid[0x40]; 4021 4022 u8 port_guid[0x40]; 4023 4024 u8 node_guid[0x40]; 4025 4026 u8 cap_mask1[0x20]; 4027 4028 u8 cap_mask1_field_select[0x20]; 4029 4030 u8 cap_mask2[0x20]; 4031 4032 u8 cap_mask2_field_select[0x20]; 4033 4034 u8 reserved_at_280[0x80]; 4035 4036 u8 lid[0x10]; 4037 u8 reserved_at_310[0x4]; 4038 u8 init_type_reply[0x4]; 4039 u8 lmc[0x3]; 4040 u8 subnet_timeout[0x5]; 4041 4042 u8 sm_lid[0x10]; 4043 u8 sm_sl[0x4]; 4044 u8 reserved_at_334[0xc]; 4045 4046 u8 qkey_violation_counter[0x10]; 4047 u8 pkey_violation_counter[0x10]; 4048 4049 u8 reserved_at_360[0xca0]; 4050 }; 4051 4052 struct mlx5_ifc_esw_vport_context_bits { 4053 u8 fdb_to_vport_reg_c[0x1]; 4054 u8 reserved_at_1[0x2]; 4055 u8 vport_svlan_strip[0x1]; 4056 u8 vport_cvlan_strip[0x1]; 4057 u8 vport_svlan_insert[0x1]; 4058 u8 vport_cvlan_insert[0x2]; 4059 u8 fdb_to_vport_reg_c_id[0x8]; 4060 u8 reserved_at_10[0x10]; 4061 4062 u8 reserved_at_20[0x20]; 4063 4064 u8 svlan_cfi[0x1]; 4065 u8 svlan_pcp[0x3]; 4066 u8 svlan_id[0xc]; 4067 u8 cvlan_cfi[0x1]; 4068 u8 cvlan_pcp[0x3]; 4069 u8 cvlan_id[0xc]; 4070 4071 u8 reserved_at_60[0x720]; 4072 4073 u8 sw_steering_vport_icm_address_rx[0x40]; 4074 4075 u8 sw_steering_vport_icm_address_tx[0x40]; 4076 }; 4077 4078 enum { 4079 MLX5_EQC_STATUS_OK = 0x0, 4080 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4081 }; 4082 4083 enum { 4084 MLX5_EQC_ST_ARMED = 0x9, 4085 MLX5_EQC_ST_FIRED = 0xa, 4086 }; 4087 4088 struct mlx5_ifc_eqc_bits { 4089 u8 status[0x4]; 4090 u8 reserved_at_4[0x9]; 4091 u8 ec[0x1]; 4092 u8 oi[0x1]; 4093 u8 reserved_at_f[0x5]; 4094 u8 st[0x4]; 4095 u8 reserved_at_18[0x8]; 4096 4097 u8 reserved_at_20[0x20]; 4098 4099 u8 reserved_at_40[0x14]; 4100 u8 page_offset[0x6]; 4101 u8 reserved_at_5a[0x6]; 4102 4103 u8 reserved_at_60[0x3]; 4104 u8 log_eq_size[0x5]; 4105 u8 uar_page[0x18]; 4106 4107 u8 reserved_at_80[0x20]; 4108 4109 u8 reserved_at_a0[0x14]; 4110 u8 intr[0xc]; 4111 4112 u8 reserved_at_c0[0x3]; 4113 u8 log_page_size[0x5]; 4114 u8 reserved_at_c8[0x18]; 4115 4116 u8 reserved_at_e0[0x60]; 4117 4118 u8 reserved_at_140[0x8]; 4119 u8 consumer_counter[0x18]; 4120 4121 u8 reserved_at_160[0x8]; 4122 u8 producer_counter[0x18]; 4123 4124 u8 reserved_at_180[0x80]; 4125 }; 4126 4127 enum { 4128 MLX5_DCTC_STATE_ACTIVE = 0x0, 4129 MLX5_DCTC_STATE_DRAINING = 0x1, 4130 MLX5_DCTC_STATE_DRAINED = 0x2, 4131 }; 4132 4133 enum { 4134 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4135 MLX5_DCTC_CS_RES_NA = 0x1, 4136 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4137 }; 4138 4139 enum { 4140 MLX5_DCTC_MTU_256_BYTES = 0x1, 4141 MLX5_DCTC_MTU_512_BYTES = 0x2, 4142 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4143 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4144 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4145 }; 4146 4147 struct mlx5_ifc_dctc_bits { 4148 u8 reserved_at_0[0x4]; 4149 u8 state[0x4]; 4150 u8 reserved_at_8[0x18]; 4151 4152 u8 reserved_at_20[0x8]; 4153 u8 user_index[0x18]; 4154 4155 u8 reserved_at_40[0x8]; 4156 u8 cqn[0x18]; 4157 4158 u8 counter_set_id[0x8]; 4159 u8 atomic_mode[0x4]; 4160 u8 rre[0x1]; 4161 u8 rwe[0x1]; 4162 u8 rae[0x1]; 4163 u8 atomic_like_write_en[0x1]; 4164 u8 latency_sensitive[0x1]; 4165 u8 rlky[0x1]; 4166 u8 free_ar[0x1]; 4167 u8 reserved_at_73[0xd]; 4168 4169 u8 reserved_at_80[0x8]; 4170 u8 cs_res[0x8]; 4171 u8 reserved_at_90[0x3]; 4172 u8 min_rnr_nak[0x5]; 4173 u8 reserved_at_98[0x8]; 4174 4175 u8 reserved_at_a0[0x8]; 4176 u8 srqn_xrqn[0x18]; 4177 4178 u8 reserved_at_c0[0x8]; 4179 u8 pd[0x18]; 4180 4181 u8 tclass[0x8]; 4182 u8 reserved_at_e8[0x4]; 4183 u8 flow_label[0x14]; 4184 4185 u8 dc_access_key[0x40]; 4186 4187 u8 reserved_at_140[0x5]; 4188 u8 mtu[0x3]; 4189 u8 port[0x8]; 4190 u8 pkey_index[0x10]; 4191 4192 u8 reserved_at_160[0x8]; 4193 u8 my_addr_index[0x8]; 4194 u8 reserved_at_170[0x8]; 4195 u8 hop_limit[0x8]; 4196 4197 u8 dc_access_key_violation_count[0x20]; 4198 4199 u8 reserved_at_1a0[0x14]; 4200 u8 dei_cfi[0x1]; 4201 u8 eth_prio[0x3]; 4202 u8 ecn[0x2]; 4203 u8 dscp[0x6]; 4204 4205 u8 reserved_at_1c0[0x20]; 4206 u8 ece[0x20]; 4207 }; 4208 4209 enum { 4210 MLX5_CQC_STATUS_OK = 0x0, 4211 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4212 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4213 }; 4214 4215 enum { 4216 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4217 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4218 }; 4219 4220 enum { 4221 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4222 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4223 MLX5_CQC_ST_FIRED = 0xa, 4224 }; 4225 4226 enum { 4227 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4228 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4229 MLX5_CQ_PERIOD_NUM_MODES 4230 }; 4231 4232 struct mlx5_ifc_cqc_bits { 4233 u8 status[0x4]; 4234 u8 reserved_at_4[0x2]; 4235 u8 dbr_umem_valid[0x1]; 4236 u8 apu_cq[0x1]; 4237 u8 cqe_sz[0x3]; 4238 u8 cc[0x1]; 4239 u8 reserved_at_c[0x1]; 4240 u8 scqe_break_moderation_en[0x1]; 4241 u8 oi[0x1]; 4242 u8 cq_period_mode[0x2]; 4243 u8 cqe_comp_en[0x1]; 4244 u8 mini_cqe_res_format[0x2]; 4245 u8 st[0x4]; 4246 u8 reserved_at_18[0x6]; 4247 u8 cqe_compression_layout[0x2]; 4248 4249 u8 reserved_at_20[0x20]; 4250 4251 u8 reserved_at_40[0x14]; 4252 u8 page_offset[0x6]; 4253 u8 reserved_at_5a[0x6]; 4254 4255 u8 reserved_at_60[0x3]; 4256 u8 log_cq_size[0x5]; 4257 u8 uar_page[0x18]; 4258 4259 u8 reserved_at_80[0x4]; 4260 u8 cq_period[0xc]; 4261 u8 cq_max_count[0x10]; 4262 4263 u8 c_eqn_or_apu_element[0x20]; 4264 4265 u8 reserved_at_c0[0x3]; 4266 u8 log_page_size[0x5]; 4267 u8 reserved_at_c8[0x18]; 4268 4269 u8 reserved_at_e0[0x20]; 4270 4271 u8 reserved_at_100[0x8]; 4272 u8 last_notified_index[0x18]; 4273 4274 u8 reserved_at_120[0x8]; 4275 u8 last_solicit_index[0x18]; 4276 4277 u8 reserved_at_140[0x8]; 4278 u8 consumer_counter[0x18]; 4279 4280 u8 reserved_at_160[0x8]; 4281 u8 producer_counter[0x18]; 4282 4283 u8 reserved_at_180[0x40]; 4284 4285 u8 dbr_addr[0x40]; 4286 }; 4287 4288 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4289 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4290 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4291 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4292 u8 reserved_at_0[0x800]; 4293 }; 4294 4295 struct mlx5_ifc_query_adapter_param_block_bits { 4296 u8 reserved_at_0[0xc0]; 4297 4298 u8 reserved_at_c0[0x8]; 4299 u8 ieee_vendor_id[0x18]; 4300 4301 u8 reserved_at_e0[0x10]; 4302 u8 vsd_vendor_id[0x10]; 4303 4304 u8 vsd[208][0x8]; 4305 4306 u8 vsd_contd_psid[16][0x8]; 4307 }; 4308 4309 enum { 4310 MLX5_XRQC_STATE_GOOD = 0x0, 4311 MLX5_XRQC_STATE_ERROR = 0x1, 4312 }; 4313 4314 enum { 4315 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4316 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4317 }; 4318 4319 enum { 4320 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4321 }; 4322 4323 struct mlx5_ifc_tag_matching_topology_context_bits { 4324 u8 log_matching_list_sz[0x4]; 4325 u8 reserved_at_4[0xc]; 4326 u8 append_next_index[0x10]; 4327 4328 u8 sw_phase_cnt[0x10]; 4329 u8 hw_phase_cnt[0x10]; 4330 4331 u8 reserved_at_40[0x40]; 4332 }; 4333 4334 struct mlx5_ifc_xrqc_bits { 4335 u8 state[0x4]; 4336 u8 rlkey[0x1]; 4337 u8 reserved_at_5[0xf]; 4338 u8 topology[0x4]; 4339 u8 reserved_at_18[0x4]; 4340 u8 offload[0x4]; 4341 4342 u8 reserved_at_20[0x8]; 4343 u8 user_index[0x18]; 4344 4345 u8 reserved_at_40[0x8]; 4346 u8 cqn[0x18]; 4347 4348 u8 reserved_at_60[0xa0]; 4349 4350 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4351 4352 u8 reserved_at_180[0x280]; 4353 4354 struct mlx5_ifc_wq_bits wq; 4355 }; 4356 4357 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4358 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4359 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4360 u8 reserved_at_0[0x20]; 4361 }; 4362 4363 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4364 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4365 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4366 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4367 u8 reserved_at_0[0x20]; 4368 }; 4369 4370 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4371 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4372 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4373 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4374 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4375 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4376 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4377 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4378 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4379 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4380 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4381 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4382 u8 reserved_at_0[0x7c0]; 4383 }; 4384 4385 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4386 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4387 u8 reserved_at_0[0x7c0]; 4388 }; 4389 4390 union mlx5_ifc_event_auto_bits { 4391 struct mlx5_ifc_comp_event_bits comp_event; 4392 struct mlx5_ifc_dct_events_bits dct_events; 4393 struct mlx5_ifc_qp_events_bits qp_events; 4394 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4395 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4396 struct mlx5_ifc_cq_error_bits cq_error; 4397 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4398 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4399 struct mlx5_ifc_gpio_event_bits gpio_event; 4400 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4401 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4402 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4403 u8 reserved_at_0[0xe0]; 4404 }; 4405 4406 struct mlx5_ifc_health_buffer_bits { 4407 u8 reserved_at_0[0x100]; 4408 4409 u8 assert_existptr[0x20]; 4410 4411 u8 assert_callra[0x20]; 4412 4413 u8 reserved_at_140[0x20]; 4414 4415 u8 time[0x20]; 4416 4417 u8 fw_version[0x20]; 4418 4419 u8 hw_id[0x20]; 4420 4421 u8 rfr[0x1]; 4422 u8 reserved_at_1c1[0x3]; 4423 u8 valid[0x1]; 4424 u8 severity[0x3]; 4425 u8 reserved_at_1c8[0x18]; 4426 4427 u8 irisc_index[0x8]; 4428 u8 synd[0x8]; 4429 u8 ext_synd[0x10]; 4430 }; 4431 4432 struct mlx5_ifc_register_loopback_control_bits { 4433 u8 no_lb[0x1]; 4434 u8 reserved_at_1[0x7]; 4435 u8 port[0x8]; 4436 u8 reserved_at_10[0x10]; 4437 4438 u8 reserved_at_20[0x60]; 4439 }; 4440 4441 struct mlx5_ifc_vport_tc_element_bits { 4442 u8 traffic_class[0x4]; 4443 u8 reserved_at_4[0xc]; 4444 u8 vport_number[0x10]; 4445 }; 4446 4447 struct mlx5_ifc_vport_element_bits { 4448 u8 reserved_at_0[0x10]; 4449 u8 vport_number[0x10]; 4450 }; 4451 4452 enum { 4453 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4454 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4455 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4456 }; 4457 4458 struct mlx5_ifc_tsar_element_bits { 4459 u8 reserved_at_0[0x8]; 4460 u8 tsar_type[0x8]; 4461 u8 reserved_at_10[0x10]; 4462 }; 4463 4464 enum { 4465 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4466 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4467 }; 4468 4469 struct mlx5_ifc_teardown_hca_out_bits { 4470 u8 status[0x8]; 4471 u8 reserved_at_8[0x18]; 4472 4473 u8 syndrome[0x20]; 4474 4475 u8 reserved_at_40[0x3f]; 4476 4477 u8 state[0x1]; 4478 }; 4479 4480 enum { 4481 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4482 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4483 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4484 }; 4485 4486 struct mlx5_ifc_teardown_hca_in_bits { 4487 u8 opcode[0x10]; 4488 u8 reserved_at_10[0x10]; 4489 4490 u8 reserved_at_20[0x10]; 4491 u8 op_mod[0x10]; 4492 4493 u8 reserved_at_40[0x10]; 4494 u8 profile[0x10]; 4495 4496 u8 reserved_at_60[0x20]; 4497 }; 4498 4499 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4500 u8 status[0x8]; 4501 u8 reserved_at_8[0x18]; 4502 4503 u8 syndrome[0x20]; 4504 4505 u8 reserved_at_40[0x40]; 4506 }; 4507 4508 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4509 u8 opcode[0x10]; 4510 u8 uid[0x10]; 4511 4512 u8 reserved_at_20[0x10]; 4513 u8 op_mod[0x10]; 4514 4515 u8 reserved_at_40[0x8]; 4516 u8 qpn[0x18]; 4517 4518 u8 reserved_at_60[0x20]; 4519 4520 u8 opt_param_mask[0x20]; 4521 4522 u8 reserved_at_a0[0x20]; 4523 4524 struct mlx5_ifc_qpc_bits qpc; 4525 4526 u8 reserved_at_800[0x80]; 4527 }; 4528 4529 struct mlx5_ifc_sqd2rts_qp_out_bits { 4530 u8 status[0x8]; 4531 u8 reserved_at_8[0x18]; 4532 4533 u8 syndrome[0x20]; 4534 4535 u8 reserved_at_40[0x40]; 4536 }; 4537 4538 struct mlx5_ifc_sqd2rts_qp_in_bits { 4539 u8 opcode[0x10]; 4540 u8 uid[0x10]; 4541 4542 u8 reserved_at_20[0x10]; 4543 u8 op_mod[0x10]; 4544 4545 u8 reserved_at_40[0x8]; 4546 u8 qpn[0x18]; 4547 4548 u8 reserved_at_60[0x20]; 4549 4550 u8 opt_param_mask[0x20]; 4551 4552 u8 reserved_at_a0[0x20]; 4553 4554 struct mlx5_ifc_qpc_bits qpc; 4555 4556 u8 reserved_at_800[0x80]; 4557 }; 4558 4559 struct mlx5_ifc_set_roce_address_out_bits { 4560 u8 status[0x8]; 4561 u8 reserved_at_8[0x18]; 4562 4563 u8 syndrome[0x20]; 4564 4565 u8 reserved_at_40[0x40]; 4566 }; 4567 4568 struct mlx5_ifc_set_roce_address_in_bits { 4569 u8 opcode[0x10]; 4570 u8 reserved_at_10[0x10]; 4571 4572 u8 reserved_at_20[0x10]; 4573 u8 op_mod[0x10]; 4574 4575 u8 roce_address_index[0x10]; 4576 u8 reserved_at_50[0xc]; 4577 u8 vhca_port_num[0x4]; 4578 4579 u8 reserved_at_60[0x20]; 4580 4581 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4582 }; 4583 4584 struct mlx5_ifc_set_mad_demux_out_bits { 4585 u8 status[0x8]; 4586 u8 reserved_at_8[0x18]; 4587 4588 u8 syndrome[0x20]; 4589 4590 u8 reserved_at_40[0x40]; 4591 }; 4592 4593 enum { 4594 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4595 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4596 }; 4597 4598 struct mlx5_ifc_set_mad_demux_in_bits { 4599 u8 opcode[0x10]; 4600 u8 reserved_at_10[0x10]; 4601 4602 u8 reserved_at_20[0x10]; 4603 u8 op_mod[0x10]; 4604 4605 u8 reserved_at_40[0x20]; 4606 4607 u8 reserved_at_60[0x6]; 4608 u8 demux_mode[0x2]; 4609 u8 reserved_at_68[0x18]; 4610 }; 4611 4612 struct mlx5_ifc_set_l2_table_entry_out_bits { 4613 u8 status[0x8]; 4614 u8 reserved_at_8[0x18]; 4615 4616 u8 syndrome[0x20]; 4617 4618 u8 reserved_at_40[0x40]; 4619 }; 4620 4621 struct mlx5_ifc_set_l2_table_entry_in_bits { 4622 u8 opcode[0x10]; 4623 u8 reserved_at_10[0x10]; 4624 4625 u8 reserved_at_20[0x10]; 4626 u8 op_mod[0x10]; 4627 4628 u8 reserved_at_40[0x60]; 4629 4630 u8 reserved_at_a0[0x8]; 4631 u8 table_index[0x18]; 4632 4633 u8 reserved_at_c0[0x20]; 4634 4635 u8 reserved_at_e0[0x13]; 4636 u8 vlan_valid[0x1]; 4637 u8 vlan[0xc]; 4638 4639 struct mlx5_ifc_mac_address_layout_bits mac_address; 4640 4641 u8 reserved_at_140[0xc0]; 4642 }; 4643 4644 struct mlx5_ifc_set_issi_out_bits { 4645 u8 status[0x8]; 4646 u8 reserved_at_8[0x18]; 4647 4648 u8 syndrome[0x20]; 4649 4650 u8 reserved_at_40[0x40]; 4651 }; 4652 4653 struct mlx5_ifc_set_issi_in_bits { 4654 u8 opcode[0x10]; 4655 u8 reserved_at_10[0x10]; 4656 4657 u8 reserved_at_20[0x10]; 4658 u8 op_mod[0x10]; 4659 4660 u8 reserved_at_40[0x10]; 4661 u8 current_issi[0x10]; 4662 4663 u8 reserved_at_60[0x20]; 4664 }; 4665 4666 struct mlx5_ifc_set_hca_cap_out_bits { 4667 u8 status[0x8]; 4668 u8 reserved_at_8[0x18]; 4669 4670 u8 syndrome[0x20]; 4671 4672 u8 reserved_at_40[0x40]; 4673 }; 4674 4675 struct mlx5_ifc_set_hca_cap_in_bits { 4676 u8 opcode[0x10]; 4677 u8 reserved_at_10[0x10]; 4678 4679 u8 reserved_at_20[0x10]; 4680 u8 op_mod[0x10]; 4681 4682 u8 other_function[0x1]; 4683 u8 reserved_at_41[0xf]; 4684 u8 function_id[0x10]; 4685 4686 u8 reserved_at_60[0x20]; 4687 4688 union mlx5_ifc_hca_cap_union_bits capability; 4689 }; 4690 4691 enum { 4692 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4693 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4694 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4695 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4696 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4697 }; 4698 4699 struct mlx5_ifc_set_fte_out_bits { 4700 u8 status[0x8]; 4701 u8 reserved_at_8[0x18]; 4702 4703 u8 syndrome[0x20]; 4704 4705 u8 reserved_at_40[0x40]; 4706 }; 4707 4708 struct mlx5_ifc_set_fte_in_bits { 4709 u8 opcode[0x10]; 4710 u8 reserved_at_10[0x10]; 4711 4712 u8 reserved_at_20[0x10]; 4713 u8 op_mod[0x10]; 4714 4715 u8 other_vport[0x1]; 4716 u8 reserved_at_41[0xf]; 4717 u8 vport_number[0x10]; 4718 4719 u8 reserved_at_60[0x20]; 4720 4721 u8 table_type[0x8]; 4722 u8 reserved_at_88[0x18]; 4723 4724 u8 reserved_at_a0[0x8]; 4725 u8 table_id[0x18]; 4726 4727 u8 ignore_flow_level[0x1]; 4728 u8 reserved_at_c1[0x17]; 4729 u8 modify_enable_mask[0x8]; 4730 4731 u8 reserved_at_e0[0x20]; 4732 4733 u8 flow_index[0x20]; 4734 4735 u8 reserved_at_120[0xe0]; 4736 4737 struct mlx5_ifc_flow_context_bits flow_context; 4738 }; 4739 4740 struct mlx5_ifc_rts2rts_qp_out_bits { 4741 u8 status[0x8]; 4742 u8 reserved_at_8[0x18]; 4743 4744 u8 syndrome[0x20]; 4745 4746 u8 reserved_at_40[0x20]; 4747 u8 ece[0x20]; 4748 }; 4749 4750 struct mlx5_ifc_rts2rts_qp_in_bits { 4751 u8 opcode[0x10]; 4752 u8 uid[0x10]; 4753 4754 u8 reserved_at_20[0x10]; 4755 u8 op_mod[0x10]; 4756 4757 u8 reserved_at_40[0x8]; 4758 u8 qpn[0x18]; 4759 4760 u8 reserved_at_60[0x20]; 4761 4762 u8 opt_param_mask[0x20]; 4763 4764 u8 ece[0x20]; 4765 4766 struct mlx5_ifc_qpc_bits qpc; 4767 4768 u8 reserved_at_800[0x80]; 4769 }; 4770 4771 struct mlx5_ifc_rtr2rts_qp_out_bits { 4772 u8 status[0x8]; 4773 u8 reserved_at_8[0x18]; 4774 4775 u8 syndrome[0x20]; 4776 4777 u8 reserved_at_40[0x20]; 4778 u8 ece[0x20]; 4779 }; 4780 4781 struct mlx5_ifc_rtr2rts_qp_in_bits { 4782 u8 opcode[0x10]; 4783 u8 uid[0x10]; 4784 4785 u8 reserved_at_20[0x10]; 4786 u8 op_mod[0x10]; 4787 4788 u8 reserved_at_40[0x8]; 4789 u8 qpn[0x18]; 4790 4791 u8 reserved_at_60[0x20]; 4792 4793 u8 opt_param_mask[0x20]; 4794 4795 u8 ece[0x20]; 4796 4797 struct mlx5_ifc_qpc_bits qpc; 4798 4799 u8 reserved_at_800[0x80]; 4800 }; 4801 4802 struct mlx5_ifc_rst2init_qp_out_bits { 4803 u8 status[0x8]; 4804 u8 reserved_at_8[0x18]; 4805 4806 u8 syndrome[0x20]; 4807 4808 u8 reserved_at_40[0x20]; 4809 u8 ece[0x20]; 4810 }; 4811 4812 struct mlx5_ifc_rst2init_qp_in_bits { 4813 u8 opcode[0x10]; 4814 u8 uid[0x10]; 4815 4816 u8 reserved_at_20[0x10]; 4817 u8 op_mod[0x10]; 4818 4819 u8 reserved_at_40[0x8]; 4820 u8 qpn[0x18]; 4821 4822 u8 reserved_at_60[0x20]; 4823 4824 u8 opt_param_mask[0x20]; 4825 4826 u8 ece[0x20]; 4827 4828 struct mlx5_ifc_qpc_bits qpc; 4829 4830 u8 reserved_at_800[0x80]; 4831 }; 4832 4833 struct mlx5_ifc_query_xrq_out_bits { 4834 u8 status[0x8]; 4835 u8 reserved_at_8[0x18]; 4836 4837 u8 syndrome[0x20]; 4838 4839 u8 reserved_at_40[0x40]; 4840 4841 struct mlx5_ifc_xrqc_bits xrq_context; 4842 }; 4843 4844 struct mlx5_ifc_query_xrq_in_bits { 4845 u8 opcode[0x10]; 4846 u8 reserved_at_10[0x10]; 4847 4848 u8 reserved_at_20[0x10]; 4849 u8 op_mod[0x10]; 4850 4851 u8 reserved_at_40[0x8]; 4852 u8 xrqn[0x18]; 4853 4854 u8 reserved_at_60[0x20]; 4855 }; 4856 4857 struct mlx5_ifc_query_xrc_srq_out_bits { 4858 u8 status[0x8]; 4859 u8 reserved_at_8[0x18]; 4860 4861 u8 syndrome[0x20]; 4862 4863 u8 reserved_at_40[0x40]; 4864 4865 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4866 4867 u8 reserved_at_280[0x600]; 4868 4869 u8 pas[][0x40]; 4870 }; 4871 4872 struct mlx5_ifc_query_xrc_srq_in_bits { 4873 u8 opcode[0x10]; 4874 u8 reserved_at_10[0x10]; 4875 4876 u8 reserved_at_20[0x10]; 4877 u8 op_mod[0x10]; 4878 4879 u8 reserved_at_40[0x8]; 4880 u8 xrc_srqn[0x18]; 4881 4882 u8 reserved_at_60[0x20]; 4883 }; 4884 4885 enum { 4886 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4887 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4888 }; 4889 4890 struct mlx5_ifc_query_vport_state_out_bits { 4891 u8 status[0x8]; 4892 u8 reserved_at_8[0x18]; 4893 4894 u8 syndrome[0x20]; 4895 4896 u8 reserved_at_40[0x20]; 4897 4898 u8 reserved_at_60[0x18]; 4899 u8 admin_state[0x4]; 4900 u8 state[0x4]; 4901 }; 4902 4903 enum { 4904 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4905 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4906 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4907 }; 4908 4909 struct mlx5_ifc_arm_monitor_counter_in_bits { 4910 u8 opcode[0x10]; 4911 u8 uid[0x10]; 4912 4913 u8 reserved_at_20[0x10]; 4914 u8 op_mod[0x10]; 4915 4916 u8 reserved_at_40[0x20]; 4917 4918 u8 reserved_at_60[0x20]; 4919 }; 4920 4921 struct mlx5_ifc_arm_monitor_counter_out_bits { 4922 u8 status[0x8]; 4923 u8 reserved_at_8[0x18]; 4924 4925 u8 syndrome[0x20]; 4926 4927 u8 reserved_at_40[0x40]; 4928 }; 4929 4930 enum { 4931 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4932 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4933 }; 4934 4935 enum mlx5_monitor_counter_ppcnt { 4936 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4937 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4938 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4939 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4940 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4941 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4942 }; 4943 4944 enum { 4945 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4946 }; 4947 4948 struct mlx5_ifc_monitor_counter_output_bits { 4949 u8 reserved_at_0[0x4]; 4950 u8 type[0x4]; 4951 u8 reserved_at_8[0x8]; 4952 u8 counter[0x10]; 4953 4954 u8 counter_group_id[0x20]; 4955 }; 4956 4957 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4958 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4959 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4960 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4961 4962 struct mlx5_ifc_set_monitor_counter_in_bits { 4963 u8 opcode[0x10]; 4964 u8 uid[0x10]; 4965 4966 u8 reserved_at_20[0x10]; 4967 u8 op_mod[0x10]; 4968 4969 u8 reserved_at_40[0x10]; 4970 u8 num_of_counters[0x10]; 4971 4972 u8 reserved_at_60[0x20]; 4973 4974 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4975 }; 4976 4977 struct mlx5_ifc_set_monitor_counter_out_bits { 4978 u8 status[0x8]; 4979 u8 reserved_at_8[0x18]; 4980 4981 u8 syndrome[0x20]; 4982 4983 u8 reserved_at_40[0x40]; 4984 }; 4985 4986 struct mlx5_ifc_query_vport_state_in_bits { 4987 u8 opcode[0x10]; 4988 u8 reserved_at_10[0x10]; 4989 4990 u8 reserved_at_20[0x10]; 4991 u8 op_mod[0x10]; 4992 4993 u8 other_vport[0x1]; 4994 u8 reserved_at_41[0xf]; 4995 u8 vport_number[0x10]; 4996 4997 u8 reserved_at_60[0x20]; 4998 }; 4999 5000 struct mlx5_ifc_query_vnic_env_out_bits { 5001 u8 status[0x8]; 5002 u8 reserved_at_8[0x18]; 5003 5004 u8 syndrome[0x20]; 5005 5006 u8 reserved_at_40[0x40]; 5007 5008 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5009 }; 5010 5011 enum { 5012 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5013 }; 5014 5015 struct mlx5_ifc_query_vnic_env_in_bits { 5016 u8 opcode[0x10]; 5017 u8 reserved_at_10[0x10]; 5018 5019 u8 reserved_at_20[0x10]; 5020 u8 op_mod[0x10]; 5021 5022 u8 other_vport[0x1]; 5023 u8 reserved_at_41[0xf]; 5024 u8 vport_number[0x10]; 5025 5026 u8 reserved_at_60[0x20]; 5027 }; 5028 5029 struct mlx5_ifc_query_vport_counter_out_bits { 5030 u8 status[0x8]; 5031 u8 reserved_at_8[0x18]; 5032 5033 u8 syndrome[0x20]; 5034 5035 u8 reserved_at_40[0x40]; 5036 5037 struct mlx5_ifc_traffic_counter_bits received_errors; 5038 5039 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5040 5041 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5042 5043 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5044 5045 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5046 5047 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5048 5049 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5050 5051 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5052 5053 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5054 5055 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5056 5057 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5058 5059 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5060 5061 u8 reserved_at_680[0xa00]; 5062 }; 5063 5064 enum { 5065 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5066 }; 5067 5068 struct mlx5_ifc_query_vport_counter_in_bits { 5069 u8 opcode[0x10]; 5070 u8 reserved_at_10[0x10]; 5071 5072 u8 reserved_at_20[0x10]; 5073 u8 op_mod[0x10]; 5074 5075 u8 other_vport[0x1]; 5076 u8 reserved_at_41[0xb]; 5077 u8 port_num[0x4]; 5078 u8 vport_number[0x10]; 5079 5080 u8 reserved_at_60[0x60]; 5081 5082 u8 clear[0x1]; 5083 u8 reserved_at_c1[0x1f]; 5084 5085 u8 reserved_at_e0[0x20]; 5086 }; 5087 5088 struct mlx5_ifc_query_tis_out_bits { 5089 u8 status[0x8]; 5090 u8 reserved_at_8[0x18]; 5091 5092 u8 syndrome[0x20]; 5093 5094 u8 reserved_at_40[0x40]; 5095 5096 struct mlx5_ifc_tisc_bits tis_context; 5097 }; 5098 5099 struct mlx5_ifc_query_tis_in_bits { 5100 u8 opcode[0x10]; 5101 u8 reserved_at_10[0x10]; 5102 5103 u8 reserved_at_20[0x10]; 5104 u8 op_mod[0x10]; 5105 5106 u8 reserved_at_40[0x8]; 5107 u8 tisn[0x18]; 5108 5109 u8 reserved_at_60[0x20]; 5110 }; 5111 5112 struct mlx5_ifc_query_tir_out_bits { 5113 u8 status[0x8]; 5114 u8 reserved_at_8[0x18]; 5115 5116 u8 syndrome[0x20]; 5117 5118 u8 reserved_at_40[0xc0]; 5119 5120 struct mlx5_ifc_tirc_bits tir_context; 5121 }; 5122 5123 struct mlx5_ifc_query_tir_in_bits { 5124 u8 opcode[0x10]; 5125 u8 reserved_at_10[0x10]; 5126 5127 u8 reserved_at_20[0x10]; 5128 u8 op_mod[0x10]; 5129 5130 u8 reserved_at_40[0x8]; 5131 u8 tirn[0x18]; 5132 5133 u8 reserved_at_60[0x20]; 5134 }; 5135 5136 struct mlx5_ifc_query_srq_out_bits { 5137 u8 status[0x8]; 5138 u8 reserved_at_8[0x18]; 5139 5140 u8 syndrome[0x20]; 5141 5142 u8 reserved_at_40[0x40]; 5143 5144 struct mlx5_ifc_srqc_bits srq_context_entry; 5145 5146 u8 reserved_at_280[0x600]; 5147 5148 u8 pas[][0x40]; 5149 }; 5150 5151 struct mlx5_ifc_query_srq_in_bits { 5152 u8 opcode[0x10]; 5153 u8 reserved_at_10[0x10]; 5154 5155 u8 reserved_at_20[0x10]; 5156 u8 op_mod[0x10]; 5157 5158 u8 reserved_at_40[0x8]; 5159 u8 srqn[0x18]; 5160 5161 u8 reserved_at_60[0x20]; 5162 }; 5163 5164 struct mlx5_ifc_query_sq_out_bits { 5165 u8 status[0x8]; 5166 u8 reserved_at_8[0x18]; 5167 5168 u8 syndrome[0x20]; 5169 5170 u8 reserved_at_40[0xc0]; 5171 5172 struct mlx5_ifc_sqc_bits sq_context; 5173 }; 5174 5175 struct mlx5_ifc_query_sq_in_bits { 5176 u8 opcode[0x10]; 5177 u8 reserved_at_10[0x10]; 5178 5179 u8 reserved_at_20[0x10]; 5180 u8 op_mod[0x10]; 5181 5182 u8 reserved_at_40[0x8]; 5183 u8 sqn[0x18]; 5184 5185 u8 reserved_at_60[0x20]; 5186 }; 5187 5188 struct mlx5_ifc_query_special_contexts_out_bits { 5189 u8 status[0x8]; 5190 u8 reserved_at_8[0x18]; 5191 5192 u8 syndrome[0x20]; 5193 5194 u8 dump_fill_mkey[0x20]; 5195 5196 u8 resd_lkey[0x20]; 5197 5198 u8 null_mkey[0x20]; 5199 5200 u8 reserved_at_a0[0x60]; 5201 }; 5202 5203 struct mlx5_ifc_query_special_contexts_in_bits { 5204 u8 opcode[0x10]; 5205 u8 reserved_at_10[0x10]; 5206 5207 u8 reserved_at_20[0x10]; 5208 u8 op_mod[0x10]; 5209 5210 u8 reserved_at_40[0x40]; 5211 }; 5212 5213 struct mlx5_ifc_query_scheduling_element_out_bits { 5214 u8 opcode[0x10]; 5215 u8 reserved_at_10[0x10]; 5216 5217 u8 reserved_at_20[0x10]; 5218 u8 op_mod[0x10]; 5219 5220 u8 reserved_at_40[0xc0]; 5221 5222 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5223 5224 u8 reserved_at_300[0x100]; 5225 }; 5226 5227 enum { 5228 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5229 SCHEDULING_HIERARCHY_NIC = 0x3, 5230 }; 5231 5232 struct mlx5_ifc_query_scheduling_element_in_bits { 5233 u8 opcode[0x10]; 5234 u8 reserved_at_10[0x10]; 5235 5236 u8 reserved_at_20[0x10]; 5237 u8 op_mod[0x10]; 5238 5239 u8 scheduling_hierarchy[0x8]; 5240 u8 reserved_at_48[0x18]; 5241 5242 u8 scheduling_element_id[0x20]; 5243 5244 u8 reserved_at_80[0x180]; 5245 }; 5246 5247 struct mlx5_ifc_query_rqt_out_bits { 5248 u8 status[0x8]; 5249 u8 reserved_at_8[0x18]; 5250 5251 u8 syndrome[0x20]; 5252 5253 u8 reserved_at_40[0xc0]; 5254 5255 struct mlx5_ifc_rqtc_bits rqt_context; 5256 }; 5257 5258 struct mlx5_ifc_query_rqt_in_bits { 5259 u8 opcode[0x10]; 5260 u8 reserved_at_10[0x10]; 5261 5262 u8 reserved_at_20[0x10]; 5263 u8 op_mod[0x10]; 5264 5265 u8 reserved_at_40[0x8]; 5266 u8 rqtn[0x18]; 5267 5268 u8 reserved_at_60[0x20]; 5269 }; 5270 5271 struct mlx5_ifc_query_rq_out_bits { 5272 u8 status[0x8]; 5273 u8 reserved_at_8[0x18]; 5274 5275 u8 syndrome[0x20]; 5276 5277 u8 reserved_at_40[0xc0]; 5278 5279 struct mlx5_ifc_rqc_bits rq_context; 5280 }; 5281 5282 struct mlx5_ifc_query_rq_in_bits { 5283 u8 opcode[0x10]; 5284 u8 reserved_at_10[0x10]; 5285 5286 u8 reserved_at_20[0x10]; 5287 u8 op_mod[0x10]; 5288 5289 u8 reserved_at_40[0x8]; 5290 u8 rqn[0x18]; 5291 5292 u8 reserved_at_60[0x20]; 5293 }; 5294 5295 struct mlx5_ifc_query_roce_address_out_bits { 5296 u8 status[0x8]; 5297 u8 reserved_at_8[0x18]; 5298 5299 u8 syndrome[0x20]; 5300 5301 u8 reserved_at_40[0x40]; 5302 5303 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5304 }; 5305 5306 struct mlx5_ifc_query_roce_address_in_bits { 5307 u8 opcode[0x10]; 5308 u8 reserved_at_10[0x10]; 5309 5310 u8 reserved_at_20[0x10]; 5311 u8 op_mod[0x10]; 5312 5313 u8 roce_address_index[0x10]; 5314 u8 reserved_at_50[0xc]; 5315 u8 vhca_port_num[0x4]; 5316 5317 u8 reserved_at_60[0x20]; 5318 }; 5319 5320 struct mlx5_ifc_query_rmp_out_bits { 5321 u8 status[0x8]; 5322 u8 reserved_at_8[0x18]; 5323 5324 u8 syndrome[0x20]; 5325 5326 u8 reserved_at_40[0xc0]; 5327 5328 struct mlx5_ifc_rmpc_bits rmp_context; 5329 }; 5330 5331 struct mlx5_ifc_query_rmp_in_bits { 5332 u8 opcode[0x10]; 5333 u8 reserved_at_10[0x10]; 5334 5335 u8 reserved_at_20[0x10]; 5336 u8 op_mod[0x10]; 5337 5338 u8 reserved_at_40[0x8]; 5339 u8 rmpn[0x18]; 5340 5341 u8 reserved_at_60[0x20]; 5342 }; 5343 5344 struct mlx5_ifc_query_qp_out_bits { 5345 u8 status[0x8]; 5346 u8 reserved_at_8[0x18]; 5347 5348 u8 syndrome[0x20]; 5349 5350 u8 reserved_at_40[0x40]; 5351 5352 u8 opt_param_mask[0x20]; 5353 5354 u8 ece[0x20]; 5355 5356 struct mlx5_ifc_qpc_bits qpc; 5357 5358 u8 reserved_at_800[0x80]; 5359 5360 u8 pas[][0x40]; 5361 }; 5362 5363 struct mlx5_ifc_query_qp_in_bits { 5364 u8 opcode[0x10]; 5365 u8 reserved_at_10[0x10]; 5366 5367 u8 reserved_at_20[0x10]; 5368 u8 op_mod[0x10]; 5369 5370 u8 reserved_at_40[0x8]; 5371 u8 qpn[0x18]; 5372 5373 u8 reserved_at_60[0x20]; 5374 }; 5375 5376 struct mlx5_ifc_query_q_counter_out_bits { 5377 u8 status[0x8]; 5378 u8 reserved_at_8[0x18]; 5379 5380 u8 syndrome[0x20]; 5381 5382 u8 reserved_at_40[0x40]; 5383 5384 u8 rx_write_requests[0x20]; 5385 5386 u8 reserved_at_a0[0x20]; 5387 5388 u8 rx_read_requests[0x20]; 5389 5390 u8 reserved_at_e0[0x20]; 5391 5392 u8 rx_atomic_requests[0x20]; 5393 5394 u8 reserved_at_120[0x20]; 5395 5396 u8 rx_dct_connect[0x20]; 5397 5398 u8 reserved_at_160[0x20]; 5399 5400 u8 out_of_buffer[0x20]; 5401 5402 u8 reserved_at_1a0[0x20]; 5403 5404 u8 out_of_sequence[0x20]; 5405 5406 u8 reserved_at_1e0[0x20]; 5407 5408 u8 duplicate_request[0x20]; 5409 5410 u8 reserved_at_220[0x20]; 5411 5412 u8 rnr_nak_retry_err[0x20]; 5413 5414 u8 reserved_at_260[0x20]; 5415 5416 u8 packet_seq_err[0x20]; 5417 5418 u8 reserved_at_2a0[0x20]; 5419 5420 u8 implied_nak_seq_err[0x20]; 5421 5422 u8 reserved_at_2e0[0x20]; 5423 5424 u8 local_ack_timeout_err[0x20]; 5425 5426 u8 reserved_at_320[0xa0]; 5427 5428 u8 resp_local_length_error[0x20]; 5429 5430 u8 req_local_length_error[0x20]; 5431 5432 u8 resp_local_qp_error[0x20]; 5433 5434 u8 local_operation_error[0x20]; 5435 5436 u8 resp_local_protection[0x20]; 5437 5438 u8 req_local_protection[0x20]; 5439 5440 u8 resp_cqe_error[0x20]; 5441 5442 u8 req_cqe_error[0x20]; 5443 5444 u8 req_mw_binding[0x20]; 5445 5446 u8 req_bad_response[0x20]; 5447 5448 u8 req_remote_invalid_request[0x20]; 5449 5450 u8 resp_remote_invalid_request[0x20]; 5451 5452 u8 req_remote_access_errors[0x20]; 5453 5454 u8 resp_remote_access_errors[0x20]; 5455 5456 u8 req_remote_operation_errors[0x20]; 5457 5458 u8 req_transport_retries_exceeded[0x20]; 5459 5460 u8 cq_overflow[0x20]; 5461 5462 u8 resp_cqe_flush_error[0x20]; 5463 5464 u8 req_cqe_flush_error[0x20]; 5465 5466 u8 reserved_at_620[0x20]; 5467 5468 u8 roce_adp_retrans[0x20]; 5469 5470 u8 roce_adp_retrans_to[0x20]; 5471 5472 u8 roce_slow_restart[0x20]; 5473 5474 u8 roce_slow_restart_cnps[0x20]; 5475 5476 u8 roce_slow_restart_trans[0x20]; 5477 5478 u8 reserved_at_6e0[0x120]; 5479 }; 5480 5481 struct mlx5_ifc_query_q_counter_in_bits { 5482 u8 opcode[0x10]; 5483 u8 reserved_at_10[0x10]; 5484 5485 u8 reserved_at_20[0x10]; 5486 u8 op_mod[0x10]; 5487 5488 u8 reserved_at_40[0x80]; 5489 5490 u8 clear[0x1]; 5491 u8 reserved_at_c1[0x1f]; 5492 5493 u8 reserved_at_e0[0x18]; 5494 u8 counter_set_id[0x8]; 5495 }; 5496 5497 struct mlx5_ifc_query_pages_out_bits { 5498 u8 status[0x8]; 5499 u8 reserved_at_8[0x18]; 5500 5501 u8 syndrome[0x20]; 5502 5503 u8 embedded_cpu_function[0x1]; 5504 u8 reserved_at_41[0xf]; 5505 u8 function_id[0x10]; 5506 5507 u8 num_pages[0x20]; 5508 }; 5509 5510 enum { 5511 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5512 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5513 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5514 }; 5515 5516 struct mlx5_ifc_query_pages_in_bits { 5517 u8 opcode[0x10]; 5518 u8 reserved_at_10[0x10]; 5519 5520 u8 reserved_at_20[0x10]; 5521 u8 op_mod[0x10]; 5522 5523 u8 embedded_cpu_function[0x1]; 5524 u8 reserved_at_41[0xf]; 5525 u8 function_id[0x10]; 5526 5527 u8 reserved_at_60[0x20]; 5528 }; 5529 5530 struct mlx5_ifc_query_nic_vport_context_out_bits { 5531 u8 status[0x8]; 5532 u8 reserved_at_8[0x18]; 5533 5534 u8 syndrome[0x20]; 5535 5536 u8 reserved_at_40[0x40]; 5537 5538 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5539 }; 5540 5541 struct mlx5_ifc_query_nic_vport_context_in_bits { 5542 u8 opcode[0x10]; 5543 u8 reserved_at_10[0x10]; 5544 5545 u8 reserved_at_20[0x10]; 5546 u8 op_mod[0x10]; 5547 5548 u8 other_vport[0x1]; 5549 u8 reserved_at_41[0xf]; 5550 u8 vport_number[0x10]; 5551 5552 u8 reserved_at_60[0x5]; 5553 u8 allowed_list_type[0x3]; 5554 u8 reserved_at_68[0x18]; 5555 }; 5556 5557 struct mlx5_ifc_query_mkey_out_bits { 5558 u8 status[0x8]; 5559 u8 reserved_at_8[0x18]; 5560 5561 u8 syndrome[0x20]; 5562 5563 u8 reserved_at_40[0x40]; 5564 5565 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5566 5567 u8 reserved_at_280[0x600]; 5568 5569 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5570 5571 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5572 }; 5573 5574 struct mlx5_ifc_query_mkey_in_bits { 5575 u8 opcode[0x10]; 5576 u8 reserved_at_10[0x10]; 5577 5578 u8 reserved_at_20[0x10]; 5579 u8 op_mod[0x10]; 5580 5581 u8 reserved_at_40[0x8]; 5582 u8 mkey_index[0x18]; 5583 5584 u8 pg_access[0x1]; 5585 u8 reserved_at_61[0x1f]; 5586 }; 5587 5588 struct mlx5_ifc_query_mad_demux_out_bits { 5589 u8 status[0x8]; 5590 u8 reserved_at_8[0x18]; 5591 5592 u8 syndrome[0x20]; 5593 5594 u8 reserved_at_40[0x40]; 5595 5596 u8 mad_dumux_parameters_block[0x20]; 5597 }; 5598 5599 struct mlx5_ifc_query_mad_demux_in_bits { 5600 u8 opcode[0x10]; 5601 u8 reserved_at_10[0x10]; 5602 5603 u8 reserved_at_20[0x10]; 5604 u8 op_mod[0x10]; 5605 5606 u8 reserved_at_40[0x40]; 5607 }; 5608 5609 struct mlx5_ifc_query_l2_table_entry_out_bits { 5610 u8 status[0x8]; 5611 u8 reserved_at_8[0x18]; 5612 5613 u8 syndrome[0x20]; 5614 5615 u8 reserved_at_40[0xa0]; 5616 5617 u8 reserved_at_e0[0x13]; 5618 u8 vlan_valid[0x1]; 5619 u8 vlan[0xc]; 5620 5621 struct mlx5_ifc_mac_address_layout_bits mac_address; 5622 5623 u8 reserved_at_140[0xc0]; 5624 }; 5625 5626 struct mlx5_ifc_query_l2_table_entry_in_bits { 5627 u8 opcode[0x10]; 5628 u8 reserved_at_10[0x10]; 5629 5630 u8 reserved_at_20[0x10]; 5631 u8 op_mod[0x10]; 5632 5633 u8 reserved_at_40[0x60]; 5634 5635 u8 reserved_at_a0[0x8]; 5636 u8 table_index[0x18]; 5637 5638 u8 reserved_at_c0[0x140]; 5639 }; 5640 5641 struct mlx5_ifc_query_issi_out_bits { 5642 u8 status[0x8]; 5643 u8 reserved_at_8[0x18]; 5644 5645 u8 syndrome[0x20]; 5646 5647 u8 reserved_at_40[0x10]; 5648 u8 current_issi[0x10]; 5649 5650 u8 reserved_at_60[0xa0]; 5651 5652 u8 reserved_at_100[76][0x8]; 5653 u8 supported_issi_dw0[0x20]; 5654 }; 5655 5656 struct mlx5_ifc_query_issi_in_bits { 5657 u8 opcode[0x10]; 5658 u8 reserved_at_10[0x10]; 5659 5660 u8 reserved_at_20[0x10]; 5661 u8 op_mod[0x10]; 5662 5663 u8 reserved_at_40[0x40]; 5664 }; 5665 5666 struct mlx5_ifc_set_driver_version_out_bits { 5667 u8 status[0x8]; 5668 u8 reserved_0[0x18]; 5669 5670 u8 syndrome[0x20]; 5671 u8 reserved_1[0x40]; 5672 }; 5673 5674 struct mlx5_ifc_set_driver_version_in_bits { 5675 u8 opcode[0x10]; 5676 u8 reserved_0[0x10]; 5677 5678 u8 reserved_1[0x10]; 5679 u8 op_mod[0x10]; 5680 5681 u8 reserved_2[0x40]; 5682 u8 driver_version[64][0x8]; 5683 }; 5684 5685 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5686 u8 status[0x8]; 5687 u8 reserved_at_8[0x18]; 5688 5689 u8 syndrome[0x20]; 5690 5691 u8 reserved_at_40[0x40]; 5692 5693 struct mlx5_ifc_pkey_bits pkey[]; 5694 }; 5695 5696 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5697 u8 opcode[0x10]; 5698 u8 reserved_at_10[0x10]; 5699 5700 u8 reserved_at_20[0x10]; 5701 u8 op_mod[0x10]; 5702 5703 u8 other_vport[0x1]; 5704 u8 reserved_at_41[0xb]; 5705 u8 port_num[0x4]; 5706 u8 vport_number[0x10]; 5707 5708 u8 reserved_at_60[0x10]; 5709 u8 pkey_index[0x10]; 5710 }; 5711 5712 enum { 5713 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5714 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5715 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5716 }; 5717 5718 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5719 u8 status[0x8]; 5720 u8 reserved_at_8[0x18]; 5721 5722 u8 syndrome[0x20]; 5723 5724 u8 reserved_at_40[0x20]; 5725 5726 u8 gids_num[0x10]; 5727 u8 reserved_at_70[0x10]; 5728 5729 struct mlx5_ifc_array128_auto_bits gid[]; 5730 }; 5731 5732 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5733 u8 opcode[0x10]; 5734 u8 reserved_at_10[0x10]; 5735 5736 u8 reserved_at_20[0x10]; 5737 u8 op_mod[0x10]; 5738 5739 u8 other_vport[0x1]; 5740 u8 reserved_at_41[0xb]; 5741 u8 port_num[0x4]; 5742 u8 vport_number[0x10]; 5743 5744 u8 reserved_at_60[0x10]; 5745 u8 gid_index[0x10]; 5746 }; 5747 5748 struct mlx5_ifc_query_hca_vport_context_out_bits { 5749 u8 status[0x8]; 5750 u8 reserved_at_8[0x18]; 5751 5752 u8 syndrome[0x20]; 5753 5754 u8 reserved_at_40[0x40]; 5755 5756 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5757 }; 5758 5759 struct mlx5_ifc_query_hca_vport_context_in_bits { 5760 u8 opcode[0x10]; 5761 u8 reserved_at_10[0x10]; 5762 5763 u8 reserved_at_20[0x10]; 5764 u8 op_mod[0x10]; 5765 5766 u8 other_vport[0x1]; 5767 u8 reserved_at_41[0xb]; 5768 u8 port_num[0x4]; 5769 u8 vport_number[0x10]; 5770 5771 u8 reserved_at_60[0x20]; 5772 }; 5773 5774 struct mlx5_ifc_query_hca_cap_out_bits { 5775 u8 status[0x8]; 5776 u8 reserved_at_8[0x18]; 5777 5778 u8 syndrome[0x20]; 5779 5780 u8 reserved_at_40[0x40]; 5781 5782 union mlx5_ifc_hca_cap_union_bits capability; 5783 }; 5784 5785 struct mlx5_ifc_query_hca_cap_in_bits { 5786 u8 opcode[0x10]; 5787 u8 reserved_at_10[0x10]; 5788 5789 u8 reserved_at_20[0x10]; 5790 u8 op_mod[0x10]; 5791 5792 u8 other_function[0x1]; 5793 u8 reserved_at_41[0xf]; 5794 u8 function_id[0x10]; 5795 5796 u8 reserved_at_60[0x20]; 5797 }; 5798 5799 struct mlx5_ifc_other_hca_cap_bits { 5800 u8 roce[0x1]; 5801 u8 reserved_at_1[0x27f]; 5802 }; 5803 5804 struct mlx5_ifc_query_other_hca_cap_out_bits { 5805 u8 status[0x8]; 5806 u8 reserved_at_8[0x18]; 5807 5808 u8 syndrome[0x20]; 5809 5810 u8 reserved_at_40[0x40]; 5811 5812 struct mlx5_ifc_other_hca_cap_bits other_capability; 5813 }; 5814 5815 struct mlx5_ifc_query_other_hca_cap_in_bits { 5816 u8 opcode[0x10]; 5817 u8 reserved_at_10[0x10]; 5818 5819 u8 reserved_at_20[0x10]; 5820 u8 op_mod[0x10]; 5821 5822 u8 reserved_at_40[0x10]; 5823 u8 function_id[0x10]; 5824 5825 u8 reserved_at_60[0x20]; 5826 }; 5827 5828 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5829 u8 status[0x8]; 5830 u8 reserved_at_8[0x18]; 5831 5832 u8 syndrome[0x20]; 5833 5834 u8 reserved_at_40[0x40]; 5835 }; 5836 5837 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5838 u8 opcode[0x10]; 5839 u8 reserved_at_10[0x10]; 5840 5841 u8 reserved_at_20[0x10]; 5842 u8 op_mod[0x10]; 5843 5844 u8 reserved_at_40[0x10]; 5845 u8 function_id[0x10]; 5846 u8 field_select[0x20]; 5847 5848 struct mlx5_ifc_other_hca_cap_bits other_capability; 5849 }; 5850 5851 struct mlx5_ifc_flow_table_context_bits { 5852 u8 reformat_en[0x1]; 5853 u8 decap_en[0x1]; 5854 u8 sw_owner[0x1]; 5855 u8 termination_table[0x1]; 5856 u8 table_miss_action[0x4]; 5857 u8 level[0x8]; 5858 u8 reserved_at_10[0x8]; 5859 u8 log_size[0x8]; 5860 5861 u8 reserved_at_20[0x8]; 5862 u8 table_miss_id[0x18]; 5863 5864 u8 reserved_at_40[0x8]; 5865 u8 lag_master_next_table_id[0x18]; 5866 5867 u8 reserved_at_60[0x60]; 5868 5869 u8 sw_owner_icm_root_1[0x40]; 5870 5871 u8 sw_owner_icm_root_0[0x40]; 5872 5873 }; 5874 5875 struct mlx5_ifc_query_flow_table_out_bits { 5876 u8 status[0x8]; 5877 u8 reserved_at_8[0x18]; 5878 5879 u8 syndrome[0x20]; 5880 5881 u8 reserved_at_40[0x80]; 5882 5883 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5884 }; 5885 5886 struct mlx5_ifc_query_flow_table_in_bits { 5887 u8 opcode[0x10]; 5888 u8 reserved_at_10[0x10]; 5889 5890 u8 reserved_at_20[0x10]; 5891 u8 op_mod[0x10]; 5892 5893 u8 reserved_at_40[0x40]; 5894 5895 u8 table_type[0x8]; 5896 u8 reserved_at_88[0x18]; 5897 5898 u8 reserved_at_a0[0x8]; 5899 u8 table_id[0x18]; 5900 5901 u8 reserved_at_c0[0x140]; 5902 }; 5903 5904 struct mlx5_ifc_query_fte_out_bits { 5905 u8 status[0x8]; 5906 u8 reserved_at_8[0x18]; 5907 5908 u8 syndrome[0x20]; 5909 5910 u8 reserved_at_40[0x1c0]; 5911 5912 struct mlx5_ifc_flow_context_bits flow_context; 5913 }; 5914 5915 struct mlx5_ifc_query_fte_in_bits { 5916 u8 opcode[0x10]; 5917 u8 reserved_at_10[0x10]; 5918 5919 u8 reserved_at_20[0x10]; 5920 u8 op_mod[0x10]; 5921 5922 u8 reserved_at_40[0x40]; 5923 5924 u8 table_type[0x8]; 5925 u8 reserved_at_88[0x18]; 5926 5927 u8 reserved_at_a0[0x8]; 5928 u8 table_id[0x18]; 5929 5930 u8 reserved_at_c0[0x40]; 5931 5932 u8 flow_index[0x20]; 5933 5934 u8 reserved_at_120[0xe0]; 5935 }; 5936 5937 struct mlx5_ifc_match_definer_format_0_bits { 5938 u8 reserved_at_0[0x100]; 5939 5940 u8 metadata_reg_c_0[0x20]; 5941 5942 u8 metadata_reg_c_1[0x20]; 5943 5944 u8 outer_dmac_47_16[0x20]; 5945 5946 u8 outer_dmac_15_0[0x10]; 5947 u8 outer_ethertype[0x10]; 5948 5949 u8 reserved_at_180[0x1]; 5950 u8 sx_sniffer[0x1]; 5951 u8 functional_lb[0x1]; 5952 u8 outer_ip_frag[0x1]; 5953 u8 outer_qp_type[0x2]; 5954 u8 outer_encap_type[0x2]; 5955 u8 port_number[0x2]; 5956 u8 outer_l3_type[0x2]; 5957 u8 outer_l4_type[0x2]; 5958 u8 outer_first_vlan_type[0x2]; 5959 u8 outer_first_vlan_prio[0x3]; 5960 u8 outer_first_vlan_cfi[0x1]; 5961 u8 outer_first_vlan_vid[0xc]; 5962 5963 u8 outer_l4_type_ext[0x4]; 5964 u8 reserved_at_1a4[0x2]; 5965 u8 outer_ipsec_layer[0x2]; 5966 u8 outer_l2_type[0x2]; 5967 u8 force_lb[0x1]; 5968 u8 outer_l2_ok[0x1]; 5969 u8 outer_l3_ok[0x1]; 5970 u8 outer_l4_ok[0x1]; 5971 u8 outer_second_vlan_type[0x2]; 5972 u8 outer_second_vlan_prio[0x3]; 5973 u8 outer_second_vlan_cfi[0x1]; 5974 u8 outer_second_vlan_vid[0xc]; 5975 5976 u8 outer_smac_47_16[0x20]; 5977 5978 u8 outer_smac_15_0[0x10]; 5979 u8 inner_ipv4_checksum_ok[0x1]; 5980 u8 inner_l4_checksum_ok[0x1]; 5981 u8 outer_ipv4_checksum_ok[0x1]; 5982 u8 outer_l4_checksum_ok[0x1]; 5983 u8 inner_l3_ok[0x1]; 5984 u8 inner_l4_ok[0x1]; 5985 u8 outer_l3_ok_duplicate[0x1]; 5986 u8 outer_l4_ok_duplicate[0x1]; 5987 u8 outer_tcp_cwr[0x1]; 5988 u8 outer_tcp_ece[0x1]; 5989 u8 outer_tcp_urg[0x1]; 5990 u8 outer_tcp_ack[0x1]; 5991 u8 outer_tcp_psh[0x1]; 5992 u8 outer_tcp_rst[0x1]; 5993 u8 outer_tcp_syn[0x1]; 5994 u8 outer_tcp_fin[0x1]; 5995 }; 5996 5997 struct mlx5_ifc_match_definer_format_22_bits { 5998 u8 reserved_at_0[0x100]; 5999 6000 u8 outer_ip_src_addr[0x20]; 6001 6002 u8 outer_ip_dest_addr[0x20]; 6003 6004 u8 outer_l4_sport[0x10]; 6005 u8 outer_l4_dport[0x10]; 6006 6007 u8 reserved_at_160[0x1]; 6008 u8 sx_sniffer[0x1]; 6009 u8 functional_lb[0x1]; 6010 u8 outer_ip_frag[0x1]; 6011 u8 outer_qp_type[0x2]; 6012 u8 outer_encap_type[0x2]; 6013 u8 port_number[0x2]; 6014 u8 outer_l3_type[0x2]; 6015 u8 outer_l4_type[0x2]; 6016 u8 outer_first_vlan_type[0x2]; 6017 u8 outer_first_vlan_prio[0x3]; 6018 u8 outer_first_vlan_cfi[0x1]; 6019 u8 outer_first_vlan_vid[0xc]; 6020 6021 u8 metadata_reg_c_0[0x20]; 6022 6023 u8 outer_dmac_47_16[0x20]; 6024 6025 u8 outer_smac_47_16[0x20]; 6026 6027 u8 outer_smac_15_0[0x10]; 6028 u8 outer_dmac_15_0[0x10]; 6029 }; 6030 6031 struct mlx5_ifc_match_definer_format_23_bits { 6032 u8 reserved_at_0[0x100]; 6033 6034 u8 inner_ip_src_addr[0x20]; 6035 6036 u8 inner_ip_dest_addr[0x20]; 6037 6038 u8 inner_l4_sport[0x10]; 6039 u8 inner_l4_dport[0x10]; 6040 6041 u8 reserved_at_160[0x1]; 6042 u8 sx_sniffer[0x1]; 6043 u8 functional_lb[0x1]; 6044 u8 inner_ip_frag[0x1]; 6045 u8 inner_qp_type[0x2]; 6046 u8 inner_encap_type[0x2]; 6047 u8 port_number[0x2]; 6048 u8 inner_l3_type[0x2]; 6049 u8 inner_l4_type[0x2]; 6050 u8 inner_first_vlan_type[0x2]; 6051 u8 inner_first_vlan_prio[0x3]; 6052 u8 inner_first_vlan_cfi[0x1]; 6053 u8 inner_first_vlan_vid[0xc]; 6054 6055 u8 tunnel_header_0[0x20]; 6056 6057 u8 inner_dmac_47_16[0x20]; 6058 6059 u8 inner_smac_47_16[0x20]; 6060 6061 u8 inner_smac_15_0[0x10]; 6062 u8 inner_dmac_15_0[0x10]; 6063 }; 6064 6065 struct mlx5_ifc_match_definer_format_29_bits { 6066 u8 reserved_at_0[0xc0]; 6067 6068 u8 outer_ip_dest_addr[0x80]; 6069 6070 u8 outer_ip_src_addr[0x80]; 6071 6072 u8 outer_l4_sport[0x10]; 6073 u8 outer_l4_dport[0x10]; 6074 6075 u8 reserved_at_1e0[0x20]; 6076 }; 6077 6078 struct mlx5_ifc_match_definer_format_30_bits { 6079 u8 reserved_at_0[0xa0]; 6080 6081 u8 outer_ip_dest_addr[0x80]; 6082 6083 u8 outer_ip_src_addr[0x80]; 6084 6085 u8 outer_dmac_47_16[0x20]; 6086 6087 u8 outer_smac_47_16[0x20]; 6088 6089 u8 outer_smac_15_0[0x10]; 6090 u8 outer_dmac_15_0[0x10]; 6091 }; 6092 6093 struct mlx5_ifc_match_definer_format_31_bits { 6094 u8 reserved_at_0[0xc0]; 6095 6096 u8 inner_ip_dest_addr[0x80]; 6097 6098 u8 inner_ip_src_addr[0x80]; 6099 6100 u8 inner_l4_sport[0x10]; 6101 u8 inner_l4_dport[0x10]; 6102 6103 u8 reserved_at_1e0[0x20]; 6104 }; 6105 6106 struct mlx5_ifc_match_definer_format_32_bits { 6107 u8 reserved_at_0[0xa0]; 6108 6109 u8 inner_ip_dest_addr[0x80]; 6110 6111 u8 inner_ip_src_addr[0x80]; 6112 6113 u8 inner_dmac_47_16[0x20]; 6114 6115 u8 inner_smac_47_16[0x20]; 6116 6117 u8 inner_smac_15_0[0x10]; 6118 u8 inner_dmac_15_0[0x10]; 6119 }; 6120 6121 enum { 6122 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6123 }; 6124 6125 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6126 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6127 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6128 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6129 6130 struct mlx5_ifc_match_definer_match_mask_bits { 6131 u8 reserved_at_1c0[5][0x20]; 6132 u8 match_dw_8[0x20]; 6133 u8 match_dw_7[0x20]; 6134 u8 match_dw_6[0x20]; 6135 u8 match_dw_5[0x20]; 6136 u8 match_dw_4[0x20]; 6137 u8 match_dw_3[0x20]; 6138 u8 match_dw_2[0x20]; 6139 u8 match_dw_1[0x20]; 6140 u8 match_dw_0[0x20]; 6141 6142 u8 match_byte_7[0x8]; 6143 u8 match_byte_6[0x8]; 6144 u8 match_byte_5[0x8]; 6145 u8 match_byte_4[0x8]; 6146 6147 u8 match_byte_3[0x8]; 6148 u8 match_byte_2[0x8]; 6149 u8 match_byte_1[0x8]; 6150 u8 match_byte_0[0x8]; 6151 }; 6152 6153 struct mlx5_ifc_match_definer_bits { 6154 u8 modify_field_select[0x40]; 6155 6156 u8 reserved_at_40[0x40]; 6157 6158 u8 reserved_at_80[0x10]; 6159 u8 format_id[0x10]; 6160 6161 u8 reserved_at_a0[0x60]; 6162 6163 u8 format_select_dw3[0x8]; 6164 u8 format_select_dw2[0x8]; 6165 u8 format_select_dw1[0x8]; 6166 u8 format_select_dw0[0x8]; 6167 6168 u8 format_select_dw7[0x8]; 6169 u8 format_select_dw6[0x8]; 6170 u8 format_select_dw5[0x8]; 6171 u8 format_select_dw4[0x8]; 6172 6173 u8 reserved_at_100[0x18]; 6174 u8 format_select_dw8[0x8]; 6175 6176 u8 reserved_at_120[0x20]; 6177 6178 u8 format_select_byte3[0x8]; 6179 u8 format_select_byte2[0x8]; 6180 u8 format_select_byte1[0x8]; 6181 u8 format_select_byte0[0x8]; 6182 6183 u8 format_select_byte7[0x8]; 6184 u8 format_select_byte6[0x8]; 6185 u8 format_select_byte5[0x8]; 6186 u8 format_select_byte4[0x8]; 6187 6188 u8 reserved_at_180[0x40]; 6189 6190 union { 6191 struct { 6192 u8 match_mask[16][0x20]; 6193 }; 6194 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6195 }; 6196 }; 6197 6198 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6199 u8 opcode[0x10]; 6200 u8 uid[0x10]; 6201 6202 u8 vhca_tunnel_id[0x10]; 6203 u8 obj_type[0x10]; 6204 6205 u8 obj_id[0x20]; 6206 6207 u8 reserved_at_60[0x3]; 6208 u8 log_obj_range[0x5]; 6209 u8 reserved_at_68[0x18]; 6210 }; 6211 6212 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6213 u8 status[0x8]; 6214 u8 reserved_at_8[0x18]; 6215 6216 u8 syndrome[0x20]; 6217 6218 u8 obj_id[0x20]; 6219 6220 u8 reserved_at_60[0x20]; 6221 }; 6222 6223 struct mlx5_ifc_create_match_definer_in_bits { 6224 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6225 6226 struct mlx5_ifc_match_definer_bits obj_context; 6227 }; 6228 6229 struct mlx5_ifc_create_match_definer_out_bits { 6230 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6231 }; 6232 6233 enum { 6234 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6235 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6236 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6237 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6238 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6239 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6240 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6241 }; 6242 6243 struct mlx5_ifc_query_flow_group_out_bits { 6244 u8 status[0x8]; 6245 u8 reserved_at_8[0x18]; 6246 6247 u8 syndrome[0x20]; 6248 6249 u8 reserved_at_40[0xa0]; 6250 6251 u8 start_flow_index[0x20]; 6252 6253 u8 reserved_at_100[0x20]; 6254 6255 u8 end_flow_index[0x20]; 6256 6257 u8 reserved_at_140[0xa0]; 6258 6259 u8 reserved_at_1e0[0x18]; 6260 u8 match_criteria_enable[0x8]; 6261 6262 struct mlx5_ifc_fte_match_param_bits match_criteria; 6263 6264 u8 reserved_at_1200[0xe00]; 6265 }; 6266 6267 struct mlx5_ifc_query_flow_group_in_bits { 6268 u8 opcode[0x10]; 6269 u8 reserved_at_10[0x10]; 6270 6271 u8 reserved_at_20[0x10]; 6272 u8 op_mod[0x10]; 6273 6274 u8 reserved_at_40[0x40]; 6275 6276 u8 table_type[0x8]; 6277 u8 reserved_at_88[0x18]; 6278 6279 u8 reserved_at_a0[0x8]; 6280 u8 table_id[0x18]; 6281 6282 u8 group_id[0x20]; 6283 6284 u8 reserved_at_e0[0x120]; 6285 }; 6286 6287 struct mlx5_ifc_query_flow_counter_out_bits { 6288 u8 status[0x8]; 6289 u8 reserved_at_8[0x18]; 6290 6291 u8 syndrome[0x20]; 6292 6293 u8 reserved_at_40[0x40]; 6294 6295 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6296 }; 6297 6298 struct mlx5_ifc_query_flow_counter_in_bits { 6299 u8 opcode[0x10]; 6300 u8 reserved_at_10[0x10]; 6301 6302 u8 reserved_at_20[0x10]; 6303 u8 op_mod[0x10]; 6304 6305 u8 reserved_at_40[0x80]; 6306 6307 u8 clear[0x1]; 6308 u8 reserved_at_c1[0xf]; 6309 u8 num_of_counters[0x10]; 6310 6311 u8 flow_counter_id[0x20]; 6312 }; 6313 6314 struct mlx5_ifc_query_esw_vport_context_out_bits { 6315 u8 status[0x8]; 6316 u8 reserved_at_8[0x18]; 6317 6318 u8 syndrome[0x20]; 6319 6320 u8 reserved_at_40[0x40]; 6321 6322 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6323 }; 6324 6325 struct mlx5_ifc_query_esw_vport_context_in_bits { 6326 u8 opcode[0x10]; 6327 u8 reserved_at_10[0x10]; 6328 6329 u8 reserved_at_20[0x10]; 6330 u8 op_mod[0x10]; 6331 6332 u8 other_vport[0x1]; 6333 u8 reserved_at_41[0xf]; 6334 u8 vport_number[0x10]; 6335 6336 u8 reserved_at_60[0x20]; 6337 }; 6338 6339 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6340 u8 status[0x8]; 6341 u8 reserved_at_8[0x18]; 6342 6343 u8 syndrome[0x20]; 6344 6345 u8 reserved_at_40[0x40]; 6346 }; 6347 6348 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6349 u8 reserved_at_0[0x1b]; 6350 u8 fdb_to_vport_reg_c_id[0x1]; 6351 u8 vport_cvlan_insert[0x1]; 6352 u8 vport_svlan_insert[0x1]; 6353 u8 vport_cvlan_strip[0x1]; 6354 u8 vport_svlan_strip[0x1]; 6355 }; 6356 6357 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6358 u8 opcode[0x10]; 6359 u8 reserved_at_10[0x10]; 6360 6361 u8 reserved_at_20[0x10]; 6362 u8 op_mod[0x10]; 6363 6364 u8 other_vport[0x1]; 6365 u8 reserved_at_41[0xf]; 6366 u8 vport_number[0x10]; 6367 6368 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6369 6370 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6371 }; 6372 6373 struct mlx5_ifc_query_eq_out_bits { 6374 u8 status[0x8]; 6375 u8 reserved_at_8[0x18]; 6376 6377 u8 syndrome[0x20]; 6378 6379 u8 reserved_at_40[0x40]; 6380 6381 struct mlx5_ifc_eqc_bits eq_context_entry; 6382 6383 u8 reserved_at_280[0x40]; 6384 6385 u8 event_bitmask[0x40]; 6386 6387 u8 reserved_at_300[0x580]; 6388 6389 u8 pas[][0x40]; 6390 }; 6391 6392 struct mlx5_ifc_query_eq_in_bits { 6393 u8 opcode[0x10]; 6394 u8 reserved_at_10[0x10]; 6395 6396 u8 reserved_at_20[0x10]; 6397 u8 op_mod[0x10]; 6398 6399 u8 reserved_at_40[0x18]; 6400 u8 eq_number[0x8]; 6401 6402 u8 reserved_at_60[0x20]; 6403 }; 6404 6405 struct mlx5_ifc_packet_reformat_context_in_bits { 6406 u8 reformat_type[0x8]; 6407 u8 reserved_at_8[0x4]; 6408 u8 reformat_param_0[0x4]; 6409 u8 reserved_at_10[0x6]; 6410 u8 reformat_data_size[0xa]; 6411 6412 u8 reformat_param_1[0x8]; 6413 u8 reserved_at_28[0x8]; 6414 u8 reformat_data[2][0x8]; 6415 6416 u8 more_reformat_data[][0x8]; 6417 }; 6418 6419 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6420 u8 status[0x8]; 6421 u8 reserved_at_8[0x18]; 6422 6423 u8 syndrome[0x20]; 6424 6425 u8 reserved_at_40[0xa0]; 6426 6427 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6428 }; 6429 6430 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6431 u8 opcode[0x10]; 6432 u8 reserved_at_10[0x10]; 6433 6434 u8 reserved_at_20[0x10]; 6435 u8 op_mod[0x10]; 6436 6437 u8 packet_reformat_id[0x20]; 6438 6439 u8 reserved_at_60[0xa0]; 6440 }; 6441 6442 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6443 u8 status[0x8]; 6444 u8 reserved_at_8[0x18]; 6445 6446 u8 syndrome[0x20]; 6447 6448 u8 packet_reformat_id[0x20]; 6449 6450 u8 reserved_at_60[0x20]; 6451 }; 6452 6453 enum { 6454 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6455 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6456 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6457 }; 6458 6459 enum mlx5_reformat_ctx_type { 6460 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6461 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6462 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6463 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6464 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6465 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6466 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6467 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6468 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6469 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6470 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6471 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6472 }; 6473 6474 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6475 u8 opcode[0x10]; 6476 u8 reserved_at_10[0x10]; 6477 6478 u8 reserved_at_20[0x10]; 6479 u8 op_mod[0x10]; 6480 6481 u8 reserved_at_40[0xa0]; 6482 6483 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6484 }; 6485 6486 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6487 u8 status[0x8]; 6488 u8 reserved_at_8[0x18]; 6489 6490 u8 syndrome[0x20]; 6491 6492 u8 reserved_at_40[0x40]; 6493 }; 6494 6495 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6496 u8 opcode[0x10]; 6497 u8 reserved_at_10[0x10]; 6498 6499 u8 reserved_20[0x10]; 6500 u8 op_mod[0x10]; 6501 6502 u8 packet_reformat_id[0x20]; 6503 6504 u8 reserved_60[0x20]; 6505 }; 6506 6507 struct mlx5_ifc_set_action_in_bits { 6508 u8 action_type[0x4]; 6509 u8 field[0xc]; 6510 u8 reserved_at_10[0x3]; 6511 u8 offset[0x5]; 6512 u8 reserved_at_18[0x3]; 6513 u8 length[0x5]; 6514 6515 u8 data[0x20]; 6516 }; 6517 6518 struct mlx5_ifc_add_action_in_bits { 6519 u8 action_type[0x4]; 6520 u8 field[0xc]; 6521 u8 reserved_at_10[0x10]; 6522 6523 u8 data[0x20]; 6524 }; 6525 6526 struct mlx5_ifc_copy_action_in_bits { 6527 u8 action_type[0x4]; 6528 u8 src_field[0xc]; 6529 u8 reserved_at_10[0x3]; 6530 u8 src_offset[0x5]; 6531 u8 reserved_at_18[0x3]; 6532 u8 length[0x5]; 6533 6534 u8 reserved_at_20[0x4]; 6535 u8 dst_field[0xc]; 6536 u8 reserved_at_30[0x3]; 6537 u8 dst_offset[0x5]; 6538 u8 reserved_at_38[0x8]; 6539 }; 6540 6541 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6542 struct mlx5_ifc_set_action_in_bits set_action_in; 6543 struct mlx5_ifc_add_action_in_bits add_action_in; 6544 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6545 u8 reserved_at_0[0x40]; 6546 }; 6547 6548 enum { 6549 MLX5_ACTION_TYPE_SET = 0x1, 6550 MLX5_ACTION_TYPE_ADD = 0x2, 6551 MLX5_ACTION_TYPE_COPY = 0x3, 6552 }; 6553 6554 enum { 6555 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6556 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6557 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6558 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6559 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6560 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6561 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6562 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6563 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6564 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6565 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6566 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6567 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6568 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6569 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6570 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6571 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6572 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6573 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6574 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6575 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6576 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6577 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6578 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6579 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6580 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6581 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6582 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6583 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6584 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6585 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6586 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6587 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6588 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6589 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6590 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6591 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6592 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6593 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6594 }; 6595 6596 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6597 u8 status[0x8]; 6598 u8 reserved_at_8[0x18]; 6599 6600 u8 syndrome[0x20]; 6601 6602 u8 modify_header_id[0x20]; 6603 6604 u8 reserved_at_60[0x20]; 6605 }; 6606 6607 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6608 u8 opcode[0x10]; 6609 u8 reserved_at_10[0x10]; 6610 6611 u8 reserved_at_20[0x10]; 6612 u8 op_mod[0x10]; 6613 6614 u8 reserved_at_40[0x20]; 6615 6616 u8 table_type[0x8]; 6617 u8 reserved_at_68[0x10]; 6618 u8 num_of_actions[0x8]; 6619 6620 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6621 }; 6622 6623 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6624 u8 status[0x8]; 6625 u8 reserved_at_8[0x18]; 6626 6627 u8 syndrome[0x20]; 6628 6629 u8 reserved_at_40[0x40]; 6630 }; 6631 6632 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6633 u8 opcode[0x10]; 6634 u8 reserved_at_10[0x10]; 6635 6636 u8 reserved_at_20[0x10]; 6637 u8 op_mod[0x10]; 6638 6639 u8 modify_header_id[0x20]; 6640 6641 u8 reserved_at_60[0x20]; 6642 }; 6643 6644 struct mlx5_ifc_query_modify_header_context_in_bits { 6645 u8 opcode[0x10]; 6646 u8 uid[0x10]; 6647 6648 u8 reserved_at_20[0x10]; 6649 u8 op_mod[0x10]; 6650 6651 u8 modify_header_id[0x20]; 6652 6653 u8 reserved_at_60[0xa0]; 6654 }; 6655 6656 struct mlx5_ifc_query_dct_out_bits { 6657 u8 status[0x8]; 6658 u8 reserved_at_8[0x18]; 6659 6660 u8 syndrome[0x20]; 6661 6662 u8 reserved_at_40[0x40]; 6663 6664 struct mlx5_ifc_dctc_bits dct_context_entry; 6665 6666 u8 reserved_at_280[0x180]; 6667 }; 6668 6669 struct mlx5_ifc_query_dct_in_bits { 6670 u8 opcode[0x10]; 6671 u8 reserved_at_10[0x10]; 6672 6673 u8 reserved_at_20[0x10]; 6674 u8 op_mod[0x10]; 6675 6676 u8 reserved_at_40[0x8]; 6677 u8 dctn[0x18]; 6678 6679 u8 reserved_at_60[0x20]; 6680 }; 6681 6682 struct mlx5_ifc_query_cq_out_bits { 6683 u8 status[0x8]; 6684 u8 reserved_at_8[0x18]; 6685 6686 u8 syndrome[0x20]; 6687 6688 u8 reserved_at_40[0x40]; 6689 6690 struct mlx5_ifc_cqc_bits cq_context; 6691 6692 u8 reserved_at_280[0x600]; 6693 6694 u8 pas[][0x40]; 6695 }; 6696 6697 struct mlx5_ifc_query_cq_in_bits { 6698 u8 opcode[0x10]; 6699 u8 reserved_at_10[0x10]; 6700 6701 u8 reserved_at_20[0x10]; 6702 u8 op_mod[0x10]; 6703 6704 u8 reserved_at_40[0x8]; 6705 u8 cqn[0x18]; 6706 6707 u8 reserved_at_60[0x20]; 6708 }; 6709 6710 struct mlx5_ifc_query_cong_status_out_bits { 6711 u8 status[0x8]; 6712 u8 reserved_at_8[0x18]; 6713 6714 u8 syndrome[0x20]; 6715 6716 u8 reserved_at_40[0x20]; 6717 6718 u8 enable[0x1]; 6719 u8 tag_enable[0x1]; 6720 u8 reserved_at_62[0x1e]; 6721 }; 6722 6723 struct mlx5_ifc_query_cong_status_in_bits { 6724 u8 opcode[0x10]; 6725 u8 reserved_at_10[0x10]; 6726 6727 u8 reserved_at_20[0x10]; 6728 u8 op_mod[0x10]; 6729 6730 u8 reserved_at_40[0x18]; 6731 u8 priority[0x4]; 6732 u8 cong_protocol[0x4]; 6733 6734 u8 reserved_at_60[0x20]; 6735 }; 6736 6737 struct mlx5_ifc_query_cong_statistics_out_bits { 6738 u8 status[0x8]; 6739 u8 reserved_at_8[0x18]; 6740 6741 u8 syndrome[0x20]; 6742 6743 u8 reserved_at_40[0x40]; 6744 6745 u8 rp_cur_flows[0x20]; 6746 6747 u8 sum_flows[0x20]; 6748 6749 u8 rp_cnp_ignored_high[0x20]; 6750 6751 u8 rp_cnp_ignored_low[0x20]; 6752 6753 u8 rp_cnp_handled_high[0x20]; 6754 6755 u8 rp_cnp_handled_low[0x20]; 6756 6757 u8 reserved_at_140[0x100]; 6758 6759 u8 time_stamp_high[0x20]; 6760 6761 u8 time_stamp_low[0x20]; 6762 6763 u8 accumulators_period[0x20]; 6764 6765 u8 np_ecn_marked_roce_packets_high[0x20]; 6766 6767 u8 np_ecn_marked_roce_packets_low[0x20]; 6768 6769 u8 np_cnp_sent_high[0x20]; 6770 6771 u8 np_cnp_sent_low[0x20]; 6772 6773 u8 reserved_at_320[0x560]; 6774 }; 6775 6776 struct mlx5_ifc_query_cong_statistics_in_bits { 6777 u8 opcode[0x10]; 6778 u8 reserved_at_10[0x10]; 6779 6780 u8 reserved_at_20[0x10]; 6781 u8 op_mod[0x10]; 6782 6783 u8 clear[0x1]; 6784 u8 reserved_at_41[0x1f]; 6785 6786 u8 reserved_at_60[0x20]; 6787 }; 6788 6789 struct mlx5_ifc_query_cong_params_out_bits { 6790 u8 status[0x8]; 6791 u8 reserved_at_8[0x18]; 6792 6793 u8 syndrome[0x20]; 6794 6795 u8 reserved_at_40[0x40]; 6796 6797 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6798 }; 6799 6800 struct mlx5_ifc_query_cong_params_in_bits { 6801 u8 opcode[0x10]; 6802 u8 reserved_at_10[0x10]; 6803 6804 u8 reserved_at_20[0x10]; 6805 u8 op_mod[0x10]; 6806 6807 u8 reserved_at_40[0x1c]; 6808 u8 cong_protocol[0x4]; 6809 6810 u8 reserved_at_60[0x20]; 6811 }; 6812 6813 struct mlx5_ifc_query_adapter_out_bits { 6814 u8 status[0x8]; 6815 u8 reserved_at_8[0x18]; 6816 6817 u8 syndrome[0x20]; 6818 6819 u8 reserved_at_40[0x40]; 6820 6821 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6822 }; 6823 6824 struct mlx5_ifc_query_adapter_in_bits { 6825 u8 opcode[0x10]; 6826 u8 reserved_at_10[0x10]; 6827 6828 u8 reserved_at_20[0x10]; 6829 u8 op_mod[0x10]; 6830 6831 u8 reserved_at_40[0x40]; 6832 }; 6833 6834 struct mlx5_ifc_qp_2rst_out_bits { 6835 u8 status[0x8]; 6836 u8 reserved_at_8[0x18]; 6837 6838 u8 syndrome[0x20]; 6839 6840 u8 reserved_at_40[0x40]; 6841 }; 6842 6843 struct mlx5_ifc_qp_2rst_in_bits { 6844 u8 opcode[0x10]; 6845 u8 uid[0x10]; 6846 6847 u8 reserved_at_20[0x10]; 6848 u8 op_mod[0x10]; 6849 6850 u8 reserved_at_40[0x8]; 6851 u8 qpn[0x18]; 6852 6853 u8 reserved_at_60[0x20]; 6854 }; 6855 6856 struct mlx5_ifc_qp_2err_out_bits { 6857 u8 status[0x8]; 6858 u8 reserved_at_8[0x18]; 6859 6860 u8 syndrome[0x20]; 6861 6862 u8 reserved_at_40[0x40]; 6863 }; 6864 6865 struct mlx5_ifc_qp_2err_in_bits { 6866 u8 opcode[0x10]; 6867 u8 uid[0x10]; 6868 6869 u8 reserved_at_20[0x10]; 6870 u8 op_mod[0x10]; 6871 6872 u8 reserved_at_40[0x8]; 6873 u8 qpn[0x18]; 6874 6875 u8 reserved_at_60[0x20]; 6876 }; 6877 6878 struct mlx5_ifc_page_fault_resume_out_bits { 6879 u8 status[0x8]; 6880 u8 reserved_at_8[0x18]; 6881 6882 u8 syndrome[0x20]; 6883 6884 u8 reserved_at_40[0x40]; 6885 }; 6886 6887 struct mlx5_ifc_page_fault_resume_in_bits { 6888 u8 opcode[0x10]; 6889 u8 reserved_at_10[0x10]; 6890 6891 u8 reserved_at_20[0x10]; 6892 u8 op_mod[0x10]; 6893 6894 u8 error[0x1]; 6895 u8 reserved_at_41[0x4]; 6896 u8 page_fault_type[0x3]; 6897 u8 wq_number[0x18]; 6898 6899 u8 reserved_at_60[0x8]; 6900 u8 token[0x18]; 6901 }; 6902 6903 struct mlx5_ifc_nop_out_bits { 6904 u8 status[0x8]; 6905 u8 reserved_at_8[0x18]; 6906 6907 u8 syndrome[0x20]; 6908 6909 u8 reserved_at_40[0x40]; 6910 }; 6911 6912 struct mlx5_ifc_nop_in_bits { 6913 u8 opcode[0x10]; 6914 u8 reserved_at_10[0x10]; 6915 6916 u8 reserved_at_20[0x10]; 6917 u8 op_mod[0x10]; 6918 6919 u8 reserved_at_40[0x40]; 6920 }; 6921 6922 struct mlx5_ifc_modify_vport_state_out_bits { 6923 u8 status[0x8]; 6924 u8 reserved_at_8[0x18]; 6925 6926 u8 syndrome[0x20]; 6927 6928 u8 reserved_at_40[0x40]; 6929 }; 6930 6931 struct mlx5_ifc_modify_vport_state_in_bits { 6932 u8 opcode[0x10]; 6933 u8 reserved_at_10[0x10]; 6934 6935 u8 reserved_at_20[0x10]; 6936 u8 op_mod[0x10]; 6937 6938 u8 other_vport[0x1]; 6939 u8 reserved_at_41[0xf]; 6940 u8 vport_number[0x10]; 6941 6942 u8 reserved_at_60[0x18]; 6943 u8 admin_state[0x4]; 6944 u8 reserved_at_7c[0x4]; 6945 }; 6946 6947 struct mlx5_ifc_modify_tis_out_bits { 6948 u8 status[0x8]; 6949 u8 reserved_at_8[0x18]; 6950 6951 u8 syndrome[0x20]; 6952 6953 u8 reserved_at_40[0x40]; 6954 }; 6955 6956 struct mlx5_ifc_modify_tis_bitmask_bits { 6957 u8 reserved_at_0[0x20]; 6958 6959 u8 reserved_at_20[0x1d]; 6960 u8 lag_tx_port_affinity[0x1]; 6961 u8 strict_lag_tx_port_affinity[0x1]; 6962 u8 prio[0x1]; 6963 }; 6964 6965 struct mlx5_ifc_modify_tis_in_bits { 6966 u8 opcode[0x10]; 6967 u8 uid[0x10]; 6968 6969 u8 reserved_at_20[0x10]; 6970 u8 op_mod[0x10]; 6971 6972 u8 reserved_at_40[0x8]; 6973 u8 tisn[0x18]; 6974 6975 u8 reserved_at_60[0x20]; 6976 6977 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6978 6979 u8 reserved_at_c0[0x40]; 6980 6981 struct mlx5_ifc_tisc_bits ctx; 6982 }; 6983 6984 struct mlx5_ifc_modify_tir_bitmask_bits { 6985 u8 reserved_at_0[0x20]; 6986 6987 u8 reserved_at_20[0x1b]; 6988 u8 self_lb_en[0x1]; 6989 u8 reserved_at_3c[0x1]; 6990 u8 hash[0x1]; 6991 u8 reserved_at_3e[0x1]; 6992 u8 packet_merge[0x1]; 6993 }; 6994 6995 struct mlx5_ifc_modify_tir_out_bits { 6996 u8 status[0x8]; 6997 u8 reserved_at_8[0x18]; 6998 6999 u8 syndrome[0x20]; 7000 7001 u8 reserved_at_40[0x40]; 7002 }; 7003 7004 struct mlx5_ifc_modify_tir_in_bits { 7005 u8 opcode[0x10]; 7006 u8 uid[0x10]; 7007 7008 u8 reserved_at_20[0x10]; 7009 u8 op_mod[0x10]; 7010 7011 u8 reserved_at_40[0x8]; 7012 u8 tirn[0x18]; 7013 7014 u8 reserved_at_60[0x20]; 7015 7016 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7017 7018 u8 reserved_at_c0[0x40]; 7019 7020 struct mlx5_ifc_tirc_bits ctx; 7021 }; 7022 7023 struct mlx5_ifc_modify_sq_out_bits { 7024 u8 status[0x8]; 7025 u8 reserved_at_8[0x18]; 7026 7027 u8 syndrome[0x20]; 7028 7029 u8 reserved_at_40[0x40]; 7030 }; 7031 7032 struct mlx5_ifc_modify_sq_in_bits { 7033 u8 opcode[0x10]; 7034 u8 uid[0x10]; 7035 7036 u8 reserved_at_20[0x10]; 7037 u8 op_mod[0x10]; 7038 7039 u8 sq_state[0x4]; 7040 u8 reserved_at_44[0x4]; 7041 u8 sqn[0x18]; 7042 7043 u8 reserved_at_60[0x20]; 7044 7045 u8 modify_bitmask[0x40]; 7046 7047 u8 reserved_at_c0[0x40]; 7048 7049 struct mlx5_ifc_sqc_bits ctx; 7050 }; 7051 7052 struct mlx5_ifc_modify_scheduling_element_out_bits { 7053 u8 status[0x8]; 7054 u8 reserved_at_8[0x18]; 7055 7056 u8 syndrome[0x20]; 7057 7058 u8 reserved_at_40[0x1c0]; 7059 }; 7060 7061 enum { 7062 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7063 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7064 }; 7065 7066 struct mlx5_ifc_modify_scheduling_element_in_bits { 7067 u8 opcode[0x10]; 7068 u8 reserved_at_10[0x10]; 7069 7070 u8 reserved_at_20[0x10]; 7071 u8 op_mod[0x10]; 7072 7073 u8 scheduling_hierarchy[0x8]; 7074 u8 reserved_at_48[0x18]; 7075 7076 u8 scheduling_element_id[0x20]; 7077 7078 u8 reserved_at_80[0x20]; 7079 7080 u8 modify_bitmask[0x20]; 7081 7082 u8 reserved_at_c0[0x40]; 7083 7084 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7085 7086 u8 reserved_at_300[0x100]; 7087 }; 7088 7089 struct mlx5_ifc_modify_rqt_out_bits { 7090 u8 status[0x8]; 7091 u8 reserved_at_8[0x18]; 7092 7093 u8 syndrome[0x20]; 7094 7095 u8 reserved_at_40[0x40]; 7096 }; 7097 7098 struct mlx5_ifc_rqt_bitmask_bits { 7099 u8 reserved_at_0[0x20]; 7100 7101 u8 reserved_at_20[0x1f]; 7102 u8 rqn_list[0x1]; 7103 }; 7104 7105 struct mlx5_ifc_modify_rqt_in_bits { 7106 u8 opcode[0x10]; 7107 u8 uid[0x10]; 7108 7109 u8 reserved_at_20[0x10]; 7110 u8 op_mod[0x10]; 7111 7112 u8 reserved_at_40[0x8]; 7113 u8 rqtn[0x18]; 7114 7115 u8 reserved_at_60[0x20]; 7116 7117 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7118 7119 u8 reserved_at_c0[0x40]; 7120 7121 struct mlx5_ifc_rqtc_bits ctx; 7122 }; 7123 7124 struct mlx5_ifc_modify_rq_out_bits { 7125 u8 status[0x8]; 7126 u8 reserved_at_8[0x18]; 7127 7128 u8 syndrome[0x20]; 7129 7130 u8 reserved_at_40[0x40]; 7131 }; 7132 7133 enum { 7134 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7135 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7136 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7137 }; 7138 7139 struct mlx5_ifc_modify_rq_in_bits { 7140 u8 opcode[0x10]; 7141 u8 uid[0x10]; 7142 7143 u8 reserved_at_20[0x10]; 7144 u8 op_mod[0x10]; 7145 7146 u8 rq_state[0x4]; 7147 u8 reserved_at_44[0x4]; 7148 u8 rqn[0x18]; 7149 7150 u8 reserved_at_60[0x20]; 7151 7152 u8 modify_bitmask[0x40]; 7153 7154 u8 reserved_at_c0[0x40]; 7155 7156 struct mlx5_ifc_rqc_bits ctx; 7157 }; 7158 7159 struct mlx5_ifc_modify_rmp_out_bits { 7160 u8 status[0x8]; 7161 u8 reserved_at_8[0x18]; 7162 7163 u8 syndrome[0x20]; 7164 7165 u8 reserved_at_40[0x40]; 7166 }; 7167 7168 struct mlx5_ifc_rmp_bitmask_bits { 7169 u8 reserved_at_0[0x20]; 7170 7171 u8 reserved_at_20[0x1f]; 7172 u8 lwm[0x1]; 7173 }; 7174 7175 struct mlx5_ifc_modify_rmp_in_bits { 7176 u8 opcode[0x10]; 7177 u8 uid[0x10]; 7178 7179 u8 reserved_at_20[0x10]; 7180 u8 op_mod[0x10]; 7181 7182 u8 rmp_state[0x4]; 7183 u8 reserved_at_44[0x4]; 7184 u8 rmpn[0x18]; 7185 7186 u8 reserved_at_60[0x20]; 7187 7188 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7189 7190 u8 reserved_at_c0[0x40]; 7191 7192 struct mlx5_ifc_rmpc_bits ctx; 7193 }; 7194 7195 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7196 u8 status[0x8]; 7197 u8 reserved_at_8[0x18]; 7198 7199 u8 syndrome[0x20]; 7200 7201 u8 reserved_at_40[0x40]; 7202 }; 7203 7204 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7205 u8 reserved_at_0[0x12]; 7206 u8 affiliation[0x1]; 7207 u8 reserved_at_13[0x1]; 7208 u8 disable_uc_local_lb[0x1]; 7209 u8 disable_mc_local_lb[0x1]; 7210 u8 node_guid[0x1]; 7211 u8 port_guid[0x1]; 7212 u8 min_inline[0x1]; 7213 u8 mtu[0x1]; 7214 u8 change_event[0x1]; 7215 u8 promisc[0x1]; 7216 u8 permanent_address[0x1]; 7217 u8 addresses_list[0x1]; 7218 u8 roce_en[0x1]; 7219 u8 reserved_at_1f[0x1]; 7220 }; 7221 7222 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7223 u8 opcode[0x10]; 7224 u8 reserved_at_10[0x10]; 7225 7226 u8 reserved_at_20[0x10]; 7227 u8 op_mod[0x10]; 7228 7229 u8 other_vport[0x1]; 7230 u8 reserved_at_41[0xf]; 7231 u8 vport_number[0x10]; 7232 7233 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7234 7235 u8 reserved_at_80[0x780]; 7236 7237 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7238 }; 7239 7240 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7241 u8 status[0x8]; 7242 u8 reserved_at_8[0x18]; 7243 7244 u8 syndrome[0x20]; 7245 7246 u8 reserved_at_40[0x40]; 7247 }; 7248 7249 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7250 u8 opcode[0x10]; 7251 u8 reserved_at_10[0x10]; 7252 7253 u8 reserved_at_20[0x10]; 7254 u8 op_mod[0x10]; 7255 7256 u8 other_vport[0x1]; 7257 u8 reserved_at_41[0xb]; 7258 u8 port_num[0x4]; 7259 u8 vport_number[0x10]; 7260 7261 u8 reserved_at_60[0x20]; 7262 7263 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7264 }; 7265 7266 struct mlx5_ifc_modify_cq_out_bits { 7267 u8 status[0x8]; 7268 u8 reserved_at_8[0x18]; 7269 7270 u8 syndrome[0x20]; 7271 7272 u8 reserved_at_40[0x40]; 7273 }; 7274 7275 enum { 7276 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7277 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7278 }; 7279 7280 struct mlx5_ifc_modify_cq_in_bits { 7281 u8 opcode[0x10]; 7282 u8 uid[0x10]; 7283 7284 u8 reserved_at_20[0x10]; 7285 u8 op_mod[0x10]; 7286 7287 u8 reserved_at_40[0x8]; 7288 u8 cqn[0x18]; 7289 7290 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7291 7292 struct mlx5_ifc_cqc_bits cq_context; 7293 7294 u8 reserved_at_280[0x60]; 7295 7296 u8 cq_umem_valid[0x1]; 7297 u8 reserved_at_2e1[0x1f]; 7298 7299 u8 reserved_at_300[0x580]; 7300 7301 u8 pas[][0x40]; 7302 }; 7303 7304 struct mlx5_ifc_modify_cong_status_out_bits { 7305 u8 status[0x8]; 7306 u8 reserved_at_8[0x18]; 7307 7308 u8 syndrome[0x20]; 7309 7310 u8 reserved_at_40[0x40]; 7311 }; 7312 7313 struct mlx5_ifc_modify_cong_status_in_bits { 7314 u8 opcode[0x10]; 7315 u8 reserved_at_10[0x10]; 7316 7317 u8 reserved_at_20[0x10]; 7318 u8 op_mod[0x10]; 7319 7320 u8 reserved_at_40[0x18]; 7321 u8 priority[0x4]; 7322 u8 cong_protocol[0x4]; 7323 7324 u8 enable[0x1]; 7325 u8 tag_enable[0x1]; 7326 u8 reserved_at_62[0x1e]; 7327 }; 7328 7329 struct mlx5_ifc_modify_cong_params_out_bits { 7330 u8 status[0x8]; 7331 u8 reserved_at_8[0x18]; 7332 7333 u8 syndrome[0x20]; 7334 7335 u8 reserved_at_40[0x40]; 7336 }; 7337 7338 struct mlx5_ifc_modify_cong_params_in_bits { 7339 u8 opcode[0x10]; 7340 u8 reserved_at_10[0x10]; 7341 7342 u8 reserved_at_20[0x10]; 7343 u8 op_mod[0x10]; 7344 7345 u8 reserved_at_40[0x1c]; 7346 u8 cong_protocol[0x4]; 7347 7348 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7349 7350 u8 reserved_at_80[0x80]; 7351 7352 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7353 }; 7354 7355 struct mlx5_ifc_manage_pages_out_bits { 7356 u8 status[0x8]; 7357 u8 reserved_at_8[0x18]; 7358 7359 u8 syndrome[0x20]; 7360 7361 u8 output_num_entries[0x20]; 7362 7363 u8 reserved_at_60[0x20]; 7364 7365 u8 pas[][0x40]; 7366 }; 7367 7368 enum { 7369 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7370 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7371 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7372 }; 7373 7374 struct mlx5_ifc_manage_pages_in_bits { 7375 u8 opcode[0x10]; 7376 u8 reserved_at_10[0x10]; 7377 7378 u8 reserved_at_20[0x10]; 7379 u8 op_mod[0x10]; 7380 7381 u8 embedded_cpu_function[0x1]; 7382 u8 reserved_at_41[0xf]; 7383 u8 function_id[0x10]; 7384 7385 u8 input_num_entries[0x20]; 7386 7387 u8 pas[][0x40]; 7388 }; 7389 7390 struct mlx5_ifc_mad_ifc_out_bits { 7391 u8 status[0x8]; 7392 u8 reserved_at_8[0x18]; 7393 7394 u8 syndrome[0x20]; 7395 7396 u8 reserved_at_40[0x40]; 7397 7398 u8 response_mad_packet[256][0x8]; 7399 }; 7400 7401 struct mlx5_ifc_mad_ifc_in_bits { 7402 u8 opcode[0x10]; 7403 u8 reserved_at_10[0x10]; 7404 7405 u8 reserved_at_20[0x10]; 7406 u8 op_mod[0x10]; 7407 7408 u8 remote_lid[0x10]; 7409 u8 reserved_at_50[0x8]; 7410 u8 port[0x8]; 7411 7412 u8 reserved_at_60[0x20]; 7413 7414 u8 mad[256][0x8]; 7415 }; 7416 7417 struct mlx5_ifc_init_hca_out_bits { 7418 u8 status[0x8]; 7419 u8 reserved_at_8[0x18]; 7420 7421 u8 syndrome[0x20]; 7422 7423 u8 reserved_at_40[0x40]; 7424 }; 7425 7426 struct mlx5_ifc_init_hca_in_bits { 7427 u8 opcode[0x10]; 7428 u8 reserved_at_10[0x10]; 7429 7430 u8 reserved_at_20[0x10]; 7431 u8 op_mod[0x10]; 7432 7433 u8 reserved_at_40[0x20]; 7434 7435 u8 reserved_at_60[0x2]; 7436 u8 sw_vhca_id[0xe]; 7437 u8 reserved_at_70[0x10]; 7438 7439 u8 sw_owner_id[4][0x20]; 7440 }; 7441 7442 struct mlx5_ifc_init2rtr_qp_out_bits { 7443 u8 status[0x8]; 7444 u8 reserved_at_8[0x18]; 7445 7446 u8 syndrome[0x20]; 7447 7448 u8 reserved_at_40[0x20]; 7449 u8 ece[0x20]; 7450 }; 7451 7452 struct mlx5_ifc_init2rtr_qp_in_bits { 7453 u8 opcode[0x10]; 7454 u8 uid[0x10]; 7455 7456 u8 reserved_at_20[0x10]; 7457 u8 op_mod[0x10]; 7458 7459 u8 reserved_at_40[0x8]; 7460 u8 qpn[0x18]; 7461 7462 u8 reserved_at_60[0x20]; 7463 7464 u8 opt_param_mask[0x20]; 7465 7466 u8 ece[0x20]; 7467 7468 struct mlx5_ifc_qpc_bits qpc; 7469 7470 u8 reserved_at_800[0x80]; 7471 }; 7472 7473 struct mlx5_ifc_init2init_qp_out_bits { 7474 u8 status[0x8]; 7475 u8 reserved_at_8[0x18]; 7476 7477 u8 syndrome[0x20]; 7478 7479 u8 reserved_at_40[0x20]; 7480 u8 ece[0x20]; 7481 }; 7482 7483 struct mlx5_ifc_init2init_qp_in_bits { 7484 u8 opcode[0x10]; 7485 u8 uid[0x10]; 7486 7487 u8 reserved_at_20[0x10]; 7488 u8 op_mod[0x10]; 7489 7490 u8 reserved_at_40[0x8]; 7491 u8 qpn[0x18]; 7492 7493 u8 reserved_at_60[0x20]; 7494 7495 u8 opt_param_mask[0x20]; 7496 7497 u8 ece[0x20]; 7498 7499 struct mlx5_ifc_qpc_bits qpc; 7500 7501 u8 reserved_at_800[0x80]; 7502 }; 7503 7504 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7505 u8 status[0x8]; 7506 u8 reserved_at_8[0x18]; 7507 7508 u8 syndrome[0x20]; 7509 7510 u8 reserved_at_40[0x40]; 7511 7512 u8 packet_headers_log[128][0x8]; 7513 7514 u8 packet_syndrome[64][0x8]; 7515 }; 7516 7517 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7518 u8 opcode[0x10]; 7519 u8 reserved_at_10[0x10]; 7520 7521 u8 reserved_at_20[0x10]; 7522 u8 op_mod[0x10]; 7523 7524 u8 reserved_at_40[0x40]; 7525 }; 7526 7527 struct mlx5_ifc_gen_eqe_in_bits { 7528 u8 opcode[0x10]; 7529 u8 reserved_at_10[0x10]; 7530 7531 u8 reserved_at_20[0x10]; 7532 u8 op_mod[0x10]; 7533 7534 u8 reserved_at_40[0x18]; 7535 u8 eq_number[0x8]; 7536 7537 u8 reserved_at_60[0x20]; 7538 7539 u8 eqe[64][0x8]; 7540 }; 7541 7542 struct mlx5_ifc_gen_eq_out_bits { 7543 u8 status[0x8]; 7544 u8 reserved_at_8[0x18]; 7545 7546 u8 syndrome[0x20]; 7547 7548 u8 reserved_at_40[0x40]; 7549 }; 7550 7551 struct mlx5_ifc_enable_hca_out_bits { 7552 u8 status[0x8]; 7553 u8 reserved_at_8[0x18]; 7554 7555 u8 syndrome[0x20]; 7556 7557 u8 reserved_at_40[0x20]; 7558 }; 7559 7560 struct mlx5_ifc_enable_hca_in_bits { 7561 u8 opcode[0x10]; 7562 u8 reserved_at_10[0x10]; 7563 7564 u8 reserved_at_20[0x10]; 7565 u8 op_mod[0x10]; 7566 7567 u8 embedded_cpu_function[0x1]; 7568 u8 reserved_at_41[0xf]; 7569 u8 function_id[0x10]; 7570 7571 u8 reserved_at_60[0x20]; 7572 }; 7573 7574 struct mlx5_ifc_drain_dct_out_bits { 7575 u8 status[0x8]; 7576 u8 reserved_at_8[0x18]; 7577 7578 u8 syndrome[0x20]; 7579 7580 u8 reserved_at_40[0x40]; 7581 }; 7582 7583 struct mlx5_ifc_drain_dct_in_bits { 7584 u8 opcode[0x10]; 7585 u8 uid[0x10]; 7586 7587 u8 reserved_at_20[0x10]; 7588 u8 op_mod[0x10]; 7589 7590 u8 reserved_at_40[0x8]; 7591 u8 dctn[0x18]; 7592 7593 u8 reserved_at_60[0x20]; 7594 }; 7595 7596 struct mlx5_ifc_disable_hca_out_bits { 7597 u8 status[0x8]; 7598 u8 reserved_at_8[0x18]; 7599 7600 u8 syndrome[0x20]; 7601 7602 u8 reserved_at_40[0x20]; 7603 }; 7604 7605 struct mlx5_ifc_disable_hca_in_bits { 7606 u8 opcode[0x10]; 7607 u8 reserved_at_10[0x10]; 7608 7609 u8 reserved_at_20[0x10]; 7610 u8 op_mod[0x10]; 7611 7612 u8 embedded_cpu_function[0x1]; 7613 u8 reserved_at_41[0xf]; 7614 u8 function_id[0x10]; 7615 7616 u8 reserved_at_60[0x20]; 7617 }; 7618 7619 struct mlx5_ifc_detach_from_mcg_out_bits { 7620 u8 status[0x8]; 7621 u8 reserved_at_8[0x18]; 7622 7623 u8 syndrome[0x20]; 7624 7625 u8 reserved_at_40[0x40]; 7626 }; 7627 7628 struct mlx5_ifc_detach_from_mcg_in_bits { 7629 u8 opcode[0x10]; 7630 u8 uid[0x10]; 7631 7632 u8 reserved_at_20[0x10]; 7633 u8 op_mod[0x10]; 7634 7635 u8 reserved_at_40[0x8]; 7636 u8 qpn[0x18]; 7637 7638 u8 reserved_at_60[0x20]; 7639 7640 u8 multicast_gid[16][0x8]; 7641 }; 7642 7643 struct mlx5_ifc_destroy_xrq_out_bits { 7644 u8 status[0x8]; 7645 u8 reserved_at_8[0x18]; 7646 7647 u8 syndrome[0x20]; 7648 7649 u8 reserved_at_40[0x40]; 7650 }; 7651 7652 struct mlx5_ifc_destroy_xrq_in_bits { 7653 u8 opcode[0x10]; 7654 u8 uid[0x10]; 7655 7656 u8 reserved_at_20[0x10]; 7657 u8 op_mod[0x10]; 7658 7659 u8 reserved_at_40[0x8]; 7660 u8 xrqn[0x18]; 7661 7662 u8 reserved_at_60[0x20]; 7663 }; 7664 7665 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7666 u8 status[0x8]; 7667 u8 reserved_at_8[0x18]; 7668 7669 u8 syndrome[0x20]; 7670 7671 u8 reserved_at_40[0x40]; 7672 }; 7673 7674 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7675 u8 opcode[0x10]; 7676 u8 uid[0x10]; 7677 7678 u8 reserved_at_20[0x10]; 7679 u8 op_mod[0x10]; 7680 7681 u8 reserved_at_40[0x8]; 7682 u8 xrc_srqn[0x18]; 7683 7684 u8 reserved_at_60[0x20]; 7685 }; 7686 7687 struct mlx5_ifc_destroy_tis_out_bits { 7688 u8 status[0x8]; 7689 u8 reserved_at_8[0x18]; 7690 7691 u8 syndrome[0x20]; 7692 7693 u8 reserved_at_40[0x40]; 7694 }; 7695 7696 struct mlx5_ifc_destroy_tis_in_bits { 7697 u8 opcode[0x10]; 7698 u8 uid[0x10]; 7699 7700 u8 reserved_at_20[0x10]; 7701 u8 op_mod[0x10]; 7702 7703 u8 reserved_at_40[0x8]; 7704 u8 tisn[0x18]; 7705 7706 u8 reserved_at_60[0x20]; 7707 }; 7708 7709 struct mlx5_ifc_destroy_tir_out_bits { 7710 u8 status[0x8]; 7711 u8 reserved_at_8[0x18]; 7712 7713 u8 syndrome[0x20]; 7714 7715 u8 reserved_at_40[0x40]; 7716 }; 7717 7718 struct mlx5_ifc_destroy_tir_in_bits { 7719 u8 opcode[0x10]; 7720 u8 uid[0x10]; 7721 7722 u8 reserved_at_20[0x10]; 7723 u8 op_mod[0x10]; 7724 7725 u8 reserved_at_40[0x8]; 7726 u8 tirn[0x18]; 7727 7728 u8 reserved_at_60[0x20]; 7729 }; 7730 7731 struct mlx5_ifc_destroy_srq_out_bits { 7732 u8 status[0x8]; 7733 u8 reserved_at_8[0x18]; 7734 7735 u8 syndrome[0x20]; 7736 7737 u8 reserved_at_40[0x40]; 7738 }; 7739 7740 struct mlx5_ifc_destroy_srq_in_bits { 7741 u8 opcode[0x10]; 7742 u8 uid[0x10]; 7743 7744 u8 reserved_at_20[0x10]; 7745 u8 op_mod[0x10]; 7746 7747 u8 reserved_at_40[0x8]; 7748 u8 srqn[0x18]; 7749 7750 u8 reserved_at_60[0x20]; 7751 }; 7752 7753 struct mlx5_ifc_destroy_sq_out_bits { 7754 u8 status[0x8]; 7755 u8 reserved_at_8[0x18]; 7756 7757 u8 syndrome[0x20]; 7758 7759 u8 reserved_at_40[0x40]; 7760 }; 7761 7762 struct mlx5_ifc_destroy_sq_in_bits { 7763 u8 opcode[0x10]; 7764 u8 uid[0x10]; 7765 7766 u8 reserved_at_20[0x10]; 7767 u8 op_mod[0x10]; 7768 7769 u8 reserved_at_40[0x8]; 7770 u8 sqn[0x18]; 7771 7772 u8 reserved_at_60[0x20]; 7773 }; 7774 7775 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7776 u8 status[0x8]; 7777 u8 reserved_at_8[0x18]; 7778 7779 u8 syndrome[0x20]; 7780 7781 u8 reserved_at_40[0x1c0]; 7782 }; 7783 7784 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7785 u8 opcode[0x10]; 7786 u8 reserved_at_10[0x10]; 7787 7788 u8 reserved_at_20[0x10]; 7789 u8 op_mod[0x10]; 7790 7791 u8 scheduling_hierarchy[0x8]; 7792 u8 reserved_at_48[0x18]; 7793 7794 u8 scheduling_element_id[0x20]; 7795 7796 u8 reserved_at_80[0x180]; 7797 }; 7798 7799 struct mlx5_ifc_destroy_rqt_out_bits { 7800 u8 status[0x8]; 7801 u8 reserved_at_8[0x18]; 7802 7803 u8 syndrome[0x20]; 7804 7805 u8 reserved_at_40[0x40]; 7806 }; 7807 7808 struct mlx5_ifc_destroy_rqt_in_bits { 7809 u8 opcode[0x10]; 7810 u8 uid[0x10]; 7811 7812 u8 reserved_at_20[0x10]; 7813 u8 op_mod[0x10]; 7814 7815 u8 reserved_at_40[0x8]; 7816 u8 rqtn[0x18]; 7817 7818 u8 reserved_at_60[0x20]; 7819 }; 7820 7821 struct mlx5_ifc_destroy_rq_out_bits { 7822 u8 status[0x8]; 7823 u8 reserved_at_8[0x18]; 7824 7825 u8 syndrome[0x20]; 7826 7827 u8 reserved_at_40[0x40]; 7828 }; 7829 7830 struct mlx5_ifc_destroy_rq_in_bits { 7831 u8 opcode[0x10]; 7832 u8 uid[0x10]; 7833 7834 u8 reserved_at_20[0x10]; 7835 u8 op_mod[0x10]; 7836 7837 u8 reserved_at_40[0x8]; 7838 u8 rqn[0x18]; 7839 7840 u8 reserved_at_60[0x20]; 7841 }; 7842 7843 struct mlx5_ifc_set_delay_drop_params_in_bits { 7844 u8 opcode[0x10]; 7845 u8 reserved_at_10[0x10]; 7846 7847 u8 reserved_at_20[0x10]; 7848 u8 op_mod[0x10]; 7849 7850 u8 reserved_at_40[0x20]; 7851 7852 u8 reserved_at_60[0x10]; 7853 u8 delay_drop_timeout[0x10]; 7854 }; 7855 7856 struct mlx5_ifc_set_delay_drop_params_out_bits { 7857 u8 status[0x8]; 7858 u8 reserved_at_8[0x18]; 7859 7860 u8 syndrome[0x20]; 7861 7862 u8 reserved_at_40[0x40]; 7863 }; 7864 7865 struct mlx5_ifc_destroy_rmp_out_bits { 7866 u8 status[0x8]; 7867 u8 reserved_at_8[0x18]; 7868 7869 u8 syndrome[0x20]; 7870 7871 u8 reserved_at_40[0x40]; 7872 }; 7873 7874 struct mlx5_ifc_destroy_rmp_in_bits { 7875 u8 opcode[0x10]; 7876 u8 uid[0x10]; 7877 7878 u8 reserved_at_20[0x10]; 7879 u8 op_mod[0x10]; 7880 7881 u8 reserved_at_40[0x8]; 7882 u8 rmpn[0x18]; 7883 7884 u8 reserved_at_60[0x20]; 7885 }; 7886 7887 struct mlx5_ifc_destroy_qp_out_bits { 7888 u8 status[0x8]; 7889 u8 reserved_at_8[0x18]; 7890 7891 u8 syndrome[0x20]; 7892 7893 u8 reserved_at_40[0x40]; 7894 }; 7895 7896 struct mlx5_ifc_destroy_qp_in_bits { 7897 u8 opcode[0x10]; 7898 u8 uid[0x10]; 7899 7900 u8 reserved_at_20[0x10]; 7901 u8 op_mod[0x10]; 7902 7903 u8 reserved_at_40[0x8]; 7904 u8 qpn[0x18]; 7905 7906 u8 reserved_at_60[0x20]; 7907 }; 7908 7909 struct mlx5_ifc_destroy_psv_out_bits { 7910 u8 status[0x8]; 7911 u8 reserved_at_8[0x18]; 7912 7913 u8 syndrome[0x20]; 7914 7915 u8 reserved_at_40[0x40]; 7916 }; 7917 7918 struct mlx5_ifc_destroy_psv_in_bits { 7919 u8 opcode[0x10]; 7920 u8 reserved_at_10[0x10]; 7921 7922 u8 reserved_at_20[0x10]; 7923 u8 op_mod[0x10]; 7924 7925 u8 reserved_at_40[0x8]; 7926 u8 psvn[0x18]; 7927 7928 u8 reserved_at_60[0x20]; 7929 }; 7930 7931 struct mlx5_ifc_destroy_mkey_out_bits { 7932 u8 status[0x8]; 7933 u8 reserved_at_8[0x18]; 7934 7935 u8 syndrome[0x20]; 7936 7937 u8 reserved_at_40[0x40]; 7938 }; 7939 7940 struct mlx5_ifc_destroy_mkey_in_bits { 7941 u8 opcode[0x10]; 7942 u8 uid[0x10]; 7943 7944 u8 reserved_at_20[0x10]; 7945 u8 op_mod[0x10]; 7946 7947 u8 reserved_at_40[0x8]; 7948 u8 mkey_index[0x18]; 7949 7950 u8 reserved_at_60[0x20]; 7951 }; 7952 7953 struct mlx5_ifc_destroy_flow_table_out_bits { 7954 u8 status[0x8]; 7955 u8 reserved_at_8[0x18]; 7956 7957 u8 syndrome[0x20]; 7958 7959 u8 reserved_at_40[0x40]; 7960 }; 7961 7962 struct mlx5_ifc_destroy_flow_table_in_bits { 7963 u8 opcode[0x10]; 7964 u8 reserved_at_10[0x10]; 7965 7966 u8 reserved_at_20[0x10]; 7967 u8 op_mod[0x10]; 7968 7969 u8 other_vport[0x1]; 7970 u8 reserved_at_41[0xf]; 7971 u8 vport_number[0x10]; 7972 7973 u8 reserved_at_60[0x20]; 7974 7975 u8 table_type[0x8]; 7976 u8 reserved_at_88[0x18]; 7977 7978 u8 reserved_at_a0[0x8]; 7979 u8 table_id[0x18]; 7980 7981 u8 reserved_at_c0[0x140]; 7982 }; 7983 7984 struct mlx5_ifc_destroy_flow_group_out_bits { 7985 u8 status[0x8]; 7986 u8 reserved_at_8[0x18]; 7987 7988 u8 syndrome[0x20]; 7989 7990 u8 reserved_at_40[0x40]; 7991 }; 7992 7993 struct mlx5_ifc_destroy_flow_group_in_bits { 7994 u8 opcode[0x10]; 7995 u8 reserved_at_10[0x10]; 7996 7997 u8 reserved_at_20[0x10]; 7998 u8 op_mod[0x10]; 7999 8000 u8 other_vport[0x1]; 8001 u8 reserved_at_41[0xf]; 8002 u8 vport_number[0x10]; 8003 8004 u8 reserved_at_60[0x20]; 8005 8006 u8 table_type[0x8]; 8007 u8 reserved_at_88[0x18]; 8008 8009 u8 reserved_at_a0[0x8]; 8010 u8 table_id[0x18]; 8011 8012 u8 group_id[0x20]; 8013 8014 u8 reserved_at_e0[0x120]; 8015 }; 8016 8017 struct mlx5_ifc_destroy_eq_out_bits { 8018 u8 status[0x8]; 8019 u8 reserved_at_8[0x18]; 8020 8021 u8 syndrome[0x20]; 8022 8023 u8 reserved_at_40[0x40]; 8024 }; 8025 8026 struct mlx5_ifc_destroy_eq_in_bits { 8027 u8 opcode[0x10]; 8028 u8 reserved_at_10[0x10]; 8029 8030 u8 reserved_at_20[0x10]; 8031 u8 op_mod[0x10]; 8032 8033 u8 reserved_at_40[0x18]; 8034 u8 eq_number[0x8]; 8035 8036 u8 reserved_at_60[0x20]; 8037 }; 8038 8039 struct mlx5_ifc_destroy_dct_out_bits { 8040 u8 status[0x8]; 8041 u8 reserved_at_8[0x18]; 8042 8043 u8 syndrome[0x20]; 8044 8045 u8 reserved_at_40[0x40]; 8046 }; 8047 8048 struct mlx5_ifc_destroy_dct_in_bits { 8049 u8 opcode[0x10]; 8050 u8 uid[0x10]; 8051 8052 u8 reserved_at_20[0x10]; 8053 u8 op_mod[0x10]; 8054 8055 u8 reserved_at_40[0x8]; 8056 u8 dctn[0x18]; 8057 8058 u8 reserved_at_60[0x20]; 8059 }; 8060 8061 struct mlx5_ifc_destroy_cq_out_bits { 8062 u8 status[0x8]; 8063 u8 reserved_at_8[0x18]; 8064 8065 u8 syndrome[0x20]; 8066 8067 u8 reserved_at_40[0x40]; 8068 }; 8069 8070 struct mlx5_ifc_destroy_cq_in_bits { 8071 u8 opcode[0x10]; 8072 u8 uid[0x10]; 8073 8074 u8 reserved_at_20[0x10]; 8075 u8 op_mod[0x10]; 8076 8077 u8 reserved_at_40[0x8]; 8078 u8 cqn[0x18]; 8079 8080 u8 reserved_at_60[0x20]; 8081 }; 8082 8083 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8084 u8 status[0x8]; 8085 u8 reserved_at_8[0x18]; 8086 8087 u8 syndrome[0x20]; 8088 8089 u8 reserved_at_40[0x40]; 8090 }; 8091 8092 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8093 u8 opcode[0x10]; 8094 u8 reserved_at_10[0x10]; 8095 8096 u8 reserved_at_20[0x10]; 8097 u8 op_mod[0x10]; 8098 8099 u8 reserved_at_40[0x20]; 8100 8101 u8 reserved_at_60[0x10]; 8102 u8 vxlan_udp_port[0x10]; 8103 }; 8104 8105 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8106 u8 status[0x8]; 8107 u8 reserved_at_8[0x18]; 8108 8109 u8 syndrome[0x20]; 8110 8111 u8 reserved_at_40[0x40]; 8112 }; 8113 8114 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8115 u8 opcode[0x10]; 8116 u8 reserved_at_10[0x10]; 8117 8118 u8 reserved_at_20[0x10]; 8119 u8 op_mod[0x10]; 8120 8121 u8 reserved_at_40[0x60]; 8122 8123 u8 reserved_at_a0[0x8]; 8124 u8 table_index[0x18]; 8125 8126 u8 reserved_at_c0[0x140]; 8127 }; 8128 8129 struct mlx5_ifc_delete_fte_out_bits { 8130 u8 status[0x8]; 8131 u8 reserved_at_8[0x18]; 8132 8133 u8 syndrome[0x20]; 8134 8135 u8 reserved_at_40[0x40]; 8136 }; 8137 8138 struct mlx5_ifc_delete_fte_in_bits { 8139 u8 opcode[0x10]; 8140 u8 reserved_at_10[0x10]; 8141 8142 u8 reserved_at_20[0x10]; 8143 u8 op_mod[0x10]; 8144 8145 u8 other_vport[0x1]; 8146 u8 reserved_at_41[0xf]; 8147 u8 vport_number[0x10]; 8148 8149 u8 reserved_at_60[0x20]; 8150 8151 u8 table_type[0x8]; 8152 u8 reserved_at_88[0x18]; 8153 8154 u8 reserved_at_a0[0x8]; 8155 u8 table_id[0x18]; 8156 8157 u8 reserved_at_c0[0x40]; 8158 8159 u8 flow_index[0x20]; 8160 8161 u8 reserved_at_120[0xe0]; 8162 }; 8163 8164 struct mlx5_ifc_dealloc_xrcd_out_bits { 8165 u8 status[0x8]; 8166 u8 reserved_at_8[0x18]; 8167 8168 u8 syndrome[0x20]; 8169 8170 u8 reserved_at_40[0x40]; 8171 }; 8172 8173 struct mlx5_ifc_dealloc_xrcd_in_bits { 8174 u8 opcode[0x10]; 8175 u8 uid[0x10]; 8176 8177 u8 reserved_at_20[0x10]; 8178 u8 op_mod[0x10]; 8179 8180 u8 reserved_at_40[0x8]; 8181 u8 xrcd[0x18]; 8182 8183 u8 reserved_at_60[0x20]; 8184 }; 8185 8186 struct mlx5_ifc_dealloc_uar_out_bits { 8187 u8 status[0x8]; 8188 u8 reserved_at_8[0x18]; 8189 8190 u8 syndrome[0x20]; 8191 8192 u8 reserved_at_40[0x40]; 8193 }; 8194 8195 struct mlx5_ifc_dealloc_uar_in_bits { 8196 u8 opcode[0x10]; 8197 u8 uid[0x10]; 8198 8199 u8 reserved_at_20[0x10]; 8200 u8 op_mod[0x10]; 8201 8202 u8 reserved_at_40[0x8]; 8203 u8 uar[0x18]; 8204 8205 u8 reserved_at_60[0x20]; 8206 }; 8207 8208 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8209 u8 status[0x8]; 8210 u8 reserved_at_8[0x18]; 8211 8212 u8 syndrome[0x20]; 8213 8214 u8 reserved_at_40[0x40]; 8215 }; 8216 8217 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8218 u8 opcode[0x10]; 8219 u8 uid[0x10]; 8220 8221 u8 reserved_at_20[0x10]; 8222 u8 op_mod[0x10]; 8223 8224 u8 reserved_at_40[0x8]; 8225 u8 transport_domain[0x18]; 8226 8227 u8 reserved_at_60[0x20]; 8228 }; 8229 8230 struct mlx5_ifc_dealloc_q_counter_out_bits { 8231 u8 status[0x8]; 8232 u8 reserved_at_8[0x18]; 8233 8234 u8 syndrome[0x20]; 8235 8236 u8 reserved_at_40[0x40]; 8237 }; 8238 8239 struct mlx5_ifc_dealloc_q_counter_in_bits { 8240 u8 opcode[0x10]; 8241 u8 reserved_at_10[0x10]; 8242 8243 u8 reserved_at_20[0x10]; 8244 u8 op_mod[0x10]; 8245 8246 u8 reserved_at_40[0x18]; 8247 u8 counter_set_id[0x8]; 8248 8249 u8 reserved_at_60[0x20]; 8250 }; 8251 8252 struct mlx5_ifc_dealloc_pd_out_bits { 8253 u8 status[0x8]; 8254 u8 reserved_at_8[0x18]; 8255 8256 u8 syndrome[0x20]; 8257 8258 u8 reserved_at_40[0x40]; 8259 }; 8260 8261 struct mlx5_ifc_dealloc_pd_in_bits { 8262 u8 opcode[0x10]; 8263 u8 uid[0x10]; 8264 8265 u8 reserved_at_20[0x10]; 8266 u8 op_mod[0x10]; 8267 8268 u8 reserved_at_40[0x8]; 8269 u8 pd[0x18]; 8270 8271 u8 reserved_at_60[0x20]; 8272 }; 8273 8274 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8275 u8 status[0x8]; 8276 u8 reserved_at_8[0x18]; 8277 8278 u8 syndrome[0x20]; 8279 8280 u8 reserved_at_40[0x40]; 8281 }; 8282 8283 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8284 u8 opcode[0x10]; 8285 u8 reserved_at_10[0x10]; 8286 8287 u8 reserved_at_20[0x10]; 8288 u8 op_mod[0x10]; 8289 8290 u8 flow_counter_id[0x20]; 8291 8292 u8 reserved_at_60[0x20]; 8293 }; 8294 8295 struct mlx5_ifc_create_xrq_out_bits { 8296 u8 status[0x8]; 8297 u8 reserved_at_8[0x18]; 8298 8299 u8 syndrome[0x20]; 8300 8301 u8 reserved_at_40[0x8]; 8302 u8 xrqn[0x18]; 8303 8304 u8 reserved_at_60[0x20]; 8305 }; 8306 8307 struct mlx5_ifc_create_xrq_in_bits { 8308 u8 opcode[0x10]; 8309 u8 uid[0x10]; 8310 8311 u8 reserved_at_20[0x10]; 8312 u8 op_mod[0x10]; 8313 8314 u8 reserved_at_40[0x40]; 8315 8316 struct mlx5_ifc_xrqc_bits xrq_context; 8317 }; 8318 8319 struct mlx5_ifc_create_xrc_srq_out_bits { 8320 u8 status[0x8]; 8321 u8 reserved_at_8[0x18]; 8322 8323 u8 syndrome[0x20]; 8324 8325 u8 reserved_at_40[0x8]; 8326 u8 xrc_srqn[0x18]; 8327 8328 u8 reserved_at_60[0x20]; 8329 }; 8330 8331 struct mlx5_ifc_create_xrc_srq_in_bits { 8332 u8 opcode[0x10]; 8333 u8 uid[0x10]; 8334 8335 u8 reserved_at_20[0x10]; 8336 u8 op_mod[0x10]; 8337 8338 u8 reserved_at_40[0x40]; 8339 8340 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8341 8342 u8 reserved_at_280[0x60]; 8343 8344 u8 xrc_srq_umem_valid[0x1]; 8345 u8 reserved_at_2e1[0x1f]; 8346 8347 u8 reserved_at_300[0x580]; 8348 8349 u8 pas[][0x40]; 8350 }; 8351 8352 struct mlx5_ifc_create_tis_out_bits { 8353 u8 status[0x8]; 8354 u8 reserved_at_8[0x18]; 8355 8356 u8 syndrome[0x20]; 8357 8358 u8 reserved_at_40[0x8]; 8359 u8 tisn[0x18]; 8360 8361 u8 reserved_at_60[0x20]; 8362 }; 8363 8364 struct mlx5_ifc_create_tis_in_bits { 8365 u8 opcode[0x10]; 8366 u8 uid[0x10]; 8367 8368 u8 reserved_at_20[0x10]; 8369 u8 op_mod[0x10]; 8370 8371 u8 reserved_at_40[0xc0]; 8372 8373 struct mlx5_ifc_tisc_bits ctx; 8374 }; 8375 8376 struct mlx5_ifc_create_tir_out_bits { 8377 u8 status[0x8]; 8378 u8 icm_address_63_40[0x18]; 8379 8380 u8 syndrome[0x20]; 8381 8382 u8 icm_address_39_32[0x8]; 8383 u8 tirn[0x18]; 8384 8385 u8 icm_address_31_0[0x20]; 8386 }; 8387 8388 struct mlx5_ifc_create_tir_in_bits { 8389 u8 opcode[0x10]; 8390 u8 uid[0x10]; 8391 8392 u8 reserved_at_20[0x10]; 8393 u8 op_mod[0x10]; 8394 8395 u8 reserved_at_40[0xc0]; 8396 8397 struct mlx5_ifc_tirc_bits ctx; 8398 }; 8399 8400 struct mlx5_ifc_create_srq_out_bits { 8401 u8 status[0x8]; 8402 u8 reserved_at_8[0x18]; 8403 8404 u8 syndrome[0x20]; 8405 8406 u8 reserved_at_40[0x8]; 8407 u8 srqn[0x18]; 8408 8409 u8 reserved_at_60[0x20]; 8410 }; 8411 8412 struct mlx5_ifc_create_srq_in_bits { 8413 u8 opcode[0x10]; 8414 u8 uid[0x10]; 8415 8416 u8 reserved_at_20[0x10]; 8417 u8 op_mod[0x10]; 8418 8419 u8 reserved_at_40[0x40]; 8420 8421 struct mlx5_ifc_srqc_bits srq_context_entry; 8422 8423 u8 reserved_at_280[0x600]; 8424 8425 u8 pas[][0x40]; 8426 }; 8427 8428 struct mlx5_ifc_create_sq_out_bits { 8429 u8 status[0x8]; 8430 u8 reserved_at_8[0x18]; 8431 8432 u8 syndrome[0x20]; 8433 8434 u8 reserved_at_40[0x8]; 8435 u8 sqn[0x18]; 8436 8437 u8 reserved_at_60[0x20]; 8438 }; 8439 8440 struct mlx5_ifc_create_sq_in_bits { 8441 u8 opcode[0x10]; 8442 u8 uid[0x10]; 8443 8444 u8 reserved_at_20[0x10]; 8445 u8 op_mod[0x10]; 8446 8447 u8 reserved_at_40[0xc0]; 8448 8449 struct mlx5_ifc_sqc_bits ctx; 8450 }; 8451 8452 struct mlx5_ifc_create_scheduling_element_out_bits { 8453 u8 status[0x8]; 8454 u8 reserved_at_8[0x18]; 8455 8456 u8 syndrome[0x20]; 8457 8458 u8 reserved_at_40[0x40]; 8459 8460 u8 scheduling_element_id[0x20]; 8461 8462 u8 reserved_at_a0[0x160]; 8463 }; 8464 8465 struct mlx5_ifc_create_scheduling_element_in_bits { 8466 u8 opcode[0x10]; 8467 u8 reserved_at_10[0x10]; 8468 8469 u8 reserved_at_20[0x10]; 8470 u8 op_mod[0x10]; 8471 8472 u8 scheduling_hierarchy[0x8]; 8473 u8 reserved_at_48[0x18]; 8474 8475 u8 reserved_at_60[0xa0]; 8476 8477 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8478 8479 u8 reserved_at_300[0x100]; 8480 }; 8481 8482 struct mlx5_ifc_create_rqt_out_bits { 8483 u8 status[0x8]; 8484 u8 reserved_at_8[0x18]; 8485 8486 u8 syndrome[0x20]; 8487 8488 u8 reserved_at_40[0x8]; 8489 u8 rqtn[0x18]; 8490 8491 u8 reserved_at_60[0x20]; 8492 }; 8493 8494 struct mlx5_ifc_create_rqt_in_bits { 8495 u8 opcode[0x10]; 8496 u8 uid[0x10]; 8497 8498 u8 reserved_at_20[0x10]; 8499 u8 op_mod[0x10]; 8500 8501 u8 reserved_at_40[0xc0]; 8502 8503 struct mlx5_ifc_rqtc_bits rqt_context; 8504 }; 8505 8506 struct mlx5_ifc_create_rq_out_bits { 8507 u8 status[0x8]; 8508 u8 reserved_at_8[0x18]; 8509 8510 u8 syndrome[0x20]; 8511 8512 u8 reserved_at_40[0x8]; 8513 u8 rqn[0x18]; 8514 8515 u8 reserved_at_60[0x20]; 8516 }; 8517 8518 struct mlx5_ifc_create_rq_in_bits { 8519 u8 opcode[0x10]; 8520 u8 uid[0x10]; 8521 8522 u8 reserved_at_20[0x10]; 8523 u8 op_mod[0x10]; 8524 8525 u8 reserved_at_40[0xc0]; 8526 8527 struct mlx5_ifc_rqc_bits ctx; 8528 }; 8529 8530 struct mlx5_ifc_create_rmp_out_bits { 8531 u8 status[0x8]; 8532 u8 reserved_at_8[0x18]; 8533 8534 u8 syndrome[0x20]; 8535 8536 u8 reserved_at_40[0x8]; 8537 u8 rmpn[0x18]; 8538 8539 u8 reserved_at_60[0x20]; 8540 }; 8541 8542 struct mlx5_ifc_create_rmp_in_bits { 8543 u8 opcode[0x10]; 8544 u8 uid[0x10]; 8545 8546 u8 reserved_at_20[0x10]; 8547 u8 op_mod[0x10]; 8548 8549 u8 reserved_at_40[0xc0]; 8550 8551 struct mlx5_ifc_rmpc_bits ctx; 8552 }; 8553 8554 struct mlx5_ifc_create_qp_out_bits { 8555 u8 status[0x8]; 8556 u8 reserved_at_8[0x18]; 8557 8558 u8 syndrome[0x20]; 8559 8560 u8 reserved_at_40[0x8]; 8561 u8 qpn[0x18]; 8562 8563 u8 ece[0x20]; 8564 }; 8565 8566 struct mlx5_ifc_create_qp_in_bits { 8567 u8 opcode[0x10]; 8568 u8 uid[0x10]; 8569 8570 u8 reserved_at_20[0x10]; 8571 u8 op_mod[0x10]; 8572 8573 u8 reserved_at_40[0x8]; 8574 u8 input_qpn[0x18]; 8575 8576 u8 reserved_at_60[0x20]; 8577 u8 opt_param_mask[0x20]; 8578 8579 u8 ece[0x20]; 8580 8581 struct mlx5_ifc_qpc_bits qpc; 8582 8583 u8 reserved_at_800[0x60]; 8584 8585 u8 wq_umem_valid[0x1]; 8586 u8 reserved_at_861[0x1f]; 8587 8588 u8 pas[][0x40]; 8589 }; 8590 8591 struct mlx5_ifc_create_psv_out_bits { 8592 u8 status[0x8]; 8593 u8 reserved_at_8[0x18]; 8594 8595 u8 syndrome[0x20]; 8596 8597 u8 reserved_at_40[0x40]; 8598 8599 u8 reserved_at_80[0x8]; 8600 u8 psv0_index[0x18]; 8601 8602 u8 reserved_at_a0[0x8]; 8603 u8 psv1_index[0x18]; 8604 8605 u8 reserved_at_c0[0x8]; 8606 u8 psv2_index[0x18]; 8607 8608 u8 reserved_at_e0[0x8]; 8609 u8 psv3_index[0x18]; 8610 }; 8611 8612 struct mlx5_ifc_create_psv_in_bits { 8613 u8 opcode[0x10]; 8614 u8 reserved_at_10[0x10]; 8615 8616 u8 reserved_at_20[0x10]; 8617 u8 op_mod[0x10]; 8618 8619 u8 num_psv[0x4]; 8620 u8 reserved_at_44[0x4]; 8621 u8 pd[0x18]; 8622 8623 u8 reserved_at_60[0x20]; 8624 }; 8625 8626 struct mlx5_ifc_create_mkey_out_bits { 8627 u8 status[0x8]; 8628 u8 reserved_at_8[0x18]; 8629 8630 u8 syndrome[0x20]; 8631 8632 u8 reserved_at_40[0x8]; 8633 u8 mkey_index[0x18]; 8634 8635 u8 reserved_at_60[0x20]; 8636 }; 8637 8638 struct mlx5_ifc_create_mkey_in_bits { 8639 u8 opcode[0x10]; 8640 u8 uid[0x10]; 8641 8642 u8 reserved_at_20[0x10]; 8643 u8 op_mod[0x10]; 8644 8645 u8 reserved_at_40[0x20]; 8646 8647 u8 pg_access[0x1]; 8648 u8 mkey_umem_valid[0x1]; 8649 u8 reserved_at_62[0x1e]; 8650 8651 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8652 8653 u8 reserved_at_280[0x80]; 8654 8655 u8 translations_octword_actual_size[0x20]; 8656 8657 u8 reserved_at_320[0x560]; 8658 8659 u8 klm_pas_mtt[][0x20]; 8660 }; 8661 8662 enum { 8663 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8664 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8665 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8666 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8667 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8668 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8669 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8670 }; 8671 8672 struct mlx5_ifc_create_flow_table_out_bits { 8673 u8 status[0x8]; 8674 u8 icm_address_63_40[0x18]; 8675 8676 u8 syndrome[0x20]; 8677 8678 u8 icm_address_39_32[0x8]; 8679 u8 table_id[0x18]; 8680 8681 u8 icm_address_31_0[0x20]; 8682 }; 8683 8684 struct mlx5_ifc_create_flow_table_in_bits { 8685 u8 opcode[0x10]; 8686 u8 uid[0x10]; 8687 8688 u8 reserved_at_20[0x10]; 8689 u8 op_mod[0x10]; 8690 8691 u8 other_vport[0x1]; 8692 u8 reserved_at_41[0xf]; 8693 u8 vport_number[0x10]; 8694 8695 u8 reserved_at_60[0x20]; 8696 8697 u8 table_type[0x8]; 8698 u8 reserved_at_88[0x18]; 8699 8700 u8 reserved_at_a0[0x20]; 8701 8702 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8703 }; 8704 8705 struct mlx5_ifc_create_flow_group_out_bits { 8706 u8 status[0x8]; 8707 u8 reserved_at_8[0x18]; 8708 8709 u8 syndrome[0x20]; 8710 8711 u8 reserved_at_40[0x8]; 8712 u8 group_id[0x18]; 8713 8714 u8 reserved_at_60[0x20]; 8715 }; 8716 8717 enum { 8718 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8719 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8720 }; 8721 8722 enum { 8723 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8724 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8725 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8726 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8727 }; 8728 8729 struct mlx5_ifc_create_flow_group_in_bits { 8730 u8 opcode[0x10]; 8731 u8 reserved_at_10[0x10]; 8732 8733 u8 reserved_at_20[0x10]; 8734 u8 op_mod[0x10]; 8735 8736 u8 other_vport[0x1]; 8737 u8 reserved_at_41[0xf]; 8738 u8 vport_number[0x10]; 8739 8740 u8 reserved_at_60[0x20]; 8741 8742 u8 table_type[0x8]; 8743 u8 reserved_at_88[0x4]; 8744 u8 group_type[0x4]; 8745 u8 reserved_at_90[0x10]; 8746 8747 u8 reserved_at_a0[0x8]; 8748 u8 table_id[0x18]; 8749 8750 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8751 8752 u8 reserved_at_c1[0x1f]; 8753 8754 u8 start_flow_index[0x20]; 8755 8756 u8 reserved_at_100[0x20]; 8757 8758 u8 end_flow_index[0x20]; 8759 8760 u8 reserved_at_140[0x10]; 8761 u8 match_definer_id[0x10]; 8762 8763 u8 reserved_at_160[0x80]; 8764 8765 u8 reserved_at_1e0[0x18]; 8766 u8 match_criteria_enable[0x8]; 8767 8768 struct mlx5_ifc_fte_match_param_bits match_criteria; 8769 8770 u8 reserved_at_1200[0xe00]; 8771 }; 8772 8773 struct mlx5_ifc_create_eq_out_bits { 8774 u8 status[0x8]; 8775 u8 reserved_at_8[0x18]; 8776 8777 u8 syndrome[0x20]; 8778 8779 u8 reserved_at_40[0x18]; 8780 u8 eq_number[0x8]; 8781 8782 u8 reserved_at_60[0x20]; 8783 }; 8784 8785 struct mlx5_ifc_create_eq_in_bits { 8786 u8 opcode[0x10]; 8787 u8 uid[0x10]; 8788 8789 u8 reserved_at_20[0x10]; 8790 u8 op_mod[0x10]; 8791 8792 u8 reserved_at_40[0x40]; 8793 8794 struct mlx5_ifc_eqc_bits eq_context_entry; 8795 8796 u8 reserved_at_280[0x40]; 8797 8798 u8 event_bitmask[4][0x40]; 8799 8800 u8 reserved_at_3c0[0x4c0]; 8801 8802 u8 pas[][0x40]; 8803 }; 8804 8805 struct mlx5_ifc_create_dct_out_bits { 8806 u8 status[0x8]; 8807 u8 reserved_at_8[0x18]; 8808 8809 u8 syndrome[0x20]; 8810 8811 u8 reserved_at_40[0x8]; 8812 u8 dctn[0x18]; 8813 8814 u8 ece[0x20]; 8815 }; 8816 8817 struct mlx5_ifc_create_dct_in_bits { 8818 u8 opcode[0x10]; 8819 u8 uid[0x10]; 8820 8821 u8 reserved_at_20[0x10]; 8822 u8 op_mod[0x10]; 8823 8824 u8 reserved_at_40[0x40]; 8825 8826 struct mlx5_ifc_dctc_bits dct_context_entry; 8827 8828 u8 reserved_at_280[0x180]; 8829 }; 8830 8831 struct mlx5_ifc_create_cq_out_bits { 8832 u8 status[0x8]; 8833 u8 reserved_at_8[0x18]; 8834 8835 u8 syndrome[0x20]; 8836 8837 u8 reserved_at_40[0x8]; 8838 u8 cqn[0x18]; 8839 8840 u8 reserved_at_60[0x20]; 8841 }; 8842 8843 struct mlx5_ifc_create_cq_in_bits { 8844 u8 opcode[0x10]; 8845 u8 uid[0x10]; 8846 8847 u8 reserved_at_20[0x10]; 8848 u8 op_mod[0x10]; 8849 8850 u8 reserved_at_40[0x40]; 8851 8852 struct mlx5_ifc_cqc_bits cq_context; 8853 8854 u8 reserved_at_280[0x60]; 8855 8856 u8 cq_umem_valid[0x1]; 8857 u8 reserved_at_2e1[0x59f]; 8858 8859 u8 pas[][0x40]; 8860 }; 8861 8862 struct mlx5_ifc_config_int_moderation_out_bits { 8863 u8 status[0x8]; 8864 u8 reserved_at_8[0x18]; 8865 8866 u8 syndrome[0x20]; 8867 8868 u8 reserved_at_40[0x4]; 8869 u8 min_delay[0xc]; 8870 u8 int_vector[0x10]; 8871 8872 u8 reserved_at_60[0x20]; 8873 }; 8874 8875 enum { 8876 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8877 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8878 }; 8879 8880 struct mlx5_ifc_config_int_moderation_in_bits { 8881 u8 opcode[0x10]; 8882 u8 reserved_at_10[0x10]; 8883 8884 u8 reserved_at_20[0x10]; 8885 u8 op_mod[0x10]; 8886 8887 u8 reserved_at_40[0x4]; 8888 u8 min_delay[0xc]; 8889 u8 int_vector[0x10]; 8890 8891 u8 reserved_at_60[0x20]; 8892 }; 8893 8894 struct mlx5_ifc_attach_to_mcg_out_bits { 8895 u8 status[0x8]; 8896 u8 reserved_at_8[0x18]; 8897 8898 u8 syndrome[0x20]; 8899 8900 u8 reserved_at_40[0x40]; 8901 }; 8902 8903 struct mlx5_ifc_attach_to_mcg_in_bits { 8904 u8 opcode[0x10]; 8905 u8 uid[0x10]; 8906 8907 u8 reserved_at_20[0x10]; 8908 u8 op_mod[0x10]; 8909 8910 u8 reserved_at_40[0x8]; 8911 u8 qpn[0x18]; 8912 8913 u8 reserved_at_60[0x20]; 8914 8915 u8 multicast_gid[16][0x8]; 8916 }; 8917 8918 struct mlx5_ifc_arm_xrq_out_bits { 8919 u8 status[0x8]; 8920 u8 reserved_at_8[0x18]; 8921 8922 u8 syndrome[0x20]; 8923 8924 u8 reserved_at_40[0x40]; 8925 }; 8926 8927 struct mlx5_ifc_arm_xrq_in_bits { 8928 u8 opcode[0x10]; 8929 u8 reserved_at_10[0x10]; 8930 8931 u8 reserved_at_20[0x10]; 8932 u8 op_mod[0x10]; 8933 8934 u8 reserved_at_40[0x8]; 8935 u8 xrqn[0x18]; 8936 8937 u8 reserved_at_60[0x10]; 8938 u8 lwm[0x10]; 8939 }; 8940 8941 struct mlx5_ifc_arm_xrc_srq_out_bits { 8942 u8 status[0x8]; 8943 u8 reserved_at_8[0x18]; 8944 8945 u8 syndrome[0x20]; 8946 8947 u8 reserved_at_40[0x40]; 8948 }; 8949 8950 enum { 8951 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8952 }; 8953 8954 struct mlx5_ifc_arm_xrc_srq_in_bits { 8955 u8 opcode[0x10]; 8956 u8 uid[0x10]; 8957 8958 u8 reserved_at_20[0x10]; 8959 u8 op_mod[0x10]; 8960 8961 u8 reserved_at_40[0x8]; 8962 u8 xrc_srqn[0x18]; 8963 8964 u8 reserved_at_60[0x10]; 8965 u8 lwm[0x10]; 8966 }; 8967 8968 struct mlx5_ifc_arm_rq_out_bits { 8969 u8 status[0x8]; 8970 u8 reserved_at_8[0x18]; 8971 8972 u8 syndrome[0x20]; 8973 8974 u8 reserved_at_40[0x40]; 8975 }; 8976 8977 enum { 8978 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8979 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8980 }; 8981 8982 struct mlx5_ifc_arm_rq_in_bits { 8983 u8 opcode[0x10]; 8984 u8 uid[0x10]; 8985 8986 u8 reserved_at_20[0x10]; 8987 u8 op_mod[0x10]; 8988 8989 u8 reserved_at_40[0x8]; 8990 u8 srq_number[0x18]; 8991 8992 u8 reserved_at_60[0x10]; 8993 u8 lwm[0x10]; 8994 }; 8995 8996 struct mlx5_ifc_arm_dct_out_bits { 8997 u8 status[0x8]; 8998 u8 reserved_at_8[0x18]; 8999 9000 u8 syndrome[0x20]; 9001 9002 u8 reserved_at_40[0x40]; 9003 }; 9004 9005 struct mlx5_ifc_arm_dct_in_bits { 9006 u8 opcode[0x10]; 9007 u8 reserved_at_10[0x10]; 9008 9009 u8 reserved_at_20[0x10]; 9010 u8 op_mod[0x10]; 9011 9012 u8 reserved_at_40[0x8]; 9013 u8 dct_number[0x18]; 9014 9015 u8 reserved_at_60[0x20]; 9016 }; 9017 9018 struct mlx5_ifc_alloc_xrcd_out_bits { 9019 u8 status[0x8]; 9020 u8 reserved_at_8[0x18]; 9021 9022 u8 syndrome[0x20]; 9023 9024 u8 reserved_at_40[0x8]; 9025 u8 xrcd[0x18]; 9026 9027 u8 reserved_at_60[0x20]; 9028 }; 9029 9030 struct mlx5_ifc_alloc_xrcd_in_bits { 9031 u8 opcode[0x10]; 9032 u8 uid[0x10]; 9033 9034 u8 reserved_at_20[0x10]; 9035 u8 op_mod[0x10]; 9036 9037 u8 reserved_at_40[0x40]; 9038 }; 9039 9040 struct mlx5_ifc_alloc_uar_out_bits { 9041 u8 status[0x8]; 9042 u8 reserved_at_8[0x18]; 9043 9044 u8 syndrome[0x20]; 9045 9046 u8 reserved_at_40[0x8]; 9047 u8 uar[0x18]; 9048 9049 u8 reserved_at_60[0x20]; 9050 }; 9051 9052 struct mlx5_ifc_alloc_uar_in_bits { 9053 u8 opcode[0x10]; 9054 u8 uid[0x10]; 9055 9056 u8 reserved_at_20[0x10]; 9057 u8 op_mod[0x10]; 9058 9059 u8 reserved_at_40[0x40]; 9060 }; 9061 9062 struct mlx5_ifc_alloc_transport_domain_out_bits { 9063 u8 status[0x8]; 9064 u8 reserved_at_8[0x18]; 9065 9066 u8 syndrome[0x20]; 9067 9068 u8 reserved_at_40[0x8]; 9069 u8 transport_domain[0x18]; 9070 9071 u8 reserved_at_60[0x20]; 9072 }; 9073 9074 struct mlx5_ifc_alloc_transport_domain_in_bits { 9075 u8 opcode[0x10]; 9076 u8 uid[0x10]; 9077 9078 u8 reserved_at_20[0x10]; 9079 u8 op_mod[0x10]; 9080 9081 u8 reserved_at_40[0x40]; 9082 }; 9083 9084 struct mlx5_ifc_alloc_q_counter_out_bits { 9085 u8 status[0x8]; 9086 u8 reserved_at_8[0x18]; 9087 9088 u8 syndrome[0x20]; 9089 9090 u8 reserved_at_40[0x18]; 9091 u8 counter_set_id[0x8]; 9092 9093 u8 reserved_at_60[0x20]; 9094 }; 9095 9096 struct mlx5_ifc_alloc_q_counter_in_bits { 9097 u8 opcode[0x10]; 9098 u8 uid[0x10]; 9099 9100 u8 reserved_at_20[0x10]; 9101 u8 op_mod[0x10]; 9102 9103 u8 reserved_at_40[0x40]; 9104 }; 9105 9106 struct mlx5_ifc_alloc_pd_out_bits { 9107 u8 status[0x8]; 9108 u8 reserved_at_8[0x18]; 9109 9110 u8 syndrome[0x20]; 9111 9112 u8 reserved_at_40[0x8]; 9113 u8 pd[0x18]; 9114 9115 u8 reserved_at_60[0x20]; 9116 }; 9117 9118 struct mlx5_ifc_alloc_pd_in_bits { 9119 u8 opcode[0x10]; 9120 u8 uid[0x10]; 9121 9122 u8 reserved_at_20[0x10]; 9123 u8 op_mod[0x10]; 9124 9125 u8 reserved_at_40[0x40]; 9126 }; 9127 9128 struct mlx5_ifc_alloc_flow_counter_out_bits { 9129 u8 status[0x8]; 9130 u8 reserved_at_8[0x18]; 9131 9132 u8 syndrome[0x20]; 9133 9134 u8 flow_counter_id[0x20]; 9135 9136 u8 reserved_at_60[0x20]; 9137 }; 9138 9139 struct mlx5_ifc_alloc_flow_counter_in_bits { 9140 u8 opcode[0x10]; 9141 u8 reserved_at_10[0x10]; 9142 9143 u8 reserved_at_20[0x10]; 9144 u8 op_mod[0x10]; 9145 9146 u8 reserved_at_40[0x38]; 9147 u8 flow_counter_bulk[0x8]; 9148 }; 9149 9150 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9151 u8 status[0x8]; 9152 u8 reserved_at_8[0x18]; 9153 9154 u8 syndrome[0x20]; 9155 9156 u8 reserved_at_40[0x40]; 9157 }; 9158 9159 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9160 u8 opcode[0x10]; 9161 u8 reserved_at_10[0x10]; 9162 9163 u8 reserved_at_20[0x10]; 9164 u8 op_mod[0x10]; 9165 9166 u8 reserved_at_40[0x20]; 9167 9168 u8 reserved_at_60[0x10]; 9169 u8 vxlan_udp_port[0x10]; 9170 }; 9171 9172 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9173 u8 status[0x8]; 9174 u8 reserved_at_8[0x18]; 9175 9176 u8 syndrome[0x20]; 9177 9178 u8 reserved_at_40[0x40]; 9179 }; 9180 9181 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9182 u8 rate_limit[0x20]; 9183 9184 u8 burst_upper_bound[0x20]; 9185 9186 u8 reserved_at_40[0x10]; 9187 u8 typical_packet_size[0x10]; 9188 9189 u8 reserved_at_60[0x120]; 9190 }; 9191 9192 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9193 u8 opcode[0x10]; 9194 u8 uid[0x10]; 9195 9196 u8 reserved_at_20[0x10]; 9197 u8 op_mod[0x10]; 9198 9199 u8 reserved_at_40[0x10]; 9200 u8 rate_limit_index[0x10]; 9201 9202 u8 reserved_at_60[0x20]; 9203 9204 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9205 }; 9206 9207 struct mlx5_ifc_access_register_out_bits { 9208 u8 status[0x8]; 9209 u8 reserved_at_8[0x18]; 9210 9211 u8 syndrome[0x20]; 9212 9213 u8 reserved_at_40[0x40]; 9214 9215 u8 register_data[][0x20]; 9216 }; 9217 9218 enum { 9219 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9220 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9221 }; 9222 9223 struct mlx5_ifc_access_register_in_bits { 9224 u8 opcode[0x10]; 9225 u8 reserved_at_10[0x10]; 9226 9227 u8 reserved_at_20[0x10]; 9228 u8 op_mod[0x10]; 9229 9230 u8 reserved_at_40[0x10]; 9231 u8 register_id[0x10]; 9232 9233 u8 argument[0x20]; 9234 9235 u8 register_data[][0x20]; 9236 }; 9237 9238 struct mlx5_ifc_sltp_reg_bits { 9239 u8 status[0x4]; 9240 u8 version[0x4]; 9241 u8 local_port[0x8]; 9242 u8 pnat[0x2]; 9243 u8 reserved_at_12[0x2]; 9244 u8 lane[0x4]; 9245 u8 reserved_at_18[0x8]; 9246 9247 u8 reserved_at_20[0x20]; 9248 9249 u8 reserved_at_40[0x7]; 9250 u8 polarity[0x1]; 9251 u8 ob_tap0[0x8]; 9252 u8 ob_tap1[0x8]; 9253 u8 ob_tap2[0x8]; 9254 9255 u8 reserved_at_60[0xc]; 9256 u8 ob_preemp_mode[0x4]; 9257 u8 ob_reg[0x8]; 9258 u8 ob_bias[0x8]; 9259 9260 u8 reserved_at_80[0x20]; 9261 }; 9262 9263 struct mlx5_ifc_slrg_reg_bits { 9264 u8 status[0x4]; 9265 u8 version[0x4]; 9266 u8 local_port[0x8]; 9267 u8 pnat[0x2]; 9268 u8 reserved_at_12[0x2]; 9269 u8 lane[0x4]; 9270 u8 reserved_at_18[0x8]; 9271 9272 u8 time_to_link_up[0x10]; 9273 u8 reserved_at_30[0xc]; 9274 u8 grade_lane_speed[0x4]; 9275 9276 u8 grade_version[0x8]; 9277 u8 grade[0x18]; 9278 9279 u8 reserved_at_60[0x4]; 9280 u8 height_grade_type[0x4]; 9281 u8 height_grade[0x18]; 9282 9283 u8 height_dz[0x10]; 9284 u8 height_dv[0x10]; 9285 9286 u8 reserved_at_a0[0x10]; 9287 u8 height_sigma[0x10]; 9288 9289 u8 reserved_at_c0[0x20]; 9290 9291 u8 reserved_at_e0[0x4]; 9292 u8 phase_grade_type[0x4]; 9293 u8 phase_grade[0x18]; 9294 9295 u8 reserved_at_100[0x8]; 9296 u8 phase_eo_pos[0x8]; 9297 u8 reserved_at_110[0x8]; 9298 u8 phase_eo_neg[0x8]; 9299 9300 u8 ffe_set_tested[0x10]; 9301 u8 test_errors_per_lane[0x10]; 9302 }; 9303 9304 struct mlx5_ifc_pvlc_reg_bits { 9305 u8 reserved_at_0[0x8]; 9306 u8 local_port[0x8]; 9307 u8 reserved_at_10[0x10]; 9308 9309 u8 reserved_at_20[0x1c]; 9310 u8 vl_hw_cap[0x4]; 9311 9312 u8 reserved_at_40[0x1c]; 9313 u8 vl_admin[0x4]; 9314 9315 u8 reserved_at_60[0x1c]; 9316 u8 vl_operational[0x4]; 9317 }; 9318 9319 struct mlx5_ifc_pude_reg_bits { 9320 u8 swid[0x8]; 9321 u8 local_port[0x8]; 9322 u8 reserved_at_10[0x4]; 9323 u8 admin_status[0x4]; 9324 u8 reserved_at_18[0x4]; 9325 u8 oper_status[0x4]; 9326 9327 u8 reserved_at_20[0x60]; 9328 }; 9329 9330 struct mlx5_ifc_ptys_reg_bits { 9331 u8 reserved_at_0[0x1]; 9332 u8 an_disable_admin[0x1]; 9333 u8 an_disable_cap[0x1]; 9334 u8 reserved_at_3[0x5]; 9335 u8 local_port[0x8]; 9336 u8 reserved_at_10[0xd]; 9337 u8 proto_mask[0x3]; 9338 9339 u8 an_status[0x4]; 9340 u8 reserved_at_24[0xc]; 9341 u8 data_rate_oper[0x10]; 9342 9343 u8 ext_eth_proto_capability[0x20]; 9344 9345 u8 eth_proto_capability[0x20]; 9346 9347 u8 ib_link_width_capability[0x10]; 9348 u8 ib_proto_capability[0x10]; 9349 9350 u8 ext_eth_proto_admin[0x20]; 9351 9352 u8 eth_proto_admin[0x20]; 9353 9354 u8 ib_link_width_admin[0x10]; 9355 u8 ib_proto_admin[0x10]; 9356 9357 u8 ext_eth_proto_oper[0x20]; 9358 9359 u8 eth_proto_oper[0x20]; 9360 9361 u8 ib_link_width_oper[0x10]; 9362 u8 ib_proto_oper[0x10]; 9363 9364 u8 reserved_at_160[0x1c]; 9365 u8 connector_type[0x4]; 9366 9367 u8 eth_proto_lp_advertise[0x20]; 9368 9369 u8 reserved_at_1a0[0x60]; 9370 }; 9371 9372 struct mlx5_ifc_mlcr_reg_bits { 9373 u8 reserved_at_0[0x8]; 9374 u8 local_port[0x8]; 9375 u8 reserved_at_10[0x20]; 9376 9377 u8 beacon_duration[0x10]; 9378 u8 reserved_at_40[0x10]; 9379 9380 u8 beacon_remain[0x10]; 9381 }; 9382 9383 struct mlx5_ifc_ptas_reg_bits { 9384 u8 reserved_at_0[0x20]; 9385 9386 u8 algorithm_options[0x10]; 9387 u8 reserved_at_30[0x4]; 9388 u8 repetitions_mode[0x4]; 9389 u8 num_of_repetitions[0x8]; 9390 9391 u8 grade_version[0x8]; 9392 u8 height_grade_type[0x4]; 9393 u8 phase_grade_type[0x4]; 9394 u8 height_grade_weight[0x8]; 9395 u8 phase_grade_weight[0x8]; 9396 9397 u8 gisim_measure_bits[0x10]; 9398 u8 adaptive_tap_measure_bits[0x10]; 9399 9400 u8 ber_bath_high_error_threshold[0x10]; 9401 u8 ber_bath_mid_error_threshold[0x10]; 9402 9403 u8 ber_bath_low_error_threshold[0x10]; 9404 u8 one_ratio_high_threshold[0x10]; 9405 9406 u8 one_ratio_high_mid_threshold[0x10]; 9407 u8 one_ratio_low_mid_threshold[0x10]; 9408 9409 u8 one_ratio_low_threshold[0x10]; 9410 u8 ndeo_error_threshold[0x10]; 9411 9412 u8 mixer_offset_step_size[0x10]; 9413 u8 reserved_at_110[0x8]; 9414 u8 mix90_phase_for_voltage_bath[0x8]; 9415 9416 u8 mixer_offset_start[0x10]; 9417 u8 mixer_offset_end[0x10]; 9418 9419 u8 reserved_at_140[0x15]; 9420 u8 ber_test_time[0xb]; 9421 }; 9422 9423 struct mlx5_ifc_pspa_reg_bits { 9424 u8 swid[0x8]; 9425 u8 local_port[0x8]; 9426 u8 sub_port[0x8]; 9427 u8 reserved_at_18[0x8]; 9428 9429 u8 reserved_at_20[0x20]; 9430 }; 9431 9432 struct mlx5_ifc_pqdr_reg_bits { 9433 u8 reserved_at_0[0x8]; 9434 u8 local_port[0x8]; 9435 u8 reserved_at_10[0x5]; 9436 u8 prio[0x3]; 9437 u8 reserved_at_18[0x6]; 9438 u8 mode[0x2]; 9439 9440 u8 reserved_at_20[0x20]; 9441 9442 u8 reserved_at_40[0x10]; 9443 u8 min_threshold[0x10]; 9444 9445 u8 reserved_at_60[0x10]; 9446 u8 max_threshold[0x10]; 9447 9448 u8 reserved_at_80[0x10]; 9449 u8 mark_probability_denominator[0x10]; 9450 9451 u8 reserved_at_a0[0x60]; 9452 }; 9453 9454 struct mlx5_ifc_ppsc_reg_bits { 9455 u8 reserved_at_0[0x8]; 9456 u8 local_port[0x8]; 9457 u8 reserved_at_10[0x10]; 9458 9459 u8 reserved_at_20[0x60]; 9460 9461 u8 reserved_at_80[0x1c]; 9462 u8 wrps_admin[0x4]; 9463 9464 u8 reserved_at_a0[0x1c]; 9465 u8 wrps_status[0x4]; 9466 9467 u8 reserved_at_c0[0x8]; 9468 u8 up_threshold[0x8]; 9469 u8 reserved_at_d0[0x8]; 9470 u8 down_threshold[0x8]; 9471 9472 u8 reserved_at_e0[0x20]; 9473 9474 u8 reserved_at_100[0x1c]; 9475 u8 srps_admin[0x4]; 9476 9477 u8 reserved_at_120[0x1c]; 9478 u8 srps_status[0x4]; 9479 9480 u8 reserved_at_140[0x40]; 9481 }; 9482 9483 struct mlx5_ifc_pplr_reg_bits { 9484 u8 reserved_at_0[0x8]; 9485 u8 local_port[0x8]; 9486 u8 reserved_at_10[0x10]; 9487 9488 u8 reserved_at_20[0x8]; 9489 u8 lb_cap[0x8]; 9490 u8 reserved_at_30[0x8]; 9491 u8 lb_en[0x8]; 9492 }; 9493 9494 struct mlx5_ifc_pplm_reg_bits { 9495 u8 reserved_at_0[0x8]; 9496 u8 local_port[0x8]; 9497 u8 reserved_at_10[0x10]; 9498 9499 u8 reserved_at_20[0x20]; 9500 9501 u8 port_profile_mode[0x8]; 9502 u8 static_port_profile[0x8]; 9503 u8 active_port_profile[0x8]; 9504 u8 reserved_at_58[0x8]; 9505 9506 u8 retransmission_active[0x8]; 9507 u8 fec_mode_active[0x18]; 9508 9509 u8 rs_fec_correction_bypass_cap[0x4]; 9510 u8 reserved_at_84[0x8]; 9511 u8 fec_override_cap_56g[0x4]; 9512 u8 fec_override_cap_100g[0x4]; 9513 u8 fec_override_cap_50g[0x4]; 9514 u8 fec_override_cap_25g[0x4]; 9515 u8 fec_override_cap_10g_40g[0x4]; 9516 9517 u8 rs_fec_correction_bypass_admin[0x4]; 9518 u8 reserved_at_a4[0x8]; 9519 u8 fec_override_admin_56g[0x4]; 9520 u8 fec_override_admin_100g[0x4]; 9521 u8 fec_override_admin_50g[0x4]; 9522 u8 fec_override_admin_25g[0x4]; 9523 u8 fec_override_admin_10g_40g[0x4]; 9524 9525 u8 fec_override_cap_400g_8x[0x10]; 9526 u8 fec_override_cap_200g_4x[0x10]; 9527 9528 u8 fec_override_cap_100g_2x[0x10]; 9529 u8 fec_override_cap_50g_1x[0x10]; 9530 9531 u8 fec_override_admin_400g_8x[0x10]; 9532 u8 fec_override_admin_200g_4x[0x10]; 9533 9534 u8 fec_override_admin_100g_2x[0x10]; 9535 u8 fec_override_admin_50g_1x[0x10]; 9536 9537 u8 reserved_at_140[0x140]; 9538 }; 9539 9540 struct mlx5_ifc_ppcnt_reg_bits { 9541 u8 swid[0x8]; 9542 u8 local_port[0x8]; 9543 u8 pnat[0x2]; 9544 u8 reserved_at_12[0x8]; 9545 u8 grp[0x6]; 9546 9547 u8 clr[0x1]; 9548 u8 reserved_at_21[0x1c]; 9549 u8 prio_tc[0x3]; 9550 9551 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9552 }; 9553 9554 struct mlx5_ifc_mpein_reg_bits { 9555 u8 reserved_at_0[0x2]; 9556 u8 depth[0x6]; 9557 u8 pcie_index[0x8]; 9558 u8 node[0x8]; 9559 u8 reserved_at_18[0x8]; 9560 9561 u8 capability_mask[0x20]; 9562 9563 u8 reserved_at_40[0x8]; 9564 u8 link_width_enabled[0x8]; 9565 u8 link_speed_enabled[0x10]; 9566 9567 u8 lane0_physical_position[0x8]; 9568 u8 link_width_active[0x8]; 9569 u8 link_speed_active[0x10]; 9570 9571 u8 num_of_pfs[0x10]; 9572 u8 num_of_vfs[0x10]; 9573 9574 u8 bdf0[0x10]; 9575 u8 reserved_at_b0[0x10]; 9576 9577 u8 max_read_request_size[0x4]; 9578 u8 max_payload_size[0x4]; 9579 u8 reserved_at_c8[0x5]; 9580 u8 pwr_status[0x3]; 9581 u8 port_type[0x4]; 9582 u8 reserved_at_d4[0xb]; 9583 u8 lane_reversal[0x1]; 9584 9585 u8 reserved_at_e0[0x14]; 9586 u8 pci_power[0xc]; 9587 9588 u8 reserved_at_100[0x20]; 9589 9590 u8 device_status[0x10]; 9591 u8 port_state[0x8]; 9592 u8 reserved_at_138[0x8]; 9593 9594 u8 reserved_at_140[0x10]; 9595 u8 receiver_detect_result[0x10]; 9596 9597 u8 reserved_at_160[0x20]; 9598 }; 9599 9600 struct mlx5_ifc_mpcnt_reg_bits { 9601 u8 reserved_at_0[0x8]; 9602 u8 pcie_index[0x8]; 9603 u8 reserved_at_10[0xa]; 9604 u8 grp[0x6]; 9605 9606 u8 clr[0x1]; 9607 u8 reserved_at_21[0x1f]; 9608 9609 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9610 }; 9611 9612 struct mlx5_ifc_ppad_reg_bits { 9613 u8 reserved_at_0[0x3]; 9614 u8 single_mac[0x1]; 9615 u8 reserved_at_4[0x4]; 9616 u8 local_port[0x8]; 9617 u8 mac_47_32[0x10]; 9618 9619 u8 mac_31_0[0x20]; 9620 9621 u8 reserved_at_40[0x40]; 9622 }; 9623 9624 struct mlx5_ifc_pmtu_reg_bits { 9625 u8 reserved_at_0[0x8]; 9626 u8 local_port[0x8]; 9627 u8 reserved_at_10[0x10]; 9628 9629 u8 max_mtu[0x10]; 9630 u8 reserved_at_30[0x10]; 9631 9632 u8 admin_mtu[0x10]; 9633 u8 reserved_at_50[0x10]; 9634 9635 u8 oper_mtu[0x10]; 9636 u8 reserved_at_70[0x10]; 9637 }; 9638 9639 struct mlx5_ifc_pmpr_reg_bits { 9640 u8 reserved_at_0[0x8]; 9641 u8 module[0x8]; 9642 u8 reserved_at_10[0x10]; 9643 9644 u8 reserved_at_20[0x18]; 9645 u8 attenuation_5g[0x8]; 9646 9647 u8 reserved_at_40[0x18]; 9648 u8 attenuation_7g[0x8]; 9649 9650 u8 reserved_at_60[0x18]; 9651 u8 attenuation_12g[0x8]; 9652 }; 9653 9654 struct mlx5_ifc_pmpe_reg_bits { 9655 u8 reserved_at_0[0x8]; 9656 u8 module[0x8]; 9657 u8 reserved_at_10[0xc]; 9658 u8 module_status[0x4]; 9659 9660 u8 reserved_at_20[0x60]; 9661 }; 9662 9663 struct mlx5_ifc_pmpc_reg_bits { 9664 u8 module_state_updated[32][0x8]; 9665 }; 9666 9667 struct mlx5_ifc_pmlpn_reg_bits { 9668 u8 reserved_at_0[0x4]; 9669 u8 mlpn_status[0x4]; 9670 u8 local_port[0x8]; 9671 u8 reserved_at_10[0x10]; 9672 9673 u8 e[0x1]; 9674 u8 reserved_at_21[0x1f]; 9675 }; 9676 9677 struct mlx5_ifc_pmlp_reg_bits { 9678 u8 rxtx[0x1]; 9679 u8 reserved_at_1[0x7]; 9680 u8 local_port[0x8]; 9681 u8 reserved_at_10[0x8]; 9682 u8 width[0x8]; 9683 9684 u8 lane0_module_mapping[0x20]; 9685 9686 u8 lane1_module_mapping[0x20]; 9687 9688 u8 lane2_module_mapping[0x20]; 9689 9690 u8 lane3_module_mapping[0x20]; 9691 9692 u8 reserved_at_a0[0x160]; 9693 }; 9694 9695 struct mlx5_ifc_pmaos_reg_bits { 9696 u8 reserved_at_0[0x8]; 9697 u8 module[0x8]; 9698 u8 reserved_at_10[0x4]; 9699 u8 admin_status[0x4]; 9700 u8 reserved_at_18[0x4]; 9701 u8 oper_status[0x4]; 9702 9703 u8 ase[0x1]; 9704 u8 ee[0x1]; 9705 u8 reserved_at_22[0x1c]; 9706 u8 e[0x2]; 9707 9708 u8 reserved_at_40[0x40]; 9709 }; 9710 9711 struct mlx5_ifc_plpc_reg_bits { 9712 u8 reserved_at_0[0x4]; 9713 u8 profile_id[0xc]; 9714 u8 reserved_at_10[0x4]; 9715 u8 proto_mask[0x4]; 9716 u8 reserved_at_18[0x8]; 9717 9718 u8 reserved_at_20[0x10]; 9719 u8 lane_speed[0x10]; 9720 9721 u8 reserved_at_40[0x17]; 9722 u8 lpbf[0x1]; 9723 u8 fec_mode_policy[0x8]; 9724 9725 u8 retransmission_capability[0x8]; 9726 u8 fec_mode_capability[0x18]; 9727 9728 u8 retransmission_support_admin[0x8]; 9729 u8 fec_mode_support_admin[0x18]; 9730 9731 u8 retransmission_request_admin[0x8]; 9732 u8 fec_mode_request_admin[0x18]; 9733 9734 u8 reserved_at_c0[0x80]; 9735 }; 9736 9737 struct mlx5_ifc_plib_reg_bits { 9738 u8 reserved_at_0[0x8]; 9739 u8 local_port[0x8]; 9740 u8 reserved_at_10[0x8]; 9741 u8 ib_port[0x8]; 9742 9743 u8 reserved_at_20[0x60]; 9744 }; 9745 9746 struct mlx5_ifc_plbf_reg_bits { 9747 u8 reserved_at_0[0x8]; 9748 u8 local_port[0x8]; 9749 u8 reserved_at_10[0xd]; 9750 u8 lbf_mode[0x3]; 9751 9752 u8 reserved_at_20[0x20]; 9753 }; 9754 9755 struct mlx5_ifc_pipg_reg_bits { 9756 u8 reserved_at_0[0x8]; 9757 u8 local_port[0x8]; 9758 u8 reserved_at_10[0x10]; 9759 9760 u8 dic[0x1]; 9761 u8 reserved_at_21[0x19]; 9762 u8 ipg[0x4]; 9763 u8 reserved_at_3e[0x2]; 9764 }; 9765 9766 struct mlx5_ifc_pifr_reg_bits { 9767 u8 reserved_at_0[0x8]; 9768 u8 local_port[0x8]; 9769 u8 reserved_at_10[0x10]; 9770 9771 u8 reserved_at_20[0xe0]; 9772 9773 u8 port_filter[8][0x20]; 9774 9775 u8 port_filter_update_en[8][0x20]; 9776 }; 9777 9778 struct mlx5_ifc_pfcc_reg_bits { 9779 u8 reserved_at_0[0x8]; 9780 u8 local_port[0x8]; 9781 u8 reserved_at_10[0xb]; 9782 u8 ppan_mask_n[0x1]; 9783 u8 minor_stall_mask[0x1]; 9784 u8 critical_stall_mask[0x1]; 9785 u8 reserved_at_1e[0x2]; 9786 9787 u8 ppan[0x4]; 9788 u8 reserved_at_24[0x4]; 9789 u8 prio_mask_tx[0x8]; 9790 u8 reserved_at_30[0x8]; 9791 u8 prio_mask_rx[0x8]; 9792 9793 u8 pptx[0x1]; 9794 u8 aptx[0x1]; 9795 u8 pptx_mask_n[0x1]; 9796 u8 reserved_at_43[0x5]; 9797 u8 pfctx[0x8]; 9798 u8 reserved_at_50[0x10]; 9799 9800 u8 pprx[0x1]; 9801 u8 aprx[0x1]; 9802 u8 pprx_mask_n[0x1]; 9803 u8 reserved_at_63[0x5]; 9804 u8 pfcrx[0x8]; 9805 u8 reserved_at_70[0x10]; 9806 9807 u8 device_stall_minor_watermark[0x10]; 9808 u8 device_stall_critical_watermark[0x10]; 9809 9810 u8 reserved_at_a0[0x60]; 9811 }; 9812 9813 struct mlx5_ifc_pelc_reg_bits { 9814 u8 op[0x4]; 9815 u8 reserved_at_4[0x4]; 9816 u8 local_port[0x8]; 9817 u8 reserved_at_10[0x10]; 9818 9819 u8 op_admin[0x8]; 9820 u8 op_capability[0x8]; 9821 u8 op_request[0x8]; 9822 u8 op_active[0x8]; 9823 9824 u8 admin[0x40]; 9825 9826 u8 capability[0x40]; 9827 9828 u8 request[0x40]; 9829 9830 u8 active[0x40]; 9831 9832 u8 reserved_at_140[0x80]; 9833 }; 9834 9835 struct mlx5_ifc_peir_reg_bits { 9836 u8 reserved_at_0[0x8]; 9837 u8 local_port[0x8]; 9838 u8 reserved_at_10[0x10]; 9839 9840 u8 reserved_at_20[0xc]; 9841 u8 error_count[0x4]; 9842 u8 reserved_at_30[0x10]; 9843 9844 u8 reserved_at_40[0xc]; 9845 u8 lane[0x4]; 9846 u8 reserved_at_50[0x8]; 9847 u8 error_type[0x8]; 9848 }; 9849 9850 struct mlx5_ifc_mpegc_reg_bits { 9851 u8 reserved_at_0[0x30]; 9852 u8 field_select[0x10]; 9853 9854 u8 tx_overflow_sense[0x1]; 9855 u8 mark_cqe[0x1]; 9856 u8 mark_cnp[0x1]; 9857 u8 reserved_at_43[0x1b]; 9858 u8 tx_lossy_overflow_oper[0x2]; 9859 9860 u8 reserved_at_60[0x100]; 9861 }; 9862 9863 enum { 9864 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9865 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9866 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9867 }; 9868 9869 struct mlx5_ifc_mtutc_reg_bits { 9870 u8 reserved_at_0[0x1c]; 9871 u8 operation[0x4]; 9872 9873 u8 freq_adjustment[0x20]; 9874 9875 u8 reserved_at_40[0x40]; 9876 9877 u8 utc_sec[0x20]; 9878 9879 u8 reserved_at_a0[0x2]; 9880 u8 utc_nsec[0x1e]; 9881 9882 u8 time_adjustment[0x20]; 9883 }; 9884 9885 struct mlx5_ifc_pcam_enhanced_features_bits { 9886 u8 reserved_at_0[0x68]; 9887 u8 fec_50G_per_lane_in_pplm[0x1]; 9888 u8 reserved_at_69[0x4]; 9889 u8 rx_icrc_encapsulated_counter[0x1]; 9890 u8 reserved_at_6e[0x4]; 9891 u8 ptys_extended_ethernet[0x1]; 9892 u8 reserved_at_73[0x3]; 9893 u8 pfcc_mask[0x1]; 9894 u8 reserved_at_77[0x3]; 9895 u8 per_lane_error_counters[0x1]; 9896 u8 rx_buffer_fullness_counters[0x1]; 9897 u8 ptys_connector_type[0x1]; 9898 u8 reserved_at_7d[0x1]; 9899 u8 ppcnt_discard_group[0x1]; 9900 u8 ppcnt_statistical_group[0x1]; 9901 }; 9902 9903 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9904 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9905 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9906 9907 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9908 u8 pplm[0x1]; 9909 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9910 9911 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9912 u8 pbmc[0x1]; 9913 u8 pptb[0x1]; 9914 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9915 u8 ppcnt[0x1]; 9916 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9917 }; 9918 9919 struct mlx5_ifc_pcam_reg_bits { 9920 u8 reserved_at_0[0x8]; 9921 u8 feature_group[0x8]; 9922 u8 reserved_at_10[0x8]; 9923 u8 access_reg_group[0x8]; 9924 9925 u8 reserved_at_20[0x20]; 9926 9927 union { 9928 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9929 u8 reserved_at_0[0x80]; 9930 } port_access_reg_cap_mask; 9931 9932 u8 reserved_at_c0[0x80]; 9933 9934 union { 9935 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9936 u8 reserved_at_0[0x80]; 9937 } feature_cap_mask; 9938 9939 u8 reserved_at_1c0[0xc0]; 9940 }; 9941 9942 struct mlx5_ifc_mcam_enhanced_features_bits { 9943 u8 reserved_at_0[0x5d]; 9944 u8 mcia_32dwords[0x1]; 9945 u8 out_pulse_duration_ns[0x1]; 9946 u8 npps_period[0x1]; 9947 u8 reserved_at_60[0xa]; 9948 u8 reset_state[0x1]; 9949 u8 ptpcyc2realtime_modify[0x1]; 9950 u8 reserved_at_6c[0x2]; 9951 u8 pci_status_and_power[0x1]; 9952 u8 reserved_at_6f[0x5]; 9953 u8 mark_tx_action_cnp[0x1]; 9954 u8 mark_tx_action_cqe[0x1]; 9955 u8 dynamic_tx_overflow[0x1]; 9956 u8 reserved_at_77[0x4]; 9957 u8 pcie_outbound_stalled[0x1]; 9958 u8 tx_overflow_buffer_pkt[0x1]; 9959 u8 mtpps_enh_out_per_adj[0x1]; 9960 u8 mtpps_fs[0x1]; 9961 u8 pcie_performance_group[0x1]; 9962 }; 9963 9964 struct mlx5_ifc_mcam_access_reg_bits { 9965 u8 reserved_at_0[0x1c]; 9966 u8 mcda[0x1]; 9967 u8 mcc[0x1]; 9968 u8 mcqi[0x1]; 9969 u8 mcqs[0x1]; 9970 9971 u8 regs_95_to_87[0x9]; 9972 u8 mpegc[0x1]; 9973 u8 mtutc[0x1]; 9974 u8 regs_84_to_68[0x11]; 9975 u8 tracer_registers[0x4]; 9976 9977 u8 regs_63_to_46[0x12]; 9978 u8 mrtc[0x1]; 9979 u8 regs_44_to_32[0xd]; 9980 9981 u8 regs_31_to_0[0x20]; 9982 }; 9983 9984 struct mlx5_ifc_mcam_access_reg_bits1 { 9985 u8 regs_127_to_96[0x20]; 9986 9987 u8 regs_95_to_64[0x20]; 9988 9989 u8 regs_63_to_32[0x20]; 9990 9991 u8 regs_31_to_0[0x20]; 9992 }; 9993 9994 struct mlx5_ifc_mcam_access_reg_bits2 { 9995 u8 regs_127_to_99[0x1d]; 9996 u8 mirc[0x1]; 9997 u8 regs_97_to_96[0x2]; 9998 9999 u8 regs_95_to_64[0x20]; 10000 10001 u8 regs_63_to_32[0x20]; 10002 10003 u8 regs_31_to_0[0x20]; 10004 }; 10005 10006 struct mlx5_ifc_mcam_reg_bits { 10007 u8 reserved_at_0[0x8]; 10008 u8 feature_group[0x8]; 10009 u8 reserved_at_10[0x8]; 10010 u8 access_reg_group[0x8]; 10011 10012 u8 reserved_at_20[0x20]; 10013 10014 union { 10015 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10016 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10017 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10018 u8 reserved_at_0[0x80]; 10019 } mng_access_reg_cap_mask; 10020 10021 u8 reserved_at_c0[0x80]; 10022 10023 union { 10024 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10025 u8 reserved_at_0[0x80]; 10026 } mng_feature_cap_mask; 10027 10028 u8 reserved_at_1c0[0x80]; 10029 }; 10030 10031 struct mlx5_ifc_qcam_access_reg_cap_mask { 10032 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10033 u8 qpdpm[0x1]; 10034 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10035 u8 qdpm[0x1]; 10036 u8 qpts[0x1]; 10037 u8 qcap[0x1]; 10038 u8 qcam_access_reg_cap_mask_0[0x1]; 10039 }; 10040 10041 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10042 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10043 u8 qpts_trust_both[0x1]; 10044 }; 10045 10046 struct mlx5_ifc_qcam_reg_bits { 10047 u8 reserved_at_0[0x8]; 10048 u8 feature_group[0x8]; 10049 u8 reserved_at_10[0x8]; 10050 u8 access_reg_group[0x8]; 10051 u8 reserved_at_20[0x20]; 10052 10053 union { 10054 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10055 u8 reserved_at_0[0x80]; 10056 } qos_access_reg_cap_mask; 10057 10058 u8 reserved_at_c0[0x80]; 10059 10060 union { 10061 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10062 u8 reserved_at_0[0x80]; 10063 } qos_feature_cap_mask; 10064 10065 u8 reserved_at_1c0[0x80]; 10066 }; 10067 10068 struct mlx5_ifc_core_dump_reg_bits { 10069 u8 reserved_at_0[0x18]; 10070 u8 core_dump_type[0x8]; 10071 10072 u8 reserved_at_20[0x30]; 10073 u8 vhca_id[0x10]; 10074 10075 u8 reserved_at_60[0x8]; 10076 u8 qpn[0x18]; 10077 u8 reserved_at_80[0x180]; 10078 }; 10079 10080 struct mlx5_ifc_pcap_reg_bits { 10081 u8 reserved_at_0[0x8]; 10082 u8 local_port[0x8]; 10083 u8 reserved_at_10[0x10]; 10084 10085 u8 port_capability_mask[4][0x20]; 10086 }; 10087 10088 struct mlx5_ifc_paos_reg_bits { 10089 u8 swid[0x8]; 10090 u8 local_port[0x8]; 10091 u8 reserved_at_10[0x4]; 10092 u8 admin_status[0x4]; 10093 u8 reserved_at_18[0x4]; 10094 u8 oper_status[0x4]; 10095 10096 u8 ase[0x1]; 10097 u8 ee[0x1]; 10098 u8 reserved_at_22[0x1c]; 10099 u8 e[0x2]; 10100 10101 u8 reserved_at_40[0x40]; 10102 }; 10103 10104 struct mlx5_ifc_pamp_reg_bits { 10105 u8 reserved_at_0[0x8]; 10106 u8 opamp_group[0x8]; 10107 u8 reserved_at_10[0xc]; 10108 u8 opamp_group_type[0x4]; 10109 10110 u8 start_index[0x10]; 10111 u8 reserved_at_30[0x4]; 10112 u8 num_of_indices[0xc]; 10113 10114 u8 index_data[18][0x10]; 10115 }; 10116 10117 struct mlx5_ifc_pcmr_reg_bits { 10118 u8 reserved_at_0[0x8]; 10119 u8 local_port[0x8]; 10120 u8 reserved_at_10[0x10]; 10121 10122 u8 entropy_force_cap[0x1]; 10123 u8 entropy_calc_cap[0x1]; 10124 u8 entropy_gre_calc_cap[0x1]; 10125 u8 reserved_at_23[0xf]; 10126 u8 rx_ts_over_crc_cap[0x1]; 10127 u8 reserved_at_33[0xb]; 10128 u8 fcs_cap[0x1]; 10129 u8 reserved_at_3f[0x1]; 10130 10131 u8 entropy_force[0x1]; 10132 u8 entropy_calc[0x1]; 10133 u8 entropy_gre_calc[0x1]; 10134 u8 reserved_at_43[0xf]; 10135 u8 rx_ts_over_crc[0x1]; 10136 u8 reserved_at_53[0xb]; 10137 u8 fcs_chk[0x1]; 10138 u8 reserved_at_5f[0x1]; 10139 }; 10140 10141 struct mlx5_ifc_lane_2_module_mapping_bits { 10142 u8 reserved_at_0[0x4]; 10143 u8 rx_lane[0x4]; 10144 u8 reserved_at_8[0x4]; 10145 u8 tx_lane[0x4]; 10146 u8 reserved_at_10[0x8]; 10147 u8 module[0x8]; 10148 }; 10149 10150 struct mlx5_ifc_bufferx_reg_bits { 10151 u8 reserved_at_0[0x6]; 10152 u8 lossy[0x1]; 10153 u8 epsb[0x1]; 10154 u8 reserved_at_8[0x8]; 10155 u8 size[0x10]; 10156 10157 u8 xoff_threshold[0x10]; 10158 u8 xon_threshold[0x10]; 10159 }; 10160 10161 struct mlx5_ifc_set_node_in_bits { 10162 u8 node_description[64][0x8]; 10163 }; 10164 10165 struct mlx5_ifc_register_power_settings_bits { 10166 u8 reserved_at_0[0x18]; 10167 u8 power_settings_level[0x8]; 10168 10169 u8 reserved_at_20[0x60]; 10170 }; 10171 10172 struct mlx5_ifc_register_host_endianness_bits { 10173 u8 he[0x1]; 10174 u8 reserved_at_1[0x1f]; 10175 10176 u8 reserved_at_20[0x60]; 10177 }; 10178 10179 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10180 u8 reserved_at_0[0x20]; 10181 10182 u8 mkey[0x20]; 10183 10184 u8 addressh_63_32[0x20]; 10185 10186 u8 addressl_31_0[0x20]; 10187 }; 10188 10189 struct mlx5_ifc_ud_adrs_vector_bits { 10190 u8 dc_key[0x40]; 10191 10192 u8 ext[0x1]; 10193 u8 reserved_at_41[0x7]; 10194 u8 destination_qp_dct[0x18]; 10195 10196 u8 static_rate[0x4]; 10197 u8 sl_eth_prio[0x4]; 10198 u8 fl[0x1]; 10199 u8 mlid[0x7]; 10200 u8 rlid_udp_sport[0x10]; 10201 10202 u8 reserved_at_80[0x20]; 10203 10204 u8 rmac_47_16[0x20]; 10205 10206 u8 rmac_15_0[0x10]; 10207 u8 tclass[0x8]; 10208 u8 hop_limit[0x8]; 10209 10210 u8 reserved_at_e0[0x1]; 10211 u8 grh[0x1]; 10212 u8 reserved_at_e2[0x2]; 10213 u8 src_addr_index[0x8]; 10214 u8 flow_label[0x14]; 10215 10216 u8 rgid_rip[16][0x8]; 10217 }; 10218 10219 struct mlx5_ifc_pages_req_event_bits { 10220 u8 reserved_at_0[0x10]; 10221 u8 function_id[0x10]; 10222 10223 u8 num_pages[0x20]; 10224 10225 u8 reserved_at_40[0xa0]; 10226 }; 10227 10228 struct mlx5_ifc_eqe_bits { 10229 u8 reserved_at_0[0x8]; 10230 u8 event_type[0x8]; 10231 u8 reserved_at_10[0x8]; 10232 u8 event_sub_type[0x8]; 10233 10234 u8 reserved_at_20[0xe0]; 10235 10236 union mlx5_ifc_event_auto_bits event_data; 10237 10238 u8 reserved_at_1e0[0x10]; 10239 u8 signature[0x8]; 10240 u8 reserved_at_1f8[0x7]; 10241 u8 owner[0x1]; 10242 }; 10243 10244 enum { 10245 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10246 }; 10247 10248 struct mlx5_ifc_cmd_queue_entry_bits { 10249 u8 type[0x8]; 10250 u8 reserved_at_8[0x18]; 10251 10252 u8 input_length[0x20]; 10253 10254 u8 input_mailbox_pointer_63_32[0x20]; 10255 10256 u8 input_mailbox_pointer_31_9[0x17]; 10257 u8 reserved_at_77[0x9]; 10258 10259 u8 command_input_inline_data[16][0x8]; 10260 10261 u8 command_output_inline_data[16][0x8]; 10262 10263 u8 output_mailbox_pointer_63_32[0x20]; 10264 10265 u8 output_mailbox_pointer_31_9[0x17]; 10266 u8 reserved_at_1b7[0x9]; 10267 10268 u8 output_length[0x20]; 10269 10270 u8 token[0x8]; 10271 u8 signature[0x8]; 10272 u8 reserved_at_1f0[0x8]; 10273 u8 status[0x7]; 10274 u8 ownership[0x1]; 10275 }; 10276 10277 struct mlx5_ifc_cmd_out_bits { 10278 u8 status[0x8]; 10279 u8 reserved_at_8[0x18]; 10280 10281 u8 syndrome[0x20]; 10282 10283 u8 command_output[0x20]; 10284 }; 10285 10286 struct mlx5_ifc_cmd_in_bits { 10287 u8 opcode[0x10]; 10288 u8 reserved_at_10[0x10]; 10289 10290 u8 reserved_at_20[0x10]; 10291 u8 op_mod[0x10]; 10292 10293 u8 command[][0x20]; 10294 }; 10295 10296 struct mlx5_ifc_cmd_if_box_bits { 10297 u8 mailbox_data[512][0x8]; 10298 10299 u8 reserved_at_1000[0x180]; 10300 10301 u8 next_pointer_63_32[0x20]; 10302 10303 u8 next_pointer_31_10[0x16]; 10304 u8 reserved_at_11b6[0xa]; 10305 10306 u8 block_number[0x20]; 10307 10308 u8 reserved_at_11e0[0x8]; 10309 u8 token[0x8]; 10310 u8 ctrl_signature[0x8]; 10311 u8 signature[0x8]; 10312 }; 10313 10314 struct mlx5_ifc_mtt_bits { 10315 u8 ptag_63_32[0x20]; 10316 10317 u8 ptag_31_8[0x18]; 10318 u8 reserved_at_38[0x6]; 10319 u8 wr_en[0x1]; 10320 u8 rd_en[0x1]; 10321 }; 10322 10323 struct mlx5_ifc_query_wol_rol_out_bits { 10324 u8 status[0x8]; 10325 u8 reserved_at_8[0x18]; 10326 10327 u8 syndrome[0x20]; 10328 10329 u8 reserved_at_40[0x10]; 10330 u8 rol_mode[0x8]; 10331 u8 wol_mode[0x8]; 10332 10333 u8 reserved_at_60[0x20]; 10334 }; 10335 10336 struct mlx5_ifc_query_wol_rol_in_bits { 10337 u8 opcode[0x10]; 10338 u8 reserved_at_10[0x10]; 10339 10340 u8 reserved_at_20[0x10]; 10341 u8 op_mod[0x10]; 10342 10343 u8 reserved_at_40[0x40]; 10344 }; 10345 10346 struct mlx5_ifc_set_wol_rol_out_bits { 10347 u8 status[0x8]; 10348 u8 reserved_at_8[0x18]; 10349 10350 u8 syndrome[0x20]; 10351 10352 u8 reserved_at_40[0x40]; 10353 }; 10354 10355 struct mlx5_ifc_set_wol_rol_in_bits { 10356 u8 opcode[0x10]; 10357 u8 reserved_at_10[0x10]; 10358 10359 u8 reserved_at_20[0x10]; 10360 u8 op_mod[0x10]; 10361 10362 u8 rol_mode_valid[0x1]; 10363 u8 wol_mode_valid[0x1]; 10364 u8 reserved_at_42[0xe]; 10365 u8 rol_mode[0x8]; 10366 u8 wol_mode[0x8]; 10367 10368 u8 reserved_at_60[0x20]; 10369 }; 10370 10371 enum { 10372 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10373 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10374 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10375 }; 10376 10377 enum { 10378 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10379 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10380 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10381 }; 10382 10383 enum { 10384 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10385 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10386 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10387 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10388 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10389 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10390 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10391 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10392 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10393 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10394 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10395 }; 10396 10397 struct mlx5_ifc_initial_seg_bits { 10398 u8 fw_rev_minor[0x10]; 10399 u8 fw_rev_major[0x10]; 10400 10401 u8 cmd_interface_rev[0x10]; 10402 u8 fw_rev_subminor[0x10]; 10403 10404 u8 reserved_at_40[0x40]; 10405 10406 u8 cmdq_phy_addr_63_32[0x20]; 10407 10408 u8 cmdq_phy_addr_31_12[0x14]; 10409 u8 reserved_at_b4[0x2]; 10410 u8 nic_interface[0x2]; 10411 u8 log_cmdq_size[0x4]; 10412 u8 log_cmdq_stride[0x4]; 10413 10414 u8 command_doorbell_vector[0x20]; 10415 10416 u8 reserved_at_e0[0xf00]; 10417 10418 u8 initializing[0x1]; 10419 u8 reserved_at_fe1[0x4]; 10420 u8 nic_interface_supported[0x3]; 10421 u8 embedded_cpu[0x1]; 10422 u8 reserved_at_fe9[0x17]; 10423 10424 struct mlx5_ifc_health_buffer_bits health_buffer; 10425 10426 u8 no_dram_nic_offset[0x20]; 10427 10428 u8 reserved_at_1220[0x6e40]; 10429 10430 u8 reserved_at_8060[0x1f]; 10431 u8 clear_int[0x1]; 10432 10433 u8 health_syndrome[0x8]; 10434 u8 health_counter[0x18]; 10435 10436 u8 reserved_at_80a0[0x17fc0]; 10437 }; 10438 10439 struct mlx5_ifc_mtpps_reg_bits { 10440 u8 reserved_at_0[0xc]; 10441 u8 cap_number_of_pps_pins[0x4]; 10442 u8 reserved_at_10[0x4]; 10443 u8 cap_max_num_of_pps_in_pins[0x4]; 10444 u8 reserved_at_18[0x4]; 10445 u8 cap_max_num_of_pps_out_pins[0x4]; 10446 10447 u8 reserved_at_20[0x13]; 10448 u8 cap_log_min_npps_period[0x5]; 10449 u8 reserved_at_38[0x3]; 10450 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10451 10452 u8 reserved_at_40[0x4]; 10453 u8 cap_pin_3_mode[0x4]; 10454 u8 reserved_at_48[0x4]; 10455 u8 cap_pin_2_mode[0x4]; 10456 u8 reserved_at_50[0x4]; 10457 u8 cap_pin_1_mode[0x4]; 10458 u8 reserved_at_58[0x4]; 10459 u8 cap_pin_0_mode[0x4]; 10460 10461 u8 reserved_at_60[0x4]; 10462 u8 cap_pin_7_mode[0x4]; 10463 u8 reserved_at_68[0x4]; 10464 u8 cap_pin_6_mode[0x4]; 10465 u8 reserved_at_70[0x4]; 10466 u8 cap_pin_5_mode[0x4]; 10467 u8 reserved_at_78[0x4]; 10468 u8 cap_pin_4_mode[0x4]; 10469 10470 u8 field_select[0x20]; 10471 u8 reserved_at_a0[0x20]; 10472 10473 u8 npps_period[0x40]; 10474 10475 u8 enable[0x1]; 10476 u8 reserved_at_101[0xb]; 10477 u8 pattern[0x4]; 10478 u8 reserved_at_110[0x4]; 10479 u8 pin_mode[0x4]; 10480 u8 pin[0x8]; 10481 10482 u8 reserved_at_120[0x2]; 10483 u8 out_pulse_duration_ns[0x1e]; 10484 10485 u8 time_stamp[0x40]; 10486 10487 u8 out_pulse_duration[0x10]; 10488 u8 out_periodic_adjustment[0x10]; 10489 u8 enhanced_out_periodic_adjustment[0x20]; 10490 10491 u8 reserved_at_1c0[0x20]; 10492 }; 10493 10494 struct mlx5_ifc_mtppse_reg_bits { 10495 u8 reserved_at_0[0x18]; 10496 u8 pin[0x8]; 10497 u8 event_arm[0x1]; 10498 u8 reserved_at_21[0x1b]; 10499 u8 event_generation_mode[0x4]; 10500 u8 reserved_at_40[0x40]; 10501 }; 10502 10503 struct mlx5_ifc_mcqs_reg_bits { 10504 u8 last_index_flag[0x1]; 10505 u8 reserved_at_1[0x7]; 10506 u8 fw_device[0x8]; 10507 u8 component_index[0x10]; 10508 10509 u8 reserved_at_20[0x10]; 10510 u8 identifier[0x10]; 10511 10512 u8 reserved_at_40[0x17]; 10513 u8 component_status[0x5]; 10514 u8 component_update_state[0x4]; 10515 10516 u8 last_update_state_changer_type[0x4]; 10517 u8 last_update_state_changer_host_id[0x4]; 10518 u8 reserved_at_68[0x18]; 10519 }; 10520 10521 struct mlx5_ifc_mcqi_cap_bits { 10522 u8 supported_info_bitmask[0x20]; 10523 10524 u8 component_size[0x20]; 10525 10526 u8 max_component_size[0x20]; 10527 10528 u8 log_mcda_word_size[0x4]; 10529 u8 reserved_at_64[0xc]; 10530 u8 mcda_max_write_size[0x10]; 10531 10532 u8 rd_en[0x1]; 10533 u8 reserved_at_81[0x1]; 10534 u8 match_chip_id[0x1]; 10535 u8 match_psid[0x1]; 10536 u8 check_user_timestamp[0x1]; 10537 u8 match_base_guid_mac[0x1]; 10538 u8 reserved_at_86[0x1a]; 10539 }; 10540 10541 struct mlx5_ifc_mcqi_version_bits { 10542 u8 reserved_at_0[0x2]; 10543 u8 build_time_valid[0x1]; 10544 u8 user_defined_time_valid[0x1]; 10545 u8 reserved_at_4[0x14]; 10546 u8 version_string_length[0x8]; 10547 10548 u8 version[0x20]; 10549 10550 u8 build_time[0x40]; 10551 10552 u8 user_defined_time[0x40]; 10553 10554 u8 build_tool_version[0x20]; 10555 10556 u8 reserved_at_e0[0x20]; 10557 10558 u8 version_string[92][0x8]; 10559 }; 10560 10561 struct mlx5_ifc_mcqi_activation_method_bits { 10562 u8 pending_server_ac_power_cycle[0x1]; 10563 u8 pending_server_dc_power_cycle[0x1]; 10564 u8 pending_server_reboot[0x1]; 10565 u8 pending_fw_reset[0x1]; 10566 u8 auto_activate[0x1]; 10567 u8 all_hosts_sync[0x1]; 10568 u8 device_hw_reset[0x1]; 10569 u8 reserved_at_7[0x19]; 10570 }; 10571 10572 union mlx5_ifc_mcqi_reg_data_bits { 10573 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10574 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10575 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10576 }; 10577 10578 struct mlx5_ifc_mcqi_reg_bits { 10579 u8 read_pending_component[0x1]; 10580 u8 reserved_at_1[0xf]; 10581 u8 component_index[0x10]; 10582 10583 u8 reserved_at_20[0x20]; 10584 10585 u8 reserved_at_40[0x1b]; 10586 u8 info_type[0x5]; 10587 10588 u8 info_size[0x20]; 10589 10590 u8 offset[0x20]; 10591 10592 u8 reserved_at_a0[0x10]; 10593 u8 data_size[0x10]; 10594 10595 union mlx5_ifc_mcqi_reg_data_bits data[]; 10596 }; 10597 10598 struct mlx5_ifc_mcc_reg_bits { 10599 u8 reserved_at_0[0x4]; 10600 u8 time_elapsed_since_last_cmd[0xc]; 10601 u8 reserved_at_10[0x8]; 10602 u8 instruction[0x8]; 10603 10604 u8 reserved_at_20[0x10]; 10605 u8 component_index[0x10]; 10606 10607 u8 reserved_at_40[0x8]; 10608 u8 update_handle[0x18]; 10609 10610 u8 handle_owner_type[0x4]; 10611 u8 handle_owner_host_id[0x4]; 10612 u8 reserved_at_68[0x1]; 10613 u8 control_progress[0x7]; 10614 u8 error_code[0x8]; 10615 u8 reserved_at_78[0x4]; 10616 u8 control_state[0x4]; 10617 10618 u8 component_size[0x20]; 10619 10620 u8 reserved_at_a0[0x60]; 10621 }; 10622 10623 struct mlx5_ifc_mcda_reg_bits { 10624 u8 reserved_at_0[0x8]; 10625 u8 update_handle[0x18]; 10626 10627 u8 offset[0x20]; 10628 10629 u8 reserved_at_40[0x10]; 10630 u8 size[0x10]; 10631 10632 u8 reserved_at_60[0x20]; 10633 10634 u8 data[][0x20]; 10635 }; 10636 10637 enum { 10638 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10639 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10640 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10641 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10642 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10643 }; 10644 10645 enum { 10646 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10647 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10648 }; 10649 10650 enum { 10651 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10652 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10653 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10654 }; 10655 10656 struct mlx5_ifc_mfrl_reg_bits { 10657 u8 reserved_at_0[0x20]; 10658 10659 u8 reserved_at_20[0x2]; 10660 u8 pci_sync_for_fw_update_start[0x1]; 10661 u8 pci_sync_for_fw_update_resp[0x2]; 10662 u8 rst_type_sel[0x3]; 10663 u8 reserved_at_28[0x4]; 10664 u8 reset_state[0x4]; 10665 u8 reset_type[0x8]; 10666 u8 reset_level[0x8]; 10667 }; 10668 10669 struct mlx5_ifc_mirc_reg_bits { 10670 u8 reserved_at_0[0x18]; 10671 u8 status_code[0x8]; 10672 10673 u8 reserved_at_20[0x20]; 10674 }; 10675 10676 struct mlx5_ifc_pddr_monitor_opcode_bits { 10677 u8 reserved_at_0[0x10]; 10678 u8 monitor_opcode[0x10]; 10679 }; 10680 10681 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10682 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10683 u8 reserved_at_0[0x20]; 10684 }; 10685 10686 enum { 10687 /* Monitor opcodes */ 10688 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10689 }; 10690 10691 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10692 u8 reserved_at_0[0x10]; 10693 u8 group_opcode[0x10]; 10694 10695 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10696 10697 u8 reserved_at_40[0x20]; 10698 10699 u8 status_message[59][0x20]; 10700 }; 10701 10702 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10703 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10704 u8 reserved_at_0[0x7c0]; 10705 }; 10706 10707 enum { 10708 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10709 }; 10710 10711 struct mlx5_ifc_pddr_reg_bits { 10712 u8 reserved_at_0[0x8]; 10713 u8 local_port[0x8]; 10714 u8 pnat[0x2]; 10715 u8 reserved_at_12[0xe]; 10716 10717 u8 reserved_at_20[0x18]; 10718 u8 page_select[0x8]; 10719 10720 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10721 }; 10722 10723 struct mlx5_ifc_mrtc_reg_bits { 10724 u8 time_synced[0x1]; 10725 u8 reserved_at_1[0x1f]; 10726 10727 u8 reserved_at_20[0x20]; 10728 10729 u8 time_h[0x20]; 10730 10731 u8 time_l[0x20]; 10732 }; 10733 10734 union mlx5_ifc_ports_control_registers_document_bits { 10735 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10736 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10737 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10738 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10739 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10740 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10741 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10742 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10743 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10744 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10745 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10746 struct mlx5_ifc_paos_reg_bits paos_reg; 10747 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10748 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10749 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10750 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10751 struct mlx5_ifc_peir_reg_bits peir_reg; 10752 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10753 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10754 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10755 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10756 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10757 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10758 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10759 struct mlx5_ifc_plib_reg_bits plib_reg; 10760 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10761 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10762 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10763 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10764 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10765 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10766 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10767 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10768 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10769 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10770 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10771 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10772 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10773 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10774 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10775 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10776 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10777 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10778 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10779 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10780 struct mlx5_ifc_pude_reg_bits pude_reg; 10781 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10782 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10783 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10784 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10785 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10786 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10787 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10788 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10789 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10790 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10791 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10792 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10793 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10794 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10795 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10796 u8 reserved_at_0[0x60e0]; 10797 }; 10798 10799 union mlx5_ifc_debug_enhancements_document_bits { 10800 struct mlx5_ifc_health_buffer_bits health_buffer; 10801 u8 reserved_at_0[0x200]; 10802 }; 10803 10804 union mlx5_ifc_uplink_pci_interface_document_bits { 10805 struct mlx5_ifc_initial_seg_bits initial_seg; 10806 u8 reserved_at_0[0x20060]; 10807 }; 10808 10809 struct mlx5_ifc_set_flow_table_root_out_bits { 10810 u8 status[0x8]; 10811 u8 reserved_at_8[0x18]; 10812 10813 u8 syndrome[0x20]; 10814 10815 u8 reserved_at_40[0x40]; 10816 }; 10817 10818 struct mlx5_ifc_set_flow_table_root_in_bits { 10819 u8 opcode[0x10]; 10820 u8 reserved_at_10[0x10]; 10821 10822 u8 reserved_at_20[0x10]; 10823 u8 op_mod[0x10]; 10824 10825 u8 other_vport[0x1]; 10826 u8 reserved_at_41[0xf]; 10827 u8 vport_number[0x10]; 10828 10829 u8 reserved_at_60[0x20]; 10830 10831 u8 table_type[0x8]; 10832 u8 reserved_at_88[0x7]; 10833 u8 table_of_other_vport[0x1]; 10834 u8 table_vport_number[0x10]; 10835 10836 u8 reserved_at_a0[0x8]; 10837 u8 table_id[0x18]; 10838 10839 u8 reserved_at_c0[0x8]; 10840 u8 underlay_qpn[0x18]; 10841 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10842 u8 reserved_at_e1[0xf]; 10843 u8 table_eswitch_owner_vhca_id[0x10]; 10844 u8 reserved_at_100[0x100]; 10845 }; 10846 10847 enum { 10848 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10849 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10850 }; 10851 10852 struct mlx5_ifc_modify_flow_table_out_bits { 10853 u8 status[0x8]; 10854 u8 reserved_at_8[0x18]; 10855 10856 u8 syndrome[0x20]; 10857 10858 u8 reserved_at_40[0x40]; 10859 }; 10860 10861 struct mlx5_ifc_modify_flow_table_in_bits { 10862 u8 opcode[0x10]; 10863 u8 reserved_at_10[0x10]; 10864 10865 u8 reserved_at_20[0x10]; 10866 u8 op_mod[0x10]; 10867 10868 u8 other_vport[0x1]; 10869 u8 reserved_at_41[0xf]; 10870 u8 vport_number[0x10]; 10871 10872 u8 reserved_at_60[0x10]; 10873 u8 modify_field_select[0x10]; 10874 10875 u8 table_type[0x8]; 10876 u8 reserved_at_88[0x18]; 10877 10878 u8 reserved_at_a0[0x8]; 10879 u8 table_id[0x18]; 10880 10881 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10882 }; 10883 10884 struct mlx5_ifc_ets_tcn_config_reg_bits { 10885 u8 g[0x1]; 10886 u8 b[0x1]; 10887 u8 r[0x1]; 10888 u8 reserved_at_3[0x9]; 10889 u8 group[0x4]; 10890 u8 reserved_at_10[0x9]; 10891 u8 bw_allocation[0x7]; 10892 10893 u8 reserved_at_20[0xc]; 10894 u8 max_bw_units[0x4]; 10895 u8 reserved_at_30[0x8]; 10896 u8 max_bw_value[0x8]; 10897 }; 10898 10899 struct mlx5_ifc_ets_global_config_reg_bits { 10900 u8 reserved_at_0[0x2]; 10901 u8 r[0x1]; 10902 u8 reserved_at_3[0x1d]; 10903 10904 u8 reserved_at_20[0xc]; 10905 u8 max_bw_units[0x4]; 10906 u8 reserved_at_30[0x8]; 10907 u8 max_bw_value[0x8]; 10908 }; 10909 10910 struct mlx5_ifc_qetc_reg_bits { 10911 u8 reserved_at_0[0x8]; 10912 u8 port_number[0x8]; 10913 u8 reserved_at_10[0x30]; 10914 10915 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10916 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10917 }; 10918 10919 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10920 u8 e[0x1]; 10921 u8 reserved_at_01[0x0b]; 10922 u8 prio[0x04]; 10923 }; 10924 10925 struct mlx5_ifc_qpdpm_reg_bits { 10926 u8 reserved_at_0[0x8]; 10927 u8 local_port[0x8]; 10928 u8 reserved_at_10[0x10]; 10929 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10930 }; 10931 10932 struct mlx5_ifc_qpts_reg_bits { 10933 u8 reserved_at_0[0x8]; 10934 u8 local_port[0x8]; 10935 u8 reserved_at_10[0x2d]; 10936 u8 trust_state[0x3]; 10937 }; 10938 10939 struct mlx5_ifc_pptb_reg_bits { 10940 u8 reserved_at_0[0x2]; 10941 u8 mm[0x2]; 10942 u8 reserved_at_4[0x4]; 10943 u8 local_port[0x8]; 10944 u8 reserved_at_10[0x6]; 10945 u8 cm[0x1]; 10946 u8 um[0x1]; 10947 u8 pm[0x8]; 10948 10949 u8 prio_x_buff[0x20]; 10950 10951 u8 pm_msb[0x8]; 10952 u8 reserved_at_48[0x10]; 10953 u8 ctrl_buff[0x4]; 10954 u8 untagged_buff[0x4]; 10955 }; 10956 10957 struct mlx5_ifc_sbcam_reg_bits { 10958 u8 reserved_at_0[0x8]; 10959 u8 feature_group[0x8]; 10960 u8 reserved_at_10[0x8]; 10961 u8 access_reg_group[0x8]; 10962 10963 u8 reserved_at_20[0x20]; 10964 10965 u8 sb_access_reg_cap_mask[4][0x20]; 10966 10967 u8 reserved_at_c0[0x80]; 10968 10969 u8 sb_feature_cap_mask[4][0x20]; 10970 10971 u8 reserved_at_1c0[0x40]; 10972 10973 u8 cap_total_buffer_size[0x20]; 10974 10975 u8 cap_cell_size[0x10]; 10976 u8 cap_max_pg_buffers[0x8]; 10977 u8 cap_num_pool_supported[0x8]; 10978 10979 u8 reserved_at_240[0x8]; 10980 u8 cap_sbsr_stat_size[0x8]; 10981 u8 cap_max_tclass_data[0x8]; 10982 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10983 }; 10984 10985 struct mlx5_ifc_pbmc_reg_bits { 10986 u8 reserved_at_0[0x8]; 10987 u8 local_port[0x8]; 10988 u8 reserved_at_10[0x10]; 10989 10990 u8 xoff_timer_value[0x10]; 10991 u8 xoff_refresh[0x10]; 10992 10993 u8 reserved_at_40[0x9]; 10994 u8 fullness_threshold[0x7]; 10995 u8 port_buffer_size[0x10]; 10996 10997 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10998 10999 u8 reserved_at_2e0[0x80]; 11000 }; 11001 11002 struct mlx5_ifc_qtct_reg_bits { 11003 u8 reserved_at_0[0x8]; 11004 u8 port_number[0x8]; 11005 u8 reserved_at_10[0xd]; 11006 u8 prio[0x3]; 11007 11008 u8 reserved_at_20[0x1d]; 11009 u8 tclass[0x3]; 11010 }; 11011 11012 struct mlx5_ifc_mcia_reg_bits { 11013 u8 l[0x1]; 11014 u8 reserved_at_1[0x7]; 11015 u8 module[0x8]; 11016 u8 reserved_at_10[0x8]; 11017 u8 status[0x8]; 11018 11019 u8 i2c_device_address[0x8]; 11020 u8 page_number[0x8]; 11021 u8 device_address[0x10]; 11022 11023 u8 reserved_at_40[0x10]; 11024 u8 size[0x10]; 11025 11026 u8 reserved_at_60[0x20]; 11027 11028 u8 dword_0[0x20]; 11029 u8 dword_1[0x20]; 11030 u8 dword_2[0x20]; 11031 u8 dword_3[0x20]; 11032 u8 dword_4[0x20]; 11033 u8 dword_5[0x20]; 11034 u8 dword_6[0x20]; 11035 u8 dword_7[0x20]; 11036 u8 dword_8[0x20]; 11037 u8 dword_9[0x20]; 11038 u8 dword_10[0x20]; 11039 u8 dword_11[0x20]; 11040 }; 11041 11042 struct mlx5_ifc_dcbx_param_bits { 11043 u8 dcbx_cee_cap[0x1]; 11044 u8 dcbx_ieee_cap[0x1]; 11045 u8 dcbx_standby_cap[0x1]; 11046 u8 reserved_at_3[0x5]; 11047 u8 port_number[0x8]; 11048 u8 reserved_at_10[0xa]; 11049 u8 max_application_table_size[6]; 11050 u8 reserved_at_20[0x15]; 11051 u8 version_oper[0x3]; 11052 u8 reserved_at_38[5]; 11053 u8 version_admin[0x3]; 11054 u8 willing_admin[0x1]; 11055 u8 reserved_at_41[0x3]; 11056 u8 pfc_cap_oper[0x4]; 11057 u8 reserved_at_48[0x4]; 11058 u8 pfc_cap_admin[0x4]; 11059 u8 reserved_at_50[0x4]; 11060 u8 num_of_tc_oper[0x4]; 11061 u8 reserved_at_58[0x4]; 11062 u8 num_of_tc_admin[0x4]; 11063 u8 remote_willing[0x1]; 11064 u8 reserved_at_61[3]; 11065 u8 remote_pfc_cap[4]; 11066 u8 reserved_at_68[0x14]; 11067 u8 remote_num_of_tc[0x4]; 11068 u8 reserved_at_80[0x18]; 11069 u8 error[0x8]; 11070 u8 reserved_at_a0[0x160]; 11071 }; 11072 11073 enum { 11074 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11075 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11076 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11077 }; 11078 11079 struct mlx5_ifc_lagc_bits { 11080 u8 fdb_selection_mode[0x1]; 11081 u8 reserved_at_1[0x14]; 11082 u8 port_select_mode[0x3]; 11083 u8 reserved_at_18[0x5]; 11084 u8 lag_state[0x3]; 11085 11086 u8 reserved_at_20[0xc]; 11087 u8 active_port[0x4]; 11088 u8 reserved_at_30[0x4]; 11089 u8 tx_remap_affinity_2[0x4]; 11090 u8 reserved_at_38[0x4]; 11091 u8 tx_remap_affinity_1[0x4]; 11092 }; 11093 11094 struct mlx5_ifc_create_lag_out_bits { 11095 u8 status[0x8]; 11096 u8 reserved_at_8[0x18]; 11097 11098 u8 syndrome[0x20]; 11099 11100 u8 reserved_at_40[0x40]; 11101 }; 11102 11103 struct mlx5_ifc_create_lag_in_bits { 11104 u8 opcode[0x10]; 11105 u8 reserved_at_10[0x10]; 11106 11107 u8 reserved_at_20[0x10]; 11108 u8 op_mod[0x10]; 11109 11110 struct mlx5_ifc_lagc_bits ctx; 11111 }; 11112 11113 struct mlx5_ifc_modify_lag_out_bits { 11114 u8 status[0x8]; 11115 u8 reserved_at_8[0x18]; 11116 11117 u8 syndrome[0x20]; 11118 11119 u8 reserved_at_40[0x40]; 11120 }; 11121 11122 struct mlx5_ifc_modify_lag_in_bits { 11123 u8 opcode[0x10]; 11124 u8 reserved_at_10[0x10]; 11125 11126 u8 reserved_at_20[0x10]; 11127 u8 op_mod[0x10]; 11128 11129 u8 reserved_at_40[0x20]; 11130 u8 field_select[0x20]; 11131 11132 struct mlx5_ifc_lagc_bits ctx; 11133 }; 11134 11135 struct mlx5_ifc_query_lag_out_bits { 11136 u8 status[0x8]; 11137 u8 reserved_at_8[0x18]; 11138 11139 u8 syndrome[0x20]; 11140 11141 struct mlx5_ifc_lagc_bits ctx; 11142 }; 11143 11144 struct mlx5_ifc_query_lag_in_bits { 11145 u8 opcode[0x10]; 11146 u8 reserved_at_10[0x10]; 11147 11148 u8 reserved_at_20[0x10]; 11149 u8 op_mod[0x10]; 11150 11151 u8 reserved_at_40[0x40]; 11152 }; 11153 11154 struct mlx5_ifc_destroy_lag_out_bits { 11155 u8 status[0x8]; 11156 u8 reserved_at_8[0x18]; 11157 11158 u8 syndrome[0x20]; 11159 11160 u8 reserved_at_40[0x40]; 11161 }; 11162 11163 struct mlx5_ifc_destroy_lag_in_bits { 11164 u8 opcode[0x10]; 11165 u8 reserved_at_10[0x10]; 11166 11167 u8 reserved_at_20[0x10]; 11168 u8 op_mod[0x10]; 11169 11170 u8 reserved_at_40[0x40]; 11171 }; 11172 11173 struct mlx5_ifc_create_vport_lag_out_bits { 11174 u8 status[0x8]; 11175 u8 reserved_at_8[0x18]; 11176 11177 u8 syndrome[0x20]; 11178 11179 u8 reserved_at_40[0x40]; 11180 }; 11181 11182 struct mlx5_ifc_create_vport_lag_in_bits { 11183 u8 opcode[0x10]; 11184 u8 reserved_at_10[0x10]; 11185 11186 u8 reserved_at_20[0x10]; 11187 u8 op_mod[0x10]; 11188 11189 u8 reserved_at_40[0x40]; 11190 }; 11191 11192 struct mlx5_ifc_destroy_vport_lag_out_bits { 11193 u8 status[0x8]; 11194 u8 reserved_at_8[0x18]; 11195 11196 u8 syndrome[0x20]; 11197 11198 u8 reserved_at_40[0x40]; 11199 }; 11200 11201 struct mlx5_ifc_destroy_vport_lag_in_bits { 11202 u8 opcode[0x10]; 11203 u8 reserved_at_10[0x10]; 11204 11205 u8 reserved_at_20[0x10]; 11206 u8 op_mod[0x10]; 11207 11208 u8 reserved_at_40[0x40]; 11209 }; 11210 11211 enum { 11212 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11213 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11214 }; 11215 11216 struct mlx5_ifc_modify_memic_in_bits { 11217 u8 opcode[0x10]; 11218 u8 uid[0x10]; 11219 11220 u8 reserved_at_20[0x10]; 11221 u8 op_mod[0x10]; 11222 11223 u8 reserved_at_40[0x20]; 11224 11225 u8 reserved_at_60[0x18]; 11226 u8 memic_operation_type[0x8]; 11227 11228 u8 memic_start_addr[0x40]; 11229 11230 u8 reserved_at_c0[0x140]; 11231 }; 11232 11233 struct mlx5_ifc_modify_memic_out_bits { 11234 u8 status[0x8]; 11235 u8 reserved_at_8[0x18]; 11236 11237 u8 syndrome[0x20]; 11238 11239 u8 reserved_at_40[0x40]; 11240 11241 u8 memic_operation_addr[0x40]; 11242 11243 u8 reserved_at_c0[0x140]; 11244 }; 11245 11246 struct mlx5_ifc_alloc_memic_in_bits { 11247 u8 opcode[0x10]; 11248 u8 reserved_at_10[0x10]; 11249 11250 u8 reserved_at_20[0x10]; 11251 u8 op_mod[0x10]; 11252 11253 u8 reserved_at_30[0x20]; 11254 11255 u8 reserved_at_40[0x18]; 11256 u8 log_memic_addr_alignment[0x8]; 11257 11258 u8 range_start_addr[0x40]; 11259 11260 u8 range_size[0x20]; 11261 11262 u8 memic_size[0x20]; 11263 }; 11264 11265 struct mlx5_ifc_alloc_memic_out_bits { 11266 u8 status[0x8]; 11267 u8 reserved_at_8[0x18]; 11268 11269 u8 syndrome[0x20]; 11270 11271 u8 memic_start_addr[0x40]; 11272 }; 11273 11274 struct mlx5_ifc_dealloc_memic_in_bits { 11275 u8 opcode[0x10]; 11276 u8 reserved_at_10[0x10]; 11277 11278 u8 reserved_at_20[0x10]; 11279 u8 op_mod[0x10]; 11280 11281 u8 reserved_at_40[0x40]; 11282 11283 u8 memic_start_addr[0x40]; 11284 11285 u8 memic_size[0x20]; 11286 11287 u8 reserved_at_e0[0x20]; 11288 }; 11289 11290 struct mlx5_ifc_dealloc_memic_out_bits { 11291 u8 status[0x8]; 11292 u8 reserved_at_8[0x18]; 11293 11294 u8 syndrome[0x20]; 11295 11296 u8 reserved_at_40[0x40]; 11297 }; 11298 11299 struct mlx5_ifc_umem_bits { 11300 u8 reserved_at_0[0x80]; 11301 11302 u8 ats[0x1]; 11303 u8 reserved_at_81[0x1a]; 11304 u8 log_page_size[0x5]; 11305 11306 u8 page_offset[0x20]; 11307 11308 u8 num_of_mtt[0x40]; 11309 11310 struct mlx5_ifc_mtt_bits mtt[]; 11311 }; 11312 11313 struct mlx5_ifc_uctx_bits { 11314 u8 cap[0x20]; 11315 11316 u8 reserved_at_20[0x160]; 11317 }; 11318 11319 struct mlx5_ifc_sw_icm_bits { 11320 u8 modify_field_select[0x40]; 11321 11322 u8 reserved_at_40[0x18]; 11323 u8 log_sw_icm_size[0x8]; 11324 11325 u8 reserved_at_60[0x20]; 11326 11327 u8 sw_icm_start_addr[0x40]; 11328 11329 u8 reserved_at_c0[0x140]; 11330 }; 11331 11332 struct mlx5_ifc_geneve_tlv_option_bits { 11333 u8 modify_field_select[0x40]; 11334 11335 u8 reserved_at_40[0x18]; 11336 u8 geneve_option_fte_index[0x8]; 11337 11338 u8 option_class[0x10]; 11339 u8 option_type[0x8]; 11340 u8 reserved_at_78[0x3]; 11341 u8 option_data_length[0x5]; 11342 11343 u8 reserved_at_80[0x180]; 11344 }; 11345 11346 struct mlx5_ifc_create_umem_in_bits { 11347 u8 opcode[0x10]; 11348 u8 uid[0x10]; 11349 11350 u8 reserved_at_20[0x10]; 11351 u8 op_mod[0x10]; 11352 11353 u8 reserved_at_40[0x40]; 11354 11355 struct mlx5_ifc_umem_bits umem; 11356 }; 11357 11358 struct mlx5_ifc_create_umem_out_bits { 11359 u8 status[0x8]; 11360 u8 reserved_at_8[0x18]; 11361 11362 u8 syndrome[0x20]; 11363 11364 u8 reserved_at_40[0x8]; 11365 u8 umem_id[0x18]; 11366 11367 u8 reserved_at_60[0x20]; 11368 }; 11369 11370 struct mlx5_ifc_destroy_umem_in_bits { 11371 u8 opcode[0x10]; 11372 u8 uid[0x10]; 11373 11374 u8 reserved_at_20[0x10]; 11375 u8 op_mod[0x10]; 11376 11377 u8 reserved_at_40[0x8]; 11378 u8 umem_id[0x18]; 11379 11380 u8 reserved_at_60[0x20]; 11381 }; 11382 11383 struct mlx5_ifc_destroy_umem_out_bits { 11384 u8 status[0x8]; 11385 u8 reserved_at_8[0x18]; 11386 11387 u8 syndrome[0x20]; 11388 11389 u8 reserved_at_40[0x40]; 11390 }; 11391 11392 struct mlx5_ifc_create_uctx_in_bits { 11393 u8 opcode[0x10]; 11394 u8 reserved_at_10[0x10]; 11395 11396 u8 reserved_at_20[0x10]; 11397 u8 op_mod[0x10]; 11398 11399 u8 reserved_at_40[0x40]; 11400 11401 struct mlx5_ifc_uctx_bits uctx; 11402 }; 11403 11404 struct mlx5_ifc_create_uctx_out_bits { 11405 u8 status[0x8]; 11406 u8 reserved_at_8[0x18]; 11407 11408 u8 syndrome[0x20]; 11409 11410 u8 reserved_at_40[0x10]; 11411 u8 uid[0x10]; 11412 11413 u8 reserved_at_60[0x20]; 11414 }; 11415 11416 struct mlx5_ifc_destroy_uctx_in_bits { 11417 u8 opcode[0x10]; 11418 u8 reserved_at_10[0x10]; 11419 11420 u8 reserved_at_20[0x10]; 11421 u8 op_mod[0x10]; 11422 11423 u8 reserved_at_40[0x10]; 11424 u8 uid[0x10]; 11425 11426 u8 reserved_at_60[0x20]; 11427 }; 11428 11429 struct mlx5_ifc_destroy_uctx_out_bits { 11430 u8 status[0x8]; 11431 u8 reserved_at_8[0x18]; 11432 11433 u8 syndrome[0x20]; 11434 11435 u8 reserved_at_40[0x40]; 11436 }; 11437 11438 struct mlx5_ifc_create_sw_icm_in_bits { 11439 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11440 struct mlx5_ifc_sw_icm_bits sw_icm; 11441 }; 11442 11443 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11444 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11445 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11446 }; 11447 11448 struct mlx5_ifc_mtrc_string_db_param_bits { 11449 u8 string_db_base_address[0x20]; 11450 11451 u8 reserved_at_20[0x8]; 11452 u8 string_db_size[0x18]; 11453 }; 11454 11455 struct mlx5_ifc_mtrc_cap_bits { 11456 u8 trace_owner[0x1]; 11457 u8 trace_to_memory[0x1]; 11458 u8 reserved_at_2[0x4]; 11459 u8 trc_ver[0x2]; 11460 u8 reserved_at_8[0x14]; 11461 u8 num_string_db[0x4]; 11462 11463 u8 first_string_trace[0x8]; 11464 u8 num_string_trace[0x8]; 11465 u8 reserved_at_30[0x28]; 11466 11467 u8 log_max_trace_buffer_size[0x8]; 11468 11469 u8 reserved_at_60[0x20]; 11470 11471 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11472 11473 u8 reserved_at_280[0x180]; 11474 }; 11475 11476 struct mlx5_ifc_mtrc_conf_bits { 11477 u8 reserved_at_0[0x1c]; 11478 u8 trace_mode[0x4]; 11479 u8 reserved_at_20[0x18]; 11480 u8 log_trace_buffer_size[0x8]; 11481 u8 trace_mkey[0x20]; 11482 u8 reserved_at_60[0x3a0]; 11483 }; 11484 11485 struct mlx5_ifc_mtrc_stdb_bits { 11486 u8 string_db_index[0x4]; 11487 u8 reserved_at_4[0x4]; 11488 u8 read_size[0x18]; 11489 u8 start_offset[0x20]; 11490 u8 string_db_data[]; 11491 }; 11492 11493 struct mlx5_ifc_mtrc_ctrl_bits { 11494 u8 trace_status[0x2]; 11495 u8 reserved_at_2[0x2]; 11496 u8 arm_event[0x1]; 11497 u8 reserved_at_5[0xb]; 11498 u8 modify_field_select[0x10]; 11499 u8 reserved_at_20[0x2b]; 11500 u8 current_timestamp52_32[0x15]; 11501 u8 current_timestamp31_0[0x20]; 11502 u8 reserved_at_80[0x180]; 11503 }; 11504 11505 struct mlx5_ifc_host_params_context_bits { 11506 u8 host_number[0x8]; 11507 u8 reserved_at_8[0x7]; 11508 u8 host_pf_disabled[0x1]; 11509 u8 host_num_of_vfs[0x10]; 11510 11511 u8 host_total_vfs[0x10]; 11512 u8 host_pci_bus[0x10]; 11513 11514 u8 reserved_at_40[0x10]; 11515 u8 host_pci_device[0x10]; 11516 11517 u8 reserved_at_60[0x10]; 11518 u8 host_pci_function[0x10]; 11519 11520 u8 reserved_at_80[0x180]; 11521 }; 11522 11523 struct mlx5_ifc_query_esw_functions_in_bits { 11524 u8 opcode[0x10]; 11525 u8 reserved_at_10[0x10]; 11526 11527 u8 reserved_at_20[0x10]; 11528 u8 op_mod[0x10]; 11529 11530 u8 reserved_at_40[0x40]; 11531 }; 11532 11533 struct mlx5_ifc_query_esw_functions_out_bits { 11534 u8 status[0x8]; 11535 u8 reserved_at_8[0x18]; 11536 11537 u8 syndrome[0x20]; 11538 11539 u8 reserved_at_40[0x40]; 11540 11541 struct mlx5_ifc_host_params_context_bits host_params_context; 11542 11543 u8 reserved_at_280[0x180]; 11544 u8 host_sf_enable[][0x40]; 11545 }; 11546 11547 struct mlx5_ifc_sf_partition_bits { 11548 u8 reserved_at_0[0x10]; 11549 u8 log_num_sf[0x8]; 11550 u8 log_sf_bar_size[0x8]; 11551 }; 11552 11553 struct mlx5_ifc_query_sf_partitions_out_bits { 11554 u8 status[0x8]; 11555 u8 reserved_at_8[0x18]; 11556 11557 u8 syndrome[0x20]; 11558 11559 u8 reserved_at_40[0x18]; 11560 u8 num_sf_partitions[0x8]; 11561 11562 u8 reserved_at_60[0x20]; 11563 11564 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11565 }; 11566 11567 struct mlx5_ifc_query_sf_partitions_in_bits { 11568 u8 opcode[0x10]; 11569 u8 reserved_at_10[0x10]; 11570 11571 u8 reserved_at_20[0x10]; 11572 u8 op_mod[0x10]; 11573 11574 u8 reserved_at_40[0x40]; 11575 }; 11576 11577 struct mlx5_ifc_dealloc_sf_out_bits { 11578 u8 status[0x8]; 11579 u8 reserved_at_8[0x18]; 11580 11581 u8 syndrome[0x20]; 11582 11583 u8 reserved_at_40[0x40]; 11584 }; 11585 11586 struct mlx5_ifc_dealloc_sf_in_bits { 11587 u8 opcode[0x10]; 11588 u8 reserved_at_10[0x10]; 11589 11590 u8 reserved_at_20[0x10]; 11591 u8 op_mod[0x10]; 11592 11593 u8 reserved_at_40[0x10]; 11594 u8 function_id[0x10]; 11595 11596 u8 reserved_at_60[0x20]; 11597 }; 11598 11599 struct mlx5_ifc_alloc_sf_out_bits { 11600 u8 status[0x8]; 11601 u8 reserved_at_8[0x18]; 11602 11603 u8 syndrome[0x20]; 11604 11605 u8 reserved_at_40[0x40]; 11606 }; 11607 11608 struct mlx5_ifc_alloc_sf_in_bits { 11609 u8 opcode[0x10]; 11610 u8 reserved_at_10[0x10]; 11611 11612 u8 reserved_at_20[0x10]; 11613 u8 op_mod[0x10]; 11614 11615 u8 reserved_at_40[0x10]; 11616 u8 function_id[0x10]; 11617 11618 u8 reserved_at_60[0x20]; 11619 }; 11620 11621 struct mlx5_ifc_affiliated_event_header_bits { 11622 u8 reserved_at_0[0x10]; 11623 u8 obj_type[0x10]; 11624 11625 u8 obj_id[0x20]; 11626 }; 11627 11628 enum { 11629 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11630 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11631 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11632 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11633 }; 11634 11635 enum { 11636 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11637 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11638 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11639 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11640 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11641 }; 11642 11643 enum { 11644 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11645 }; 11646 11647 enum { 11648 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 11649 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 11650 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 11651 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 11652 }; 11653 11654 enum { 11655 MLX5_IPSEC_ASO_MODE = 0x0, 11656 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 11657 MLX5_IPSEC_ASO_INC_SN = 0x2, 11658 }; 11659 11660 struct mlx5_ifc_ipsec_aso_bits { 11661 u8 valid[0x1]; 11662 u8 reserved_at_201[0x1]; 11663 u8 mode[0x2]; 11664 u8 window_sz[0x2]; 11665 u8 soft_lft_arm[0x1]; 11666 u8 hard_lft_arm[0x1]; 11667 u8 remove_flow_enable[0x1]; 11668 u8 esn_event_arm[0x1]; 11669 u8 reserved_at_20a[0x16]; 11670 11671 u8 remove_flow_pkt_cnt[0x20]; 11672 11673 u8 remove_flow_soft_lft[0x20]; 11674 11675 u8 reserved_at_260[0x80]; 11676 11677 u8 mode_parameter[0x20]; 11678 11679 u8 replay_protection_window[0x100]; 11680 }; 11681 11682 struct mlx5_ifc_ipsec_obj_bits { 11683 u8 modify_field_select[0x40]; 11684 u8 full_offload[0x1]; 11685 u8 reserved_at_41[0x1]; 11686 u8 esn_en[0x1]; 11687 u8 esn_overlap[0x1]; 11688 u8 reserved_at_44[0x2]; 11689 u8 icv_length[0x2]; 11690 u8 reserved_at_48[0x4]; 11691 u8 aso_return_reg[0x4]; 11692 u8 reserved_at_50[0x10]; 11693 11694 u8 esn_msb[0x20]; 11695 11696 u8 reserved_at_80[0x8]; 11697 u8 dekn[0x18]; 11698 11699 u8 salt[0x20]; 11700 11701 u8 implicit_iv[0x40]; 11702 11703 u8 reserved_at_100[0x8]; 11704 u8 ipsec_aso_access_pd[0x18]; 11705 u8 reserved_at_120[0xe0]; 11706 11707 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 11708 }; 11709 11710 struct mlx5_ifc_create_ipsec_obj_in_bits { 11711 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11712 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11713 }; 11714 11715 enum { 11716 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11717 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11718 }; 11719 11720 struct mlx5_ifc_query_ipsec_obj_out_bits { 11721 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11722 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11723 }; 11724 11725 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11726 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11727 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11728 }; 11729 11730 enum { 11731 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 11732 }; 11733 11734 enum { 11735 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 11736 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 11737 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 11738 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 11739 }; 11740 11741 #define MLX5_MACSEC_ASO_INC_SN 0x2 11742 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 11743 11744 struct mlx5_ifc_macsec_aso_bits { 11745 u8 valid[0x1]; 11746 u8 reserved_at_1[0x1]; 11747 u8 mode[0x2]; 11748 u8 window_size[0x2]; 11749 u8 soft_lifetime_arm[0x1]; 11750 u8 hard_lifetime_arm[0x1]; 11751 u8 remove_flow_enable[0x1]; 11752 u8 epn_event_arm[0x1]; 11753 u8 reserved_at_a[0x16]; 11754 11755 u8 remove_flow_packet_count[0x20]; 11756 11757 u8 remove_flow_soft_lifetime[0x20]; 11758 11759 u8 reserved_at_60[0x80]; 11760 11761 u8 mode_parameter[0x20]; 11762 11763 u8 replay_protection_window[8][0x20]; 11764 }; 11765 11766 struct mlx5_ifc_macsec_offload_obj_bits { 11767 u8 modify_field_select[0x40]; 11768 11769 u8 confidentiality_en[0x1]; 11770 u8 reserved_at_41[0x1]; 11771 u8 epn_en[0x1]; 11772 u8 epn_overlap[0x1]; 11773 u8 reserved_at_44[0x2]; 11774 u8 confidentiality_offset[0x2]; 11775 u8 reserved_at_48[0x4]; 11776 u8 aso_return_reg[0x4]; 11777 u8 reserved_at_50[0x10]; 11778 11779 u8 epn_msb[0x20]; 11780 11781 u8 reserved_at_80[0x8]; 11782 u8 dekn[0x18]; 11783 11784 u8 reserved_at_a0[0x20]; 11785 11786 u8 sci[0x40]; 11787 11788 u8 reserved_at_100[0x8]; 11789 u8 macsec_aso_access_pd[0x18]; 11790 11791 u8 reserved_at_120[0x60]; 11792 11793 u8 salt[3][0x20]; 11794 11795 u8 reserved_at_1e0[0x20]; 11796 11797 struct mlx5_ifc_macsec_aso_bits macsec_aso; 11798 }; 11799 11800 struct mlx5_ifc_create_macsec_obj_in_bits { 11801 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11802 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11803 }; 11804 11805 struct mlx5_ifc_modify_macsec_obj_in_bits { 11806 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11807 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11808 }; 11809 11810 enum { 11811 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 11812 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 11813 }; 11814 11815 struct mlx5_ifc_query_macsec_obj_out_bits { 11816 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11817 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11818 }; 11819 11820 struct mlx5_ifc_encryption_key_obj_bits { 11821 u8 modify_field_select[0x40]; 11822 11823 u8 reserved_at_40[0x14]; 11824 u8 key_size[0x4]; 11825 u8 reserved_at_58[0x4]; 11826 u8 key_type[0x4]; 11827 11828 u8 reserved_at_60[0x8]; 11829 u8 pd[0x18]; 11830 11831 u8 reserved_at_80[0x180]; 11832 u8 key[8][0x20]; 11833 11834 u8 reserved_at_300[0x500]; 11835 }; 11836 11837 struct mlx5_ifc_create_encryption_key_in_bits { 11838 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11839 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11840 }; 11841 11842 enum { 11843 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 11844 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 11845 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 11846 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 11847 }; 11848 11849 struct mlx5_ifc_flow_meter_parameters_bits { 11850 u8 valid[0x1]; 11851 u8 bucket_overflow[0x1]; 11852 u8 start_color[0x2]; 11853 u8 both_buckets_on_green[0x1]; 11854 u8 reserved_at_5[0x1]; 11855 u8 meter_mode[0x2]; 11856 u8 reserved_at_8[0x18]; 11857 11858 u8 reserved_at_20[0x20]; 11859 11860 u8 reserved_at_40[0x3]; 11861 u8 cbs_exponent[0x5]; 11862 u8 cbs_mantissa[0x8]; 11863 u8 reserved_at_50[0x3]; 11864 u8 cir_exponent[0x5]; 11865 u8 cir_mantissa[0x8]; 11866 11867 u8 reserved_at_60[0x20]; 11868 11869 u8 reserved_at_80[0x3]; 11870 u8 ebs_exponent[0x5]; 11871 u8 ebs_mantissa[0x8]; 11872 u8 reserved_at_90[0x3]; 11873 u8 eir_exponent[0x5]; 11874 u8 eir_mantissa[0x8]; 11875 11876 u8 reserved_at_a0[0x60]; 11877 }; 11878 11879 struct mlx5_ifc_flow_meter_aso_obj_bits { 11880 u8 modify_field_select[0x40]; 11881 11882 u8 reserved_at_40[0x40]; 11883 11884 u8 reserved_at_80[0x8]; 11885 u8 meter_aso_access_pd[0x18]; 11886 11887 u8 reserved_at_a0[0x160]; 11888 11889 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 11890 }; 11891 11892 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 11893 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11894 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 11895 }; 11896 11897 struct mlx5_ifc_sampler_obj_bits { 11898 u8 modify_field_select[0x40]; 11899 11900 u8 table_type[0x8]; 11901 u8 level[0x8]; 11902 u8 reserved_at_50[0xf]; 11903 u8 ignore_flow_level[0x1]; 11904 11905 u8 sample_ratio[0x20]; 11906 11907 u8 reserved_at_80[0x8]; 11908 u8 sample_table_id[0x18]; 11909 11910 u8 reserved_at_a0[0x8]; 11911 u8 default_table_id[0x18]; 11912 11913 u8 sw_steering_icm_address_rx[0x40]; 11914 u8 sw_steering_icm_address_tx[0x40]; 11915 11916 u8 reserved_at_140[0xa0]; 11917 }; 11918 11919 struct mlx5_ifc_create_sampler_obj_in_bits { 11920 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11921 struct mlx5_ifc_sampler_obj_bits sampler_object; 11922 }; 11923 11924 struct mlx5_ifc_query_sampler_obj_out_bits { 11925 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11926 struct mlx5_ifc_sampler_obj_bits sampler_object; 11927 }; 11928 11929 enum { 11930 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11931 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11932 }; 11933 11934 enum { 11935 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11936 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11937 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_MACSEC = 0x4, 11938 }; 11939 11940 struct mlx5_ifc_tls_static_params_bits { 11941 u8 const_2[0x2]; 11942 u8 tls_version[0x4]; 11943 u8 const_1[0x2]; 11944 u8 reserved_at_8[0x14]; 11945 u8 encryption_standard[0x4]; 11946 11947 u8 reserved_at_20[0x20]; 11948 11949 u8 initial_record_number[0x40]; 11950 11951 u8 resync_tcp_sn[0x20]; 11952 11953 u8 gcm_iv[0x20]; 11954 11955 u8 implicit_iv[0x40]; 11956 11957 u8 reserved_at_100[0x8]; 11958 u8 dek_index[0x18]; 11959 11960 u8 reserved_at_120[0xe0]; 11961 }; 11962 11963 struct mlx5_ifc_tls_progress_params_bits { 11964 u8 next_record_tcp_sn[0x20]; 11965 11966 u8 hw_resync_tcp_sn[0x20]; 11967 11968 u8 record_tracker_state[0x2]; 11969 u8 auth_state[0x2]; 11970 u8 reserved_at_44[0x4]; 11971 u8 hw_offset_record_number[0x18]; 11972 }; 11973 11974 enum { 11975 MLX5_MTT_PERM_READ = 1 << 0, 11976 MLX5_MTT_PERM_WRITE = 1 << 1, 11977 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11978 }; 11979 11980 enum { 11981 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11982 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11983 }; 11984 11985 struct mlx5_ifc_suspend_vhca_in_bits { 11986 u8 opcode[0x10]; 11987 u8 uid[0x10]; 11988 11989 u8 reserved_at_20[0x10]; 11990 u8 op_mod[0x10]; 11991 11992 u8 reserved_at_40[0x10]; 11993 u8 vhca_id[0x10]; 11994 11995 u8 reserved_at_60[0x20]; 11996 }; 11997 11998 struct mlx5_ifc_suspend_vhca_out_bits { 11999 u8 status[0x8]; 12000 u8 reserved_at_8[0x18]; 12001 12002 u8 syndrome[0x20]; 12003 12004 u8 reserved_at_40[0x40]; 12005 }; 12006 12007 enum { 12008 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12009 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12010 }; 12011 12012 struct mlx5_ifc_resume_vhca_in_bits { 12013 u8 opcode[0x10]; 12014 u8 uid[0x10]; 12015 12016 u8 reserved_at_20[0x10]; 12017 u8 op_mod[0x10]; 12018 12019 u8 reserved_at_40[0x10]; 12020 u8 vhca_id[0x10]; 12021 12022 u8 reserved_at_60[0x20]; 12023 }; 12024 12025 struct mlx5_ifc_resume_vhca_out_bits { 12026 u8 status[0x8]; 12027 u8 reserved_at_8[0x18]; 12028 12029 u8 syndrome[0x20]; 12030 12031 u8 reserved_at_40[0x40]; 12032 }; 12033 12034 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12035 u8 opcode[0x10]; 12036 u8 uid[0x10]; 12037 12038 u8 reserved_at_20[0x10]; 12039 u8 op_mod[0x10]; 12040 12041 u8 incremental[0x1]; 12042 u8 reserved_at_41[0xf]; 12043 u8 vhca_id[0x10]; 12044 12045 u8 reserved_at_60[0x20]; 12046 }; 12047 12048 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12049 u8 status[0x8]; 12050 u8 reserved_at_8[0x18]; 12051 12052 u8 syndrome[0x20]; 12053 12054 u8 reserved_at_40[0x40]; 12055 12056 u8 required_umem_size[0x20]; 12057 12058 u8 reserved_at_a0[0x160]; 12059 }; 12060 12061 struct mlx5_ifc_save_vhca_state_in_bits { 12062 u8 opcode[0x10]; 12063 u8 uid[0x10]; 12064 12065 u8 reserved_at_20[0x10]; 12066 u8 op_mod[0x10]; 12067 12068 u8 incremental[0x1]; 12069 u8 set_track[0x1]; 12070 u8 reserved_at_42[0xe]; 12071 u8 vhca_id[0x10]; 12072 12073 u8 reserved_at_60[0x20]; 12074 12075 u8 va[0x40]; 12076 12077 u8 mkey[0x20]; 12078 12079 u8 size[0x20]; 12080 }; 12081 12082 struct mlx5_ifc_save_vhca_state_out_bits { 12083 u8 status[0x8]; 12084 u8 reserved_at_8[0x18]; 12085 12086 u8 syndrome[0x20]; 12087 12088 u8 actual_image_size[0x20]; 12089 12090 u8 reserved_at_60[0x20]; 12091 }; 12092 12093 struct mlx5_ifc_load_vhca_state_in_bits { 12094 u8 opcode[0x10]; 12095 u8 uid[0x10]; 12096 12097 u8 reserved_at_20[0x10]; 12098 u8 op_mod[0x10]; 12099 12100 u8 reserved_at_40[0x10]; 12101 u8 vhca_id[0x10]; 12102 12103 u8 reserved_at_60[0x20]; 12104 12105 u8 va[0x40]; 12106 12107 u8 mkey[0x20]; 12108 12109 u8 size[0x20]; 12110 }; 12111 12112 struct mlx5_ifc_load_vhca_state_out_bits { 12113 u8 status[0x8]; 12114 u8 reserved_at_8[0x18]; 12115 12116 u8 syndrome[0x20]; 12117 12118 u8 reserved_at_40[0x40]; 12119 }; 12120 12121 struct mlx5_ifc_adv_virtualization_cap_bits { 12122 u8 reserved_at_0[0x3]; 12123 u8 pg_track_log_max_num[0x5]; 12124 u8 pg_track_max_num_range[0x8]; 12125 u8 pg_track_log_min_addr_space[0x8]; 12126 u8 pg_track_log_max_addr_space[0x8]; 12127 12128 u8 reserved_at_20[0x3]; 12129 u8 pg_track_log_min_msg_size[0x5]; 12130 u8 reserved_at_28[0x3]; 12131 u8 pg_track_log_max_msg_size[0x5]; 12132 u8 reserved_at_30[0x3]; 12133 u8 pg_track_log_min_page_size[0x5]; 12134 u8 reserved_at_38[0x3]; 12135 u8 pg_track_log_max_page_size[0x5]; 12136 12137 u8 reserved_at_40[0x7c0]; 12138 }; 12139 12140 struct mlx5_ifc_page_track_report_entry_bits { 12141 u8 dirty_address_high[0x20]; 12142 12143 u8 dirty_address_low[0x20]; 12144 }; 12145 12146 enum { 12147 MLX5_PAGE_TRACK_STATE_TRACKING, 12148 MLX5_PAGE_TRACK_STATE_REPORTING, 12149 MLX5_PAGE_TRACK_STATE_ERROR, 12150 }; 12151 12152 struct mlx5_ifc_page_track_range_bits { 12153 u8 start_address[0x40]; 12154 12155 u8 length[0x40]; 12156 }; 12157 12158 struct mlx5_ifc_page_track_bits { 12159 u8 modify_field_select[0x40]; 12160 12161 u8 reserved_at_40[0x10]; 12162 u8 vhca_id[0x10]; 12163 12164 u8 reserved_at_60[0x20]; 12165 12166 u8 state[0x4]; 12167 u8 track_type[0x4]; 12168 u8 log_addr_space_size[0x8]; 12169 u8 reserved_at_90[0x3]; 12170 u8 log_page_size[0x5]; 12171 u8 reserved_at_98[0x3]; 12172 u8 log_msg_size[0x5]; 12173 12174 u8 reserved_at_a0[0x8]; 12175 u8 reporting_qpn[0x18]; 12176 12177 u8 reserved_at_c0[0x18]; 12178 u8 num_ranges[0x8]; 12179 12180 u8 reserved_at_e0[0x20]; 12181 12182 u8 range_start_address[0x40]; 12183 12184 u8 length[0x40]; 12185 12186 struct mlx5_ifc_page_track_range_bits track_range[0]; 12187 }; 12188 12189 struct mlx5_ifc_create_page_track_obj_in_bits { 12190 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12191 struct mlx5_ifc_page_track_bits obj_context; 12192 }; 12193 12194 struct mlx5_ifc_modify_page_track_obj_in_bits { 12195 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12196 struct mlx5_ifc_page_track_bits obj_context; 12197 }; 12198 12199 #endif /* MLX5_IFC_H */ 12200