1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 enum { 36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb 60 }; 61 62 enum { 63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 67 }; 68 69 enum { 70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 72 }; 73 74 enum { 75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 77 MLX5_CMD_OP_INIT_HCA = 0x102, 78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 79 MLX5_CMD_OP_ENABLE_HCA = 0x104, 80 MLX5_CMD_OP_DISABLE_HCA = 0x105, 81 MLX5_CMD_OP_QUERY_PAGES = 0x107, 82 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 83 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 85 MLX5_CMD_OP_SET_ISSI = 0x10b, 86 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 87 MLX5_CMD_OP_CREATE_MKEY = 0x200, 88 MLX5_CMD_OP_QUERY_MKEY = 0x201, 89 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 90 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 91 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 92 MLX5_CMD_OP_CREATE_EQ = 0x301, 93 MLX5_CMD_OP_DESTROY_EQ = 0x302, 94 MLX5_CMD_OP_QUERY_EQ = 0x303, 95 MLX5_CMD_OP_GEN_EQE = 0x304, 96 MLX5_CMD_OP_CREATE_CQ = 0x400, 97 MLX5_CMD_OP_DESTROY_CQ = 0x401, 98 MLX5_CMD_OP_QUERY_CQ = 0x402, 99 MLX5_CMD_OP_MODIFY_CQ = 0x403, 100 MLX5_CMD_OP_CREATE_QP = 0x500, 101 MLX5_CMD_OP_DESTROY_QP = 0x501, 102 MLX5_CMD_OP_RST2INIT_QP = 0x502, 103 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 104 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 105 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 106 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 107 MLX5_CMD_OP_2ERR_QP = 0x507, 108 MLX5_CMD_OP_2RST_QP = 0x50a, 109 MLX5_CMD_OP_QUERY_QP = 0x50b, 110 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 111 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 112 MLX5_CMD_OP_CREATE_PSV = 0x600, 113 MLX5_CMD_OP_DESTROY_PSV = 0x601, 114 MLX5_CMD_OP_CREATE_SRQ = 0x700, 115 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 116 MLX5_CMD_OP_QUERY_SRQ = 0x702, 117 MLX5_CMD_OP_ARM_RQ = 0x703, 118 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 119 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 120 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 121 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 122 MLX5_CMD_OP_CREATE_DCT = 0x710, 123 MLX5_CMD_OP_DESTROY_DCT = 0x711, 124 MLX5_CMD_OP_DRAIN_DCT = 0x712, 125 MLX5_CMD_OP_QUERY_DCT = 0x713, 126 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 127 MLX5_CMD_OP_CREATE_XRQ = 0x717, 128 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 129 MLX5_CMD_OP_QUERY_XRQ = 0x719, 130 MLX5_CMD_OP_ARM_XRQ = 0x71a, 131 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 132 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 133 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 134 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 135 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 136 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 137 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 138 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 139 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 140 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 141 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 142 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 143 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 144 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 145 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 146 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 147 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 148 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 149 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 150 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 151 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 152 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 153 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 154 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 155 MLX5_CMD_OP_ALLOC_PD = 0x800, 156 MLX5_CMD_OP_DEALLOC_PD = 0x801, 157 MLX5_CMD_OP_ALLOC_UAR = 0x802, 158 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 159 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 160 MLX5_CMD_OP_ACCESS_REG = 0x805, 161 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 162 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 163 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 164 MLX5_CMD_OP_MAD_IFC = 0x50d, 165 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 166 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 167 MLX5_CMD_OP_NOP = 0x80d, 168 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 169 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 170 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 171 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 172 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 173 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 174 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 175 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 176 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 177 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 178 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 179 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 180 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 181 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 182 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 183 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 184 MLX5_CMD_OP_CREATE_LAG = 0x840, 185 MLX5_CMD_OP_MODIFY_LAG = 0x841, 186 MLX5_CMD_OP_QUERY_LAG = 0x842, 187 MLX5_CMD_OP_DESTROY_LAG = 0x843, 188 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 189 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 190 MLX5_CMD_OP_CREATE_TIR = 0x900, 191 MLX5_CMD_OP_MODIFY_TIR = 0x901, 192 MLX5_CMD_OP_DESTROY_TIR = 0x902, 193 MLX5_CMD_OP_QUERY_TIR = 0x903, 194 MLX5_CMD_OP_CREATE_SQ = 0x904, 195 MLX5_CMD_OP_MODIFY_SQ = 0x905, 196 MLX5_CMD_OP_DESTROY_SQ = 0x906, 197 MLX5_CMD_OP_QUERY_SQ = 0x907, 198 MLX5_CMD_OP_CREATE_RQ = 0x908, 199 MLX5_CMD_OP_MODIFY_RQ = 0x909, 200 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 201 MLX5_CMD_OP_QUERY_RQ = 0x90b, 202 MLX5_CMD_OP_CREATE_RMP = 0x90c, 203 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 204 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 205 MLX5_CMD_OP_QUERY_RMP = 0x90f, 206 MLX5_CMD_OP_CREATE_TIS = 0x912, 207 MLX5_CMD_OP_MODIFY_TIS = 0x913, 208 MLX5_CMD_OP_DESTROY_TIS = 0x914, 209 MLX5_CMD_OP_QUERY_TIS = 0x915, 210 MLX5_CMD_OP_CREATE_RQT = 0x916, 211 MLX5_CMD_OP_MODIFY_RQT = 0x917, 212 MLX5_CMD_OP_DESTROY_RQT = 0x918, 213 MLX5_CMD_OP_QUERY_RQT = 0x919, 214 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 215 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 216 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 217 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 218 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 219 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 220 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 221 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 222 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 223 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 224 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 225 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 226 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 227 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 228 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 229 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 230 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 231 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 232 MLX5_CMD_OP_MAX 233 }; 234 235 struct mlx5_ifc_flow_table_fields_supported_bits { 236 u8 outer_dmac[0x1]; 237 u8 outer_smac[0x1]; 238 u8 outer_ether_type[0x1]; 239 u8 outer_ip_version[0x1]; 240 u8 outer_first_prio[0x1]; 241 u8 outer_first_cfi[0x1]; 242 u8 outer_first_vid[0x1]; 243 u8 reserved_at_7[0x1]; 244 u8 outer_second_prio[0x1]; 245 u8 outer_second_cfi[0x1]; 246 u8 outer_second_vid[0x1]; 247 u8 reserved_at_b[0x1]; 248 u8 outer_sip[0x1]; 249 u8 outer_dip[0x1]; 250 u8 outer_frag[0x1]; 251 u8 outer_ip_protocol[0x1]; 252 u8 outer_ip_ecn[0x1]; 253 u8 outer_ip_dscp[0x1]; 254 u8 outer_udp_sport[0x1]; 255 u8 outer_udp_dport[0x1]; 256 u8 outer_tcp_sport[0x1]; 257 u8 outer_tcp_dport[0x1]; 258 u8 outer_tcp_flags[0x1]; 259 u8 outer_gre_protocol[0x1]; 260 u8 outer_gre_key[0x1]; 261 u8 outer_vxlan_vni[0x1]; 262 u8 reserved_at_1a[0x5]; 263 u8 source_eswitch_port[0x1]; 264 265 u8 inner_dmac[0x1]; 266 u8 inner_smac[0x1]; 267 u8 inner_ether_type[0x1]; 268 u8 inner_ip_version[0x1]; 269 u8 inner_first_prio[0x1]; 270 u8 inner_first_cfi[0x1]; 271 u8 inner_first_vid[0x1]; 272 u8 reserved_at_27[0x1]; 273 u8 inner_second_prio[0x1]; 274 u8 inner_second_cfi[0x1]; 275 u8 inner_second_vid[0x1]; 276 u8 reserved_at_2b[0x1]; 277 u8 inner_sip[0x1]; 278 u8 inner_dip[0x1]; 279 u8 inner_frag[0x1]; 280 u8 inner_ip_protocol[0x1]; 281 u8 inner_ip_ecn[0x1]; 282 u8 inner_ip_dscp[0x1]; 283 u8 inner_udp_sport[0x1]; 284 u8 inner_udp_dport[0x1]; 285 u8 inner_tcp_sport[0x1]; 286 u8 inner_tcp_dport[0x1]; 287 u8 inner_tcp_flags[0x1]; 288 u8 reserved_at_37[0x9]; 289 290 u8 reserved_at_40[0x40]; 291 }; 292 293 struct mlx5_ifc_flow_table_prop_layout_bits { 294 u8 ft_support[0x1]; 295 u8 reserved_at_1[0x1]; 296 u8 flow_counter[0x1]; 297 u8 flow_modify_en[0x1]; 298 u8 modify_root[0x1]; 299 u8 identified_miss_table_mode[0x1]; 300 u8 flow_table_modify[0x1]; 301 u8 encap[0x1]; 302 u8 decap[0x1]; 303 u8 reserved_at_9[0x17]; 304 305 u8 reserved_at_20[0x2]; 306 u8 log_max_ft_size[0x6]; 307 u8 log_max_modify_header_context[0x8]; 308 u8 max_modify_header_actions[0x8]; 309 u8 max_ft_level[0x8]; 310 311 u8 reserved_at_40[0x20]; 312 313 u8 reserved_at_60[0x18]; 314 u8 log_max_ft_num[0x8]; 315 316 u8 reserved_at_80[0x18]; 317 u8 log_max_destination[0x8]; 318 319 u8 reserved_at_a0[0x18]; 320 u8 log_max_flow[0x8]; 321 322 u8 reserved_at_c0[0x40]; 323 324 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 325 326 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 327 }; 328 329 struct mlx5_ifc_odp_per_transport_service_cap_bits { 330 u8 send[0x1]; 331 u8 receive[0x1]; 332 u8 write[0x1]; 333 u8 read[0x1]; 334 u8 atomic[0x1]; 335 u8 srq_receive[0x1]; 336 u8 reserved_at_6[0x1a]; 337 }; 338 339 struct mlx5_ifc_ipv4_layout_bits { 340 u8 reserved_at_0[0x60]; 341 342 u8 ipv4[0x20]; 343 }; 344 345 struct mlx5_ifc_ipv6_layout_bits { 346 u8 ipv6[16][0x8]; 347 }; 348 349 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 350 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 351 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 352 u8 reserved_at_0[0x80]; 353 }; 354 355 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 356 u8 smac_47_16[0x20]; 357 358 u8 smac_15_0[0x10]; 359 u8 ethertype[0x10]; 360 361 u8 dmac_47_16[0x20]; 362 363 u8 dmac_15_0[0x10]; 364 u8 first_prio[0x3]; 365 u8 first_cfi[0x1]; 366 u8 first_vid[0xc]; 367 368 u8 ip_protocol[0x8]; 369 u8 ip_dscp[0x6]; 370 u8 ip_ecn[0x2]; 371 u8 cvlan_tag[0x1]; 372 u8 svlan_tag[0x1]; 373 u8 frag[0x1]; 374 u8 ip_version[0x4]; 375 u8 tcp_flags[0x9]; 376 377 u8 tcp_sport[0x10]; 378 u8 tcp_dport[0x10]; 379 380 u8 reserved_at_c0[0x20]; 381 382 u8 udp_sport[0x10]; 383 u8 udp_dport[0x10]; 384 385 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 386 387 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 388 }; 389 390 struct mlx5_ifc_fte_match_set_misc_bits { 391 u8 reserved_at_0[0x8]; 392 u8 source_sqn[0x18]; 393 394 u8 reserved_at_20[0x10]; 395 u8 source_port[0x10]; 396 397 u8 outer_second_prio[0x3]; 398 u8 outer_second_cfi[0x1]; 399 u8 outer_second_vid[0xc]; 400 u8 inner_second_prio[0x3]; 401 u8 inner_second_cfi[0x1]; 402 u8 inner_second_vid[0xc]; 403 404 u8 outer_second_cvlan_tag[0x1]; 405 u8 inner_second_cvlan_tag[0x1]; 406 u8 outer_second_svlan_tag[0x1]; 407 u8 inner_second_svlan_tag[0x1]; 408 u8 reserved_at_64[0xc]; 409 u8 gre_protocol[0x10]; 410 411 u8 gre_key_h[0x18]; 412 u8 gre_key_l[0x8]; 413 414 u8 vxlan_vni[0x18]; 415 u8 reserved_at_b8[0x8]; 416 417 u8 reserved_at_c0[0x20]; 418 419 u8 reserved_at_e0[0xc]; 420 u8 outer_ipv6_flow_label[0x14]; 421 422 u8 reserved_at_100[0xc]; 423 u8 inner_ipv6_flow_label[0x14]; 424 425 u8 reserved_at_120[0xe0]; 426 }; 427 428 struct mlx5_ifc_cmd_pas_bits { 429 u8 pa_h[0x20]; 430 431 u8 pa_l[0x14]; 432 u8 reserved_at_34[0xc]; 433 }; 434 435 struct mlx5_ifc_uint64_bits { 436 u8 hi[0x20]; 437 438 u8 lo[0x20]; 439 }; 440 441 enum { 442 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 443 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 444 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 445 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 446 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 447 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 448 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 449 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 450 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 451 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 452 }; 453 454 struct mlx5_ifc_ads_bits { 455 u8 fl[0x1]; 456 u8 free_ar[0x1]; 457 u8 reserved_at_2[0xe]; 458 u8 pkey_index[0x10]; 459 460 u8 reserved_at_20[0x8]; 461 u8 grh[0x1]; 462 u8 mlid[0x7]; 463 u8 rlid[0x10]; 464 465 u8 ack_timeout[0x5]; 466 u8 reserved_at_45[0x3]; 467 u8 src_addr_index[0x8]; 468 u8 reserved_at_50[0x4]; 469 u8 stat_rate[0x4]; 470 u8 hop_limit[0x8]; 471 472 u8 reserved_at_60[0x4]; 473 u8 tclass[0x8]; 474 u8 flow_label[0x14]; 475 476 u8 rgid_rip[16][0x8]; 477 478 u8 reserved_at_100[0x4]; 479 u8 f_dscp[0x1]; 480 u8 f_ecn[0x1]; 481 u8 reserved_at_106[0x1]; 482 u8 f_eth_prio[0x1]; 483 u8 ecn[0x2]; 484 u8 dscp[0x6]; 485 u8 udp_sport[0x10]; 486 487 u8 dei_cfi[0x1]; 488 u8 eth_prio[0x3]; 489 u8 sl[0x4]; 490 u8 port[0x8]; 491 u8 rmac_47_32[0x10]; 492 493 u8 rmac_31_0[0x20]; 494 }; 495 496 struct mlx5_ifc_flow_table_nic_cap_bits { 497 u8 nic_rx_multi_path_tirs[0x1]; 498 u8 nic_rx_multi_path_tirs_fts[0x1]; 499 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 500 u8 reserved_at_3[0x1fd]; 501 502 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 503 504 u8 reserved_at_400[0x200]; 505 506 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 507 508 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 509 510 u8 reserved_at_a00[0x200]; 511 512 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 513 514 u8 reserved_at_e00[0x7200]; 515 }; 516 517 struct mlx5_ifc_flow_table_eswitch_cap_bits { 518 u8 reserved_at_0[0x200]; 519 520 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 521 522 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 523 524 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 525 526 u8 reserved_at_800[0x7800]; 527 }; 528 529 struct mlx5_ifc_e_switch_cap_bits { 530 u8 vport_svlan_strip[0x1]; 531 u8 vport_cvlan_strip[0x1]; 532 u8 vport_svlan_insert[0x1]; 533 u8 vport_cvlan_insert_if_not_exist[0x1]; 534 u8 vport_cvlan_insert_overwrite[0x1]; 535 u8 reserved_at_5[0x19]; 536 u8 nic_vport_node_guid_modify[0x1]; 537 u8 nic_vport_port_guid_modify[0x1]; 538 539 u8 vxlan_encap_decap[0x1]; 540 u8 nvgre_encap_decap[0x1]; 541 u8 reserved_at_22[0x9]; 542 u8 log_max_encap_headers[0x5]; 543 u8 reserved_2b[0x6]; 544 u8 max_encap_header_size[0xa]; 545 546 u8 reserved_40[0x7c0]; 547 548 }; 549 550 struct mlx5_ifc_qos_cap_bits { 551 u8 packet_pacing[0x1]; 552 u8 esw_scheduling[0x1]; 553 u8 esw_bw_share[0x1]; 554 u8 esw_rate_limit[0x1]; 555 u8 reserved_at_4[0x1c]; 556 557 u8 reserved_at_20[0x20]; 558 559 u8 packet_pacing_max_rate[0x20]; 560 561 u8 packet_pacing_min_rate[0x20]; 562 563 u8 reserved_at_80[0x10]; 564 u8 packet_pacing_rate_table_size[0x10]; 565 566 u8 esw_element_type[0x10]; 567 u8 esw_tsar_type[0x10]; 568 569 u8 reserved_at_c0[0x10]; 570 u8 max_qos_para_vport[0x10]; 571 572 u8 max_tsar_bw_share[0x20]; 573 574 u8 reserved_at_100[0x700]; 575 }; 576 577 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 578 u8 csum_cap[0x1]; 579 u8 vlan_cap[0x1]; 580 u8 lro_cap[0x1]; 581 u8 lro_psh_flag[0x1]; 582 u8 lro_time_stamp[0x1]; 583 u8 reserved_at_5[0x2]; 584 u8 wqe_vlan_insert[0x1]; 585 u8 self_lb_en_modifiable[0x1]; 586 u8 reserved_at_9[0x2]; 587 u8 max_lso_cap[0x5]; 588 u8 multi_pkt_send_wqe[0x2]; 589 u8 wqe_inline_mode[0x2]; 590 u8 rss_ind_tbl_cap[0x4]; 591 u8 reg_umr_sq[0x1]; 592 u8 scatter_fcs[0x1]; 593 u8 reserved_at_1a[0x1]; 594 u8 tunnel_lso_const_out_ip_id[0x1]; 595 u8 reserved_at_1c[0x2]; 596 u8 tunnel_statless_gre[0x1]; 597 u8 tunnel_stateless_vxlan[0x1]; 598 599 u8 reserved_at_20[0x20]; 600 601 u8 reserved_at_40[0x10]; 602 u8 lro_min_mss_size[0x10]; 603 604 u8 reserved_at_60[0x120]; 605 606 u8 lro_timer_supported_periods[4][0x20]; 607 608 u8 reserved_at_200[0x600]; 609 }; 610 611 struct mlx5_ifc_roce_cap_bits { 612 u8 roce_apm[0x1]; 613 u8 reserved_at_1[0x1f]; 614 615 u8 reserved_at_20[0x60]; 616 617 u8 reserved_at_80[0xc]; 618 u8 l3_type[0x4]; 619 u8 reserved_at_90[0x8]; 620 u8 roce_version[0x8]; 621 622 u8 reserved_at_a0[0x10]; 623 u8 r_roce_dest_udp_port[0x10]; 624 625 u8 r_roce_max_src_udp_port[0x10]; 626 u8 r_roce_min_src_udp_port[0x10]; 627 628 u8 reserved_at_e0[0x10]; 629 u8 roce_address_table_size[0x10]; 630 631 u8 reserved_at_100[0x700]; 632 }; 633 634 enum { 635 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 636 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 637 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 638 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 640 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 644 }; 645 646 enum { 647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 648 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 649 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 650 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 651 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 652 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 653 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 654 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 656 }; 657 658 struct mlx5_ifc_atomic_caps_bits { 659 u8 reserved_at_0[0x40]; 660 661 u8 atomic_req_8B_endianess_mode[0x2]; 662 u8 reserved_at_42[0x4]; 663 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 664 665 u8 reserved_at_47[0x19]; 666 667 u8 reserved_at_60[0x20]; 668 669 u8 reserved_at_80[0x10]; 670 u8 atomic_operations[0x10]; 671 672 u8 reserved_at_a0[0x10]; 673 u8 atomic_size_qp[0x10]; 674 675 u8 reserved_at_c0[0x10]; 676 u8 atomic_size_dc[0x10]; 677 678 u8 reserved_at_e0[0x720]; 679 }; 680 681 struct mlx5_ifc_odp_cap_bits { 682 u8 reserved_at_0[0x40]; 683 684 u8 sig[0x1]; 685 u8 reserved_at_41[0x1f]; 686 687 u8 reserved_at_60[0x20]; 688 689 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 690 691 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 692 693 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 694 695 u8 reserved_at_e0[0x720]; 696 }; 697 698 struct mlx5_ifc_calc_op { 699 u8 reserved_at_0[0x10]; 700 u8 reserved_at_10[0x9]; 701 u8 op_swap_endianness[0x1]; 702 u8 op_min[0x1]; 703 u8 op_xor[0x1]; 704 u8 op_or[0x1]; 705 u8 op_and[0x1]; 706 u8 op_max[0x1]; 707 u8 op_add[0x1]; 708 }; 709 710 struct mlx5_ifc_vector_calc_cap_bits { 711 u8 calc_matrix[0x1]; 712 u8 reserved_at_1[0x1f]; 713 u8 reserved_at_20[0x8]; 714 u8 max_vec_count[0x8]; 715 u8 reserved_at_30[0xd]; 716 u8 max_chunk_size[0x3]; 717 struct mlx5_ifc_calc_op calc0; 718 struct mlx5_ifc_calc_op calc1; 719 struct mlx5_ifc_calc_op calc2; 720 struct mlx5_ifc_calc_op calc3; 721 722 u8 reserved_at_e0[0x720]; 723 }; 724 725 enum { 726 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 727 MLX5_WQ_TYPE_CYCLIC = 0x1, 728 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 729 }; 730 731 enum { 732 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 733 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 734 }; 735 736 enum { 737 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 738 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 739 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 740 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 741 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 742 }; 743 744 enum { 745 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 746 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 747 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 748 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 749 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 750 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 751 }; 752 753 enum { 754 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 755 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 756 }; 757 758 enum { 759 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 760 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 761 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 762 }; 763 764 enum { 765 MLX5_CAP_PORT_TYPE_IB = 0x0, 766 MLX5_CAP_PORT_TYPE_ETH = 0x1, 767 }; 768 769 enum { 770 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 771 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 772 MLX5_CAP_UMR_FENCE_NONE = 0x2, 773 }; 774 775 struct mlx5_ifc_cmd_hca_cap_bits { 776 u8 reserved_at_0[0x80]; 777 778 u8 log_max_srq_sz[0x8]; 779 u8 log_max_qp_sz[0x8]; 780 u8 reserved_at_90[0xb]; 781 u8 log_max_qp[0x5]; 782 783 u8 reserved_at_a0[0xb]; 784 u8 log_max_srq[0x5]; 785 u8 reserved_at_b0[0x10]; 786 787 u8 reserved_at_c0[0x8]; 788 u8 log_max_cq_sz[0x8]; 789 u8 reserved_at_d0[0xb]; 790 u8 log_max_cq[0x5]; 791 792 u8 log_max_eq_sz[0x8]; 793 u8 reserved_at_e8[0x2]; 794 u8 log_max_mkey[0x6]; 795 u8 reserved_at_f0[0xc]; 796 u8 log_max_eq[0x4]; 797 798 u8 max_indirection[0x8]; 799 u8 fixed_buffer_size[0x1]; 800 u8 log_max_mrw_sz[0x7]; 801 u8 reserved_at_110[0x2]; 802 u8 log_max_bsf_list_size[0x6]; 803 u8 umr_extended_translation_offset[0x1]; 804 u8 null_mkey[0x1]; 805 u8 log_max_klm_list_size[0x6]; 806 807 u8 reserved_at_120[0xa]; 808 u8 log_max_ra_req_dc[0x6]; 809 u8 reserved_at_130[0xa]; 810 u8 log_max_ra_res_dc[0x6]; 811 812 u8 reserved_at_140[0xa]; 813 u8 log_max_ra_req_qp[0x6]; 814 u8 reserved_at_150[0xa]; 815 u8 log_max_ra_res_qp[0x6]; 816 817 u8 end_pad[0x1]; 818 u8 cc_query_allowed[0x1]; 819 u8 cc_modify_allowed[0x1]; 820 u8 start_pad[0x1]; 821 u8 cache_line_128byte[0x1]; 822 u8 reserved_at_163[0xb]; 823 u8 gid_table_size[0x10]; 824 825 u8 out_of_seq_cnt[0x1]; 826 u8 vport_counters[0x1]; 827 u8 retransmission_q_counters[0x1]; 828 u8 reserved_at_183[0x1]; 829 u8 modify_rq_counter_set_id[0x1]; 830 u8 reserved_at_185[0x1]; 831 u8 max_qp_cnt[0xa]; 832 u8 pkey_table_size[0x10]; 833 834 u8 vport_group_manager[0x1]; 835 u8 vhca_group_manager[0x1]; 836 u8 ib_virt[0x1]; 837 u8 eth_virt[0x1]; 838 u8 reserved_at_1a4[0x1]; 839 u8 ets[0x1]; 840 u8 nic_flow_table[0x1]; 841 u8 eswitch_flow_table[0x1]; 842 u8 early_vf_enable[0x1]; 843 u8 mcam_reg[0x1]; 844 u8 pcam_reg[0x1]; 845 u8 local_ca_ack_delay[0x5]; 846 u8 port_module_event[0x1]; 847 u8 reserved_at_1b1[0x1]; 848 u8 ports_check[0x1]; 849 u8 reserved_at_1b3[0x1]; 850 u8 disable_link_up[0x1]; 851 u8 beacon_led[0x1]; 852 u8 port_type[0x2]; 853 u8 num_ports[0x8]; 854 855 u8 reserved_at_1c0[0x1]; 856 u8 pps[0x1]; 857 u8 pps_modify[0x1]; 858 u8 log_max_msg[0x5]; 859 u8 reserved_at_1c8[0x4]; 860 u8 max_tc[0x4]; 861 u8 reserved_at_1d0[0x1]; 862 u8 dcbx[0x1]; 863 u8 reserved_at_1d2[0x4]; 864 u8 rol_s[0x1]; 865 u8 rol_g[0x1]; 866 u8 reserved_at_1d8[0x1]; 867 u8 wol_s[0x1]; 868 u8 wol_g[0x1]; 869 u8 wol_a[0x1]; 870 u8 wol_b[0x1]; 871 u8 wol_m[0x1]; 872 u8 wol_u[0x1]; 873 u8 wol_p[0x1]; 874 875 u8 stat_rate_support[0x10]; 876 u8 reserved_at_1f0[0xc]; 877 u8 cqe_version[0x4]; 878 879 u8 compact_address_vector[0x1]; 880 u8 striding_rq[0x1]; 881 u8 reserved_at_202[0x1]; 882 u8 ipoib_enhanced_offloads[0x1]; 883 u8 ipoib_basic_offloads[0x1]; 884 u8 reserved_at_205[0x5]; 885 u8 umr_fence[0x2]; 886 u8 reserved_at_20c[0x3]; 887 u8 drain_sigerr[0x1]; 888 u8 cmdif_checksum[0x2]; 889 u8 sigerr_cqe[0x1]; 890 u8 reserved_at_213[0x1]; 891 u8 wq_signature[0x1]; 892 u8 sctr_data_cqe[0x1]; 893 u8 reserved_at_216[0x1]; 894 u8 sho[0x1]; 895 u8 tph[0x1]; 896 u8 rf[0x1]; 897 u8 dct[0x1]; 898 u8 qos[0x1]; 899 u8 eth_net_offloads[0x1]; 900 u8 roce[0x1]; 901 u8 atomic[0x1]; 902 u8 reserved_at_21f[0x1]; 903 904 u8 cq_oi[0x1]; 905 u8 cq_resize[0x1]; 906 u8 cq_moderation[0x1]; 907 u8 reserved_at_223[0x3]; 908 u8 cq_eq_remap[0x1]; 909 u8 pg[0x1]; 910 u8 block_lb_mc[0x1]; 911 u8 reserved_at_229[0x1]; 912 u8 scqe_break_moderation[0x1]; 913 u8 cq_period_start_from_cqe[0x1]; 914 u8 cd[0x1]; 915 u8 reserved_at_22d[0x1]; 916 u8 apm[0x1]; 917 u8 vector_calc[0x1]; 918 u8 umr_ptr_rlky[0x1]; 919 u8 imaicl[0x1]; 920 u8 reserved_at_232[0x4]; 921 u8 qkv[0x1]; 922 u8 pkv[0x1]; 923 u8 set_deth_sqpn[0x1]; 924 u8 reserved_at_239[0x3]; 925 u8 xrc[0x1]; 926 u8 ud[0x1]; 927 u8 uc[0x1]; 928 u8 rc[0x1]; 929 930 u8 uar_4k[0x1]; 931 u8 reserved_at_241[0x9]; 932 u8 uar_sz[0x6]; 933 u8 reserved_at_250[0x8]; 934 u8 log_pg_sz[0x8]; 935 936 u8 bf[0x1]; 937 u8 driver_version[0x1]; 938 u8 pad_tx_eth_packet[0x1]; 939 u8 reserved_at_263[0x8]; 940 u8 log_bf_reg_size[0x5]; 941 942 u8 reserved_at_270[0xb]; 943 u8 lag_master[0x1]; 944 u8 num_lag_ports[0x4]; 945 946 u8 reserved_at_280[0x10]; 947 u8 max_wqe_sz_sq[0x10]; 948 949 u8 reserved_at_2a0[0x10]; 950 u8 max_wqe_sz_rq[0x10]; 951 952 u8 reserved_at_2c0[0x10]; 953 u8 max_wqe_sz_sq_dc[0x10]; 954 955 u8 reserved_at_2e0[0x7]; 956 u8 max_qp_mcg[0x19]; 957 958 u8 reserved_at_300[0x18]; 959 u8 log_max_mcg[0x8]; 960 961 u8 reserved_at_320[0x3]; 962 u8 log_max_transport_domain[0x5]; 963 u8 reserved_at_328[0x3]; 964 u8 log_max_pd[0x5]; 965 u8 reserved_at_330[0xb]; 966 u8 log_max_xrcd[0x5]; 967 968 u8 reserved_at_340[0x8]; 969 u8 log_max_flow_counter_bulk[0x8]; 970 u8 max_flow_counter[0x10]; 971 972 973 u8 reserved_at_360[0x3]; 974 u8 log_max_rq[0x5]; 975 u8 reserved_at_368[0x3]; 976 u8 log_max_sq[0x5]; 977 u8 reserved_at_370[0x3]; 978 u8 log_max_tir[0x5]; 979 u8 reserved_at_378[0x3]; 980 u8 log_max_tis[0x5]; 981 982 u8 basic_cyclic_rcv_wqe[0x1]; 983 u8 reserved_at_381[0x2]; 984 u8 log_max_rmp[0x5]; 985 u8 reserved_at_388[0x3]; 986 u8 log_max_rqt[0x5]; 987 u8 reserved_at_390[0x3]; 988 u8 log_max_rqt_size[0x5]; 989 u8 reserved_at_398[0x3]; 990 u8 log_max_tis_per_sq[0x5]; 991 992 u8 reserved_at_3a0[0x3]; 993 u8 log_max_stride_sz_rq[0x5]; 994 u8 reserved_at_3a8[0x3]; 995 u8 log_min_stride_sz_rq[0x5]; 996 u8 reserved_at_3b0[0x3]; 997 u8 log_max_stride_sz_sq[0x5]; 998 u8 reserved_at_3b8[0x3]; 999 u8 log_min_stride_sz_sq[0x5]; 1000 1001 u8 reserved_at_3c0[0x1b]; 1002 u8 log_max_wq_sz[0x5]; 1003 1004 u8 nic_vport_change_event[0x1]; 1005 u8 reserved_at_3e1[0xa]; 1006 u8 log_max_vlan_list[0x5]; 1007 u8 reserved_at_3f0[0x3]; 1008 u8 log_max_current_mc_list[0x5]; 1009 u8 reserved_at_3f8[0x3]; 1010 u8 log_max_current_uc_list[0x5]; 1011 1012 u8 reserved_at_400[0x80]; 1013 1014 u8 reserved_at_480[0x3]; 1015 u8 log_max_l2_table[0x5]; 1016 u8 reserved_at_488[0x8]; 1017 u8 log_uar_page_sz[0x10]; 1018 1019 u8 reserved_at_4a0[0x20]; 1020 u8 device_frequency_mhz[0x20]; 1021 u8 device_frequency_khz[0x20]; 1022 1023 u8 reserved_at_500[0x20]; 1024 u8 num_of_uars_per_page[0x20]; 1025 u8 reserved_at_540[0x40]; 1026 1027 u8 reserved_at_580[0x3f]; 1028 u8 cqe_compression[0x1]; 1029 1030 u8 cqe_compression_timeout[0x10]; 1031 u8 cqe_compression_max_num[0x10]; 1032 1033 u8 reserved_at_5e0[0x10]; 1034 u8 tag_matching[0x1]; 1035 u8 rndv_offload_rc[0x1]; 1036 u8 rndv_offload_dc[0x1]; 1037 u8 log_tag_matching_list_sz[0x5]; 1038 u8 reserved_at_5f8[0x3]; 1039 u8 log_max_xrq[0x5]; 1040 1041 u8 reserved_at_600[0x200]; 1042 }; 1043 1044 enum mlx5_flow_destination_type { 1045 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1046 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1047 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1048 1049 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1050 }; 1051 1052 struct mlx5_ifc_dest_format_struct_bits { 1053 u8 destination_type[0x8]; 1054 u8 destination_id[0x18]; 1055 1056 u8 reserved_at_20[0x20]; 1057 }; 1058 1059 struct mlx5_ifc_flow_counter_list_bits { 1060 u8 clear[0x1]; 1061 u8 num_of_counters[0xf]; 1062 u8 flow_counter_id[0x10]; 1063 1064 u8 reserved_at_20[0x20]; 1065 }; 1066 1067 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1068 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1069 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1070 u8 reserved_at_0[0x40]; 1071 }; 1072 1073 struct mlx5_ifc_fte_match_param_bits { 1074 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1075 1076 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1077 1078 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1079 1080 u8 reserved_at_600[0xa00]; 1081 }; 1082 1083 enum { 1084 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1085 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1086 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1087 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1088 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1089 }; 1090 1091 struct mlx5_ifc_rx_hash_field_select_bits { 1092 u8 l3_prot_type[0x1]; 1093 u8 l4_prot_type[0x1]; 1094 u8 selected_fields[0x1e]; 1095 }; 1096 1097 enum { 1098 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1099 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1100 }; 1101 1102 enum { 1103 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1104 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1105 }; 1106 1107 struct mlx5_ifc_wq_bits { 1108 u8 wq_type[0x4]; 1109 u8 wq_signature[0x1]; 1110 u8 end_padding_mode[0x2]; 1111 u8 cd_slave[0x1]; 1112 u8 reserved_at_8[0x18]; 1113 1114 u8 hds_skip_first_sge[0x1]; 1115 u8 log2_hds_buf_size[0x3]; 1116 u8 reserved_at_24[0x7]; 1117 u8 page_offset[0x5]; 1118 u8 lwm[0x10]; 1119 1120 u8 reserved_at_40[0x8]; 1121 u8 pd[0x18]; 1122 1123 u8 reserved_at_60[0x8]; 1124 u8 uar_page[0x18]; 1125 1126 u8 dbr_addr[0x40]; 1127 1128 u8 hw_counter[0x20]; 1129 1130 u8 sw_counter[0x20]; 1131 1132 u8 reserved_at_100[0xc]; 1133 u8 log_wq_stride[0x4]; 1134 u8 reserved_at_110[0x3]; 1135 u8 log_wq_pg_sz[0x5]; 1136 u8 reserved_at_118[0x3]; 1137 u8 log_wq_sz[0x5]; 1138 1139 u8 reserved_at_120[0x15]; 1140 u8 log_wqe_num_of_strides[0x3]; 1141 u8 two_byte_shift_en[0x1]; 1142 u8 reserved_at_139[0x4]; 1143 u8 log_wqe_stride_size[0x3]; 1144 1145 u8 reserved_at_140[0x4c0]; 1146 1147 struct mlx5_ifc_cmd_pas_bits pas[0]; 1148 }; 1149 1150 struct mlx5_ifc_rq_num_bits { 1151 u8 reserved_at_0[0x8]; 1152 u8 rq_num[0x18]; 1153 }; 1154 1155 struct mlx5_ifc_mac_address_layout_bits { 1156 u8 reserved_at_0[0x10]; 1157 u8 mac_addr_47_32[0x10]; 1158 1159 u8 mac_addr_31_0[0x20]; 1160 }; 1161 1162 struct mlx5_ifc_vlan_layout_bits { 1163 u8 reserved_at_0[0x14]; 1164 u8 vlan[0x0c]; 1165 1166 u8 reserved_at_20[0x20]; 1167 }; 1168 1169 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1170 u8 reserved_at_0[0xa0]; 1171 1172 u8 min_time_between_cnps[0x20]; 1173 1174 u8 reserved_at_c0[0x12]; 1175 u8 cnp_dscp[0x6]; 1176 u8 reserved_at_d8[0x5]; 1177 u8 cnp_802p_prio[0x3]; 1178 1179 u8 reserved_at_e0[0x720]; 1180 }; 1181 1182 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1183 u8 reserved_at_0[0x60]; 1184 1185 u8 reserved_at_60[0x4]; 1186 u8 clamp_tgt_rate[0x1]; 1187 u8 reserved_at_65[0x3]; 1188 u8 clamp_tgt_rate_after_time_inc[0x1]; 1189 u8 reserved_at_69[0x17]; 1190 1191 u8 reserved_at_80[0x20]; 1192 1193 u8 rpg_time_reset[0x20]; 1194 1195 u8 rpg_byte_reset[0x20]; 1196 1197 u8 rpg_threshold[0x20]; 1198 1199 u8 rpg_max_rate[0x20]; 1200 1201 u8 rpg_ai_rate[0x20]; 1202 1203 u8 rpg_hai_rate[0x20]; 1204 1205 u8 rpg_gd[0x20]; 1206 1207 u8 rpg_min_dec_fac[0x20]; 1208 1209 u8 rpg_min_rate[0x20]; 1210 1211 u8 reserved_at_1c0[0xe0]; 1212 1213 u8 rate_to_set_on_first_cnp[0x20]; 1214 1215 u8 dce_tcp_g[0x20]; 1216 1217 u8 dce_tcp_rtt[0x20]; 1218 1219 u8 rate_reduce_monitor_period[0x20]; 1220 1221 u8 reserved_at_320[0x20]; 1222 1223 u8 initial_alpha_value[0x20]; 1224 1225 u8 reserved_at_360[0x4a0]; 1226 }; 1227 1228 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1229 u8 reserved_at_0[0x80]; 1230 1231 u8 rppp_max_rps[0x20]; 1232 1233 u8 rpg_time_reset[0x20]; 1234 1235 u8 rpg_byte_reset[0x20]; 1236 1237 u8 rpg_threshold[0x20]; 1238 1239 u8 rpg_max_rate[0x20]; 1240 1241 u8 rpg_ai_rate[0x20]; 1242 1243 u8 rpg_hai_rate[0x20]; 1244 1245 u8 rpg_gd[0x20]; 1246 1247 u8 rpg_min_dec_fac[0x20]; 1248 1249 u8 rpg_min_rate[0x20]; 1250 1251 u8 reserved_at_1c0[0x640]; 1252 }; 1253 1254 enum { 1255 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1256 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1257 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1258 }; 1259 1260 struct mlx5_ifc_resize_field_select_bits { 1261 u8 resize_field_select[0x20]; 1262 }; 1263 1264 enum { 1265 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1266 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1267 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1268 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1269 }; 1270 1271 struct mlx5_ifc_modify_field_select_bits { 1272 u8 modify_field_select[0x20]; 1273 }; 1274 1275 struct mlx5_ifc_field_select_r_roce_np_bits { 1276 u8 field_select_r_roce_np[0x20]; 1277 }; 1278 1279 struct mlx5_ifc_field_select_r_roce_rp_bits { 1280 u8 field_select_r_roce_rp[0x20]; 1281 }; 1282 1283 enum { 1284 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1285 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1286 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1287 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1288 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1289 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1290 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1291 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1292 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1293 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1294 }; 1295 1296 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1297 u8 field_select_8021qaurp[0x20]; 1298 }; 1299 1300 struct mlx5_ifc_phys_layer_cntrs_bits { 1301 u8 time_since_last_clear_high[0x20]; 1302 1303 u8 time_since_last_clear_low[0x20]; 1304 1305 u8 symbol_errors_high[0x20]; 1306 1307 u8 symbol_errors_low[0x20]; 1308 1309 u8 sync_headers_errors_high[0x20]; 1310 1311 u8 sync_headers_errors_low[0x20]; 1312 1313 u8 edpl_bip_errors_lane0_high[0x20]; 1314 1315 u8 edpl_bip_errors_lane0_low[0x20]; 1316 1317 u8 edpl_bip_errors_lane1_high[0x20]; 1318 1319 u8 edpl_bip_errors_lane1_low[0x20]; 1320 1321 u8 edpl_bip_errors_lane2_high[0x20]; 1322 1323 u8 edpl_bip_errors_lane2_low[0x20]; 1324 1325 u8 edpl_bip_errors_lane3_high[0x20]; 1326 1327 u8 edpl_bip_errors_lane3_low[0x20]; 1328 1329 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1330 1331 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1332 1333 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1334 1335 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1336 1337 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1338 1339 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1340 1341 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1342 1343 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1344 1345 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1346 1347 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1348 1349 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1350 1351 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1352 1353 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1354 1355 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1356 1357 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1358 1359 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1360 1361 u8 rs_fec_corrected_blocks_high[0x20]; 1362 1363 u8 rs_fec_corrected_blocks_low[0x20]; 1364 1365 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1366 1367 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1368 1369 u8 rs_fec_no_errors_blocks_high[0x20]; 1370 1371 u8 rs_fec_no_errors_blocks_low[0x20]; 1372 1373 u8 rs_fec_single_error_blocks_high[0x20]; 1374 1375 u8 rs_fec_single_error_blocks_low[0x20]; 1376 1377 u8 rs_fec_corrected_symbols_total_high[0x20]; 1378 1379 u8 rs_fec_corrected_symbols_total_low[0x20]; 1380 1381 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1382 1383 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1384 1385 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1386 1387 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1388 1389 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1390 1391 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1392 1393 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1394 1395 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1396 1397 u8 link_down_events[0x20]; 1398 1399 u8 successful_recovery_events[0x20]; 1400 1401 u8 reserved_at_640[0x180]; 1402 }; 1403 1404 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1405 u8 time_since_last_clear_high[0x20]; 1406 1407 u8 time_since_last_clear_low[0x20]; 1408 1409 u8 phy_received_bits_high[0x20]; 1410 1411 u8 phy_received_bits_low[0x20]; 1412 1413 u8 phy_symbol_errors_high[0x20]; 1414 1415 u8 phy_symbol_errors_low[0x20]; 1416 1417 u8 phy_corrected_bits_high[0x20]; 1418 1419 u8 phy_corrected_bits_low[0x20]; 1420 1421 u8 phy_corrected_bits_lane0_high[0x20]; 1422 1423 u8 phy_corrected_bits_lane0_low[0x20]; 1424 1425 u8 phy_corrected_bits_lane1_high[0x20]; 1426 1427 u8 phy_corrected_bits_lane1_low[0x20]; 1428 1429 u8 phy_corrected_bits_lane2_high[0x20]; 1430 1431 u8 phy_corrected_bits_lane2_low[0x20]; 1432 1433 u8 phy_corrected_bits_lane3_high[0x20]; 1434 1435 u8 phy_corrected_bits_lane3_low[0x20]; 1436 1437 u8 reserved_at_200[0x5c0]; 1438 }; 1439 1440 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1441 u8 symbol_error_counter[0x10]; 1442 1443 u8 link_error_recovery_counter[0x8]; 1444 1445 u8 link_downed_counter[0x8]; 1446 1447 u8 port_rcv_errors[0x10]; 1448 1449 u8 port_rcv_remote_physical_errors[0x10]; 1450 1451 u8 port_rcv_switch_relay_errors[0x10]; 1452 1453 u8 port_xmit_discards[0x10]; 1454 1455 u8 port_xmit_constraint_errors[0x8]; 1456 1457 u8 port_rcv_constraint_errors[0x8]; 1458 1459 u8 reserved_at_70[0x8]; 1460 1461 u8 link_overrun_errors[0x8]; 1462 1463 u8 reserved_at_80[0x10]; 1464 1465 u8 vl_15_dropped[0x10]; 1466 1467 u8 reserved_at_a0[0x80]; 1468 1469 u8 port_xmit_wait[0x20]; 1470 }; 1471 1472 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1473 u8 transmit_queue_high[0x20]; 1474 1475 u8 transmit_queue_low[0x20]; 1476 1477 u8 reserved_at_40[0x780]; 1478 }; 1479 1480 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1481 u8 rx_octets_high[0x20]; 1482 1483 u8 rx_octets_low[0x20]; 1484 1485 u8 reserved_at_40[0xc0]; 1486 1487 u8 rx_frames_high[0x20]; 1488 1489 u8 rx_frames_low[0x20]; 1490 1491 u8 tx_octets_high[0x20]; 1492 1493 u8 tx_octets_low[0x20]; 1494 1495 u8 reserved_at_180[0xc0]; 1496 1497 u8 tx_frames_high[0x20]; 1498 1499 u8 tx_frames_low[0x20]; 1500 1501 u8 rx_pause_high[0x20]; 1502 1503 u8 rx_pause_low[0x20]; 1504 1505 u8 rx_pause_duration_high[0x20]; 1506 1507 u8 rx_pause_duration_low[0x20]; 1508 1509 u8 tx_pause_high[0x20]; 1510 1511 u8 tx_pause_low[0x20]; 1512 1513 u8 tx_pause_duration_high[0x20]; 1514 1515 u8 tx_pause_duration_low[0x20]; 1516 1517 u8 rx_pause_transition_high[0x20]; 1518 1519 u8 rx_pause_transition_low[0x20]; 1520 1521 u8 reserved_at_3c0[0x400]; 1522 }; 1523 1524 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1525 u8 port_transmit_wait_high[0x20]; 1526 1527 u8 port_transmit_wait_low[0x20]; 1528 1529 u8 reserved_at_40[0x780]; 1530 }; 1531 1532 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1533 u8 dot3stats_alignment_errors_high[0x20]; 1534 1535 u8 dot3stats_alignment_errors_low[0x20]; 1536 1537 u8 dot3stats_fcs_errors_high[0x20]; 1538 1539 u8 dot3stats_fcs_errors_low[0x20]; 1540 1541 u8 dot3stats_single_collision_frames_high[0x20]; 1542 1543 u8 dot3stats_single_collision_frames_low[0x20]; 1544 1545 u8 dot3stats_multiple_collision_frames_high[0x20]; 1546 1547 u8 dot3stats_multiple_collision_frames_low[0x20]; 1548 1549 u8 dot3stats_sqe_test_errors_high[0x20]; 1550 1551 u8 dot3stats_sqe_test_errors_low[0x20]; 1552 1553 u8 dot3stats_deferred_transmissions_high[0x20]; 1554 1555 u8 dot3stats_deferred_transmissions_low[0x20]; 1556 1557 u8 dot3stats_late_collisions_high[0x20]; 1558 1559 u8 dot3stats_late_collisions_low[0x20]; 1560 1561 u8 dot3stats_excessive_collisions_high[0x20]; 1562 1563 u8 dot3stats_excessive_collisions_low[0x20]; 1564 1565 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1566 1567 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1568 1569 u8 dot3stats_carrier_sense_errors_high[0x20]; 1570 1571 u8 dot3stats_carrier_sense_errors_low[0x20]; 1572 1573 u8 dot3stats_frame_too_longs_high[0x20]; 1574 1575 u8 dot3stats_frame_too_longs_low[0x20]; 1576 1577 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1578 1579 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1580 1581 u8 dot3stats_symbol_errors_high[0x20]; 1582 1583 u8 dot3stats_symbol_errors_low[0x20]; 1584 1585 u8 dot3control_in_unknown_opcodes_high[0x20]; 1586 1587 u8 dot3control_in_unknown_opcodes_low[0x20]; 1588 1589 u8 dot3in_pause_frames_high[0x20]; 1590 1591 u8 dot3in_pause_frames_low[0x20]; 1592 1593 u8 dot3out_pause_frames_high[0x20]; 1594 1595 u8 dot3out_pause_frames_low[0x20]; 1596 1597 u8 reserved_at_400[0x3c0]; 1598 }; 1599 1600 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1601 u8 ether_stats_drop_events_high[0x20]; 1602 1603 u8 ether_stats_drop_events_low[0x20]; 1604 1605 u8 ether_stats_octets_high[0x20]; 1606 1607 u8 ether_stats_octets_low[0x20]; 1608 1609 u8 ether_stats_pkts_high[0x20]; 1610 1611 u8 ether_stats_pkts_low[0x20]; 1612 1613 u8 ether_stats_broadcast_pkts_high[0x20]; 1614 1615 u8 ether_stats_broadcast_pkts_low[0x20]; 1616 1617 u8 ether_stats_multicast_pkts_high[0x20]; 1618 1619 u8 ether_stats_multicast_pkts_low[0x20]; 1620 1621 u8 ether_stats_crc_align_errors_high[0x20]; 1622 1623 u8 ether_stats_crc_align_errors_low[0x20]; 1624 1625 u8 ether_stats_undersize_pkts_high[0x20]; 1626 1627 u8 ether_stats_undersize_pkts_low[0x20]; 1628 1629 u8 ether_stats_oversize_pkts_high[0x20]; 1630 1631 u8 ether_stats_oversize_pkts_low[0x20]; 1632 1633 u8 ether_stats_fragments_high[0x20]; 1634 1635 u8 ether_stats_fragments_low[0x20]; 1636 1637 u8 ether_stats_jabbers_high[0x20]; 1638 1639 u8 ether_stats_jabbers_low[0x20]; 1640 1641 u8 ether_stats_collisions_high[0x20]; 1642 1643 u8 ether_stats_collisions_low[0x20]; 1644 1645 u8 ether_stats_pkts64octets_high[0x20]; 1646 1647 u8 ether_stats_pkts64octets_low[0x20]; 1648 1649 u8 ether_stats_pkts65to127octets_high[0x20]; 1650 1651 u8 ether_stats_pkts65to127octets_low[0x20]; 1652 1653 u8 ether_stats_pkts128to255octets_high[0x20]; 1654 1655 u8 ether_stats_pkts128to255octets_low[0x20]; 1656 1657 u8 ether_stats_pkts256to511octets_high[0x20]; 1658 1659 u8 ether_stats_pkts256to511octets_low[0x20]; 1660 1661 u8 ether_stats_pkts512to1023octets_high[0x20]; 1662 1663 u8 ether_stats_pkts512to1023octets_low[0x20]; 1664 1665 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1666 1667 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1668 1669 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1670 1671 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1672 1673 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1674 1675 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1676 1677 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1678 1679 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1680 1681 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1682 1683 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1684 1685 u8 reserved_at_540[0x280]; 1686 }; 1687 1688 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1689 u8 if_in_octets_high[0x20]; 1690 1691 u8 if_in_octets_low[0x20]; 1692 1693 u8 if_in_ucast_pkts_high[0x20]; 1694 1695 u8 if_in_ucast_pkts_low[0x20]; 1696 1697 u8 if_in_discards_high[0x20]; 1698 1699 u8 if_in_discards_low[0x20]; 1700 1701 u8 if_in_errors_high[0x20]; 1702 1703 u8 if_in_errors_low[0x20]; 1704 1705 u8 if_in_unknown_protos_high[0x20]; 1706 1707 u8 if_in_unknown_protos_low[0x20]; 1708 1709 u8 if_out_octets_high[0x20]; 1710 1711 u8 if_out_octets_low[0x20]; 1712 1713 u8 if_out_ucast_pkts_high[0x20]; 1714 1715 u8 if_out_ucast_pkts_low[0x20]; 1716 1717 u8 if_out_discards_high[0x20]; 1718 1719 u8 if_out_discards_low[0x20]; 1720 1721 u8 if_out_errors_high[0x20]; 1722 1723 u8 if_out_errors_low[0x20]; 1724 1725 u8 if_in_multicast_pkts_high[0x20]; 1726 1727 u8 if_in_multicast_pkts_low[0x20]; 1728 1729 u8 if_in_broadcast_pkts_high[0x20]; 1730 1731 u8 if_in_broadcast_pkts_low[0x20]; 1732 1733 u8 if_out_multicast_pkts_high[0x20]; 1734 1735 u8 if_out_multicast_pkts_low[0x20]; 1736 1737 u8 if_out_broadcast_pkts_high[0x20]; 1738 1739 u8 if_out_broadcast_pkts_low[0x20]; 1740 1741 u8 reserved_at_340[0x480]; 1742 }; 1743 1744 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1745 u8 a_frames_transmitted_ok_high[0x20]; 1746 1747 u8 a_frames_transmitted_ok_low[0x20]; 1748 1749 u8 a_frames_received_ok_high[0x20]; 1750 1751 u8 a_frames_received_ok_low[0x20]; 1752 1753 u8 a_frame_check_sequence_errors_high[0x20]; 1754 1755 u8 a_frame_check_sequence_errors_low[0x20]; 1756 1757 u8 a_alignment_errors_high[0x20]; 1758 1759 u8 a_alignment_errors_low[0x20]; 1760 1761 u8 a_octets_transmitted_ok_high[0x20]; 1762 1763 u8 a_octets_transmitted_ok_low[0x20]; 1764 1765 u8 a_octets_received_ok_high[0x20]; 1766 1767 u8 a_octets_received_ok_low[0x20]; 1768 1769 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1770 1771 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1772 1773 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1774 1775 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1776 1777 u8 a_multicast_frames_received_ok_high[0x20]; 1778 1779 u8 a_multicast_frames_received_ok_low[0x20]; 1780 1781 u8 a_broadcast_frames_received_ok_high[0x20]; 1782 1783 u8 a_broadcast_frames_received_ok_low[0x20]; 1784 1785 u8 a_in_range_length_errors_high[0x20]; 1786 1787 u8 a_in_range_length_errors_low[0x20]; 1788 1789 u8 a_out_of_range_length_field_high[0x20]; 1790 1791 u8 a_out_of_range_length_field_low[0x20]; 1792 1793 u8 a_frame_too_long_errors_high[0x20]; 1794 1795 u8 a_frame_too_long_errors_low[0x20]; 1796 1797 u8 a_symbol_error_during_carrier_high[0x20]; 1798 1799 u8 a_symbol_error_during_carrier_low[0x20]; 1800 1801 u8 a_mac_control_frames_transmitted_high[0x20]; 1802 1803 u8 a_mac_control_frames_transmitted_low[0x20]; 1804 1805 u8 a_mac_control_frames_received_high[0x20]; 1806 1807 u8 a_mac_control_frames_received_low[0x20]; 1808 1809 u8 a_unsupported_opcodes_received_high[0x20]; 1810 1811 u8 a_unsupported_opcodes_received_low[0x20]; 1812 1813 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1814 1815 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1816 1817 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1818 1819 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1820 1821 u8 reserved_at_4c0[0x300]; 1822 }; 1823 1824 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 1825 u8 life_time_counter_high[0x20]; 1826 1827 u8 life_time_counter_low[0x20]; 1828 1829 u8 rx_errors[0x20]; 1830 1831 u8 tx_errors[0x20]; 1832 1833 u8 l0_to_recovery_eieos[0x20]; 1834 1835 u8 l0_to_recovery_ts[0x20]; 1836 1837 u8 l0_to_recovery_framing[0x20]; 1838 1839 u8 l0_to_recovery_retrain[0x20]; 1840 1841 u8 crc_error_dllp[0x20]; 1842 1843 u8 crc_error_tlp[0x20]; 1844 1845 u8 reserved_at_140[0x680]; 1846 }; 1847 1848 struct mlx5_ifc_cmd_inter_comp_event_bits { 1849 u8 command_completion_vector[0x20]; 1850 1851 u8 reserved_at_20[0xc0]; 1852 }; 1853 1854 struct mlx5_ifc_stall_vl_event_bits { 1855 u8 reserved_at_0[0x18]; 1856 u8 port_num[0x1]; 1857 u8 reserved_at_19[0x3]; 1858 u8 vl[0x4]; 1859 1860 u8 reserved_at_20[0xa0]; 1861 }; 1862 1863 struct mlx5_ifc_db_bf_congestion_event_bits { 1864 u8 event_subtype[0x8]; 1865 u8 reserved_at_8[0x8]; 1866 u8 congestion_level[0x8]; 1867 u8 reserved_at_18[0x8]; 1868 1869 u8 reserved_at_20[0xa0]; 1870 }; 1871 1872 struct mlx5_ifc_gpio_event_bits { 1873 u8 reserved_at_0[0x60]; 1874 1875 u8 gpio_event_hi[0x20]; 1876 1877 u8 gpio_event_lo[0x20]; 1878 1879 u8 reserved_at_a0[0x40]; 1880 }; 1881 1882 struct mlx5_ifc_port_state_change_event_bits { 1883 u8 reserved_at_0[0x40]; 1884 1885 u8 port_num[0x4]; 1886 u8 reserved_at_44[0x1c]; 1887 1888 u8 reserved_at_60[0x80]; 1889 }; 1890 1891 struct mlx5_ifc_dropped_packet_logged_bits { 1892 u8 reserved_at_0[0xe0]; 1893 }; 1894 1895 enum { 1896 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1897 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1898 }; 1899 1900 struct mlx5_ifc_cq_error_bits { 1901 u8 reserved_at_0[0x8]; 1902 u8 cqn[0x18]; 1903 1904 u8 reserved_at_20[0x20]; 1905 1906 u8 reserved_at_40[0x18]; 1907 u8 syndrome[0x8]; 1908 1909 u8 reserved_at_60[0x80]; 1910 }; 1911 1912 struct mlx5_ifc_rdma_page_fault_event_bits { 1913 u8 bytes_committed[0x20]; 1914 1915 u8 r_key[0x20]; 1916 1917 u8 reserved_at_40[0x10]; 1918 u8 packet_len[0x10]; 1919 1920 u8 rdma_op_len[0x20]; 1921 1922 u8 rdma_va[0x40]; 1923 1924 u8 reserved_at_c0[0x5]; 1925 u8 rdma[0x1]; 1926 u8 write[0x1]; 1927 u8 requestor[0x1]; 1928 u8 qp_number[0x18]; 1929 }; 1930 1931 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1932 u8 bytes_committed[0x20]; 1933 1934 u8 reserved_at_20[0x10]; 1935 u8 wqe_index[0x10]; 1936 1937 u8 reserved_at_40[0x10]; 1938 u8 len[0x10]; 1939 1940 u8 reserved_at_60[0x60]; 1941 1942 u8 reserved_at_c0[0x5]; 1943 u8 rdma[0x1]; 1944 u8 write_read[0x1]; 1945 u8 requestor[0x1]; 1946 u8 qpn[0x18]; 1947 }; 1948 1949 struct mlx5_ifc_qp_events_bits { 1950 u8 reserved_at_0[0xa0]; 1951 1952 u8 type[0x8]; 1953 u8 reserved_at_a8[0x18]; 1954 1955 u8 reserved_at_c0[0x8]; 1956 u8 qpn_rqn_sqn[0x18]; 1957 }; 1958 1959 struct mlx5_ifc_dct_events_bits { 1960 u8 reserved_at_0[0xc0]; 1961 1962 u8 reserved_at_c0[0x8]; 1963 u8 dct_number[0x18]; 1964 }; 1965 1966 struct mlx5_ifc_comp_event_bits { 1967 u8 reserved_at_0[0xc0]; 1968 1969 u8 reserved_at_c0[0x8]; 1970 u8 cq_number[0x18]; 1971 }; 1972 1973 enum { 1974 MLX5_QPC_STATE_RST = 0x0, 1975 MLX5_QPC_STATE_INIT = 0x1, 1976 MLX5_QPC_STATE_RTR = 0x2, 1977 MLX5_QPC_STATE_RTS = 0x3, 1978 MLX5_QPC_STATE_SQER = 0x4, 1979 MLX5_QPC_STATE_ERR = 0x6, 1980 MLX5_QPC_STATE_SQD = 0x7, 1981 MLX5_QPC_STATE_SUSPENDED = 0x9, 1982 }; 1983 1984 enum { 1985 MLX5_QPC_ST_RC = 0x0, 1986 MLX5_QPC_ST_UC = 0x1, 1987 MLX5_QPC_ST_UD = 0x2, 1988 MLX5_QPC_ST_XRC = 0x3, 1989 MLX5_QPC_ST_DCI = 0x5, 1990 MLX5_QPC_ST_QP0 = 0x7, 1991 MLX5_QPC_ST_QP1 = 0x8, 1992 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1993 MLX5_QPC_ST_REG_UMR = 0xc, 1994 }; 1995 1996 enum { 1997 MLX5_QPC_PM_STATE_ARMED = 0x0, 1998 MLX5_QPC_PM_STATE_REARM = 0x1, 1999 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2000 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2001 }; 2002 2003 enum { 2004 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2005 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2006 }; 2007 2008 enum { 2009 MLX5_QPC_MTU_256_BYTES = 0x1, 2010 MLX5_QPC_MTU_512_BYTES = 0x2, 2011 MLX5_QPC_MTU_1K_BYTES = 0x3, 2012 MLX5_QPC_MTU_2K_BYTES = 0x4, 2013 MLX5_QPC_MTU_4K_BYTES = 0x5, 2014 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2015 }; 2016 2017 enum { 2018 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2019 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2020 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2021 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2022 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2023 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2024 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2025 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2026 }; 2027 2028 enum { 2029 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2030 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2031 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2032 }; 2033 2034 enum { 2035 MLX5_QPC_CS_RES_DISABLE = 0x0, 2036 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2037 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2038 }; 2039 2040 struct mlx5_ifc_qpc_bits { 2041 u8 state[0x4]; 2042 u8 lag_tx_port_affinity[0x4]; 2043 u8 st[0x8]; 2044 u8 reserved_at_10[0x3]; 2045 u8 pm_state[0x2]; 2046 u8 reserved_at_15[0x7]; 2047 u8 end_padding_mode[0x2]; 2048 u8 reserved_at_1e[0x2]; 2049 2050 u8 wq_signature[0x1]; 2051 u8 block_lb_mc[0x1]; 2052 u8 atomic_like_write_en[0x1]; 2053 u8 latency_sensitive[0x1]; 2054 u8 reserved_at_24[0x1]; 2055 u8 drain_sigerr[0x1]; 2056 u8 reserved_at_26[0x2]; 2057 u8 pd[0x18]; 2058 2059 u8 mtu[0x3]; 2060 u8 log_msg_max[0x5]; 2061 u8 reserved_at_48[0x1]; 2062 u8 log_rq_size[0x4]; 2063 u8 log_rq_stride[0x3]; 2064 u8 no_sq[0x1]; 2065 u8 log_sq_size[0x4]; 2066 u8 reserved_at_55[0x6]; 2067 u8 rlky[0x1]; 2068 u8 ulp_stateless_offload_mode[0x4]; 2069 2070 u8 counter_set_id[0x8]; 2071 u8 uar_page[0x18]; 2072 2073 u8 reserved_at_80[0x8]; 2074 u8 user_index[0x18]; 2075 2076 u8 reserved_at_a0[0x3]; 2077 u8 log_page_size[0x5]; 2078 u8 remote_qpn[0x18]; 2079 2080 struct mlx5_ifc_ads_bits primary_address_path; 2081 2082 struct mlx5_ifc_ads_bits secondary_address_path; 2083 2084 u8 log_ack_req_freq[0x4]; 2085 u8 reserved_at_384[0x4]; 2086 u8 log_sra_max[0x3]; 2087 u8 reserved_at_38b[0x2]; 2088 u8 retry_count[0x3]; 2089 u8 rnr_retry[0x3]; 2090 u8 reserved_at_393[0x1]; 2091 u8 fre[0x1]; 2092 u8 cur_rnr_retry[0x3]; 2093 u8 cur_retry_count[0x3]; 2094 u8 reserved_at_39b[0x5]; 2095 2096 u8 reserved_at_3a0[0x20]; 2097 2098 u8 reserved_at_3c0[0x8]; 2099 u8 next_send_psn[0x18]; 2100 2101 u8 reserved_at_3e0[0x8]; 2102 u8 cqn_snd[0x18]; 2103 2104 u8 reserved_at_400[0x8]; 2105 u8 deth_sqpn[0x18]; 2106 2107 u8 reserved_at_420[0x20]; 2108 2109 u8 reserved_at_440[0x8]; 2110 u8 last_acked_psn[0x18]; 2111 2112 u8 reserved_at_460[0x8]; 2113 u8 ssn[0x18]; 2114 2115 u8 reserved_at_480[0x8]; 2116 u8 log_rra_max[0x3]; 2117 u8 reserved_at_48b[0x1]; 2118 u8 atomic_mode[0x4]; 2119 u8 rre[0x1]; 2120 u8 rwe[0x1]; 2121 u8 rae[0x1]; 2122 u8 reserved_at_493[0x1]; 2123 u8 page_offset[0x6]; 2124 u8 reserved_at_49a[0x3]; 2125 u8 cd_slave_receive[0x1]; 2126 u8 cd_slave_send[0x1]; 2127 u8 cd_master[0x1]; 2128 2129 u8 reserved_at_4a0[0x3]; 2130 u8 min_rnr_nak[0x5]; 2131 u8 next_rcv_psn[0x18]; 2132 2133 u8 reserved_at_4c0[0x8]; 2134 u8 xrcd[0x18]; 2135 2136 u8 reserved_at_4e0[0x8]; 2137 u8 cqn_rcv[0x18]; 2138 2139 u8 dbr_addr[0x40]; 2140 2141 u8 q_key[0x20]; 2142 2143 u8 reserved_at_560[0x5]; 2144 u8 rq_type[0x3]; 2145 u8 srqn_rmpn_xrqn[0x18]; 2146 2147 u8 reserved_at_580[0x8]; 2148 u8 rmsn[0x18]; 2149 2150 u8 hw_sq_wqebb_counter[0x10]; 2151 u8 sw_sq_wqebb_counter[0x10]; 2152 2153 u8 hw_rq_counter[0x20]; 2154 2155 u8 sw_rq_counter[0x20]; 2156 2157 u8 reserved_at_600[0x20]; 2158 2159 u8 reserved_at_620[0xf]; 2160 u8 cgs[0x1]; 2161 u8 cs_req[0x8]; 2162 u8 cs_res[0x8]; 2163 2164 u8 dc_access_key[0x40]; 2165 2166 u8 reserved_at_680[0xc0]; 2167 }; 2168 2169 struct mlx5_ifc_roce_addr_layout_bits { 2170 u8 source_l3_address[16][0x8]; 2171 2172 u8 reserved_at_80[0x3]; 2173 u8 vlan_valid[0x1]; 2174 u8 vlan_id[0xc]; 2175 u8 source_mac_47_32[0x10]; 2176 2177 u8 source_mac_31_0[0x20]; 2178 2179 u8 reserved_at_c0[0x14]; 2180 u8 roce_l3_type[0x4]; 2181 u8 roce_version[0x8]; 2182 2183 u8 reserved_at_e0[0x20]; 2184 }; 2185 2186 union mlx5_ifc_hca_cap_union_bits { 2187 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2188 struct mlx5_ifc_odp_cap_bits odp_cap; 2189 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2190 struct mlx5_ifc_roce_cap_bits roce_cap; 2191 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2192 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2193 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2194 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2195 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2196 struct mlx5_ifc_qos_cap_bits qos_cap; 2197 u8 reserved_at_0[0x8000]; 2198 }; 2199 2200 enum { 2201 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2202 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2203 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2204 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2205 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10, 2206 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2207 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2208 }; 2209 2210 struct mlx5_ifc_flow_context_bits { 2211 u8 reserved_at_0[0x20]; 2212 2213 u8 group_id[0x20]; 2214 2215 u8 reserved_at_40[0x8]; 2216 u8 flow_tag[0x18]; 2217 2218 u8 reserved_at_60[0x10]; 2219 u8 action[0x10]; 2220 2221 u8 reserved_at_80[0x8]; 2222 u8 destination_list_size[0x18]; 2223 2224 u8 reserved_at_a0[0x8]; 2225 u8 flow_counter_list_size[0x18]; 2226 2227 u8 encap_id[0x20]; 2228 2229 u8 modify_header_id[0x20]; 2230 2231 u8 reserved_at_100[0x100]; 2232 2233 struct mlx5_ifc_fte_match_param_bits match_value; 2234 2235 u8 reserved_at_1200[0x600]; 2236 2237 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2238 }; 2239 2240 enum { 2241 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2242 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2243 }; 2244 2245 struct mlx5_ifc_xrc_srqc_bits { 2246 u8 state[0x4]; 2247 u8 log_xrc_srq_size[0x4]; 2248 u8 reserved_at_8[0x18]; 2249 2250 u8 wq_signature[0x1]; 2251 u8 cont_srq[0x1]; 2252 u8 reserved_at_22[0x1]; 2253 u8 rlky[0x1]; 2254 u8 basic_cyclic_rcv_wqe[0x1]; 2255 u8 log_rq_stride[0x3]; 2256 u8 xrcd[0x18]; 2257 2258 u8 page_offset[0x6]; 2259 u8 reserved_at_46[0x2]; 2260 u8 cqn[0x18]; 2261 2262 u8 reserved_at_60[0x20]; 2263 2264 u8 user_index_equal_xrc_srqn[0x1]; 2265 u8 reserved_at_81[0x1]; 2266 u8 log_page_size[0x6]; 2267 u8 user_index[0x18]; 2268 2269 u8 reserved_at_a0[0x20]; 2270 2271 u8 reserved_at_c0[0x8]; 2272 u8 pd[0x18]; 2273 2274 u8 lwm[0x10]; 2275 u8 wqe_cnt[0x10]; 2276 2277 u8 reserved_at_100[0x40]; 2278 2279 u8 db_record_addr_h[0x20]; 2280 2281 u8 db_record_addr_l[0x1e]; 2282 u8 reserved_at_17e[0x2]; 2283 2284 u8 reserved_at_180[0x80]; 2285 }; 2286 2287 struct mlx5_ifc_traffic_counter_bits { 2288 u8 packets[0x40]; 2289 2290 u8 octets[0x40]; 2291 }; 2292 2293 struct mlx5_ifc_tisc_bits { 2294 u8 strict_lag_tx_port_affinity[0x1]; 2295 u8 reserved_at_1[0x3]; 2296 u8 lag_tx_port_affinity[0x04]; 2297 2298 u8 reserved_at_8[0x4]; 2299 u8 prio[0x4]; 2300 u8 reserved_at_10[0x10]; 2301 2302 u8 reserved_at_20[0x100]; 2303 2304 u8 reserved_at_120[0x8]; 2305 u8 transport_domain[0x18]; 2306 2307 u8 reserved_at_140[0x8]; 2308 u8 underlay_qpn[0x18]; 2309 u8 reserved_at_160[0x3a0]; 2310 }; 2311 2312 enum { 2313 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2314 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2315 }; 2316 2317 enum { 2318 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2319 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2320 }; 2321 2322 enum { 2323 MLX5_RX_HASH_FN_NONE = 0x0, 2324 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2325 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2326 }; 2327 2328 enum { 2329 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 2330 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 2331 }; 2332 2333 struct mlx5_ifc_tirc_bits { 2334 u8 reserved_at_0[0x20]; 2335 2336 u8 disp_type[0x4]; 2337 u8 reserved_at_24[0x1c]; 2338 2339 u8 reserved_at_40[0x40]; 2340 2341 u8 reserved_at_80[0x4]; 2342 u8 lro_timeout_period_usecs[0x10]; 2343 u8 lro_enable_mask[0x4]; 2344 u8 lro_max_ip_payload_size[0x8]; 2345 2346 u8 reserved_at_a0[0x40]; 2347 2348 u8 reserved_at_e0[0x8]; 2349 u8 inline_rqn[0x18]; 2350 2351 u8 rx_hash_symmetric[0x1]; 2352 u8 reserved_at_101[0x1]; 2353 u8 tunneled_offload_en[0x1]; 2354 u8 reserved_at_103[0x5]; 2355 u8 indirect_table[0x18]; 2356 2357 u8 rx_hash_fn[0x4]; 2358 u8 reserved_at_124[0x2]; 2359 u8 self_lb_block[0x2]; 2360 u8 transport_domain[0x18]; 2361 2362 u8 rx_hash_toeplitz_key[10][0x20]; 2363 2364 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2365 2366 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2367 2368 u8 reserved_at_2c0[0x4c0]; 2369 }; 2370 2371 enum { 2372 MLX5_SRQC_STATE_GOOD = 0x0, 2373 MLX5_SRQC_STATE_ERROR = 0x1, 2374 }; 2375 2376 struct mlx5_ifc_srqc_bits { 2377 u8 state[0x4]; 2378 u8 log_srq_size[0x4]; 2379 u8 reserved_at_8[0x18]; 2380 2381 u8 wq_signature[0x1]; 2382 u8 cont_srq[0x1]; 2383 u8 reserved_at_22[0x1]; 2384 u8 rlky[0x1]; 2385 u8 reserved_at_24[0x1]; 2386 u8 log_rq_stride[0x3]; 2387 u8 xrcd[0x18]; 2388 2389 u8 page_offset[0x6]; 2390 u8 reserved_at_46[0x2]; 2391 u8 cqn[0x18]; 2392 2393 u8 reserved_at_60[0x20]; 2394 2395 u8 reserved_at_80[0x2]; 2396 u8 log_page_size[0x6]; 2397 u8 reserved_at_88[0x18]; 2398 2399 u8 reserved_at_a0[0x20]; 2400 2401 u8 reserved_at_c0[0x8]; 2402 u8 pd[0x18]; 2403 2404 u8 lwm[0x10]; 2405 u8 wqe_cnt[0x10]; 2406 2407 u8 reserved_at_100[0x40]; 2408 2409 u8 dbr_addr[0x40]; 2410 2411 u8 reserved_at_180[0x80]; 2412 }; 2413 2414 enum { 2415 MLX5_SQC_STATE_RST = 0x0, 2416 MLX5_SQC_STATE_RDY = 0x1, 2417 MLX5_SQC_STATE_ERR = 0x3, 2418 }; 2419 2420 struct mlx5_ifc_sqc_bits { 2421 u8 rlky[0x1]; 2422 u8 cd_master[0x1]; 2423 u8 fre[0x1]; 2424 u8 flush_in_error_en[0x1]; 2425 u8 reserved_at_4[0x1]; 2426 u8 min_wqe_inline_mode[0x3]; 2427 u8 state[0x4]; 2428 u8 reg_umr[0x1]; 2429 u8 reserved_at_d[0x13]; 2430 2431 u8 reserved_at_20[0x8]; 2432 u8 user_index[0x18]; 2433 2434 u8 reserved_at_40[0x8]; 2435 u8 cqn[0x18]; 2436 2437 u8 reserved_at_60[0x90]; 2438 2439 u8 packet_pacing_rate_limit_index[0x10]; 2440 u8 tis_lst_sz[0x10]; 2441 u8 reserved_at_110[0x10]; 2442 2443 u8 reserved_at_120[0x40]; 2444 2445 u8 reserved_at_160[0x8]; 2446 u8 tis_num_0[0x18]; 2447 2448 struct mlx5_ifc_wq_bits wq; 2449 }; 2450 2451 enum { 2452 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2453 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2454 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2455 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2456 }; 2457 2458 struct mlx5_ifc_scheduling_context_bits { 2459 u8 element_type[0x8]; 2460 u8 reserved_at_8[0x18]; 2461 2462 u8 element_attributes[0x20]; 2463 2464 u8 parent_element_id[0x20]; 2465 2466 u8 reserved_at_60[0x40]; 2467 2468 u8 bw_share[0x20]; 2469 2470 u8 max_average_bw[0x20]; 2471 2472 u8 reserved_at_e0[0x120]; 2473 }; 2474 2475 struct mlx5_ifc_rqtc_bits { 2476 u8 reserved_at_0[0xa0]; 2477 2478 u8 reserved_at_a0[0x10]; 2479 u8 rqt_max_size[0x10]; 2480 2481 u8 reserved_at_c0[0x10]; 2482 u8 rqt_actual_size[0x10]; 2483 2484 u8 reserved_at_e0[0x6a0]; 2485 2486 struct mlx5_ifc_rq_num_bits rq_num[0]; 2487 }; 2488 2489 enum { 2490 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2491 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2492 }; 2493 2494 enum { 2495 MLX5_RQC_STATE_RST = 0x0, 2496 MLX5_RQC_STATE_RDY = 0x1, 2497 MLX5_RQC_STATE_ERR = 0x3, 2498 }; 2499 2500 struct mlx5_ifc_rqc_bits { 2501 u8 rlky[0x1]; 2502 u8 reserved_at_1[0x1]; 2503 u8 scatter_fcs[0x1]; 2504 u8 vsd[0x1]; 2505 u8 mem_rq_type[0x4]; 2506 u8 state[0x4]; 2507 u8 reserved_at_c[0x1]; 2508 u8 flush_in_error_en[0x1]; 2509 u8 reserved_at_e[0x12]; 2510 2511 u8 reserved_at_20[0x8]; 2512 u8 user_index[0x18]; 2513 2514 u8 reserved_at_40[0x8]; 2515 u8 cqn[0x18]; 2516 2517 u8 counter_set_id[0x8]; 2518 u8 reserved_at_68[0x18]; 2519 2520 u8 reserved_at_80[0x8]; 2521 u8 rmpn[0x18]; 2522 2523 u8 reserved_at_a0[0xe0]; 2524 2525 struct mlx5_ifc_wq_bits wq; 2526 }; 2527 2528 enum { 2529 MLX5_RMPC_STATE_RDY = 0x1, 2530 MLX5_RMPC_STATE_ERR = 0x3, 2531 }; 2532 2533 struct mlx5_ifc_rmpc_bits { 2534 u8 reserved_at_0[0x8]; 2535 u8 state[0x4]; 2536 u8 reserved_at_c[0x14]; 2537 2538 u8 basic_cyclic_rcv_wqe[0x1]; 2539 u8 reserved_at_21[0x1f]; 2540 2541 u8 reserved_at_40[0x140]; 2542 2543 struct mlx5_ifc_wq_bits wq; 2544 }; 2545 2546 struct mlx5_ifc_nic_vport_context_bits { 2547 u8 reserved_at_0[0x5]; 2548 u8 min_wqe_inline_mode[0x3]; 2549 u8 reserved_at_8[0x17]; 2550 u8 roce_en[0x1]; 2551 2552 u8 arm_change_event[0x1]; 2553 u8 reserved_at_21[0x1a]; 2554 u8 event_on_mtu[0x1]; 2555 u8 event_on_promisc_change[0x1]; 2556 u8 event_on_vlan_change[0x1]; 2557 u8 event_on_mc_address_change[0x1]; 2558 u8 event_on_uc_address_change[0x1]; 2559 2560 u8 reserved_at_40[0xf0]; 2561 2562 u8 mtu[0x10]; 2563 2564 u8 system_image_guid[0x40]; 2565 u8 port_guid[0x40]; 2566 u8 node_guid[0x40]; 2567 2568 u8 reserved_at_200[0x140]; 2569 u8 qkey_violation_counter[0x10]; 2570 u8 reserved_at_350[0x430]; 2571 2572 u8 promisc_uc[0x1]; 2573 u8 promisc_mc[0x1]; 2574 u8 promisc_all[0x1]; 2575 u8 reserved_at_783[0x2]; 2576 u8 allowed_list_type[0x3]; 2577 u8 reserved_at_788[0xc]; 2578 u8 allowed_list_size[0xc]; 2579 2580 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2581 2582 u8 reserved_at_7e0[0x20]; 2583 2584 u8 current_uc_mac_address[0][0x40]; 2585 }; 2586 2587 enum { 2588 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2589 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2590 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2591 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2592 }; 2593 2594 struct mlx5_ifc_mkc_bits { 2595 u8 reserved_at_0[0x1]; 2596 u8 free[0x1]; 2597 u8 reserved_at_2[0xd]; 2598 u8 small_fence_on_rdma_read_response[0x1]; 2599 u8 umr_en[0x1]; 2600 u8 a[0x1]; 2601 u8 rw[0x1]; 2602 u8 rr[0x1]; 2603 u8 lw[0x1]; 2604 u8 lr[0x1]; 2605 u8 access_mode[0x2]; 2606 u8 reserved_at_18[0x8]; 2607 2608 u8 qpn[0x18]; 2609 u8 mkey_7_0[0x8]; 2610 2611 u8 reserved_at_40[0x20]; 2612 2613 u8 length64[0x1]; 2614 u8 bsf_en[0x1]; 2615 u8 sync_umr[0x1]; 2616 u8 reserved_at_63[0x2]; 2617 u8 expected_sigerr_count[0x1]; 2618 u8 reserved_at_66[0x1]; 2619 u8 en_rinval[0x1]; 2620 u8 pd[0x18]; 2621 2622 u8 start_addr[0x40]; 2623 2624 u8 len[0x40]; 2625 2626 u8 bsf_octword_size[0x20]; 2627 2628 u8 reserved_at_120[0x80]; 2629 2630 u8 translations_octword_size[0x20]; 2631 2632 u8 reserved_at_1c0[0x1b]; 2633 u8 log_page_size[0x5]; 2634 2635 u8 reserved_at_1e0[0x20]; 2636 }; 2637 2638 struct mlx5_ifc_pkey_bits { 2639 u8 reserved_at_0[0x10]; 2640 u8 pkey[0x10]; 2641 }; 2642 2643 struct mlx5_ifc_array128_auto_bits { 2644 u8 array128_auto[16][0x8]; 2645 }; 2646 2647 struct mlx5_ifc_hca_vport_context_bits { 2648 u8 field_select[0x20]; 2649 2650 u8 reserved_at_20[0xe0]; 2651 2652 u8 sm_virt_aware[0x1]; 2653 u8 has_smi[0x1]; 2654 u8 has_raw[0x1]; 2655 u8 grh_required[0x1]; 2656 u8 reserved_at_104[0xc]; 2657 u8 port_physical_state[0x4]; 2658 u8 vport_state_policy[0x4]; 2659 u8 port_state[0x4]; 2660 u8 vport_state[0x4]; 2661 2662 u8 reserved_at_120[0x20]; 2663 2664 u8 system_image_guid[0x40]; 2665 2666 u8 port_guid[0x40]; 2667 2668 u8 node_guid[0x40]; 2669 2670 u8 cap_mask1[0x20]; 2671 2672 u8 cap_mask1_field_select[0x20]; 2673 2674 u8 cap_mask2[0x20]; 2675 2676 u8 cap_mask2_field_select[0x20]; 2677 2678 u8 reserved_at_280[0x80]; 2679 2680 u8 lid[0x10]; 2681 u8 reserved_at_310[0x4]; 2682 u8 init_type_reply[0x4]; 2683 u8 lmc[0x3]; 2684 u8 subnet_timeout[0x5]; 2685 2686 u8 sm_lid[0x10]; 2687 u8 sm_sl[0x4]; 2688 u8 reserved_at_334[0xc]; 2689 2690 u8 qkey_violation_counter[0x10]; 2691 u8 pkey_violation_counter[0x10]; 2692 2693 u8 reserved_at_360[0xca0]; 2694 }; 2695 2696 struct mlx5_ifc_esw_vport_context_bits { 2697 u8 reserved_at_0[0x3]; 2698 u8 vport_svlan_strip[0x1]; 2699 u8 vport_cvlan_strip[0x1]; 2700 u8 vport_svlan_insert[0x1]; 2701 u8 vport_cvlan_insert[0x2]; 2702 u8 reserved_at_8[0x18]; 2703 2704 u8 reserved_at_20[0x20]; 2705 2706 u8 svlan_cfi[0x1]; 2707 u8 svlan_pcp[0x3]; 2708 u8 svlan_id[0xc]; 2709 u8 cvlan_cfi[0x1]; 2710 u8 cvlan_pcp[0x3]; 2711 u8 cvlan_id[0xc]; 2712 2713 u8 reserved_at_60[0x7a0]; 2714 }; 2715 2716 enum { 2717 MLX5_EQC_STATUS_OK = 0x0, 2718 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2719 }; 2720 2721 enum { 2722 MLX5_EQC_ST_ARMED = 0x9, 2723 MLX5_EQC_ST_FIRED = 0xa, 2724 }; 2725 2726 struct mlx5_ifc_eqc_bits { 2727 u8 status[0x4]; 2728 u8 reserved_at_4[0x9]; 2729 u8 ec[0x1]; 2730 u8 oi[0x1]; 2731 u8 reserved_at_f[0x5]; 2732 u8 st[0x4]; 2733 u8 reserved_at_18[0x8]; 2734 2735 u8 reserved_at_20[0x20]; 2736 2737 u8 reserved_at_40[0x14]; 2738 u8 page_offset[0x6]; 2739 u8 reserved_at_5a[0x6]; 2740 2741 u8 reserved_at_60[0x3]; 2742 u8 log_eq_size[0x5]; 2743 u8 uar_page[0x18]; 2744 2745 u8 reserved_at_80[0x20]; 2746 2747 u8 reserved_at_a0[0x18]; 2748 u8 intr[0x8]; 2749 2750 u8 reserved_at_c0[0x3]; 2751 u8 log_page_size[0x5]; 2752 u8 reserved_at_c8[0x18]; 2753 2754 u8 reserved_at_e0[0x60]; 2755 2756 u8 reserved_at_140[0x8]; 2757 u8 consumer_counter[0x18]; 2758 2759 u8 reserved_at_160[0x8]; 2760 u8 producer_counter[0x18]; 2761 2762 u8 reserved_at_180[0x80]; 2763 }; 2764 2765 enum { 2766 MLX5_DCTC_STATE_ACTIVE = 0x0, 2767 MLX5_DCTC_STATE_DRAINING = 0x1, 2768 MLX5_DCTC_STATE_DRAINED = 0x2, 2769 }; 2770 2771 enum { 2772 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2773 MLX5_DCTC_CS_RES_NA = 0x1, 2774 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2775 }; 2776 2777 enum { 2778 MLX5_DCTC_MTU_256_BYTES = 0x1, 2779 MLX5_DCTC_MTU_512_BYTES = 0x2, 2780 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2781 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2782 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2783 }; 2784 2785 struct mlx5_ifc_dctc_bits { 2786 u8 reserved_at_0[0x4]; 2787 u8 state[0x4]; 2788 u8 reserved_at_8[0x18]; 2789 2790 u8 reserved_at_20[0x8]; 2791 u8 user_index[0x18]; 2792 2793 u8 reserved_at_40[0x8]; 2794 u8 cqn[0x18]; 2795 2796 u8 counter_set_id[0x8]; 2797 u8 atomic_mode[0x4]; 2798 u8 rre[0x1]; 2799 u8 rwe[0x1]; 2800 u8 rae[0x1]; 2801 u8 atomic_like_write_en[0x1]; 2802 u8 latency_sensitive[0x1]; 2803 u8 rlky[0x1]; 2804 u8 free_ar[0x1]; 2805 u8 reserved_at_73[0xd]; 2806 2807 u8 reserved_at_80[0x8]; 2808 u8 cs_res[0x8]; 2809 u8 reserved_at_90[0x3]; 2810 u8 min_rnr_nak[0x5]; 2811 u8 reserved_at_98[0x8]; 2812 2813 u8 reserved_at_a0[0x8]; 2814 u8 srqn_xrqn[0x18]; 2815 2816 u8 reserved_at_c0[0x8]; 2817 u8 pd[0x18]; 2818 2819 u8 tclass[0x8]; 2820 u8 reserved_at_e8[0x4]; 2821 u8 flow_label[0x14]; 2822 2823 u8 dc_access_key[0x40]; 2824 2825 u8 reserved_at_140[0x5]; 2826 u8 mtu[0x3]; 2827 u8 port[0x8]; 2828 u8 pkey_index[0x10]; 2829 2830 u8 reserved_at_160[0x8]; 2831 u8 my_addr_index[0x8]; 2832 u8 reserved_at_170[0x8]; 2833 u8 hop_limit[0x8]; 2834 2835 u8 dc_access_key_violation_count[0x20]; 2836 2837 u8 reserved_at_1a0[0x14]; 2838 u8 dei_cfi[0x1]; 2839 u8 eth_prio[0x3]; 2840 u8 ecn[0x2]; 2841 u8 dscp[0x6]; 2842 2843 u8 reserved_at_1c0[0x40]; 2844 }; 2845 2846 enum { 2847 MLX5_CQC_STATUS_OK = 0x0, 2848 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2849 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2850 }; 2851 2852 enum { 2853 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 2854 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 2855 }; 2856 2857 enum { 2858 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 2859 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 2860 MLX5_CQC_ST_FIRED = 0xa, 2861 }; 2862 2863 enum { 2864 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2865 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2866 MLX5_CQ_PERIOD_NUM_MODES 2867 }; 2868 2869 struct mlx5_ifc_cqc_bits { 2870 u8 status[0x4]; 2871 u8 reserved_at_4[0x4]; 2872 u8 cqe_sz[0x3]; 2873 u8 cc[0x1]; 2874 u8 reserved_at_c[0x1]; 2875 u8 scqe_break_moderation_en[0x1]; 2876 u8 oi[0x1]; 2877 u8 cq_period_mode[0x2]; 2878 u8 cqe_comp_en[0x1]; 2879 u8 mini_cqe_res_format[0x2]; 2880 u8 st[0x4]; 2881 u8 reserved_at_18[0x8]; 2882 2883 u8 reserved_at_20[0x20]; 2884 2885 u8 reserved_at_40[0x14]; 2886 u8 page_offset[0x6]; 2887 u8 reserved_at_5a[0x6]; 2888 2889 u8 reserved_at_60[0x3]; 2890 u8 log_cq_size[0x5]; 2891 u8 uar_page[0x18]; 2892 2893 u8 reserved_at_80[0x4]; 2894 u8 cq_period[0xc]; 2895 u8 cq_max_count[0x10]; 2896 2897 u8 reserved_at_a0[0x18]; 2898 u8 c_eqn[0x8]; 2899 2900 u8 reserved_at_c0[0x3]; 2901 u8 log_page_size[0x5]; 2902 u8 reserved_at_c8[0x18]; 2903 2904 u8 reserved_at_e0[0x20]; 2905 2906 u8 reserved_at_100[0x8]; 2907 u8 last_notified_index[0x18]; 2908 2909 u8 reserved_at_120[0x8]; 2910 u8 last_solicit_index[0x18]; 2911 2912 u8 reserved_at_140[0x8]; 2913 u8 consumer_counter[0x18]; 2914 2915 u8 reserved_at_160[0x8]; 2916 u8 producer_counter[0x18]; 2917 2918 u8 reserved_at_180[0x40]; 2919 2920 u8 dbr_addr[0x40]; 2921 }; 2922 2923 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2924 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2925 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2926 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2927 u8 reserved_at_0[0x800]; 2928 }; 2929 2930 struct mlx5_ifc_query_adapter_param_block_bits { 2931 u8 reserved_at_0[0xc0]; 2932 2933 u8 reserved_at_c0[0x8]; 2934 u8 ieee_vendor_id[0x18]; 2935 2936 u8 reserved_at_e0[0x10]; 2937 u8 vsd_vendor_id[0x10]; 2938 2939 u8 vsd[208][0x8]; 2940 2941 u8 vsd_contd_psid[16][0x8]; 2942 }; 2943 2944 enum { 2945 MLX5_XRQC_STATE_GOOD = 0x0, 2946 MLX5_XRQC_STATE_ERROR = 0x1, 2947 }; 2948 2949 enum { 2950 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 2951 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 2952 }; 2953 2954 enum { 2955 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 2956 }; 2957 2958 struct mlx5_ifc_tag_matching_topology_context_bits { 2959 u8 log_matching_list_sz[0x4]; 2960 u8 reserved_at_4[0xc]; 2961 u8 append_next_index[0x10]; 2962 2963 u8 sw_phase_cnt[0x10]; 2964 u8 hw_phase_cnt[0x10]; 2965 2966 u8 reserved_at_40[0x40]; 2967 }; 2968 2969 struct mlx5_ifc_xrqc_bits { 2970 u8 state[0x4]; 2971 u8 rlkey[0x1]; 2972 u8 reserved_at_5[0xf]; 2973 u8 topology[0x4]; 2974 u8 reserved_at_18[0x4]; 2975 u8 offload[0x4]; 2976 2977 u8 reserved_at_20[0x8]; 2978 u8 user_index[0x18]; 2979 2980 u8 reserved_at_40[0x8]; 2981 u8 cqn[0x18]; 2982 2983 u8 reserved_at_60[0xa0]; 2984 2985 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 2986 2987 u8 reserved_at_180[0x880]; 2988 2989 struct mlx5_ifc_wq_bits wq; 2990 }; 2991 2992 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2993 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2994 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2995 u8 reserved_at_0[0x20]; 2996 }; 2997 2998 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2999 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3000 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3001 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3002 u8 reserved_at_0[0x20]; 3003 }; 3004 3005 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3006 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3007 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3008 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3009 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3010 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3011 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3012 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3013 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3014 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3015 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3016 u8 reserved_at_0[0x7c0]; 3017 }; 3018 3019 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3020 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3021 u8 reserved_at_0[0x7c0]; 3022 }; 3023 3024 union mlx5_ifc_event_auto_bits { 3025 struct mlx5_ifc_comp_event_bits comp_event; 3026 struct mlx5_ifc_dct_events_bits dct_events; 3027 struct mlx5_ifc_qp_events_bits qp_events; 3028 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3029 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3030 struct mlx5_ifc_cq_error_bits cq_error; 3031 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3032 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3033 struct mlx5_ifc_gpio_event_bits gpio_event; 3034 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3035 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3036 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3037 u8 reserved_at_0[0xe0]; 3038 }; 3039 3040 struct mlx5_ifc_health_buffer_bits { 3041 u8 reserved_at_0[0x100]; 3042 3043 u8 assert_existptr[0x20]; 3044 3045 u8 assert_callra[0x20]; 3046 3047 u8 reserved_at_140[0x40]; 3048 3049 u8 fw_version[0x20]; 3050 3051 u8 hw_id[0x20]; 3052 3053 u8 reserved_at_1c0[0x20]; 3054 3055 u8 irisc_index[0x8]; 3056 u8 synd[0x8]; 3057 u8 ext_synd[0x10]; 3058 }; 3059 3060 struct mlx5_ifc_register_loopback_control_bits { 3061 u8 no_lb[0x1]; 3062 u8 reserved_at_1[0x7]; 3063 u8 port[0x8]; 3064 u8 reserved_at_10[0x10]; 3065 3066 u8 reserved_at_20[0x60]; 3067 }; 3068 3069 struct mlx5_ifc_vport_tc_element_bits { 3070 u8 traffic_class[0x4]; 3071 u8 reserved_at_4[0xc]; 3072 u8 vport_number[0x10]; 3073 }; 3074 3075 struct mlx5_ifc_vport_element_bits { 3076 u8 reserved_at_0[0x10]; 3077 u8 vport_number[0x10]; 3078 }; 3079 3080 enum { 3081 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3082 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3083 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3084 }; 3085 3086 struct mlx5_ifc_tsar_element_bits { 3087 u8 reserved_at_0[0x8]; 3088 u8 tsar_type[0x8]; 3089 u8 reserved_at_10[0x10]; 3090 }; 3091 3092 struct mlx5_ifc_teardown_hca_out_bits { 3093 u8 status[0x8]; 3094 u8 reserved_at_8[0x18]; 3095 3096 u8 syndrome[0x20]; 3097 3098 u8 reserved_at_40[0x40]; 3099 }; 3100 3101 enum { 3102 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3103 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1, 3104 }; 3105 3106 struct mlx5_ifc_teardown_hca_in_bits { 3107 u8 opcode[0x10]; 3108 u8 reserved_at_10[0x10]; 3109 3110 u8 reserved_at_20[0x10]; 3111 u8 op_mod[0x10]; 3112 3113 u8 reserved_at_40[0x10]; 3114 u8 profile[0x10]; 3115 3116 u8 reserved_at_60[0x20]; 3117 }; 3118 3119 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3120 u8 status[0x8]; 3121 u8 reserved_at_8[0x18]; 3122 3123 u8 syndrome[0x20]; 3124 3125 u8 reserved_at_40[0x40]; 3126 }; 3127 3128 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3129 u8 opcode[0x10]; 3130 u8 reserved_at_10[0x10]; 3131 3132 u8 reserved_at_20[0x10]; 3133 u8 op_mod[0x10]; 3134 3135 u8 reserved_at_40[0x8]; 3136 u8 qpn[0x18]; 3137 3138 u8 reserved_at_60[0x20]; 3139 3140 u8 opt_param_mask[0x20]; 3141 3142 u8 reserved_at_a0[0x20]; 3143 3144 struct mlx5_ifc_qpc_bits qpc; 3145 3146 u8 reserved_at_800[0x80]; 3147 }; 3148 3149 struct mlx5_ifc_sqd2rts_qp_out_bits { 3150 u8 status[0x8]; 3151 u8 reserved_at_8[0x18]; 3152 3153 u8 syndrome[0x20]; 3154 3155 u8 reserved_at_40[0x40]; 3156 }; 3157 3158 struct mlx5_ifc_sqd2rts_qp_in_bits { 3159 u8 opcode[0x10]; 3160 u8 reserved_at_10[0x10]; 3161 3162 u8 reserved_at_20[0x10]; 3163 u8 op_mod[0x10]; 3164 3165 u8 reserved_at_40[0x8]; 3166 u8 qpn[0x18]; 3167 3168 u8 reserved_at_60[0x20]; 3169 3170 u8 opt_param_mask[0x20]; 3171 3172 u8 reserved_at_a0[0x20]; 3173 3174 struct mlx5_ifc_qpc_bits qpc; 3175 3176 u8 reserved_at_800[0x80]; 3177 }; 3178 3179 struct mlx5_ifc_set_roce_address_out_bits { 3180 u8 status[0x8]; 3181 u8 reserved_at_8[0x18]; 3182 3183 u8 syndrome[0x20]; 3184 3185 u8 reserved_at_40[0x40]; 3186 }; 3187 3188 struct mlx5_ifc_set_roce_address_in_bits { 3189 u8 opcode[0x10]; 3190 u8 reserved_at_10[0x10]; 3191 3192 u8 reserved_at_20[0x10]; 3193 u8 op_mod[0x10]; 3194 3195 u8 roce_address_index[0x10]; 3196 u8 reserved_at_50[0x10]; 3197 3198 u8 reserved_at_60[0x20]; 3199 3200 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3201 }; 3202 3203 struct mlx5_ifc_set_mad_demux_out_bits { 3204 u8 status[0x8]; 3205 u8 reserved_at_8[0x18]; 3206 3207 u8 syndrome[0x20]; 3208 3209 u8 reserved_at_40[0x40]; 3210 }; 3211 3212 enum { 3213 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3214 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3215 }; 3216 3217 struct mlx5_ifc_set_mad_demux_in_bits { 3218 u8 opcode[0x10]; 3219 u8 reserved_at_10[0x10]; 3220 3221 u8 reserved_at_20[0x10]; 3222 u8 op_mod[0x10]; 3223 3224 u8 reserved_at_40[0x20]; 3225 3226 u8 reserved_at_60[0x6]; 3227 u8 demux_mode[0x2]; 3228 u8 reserved_at_68[0x18]; 3229 }; 3230 3231 struct mlx5_ifc_set_l2_table_entry_out_bits { 3232 u8 status[0x8]; 3233 u8 reserved_at_8[0x18]; 3234 3235 u8 syndrome[0x20]; 3236 3237 u8 reserved_at_40[0x40]; 3238 }; 3239 3240 struct mlx5_ifc_set_l2_table_entry_in_bits { 3241 u8 opcode[0x10]; 3242 u8 reserved_at_10[0x10]; 3243 3244 u8 reserved_at_20[0x10]; 3245 u8 op_mod[0x10]; 3246 3247 u8 reserved_at_40[0x60]; 3248 3249 u8 reserved_at_a0[0x8]; 3250 u8 table_index[0x18]; 3251 3252 u8 reserved_at_c0[0x20]; 3253 3254 u8 reserved_at_e0[0x13]; 3255 u8 vlan_valid[0x1]; 3256 u8 vlan[0xc]; 3257 3258 struct mlx5_ifc_mac_address_layout_bits mac_address; 3259 3260 u8 reserved_at_140[0xc0]; 3261 }; 3262 3263 struct mlx5_ifc_set_issi_out_bits { 3264 u8 status[0x8]; 3265 u8 reserved_at_8[0x18]; 3266 3267 u8 syndrome[0x20]; 3268 3269 u8 reserved_at_40[0x40]; 3270 }; 3271 3272 struct mlx5_ifc_set_issi_in_bits { 3273 u8 opcode[0x10]; 3274 u8 reserved_at_10[0x10]; 3275 3276 u8 reserved_at_20[0x10]; 3277 u8 op_mod[0x10]; 3278 3279 u8 reserved_at_40[0x10]; 3280 u8 current_issi[0x10]; 3281 3282 u8 reserved_at_60[0x20]; 3283 }; 3284 3285 struct mlx5_ifc_set_hca_cap_out_bits { 3286 u8 status[0x8]; 3287 u8 reserved_at_8[0x18]; 3288 3289 u8 syndrome[0x20]; 3290 3291 u8 reserved_at_40[0x40]; 3292 }; 3293 3294 struct mlx5_ifc_set_hca_cap_in_bits { 3295 u8 opcode[0x10]; 3296 u8 reserved_at_10[0x10]; 3297 3298 u8 reserved_at_20[0x10]; 3299 u8 op_mod[0x10]; 3300 3301 u8 reserved_at_40[0x40]; 3302 3303 union mlx5_ifc_hca_cap_union_bits capability; 3304 }; 3305 3306 enum { 3307 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3308 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3309 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3310 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3311 }; 3312 3313 struct mlx5_ifc_set_fte_out_bits { 3314 u8 status[0x8]; 3315 u8 reserved_at_8[0x18]; 3316 3317 u8 syndrome[0x20]; 3318 3319 u8 reserved_at_40[0x40]; 3320 }; 3321 3322 struct mlx5_ifc_set_fte_in_bits { 3323 u8 opcode[0x10]; 3324 u8 reserved_at_10[0x10]; 3325 3326 u8 reserved_at_20[0x10]; 3327 u8 op_mod[0x10]; 3328 3329 u8 other_vport[0x1]; 3330 u8 reserved_at_41[0xf]; 3331 u8 vport_number[0x10]; 3332 3333 u8 reserved_at_60[0x20]; 3334 3335 u8 table_type[0x8]; 3336 u8 reserved_at_88[0x18]; 3337 3338 u8 reserved_at_a0[0x8]; 3339 u8 table_id[0x18]; 3340 3341 u8 reserved_at_c0[0x18]; 3342 u8 modify_enable_mask[0x8]; 3343 3344 u8 reserved_at_e0[0x20]; 3345 3346 u8 flow_index[0x20]; 3347 3348 u8 reserved_at_120[0xe0]; 3349 3350 struct mlx5_ifc_flow_context_bits flow_context; 3351 }; 3352 3353 struct mlx5_ifc_rts2rts_qp_out_bits { 3354 u8 status[0x8]; 3355 u8 reserved_at_8[0x18]; 3356 3357 u8 syndrome[0x20]; 3358 3359 u8 reserved_at_40[0x40]; 3360 }; 3361 3362 struct mlx5_ifc_rts2rts_qp_in_bits { 3363 u8 opcode[0x10]; 3364 u8 reserved_at_10[0x10]; 3365 3366 u8 reserved_at_20[0x10]; 3367 u8 op_mod[0x10]; 3368 3369 u8 reserved_at_40[0x8]; 3370 u8 qpn[0x18]; 3371 3372 u8 reserved_at_60[0x20]; 3373 3374 u8 opt_param_mask[0x20]; 3375 3376 u8 reserved_at_a0[0x20]; 3377 3378 struct mlx5_ifc_qpc_bits qpc; 3379 3380 u8 reserved_at_800[0x80]; 3381 }; 3382 3383 struct mlx5_ifc_rtr2rts_qp_out_bits { 3384 u8 status[0x8]; 3385 u8 reserved_at_8[0x18]; 3386 3387 u8 syndrome[0x20]; 3388 3389 u8 reserved_at_40[0x40]; 3390 }; 3391 3392 struct mlx5_ifc_rtr2rts_qp_in_bits { 3393 u8 opcode[0x10]; 3394 u8 reserved_at_10[0x10]; 3395 3396 u8 reserved_at_20[0x10]; 3397 u8 op_mod[0x10]; 3398 3399 u8 reserved_at_40[0x8]; 3400 u8 qpn[0x18]; 3401 3402 u8 reserved_at_60[0x20]; 3403 3404 u8 opt_param_mask[0x20]; 3405 3406 u8 reserved_at_a0[0x20]; 3407 3408 struct mlx5_ifc_qpc_bits qpc; 3409 3410 u8 reserved_at_800[0x80]; 3411 }; 3412 3413 struct mlx5_ifc_rst2init_qp_out_bits { 3414 u8 status[0x8]; 3415 u8 reserved_at_8[0x18]; 3416 3417 u8 syndrome[0x20]; 3418 3419 u8 reserved_at_40[0x40]; 3420 }; 3421 3422 struct mlx5_ifc_rst2init_qp_in_bits { 3423 u8 opcode[0x10]; 3424 u8 reserved_at_10[0x10]; 3425 3426 u8 reserved_at_20[0x10]; 3427 u8 op_mod[0x10]; 3428 3429 u8 reserved_at_40[0x8]; 3430 u8 qpn[0x18]; 3431 3432 u8 reserved_at_60[0x20]; 3433 3434 u8 opt_param_mask[0x20]; 3435 3436 u8 reserved_at_a0[0x20]; 3437 3438 struct mlx5_ifc_qpc_bits qpc; 3439 3440 u8 reserved_at_800[0x80]; 3441 }; 3442 3443 struct mlx5_ifc_query_xrq_out_bits { 3444 u8 status[0x8]; 3445 u8 reserved_at_8[0x18]; 3446 3447 u8 syndrome[0x20]; 3448 3449 u8 reserved_at_40[0x40]; 3450 3451 struct mlx5_ifc_xrqc_bits xrq_context; 3452 }; 3453 3454 struct mlx5_ifc_query_xrq_in_bits { 3455 u8 opcode[0x10]; 3456 u8 reserved_at_10[0x10]; 3457 3458 u8 reserved_at_20[0x10]; 3459 u8 op_mod[0x10]; 3460 3461 u8 reserved_at_40[0x8]; 3462 u8 xrqn[0x18]; 3463 3464 u8 reserved_at_60[0x20]; 3465 }; 3466 3467 struct mlx5_ifc_query_xrc_srq_out_bits { 3468 u8 status[0x8]; 3469 u8 reserved_at_8[0x18]; 3470 3471 u8 syndrome[0x20]; 3472 3473 u8 reserved_at_40[0x40]; 3474 3475 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3476 3477 u8 reserved_at_280[0x600]; 3478 3479 u8 pas[0][0x40]; 3480 }; 3481 3482 struct mlx5_ifc_query_xrc_srq_in_bits { 3483 u8 opcode[0x10]; 3484 u8 reserved_at_10[0x10]; 3485 3486 u8 reserved_at_20[0x10]; 3487 u8 op_mod[0x10]; 3488 3489 u8 reserved_at_40[0x8]; 3490 u8 xrc_srqn[0x18]; 3491 3492 u8 reserved_at_60[0x20]; 3493 }; 3494 3495 enum { 3496 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3497 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3498 }; 3499 3500 struct mlx5_ifc_query_vport_state_out_bits { 3501 u8 status[0x8]; 3502 u8 reserved_at_8[0x18]; 3503 3504 u8 syndrome[0x20]; 3505 3506 u8 reserved_at_40[0x20]; 3507 3508 u8 reserved_at_60[0x18]; 3509 u8 admin_state[0x4]; 3510 u8 state[0x4]; 3511 }; 3512 3513 enum { 3514 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3515 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3516 }; 3517 3518 struct mlx5_ifc_query_vport_state_in_bits { 3519 u8 opcode[0x10]; 3520 u8 reserved_at_10[0x10]; 3521 3522 u8 reserved_at_20[0x10]; 3523 u8 op_mod[0x10]; 3524 3525 u8 other_vport[0x1]; 3526 u8 reserved_at_41[0xf]; 3527 u8 vport_number[0x10]; 3528 3529 u8 reserved_at_60[0x20]; 3530 }; 3531 3532 struct mlx5_ifc_query_vport_counter_out_bits { 3533 u8 status[0x8]; 3534 u8 reserved_at_8[0x18]; 3535 3536 u8 syndrome[0x20]; 3537 3538 u8 reserved_at_40[0x40]; 3539 3540 struct mlx5_ifc_traffic_counter_bits received_errors; 3541 3542 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3543 3544 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3545 3546 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3547 3548 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3549 3550 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3551 3552 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3553 3554 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3555 3556 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3557 3558 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3559 3560 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3561 3562 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3563 3564 u8 reserved_at_680[0xa00]; 3565 }; 3566 3567 enum { 3568 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3569 }; 3570 3571 struct mlx5_ifc_query_vport_counter_in_bits { 3572 u8 opcode[0x10]; 3573 u8 reserved_at_10[0x10]; 3574 3575 u8 reserved_at_20[0x10]; 3576 u8 op_mod[0x10]; 3577 3578 u8 other_vport[0x1]; 3579 u8 reserved_at_41[0xb]; 3580 u8 port_num[0x4]; 3581 u8 vport_number[0x10]; 3582 3583 u8 reserved_at_60[0x60]; 3584 3585 u8 clear[0x1]; 3586 u8 reserved_at_c1[0x1f]; 3587 3588 u8 reserved_at_e0[0x20]; 3589 }; 3590 3591 struct mlx5_ifc_query_tis_out_bits { 3592 u8 status[0x8]; 3593 u8 reserved_at_8[0x18]; 3594 3595 u8 syndrome[0x20]; 3596 3597 u8 reserved_at_40[0x40]; 3598 3599 struct mlx5_ifc_tisc_bits tis_context; 3600 }; 3601 3602 struct mlx5_ifc_query_tis_in_bits { 3603 u8 opcode[0x10]; 3604 u8 reserved_at_10[0x10]; 3605 3606 u8 reserved_at_20[0x10]; 3607 u8 op_mod[0x10]; 3608 3609 u8 reserved_at_40[0x8]; 3610 u8 tisn[0x18]; 3611 3612 u8 reserved_at_60[0x20]; 3613 }; 3614 3615 struct mlx5_ifc_query_tir_out_bits { 3616 u8 status[0x8]; 3617 u8 reserved_at_8[0x18]; 3618 3619 u8 syndrome[0x20]; 3620 3621 u8 reserved_at_40[0xc0]; 3622 3623 struct mlx5_ifc_tirc_bits tir_context; 3624 }; 3625 3626 struct mlx5_ifc_query_tir_in_bits { 3627 u8 opcode[0x10]; 3628 u8 reserved_at_10[0x10]; 3629 3630 u8 reserved_at_20[0x10]; 3631 u8 op_mod[0x10]; 3632 3633 u8 reserved_at_40[0x8]; 3634 u8 tirn[0x18]; 3635 3636 u8 reserved_at_60[0x20]; 3637 }; 3638 3639 struct mlx5_ifc_query_srq_out_bits { 3640 u8 status[0x8]; 3641 u8 reserved_at_8[0x18]; 3642 3643 u8 syndrome[0x20]; 3644 3645 u8 reserved_at_40[0x40]; 3646 3647 struct mlx5_ifc_srqc_bits srq_context_entry; 3648 3649 u8 reserved_at_280[0x600]; 3650 3651 u8 pas[0][0x40]; 3652 }; 3653 3654 struct mlx5_ifc_query_srq_in_bits { 3655 u8 opcode[0x10]; 3656 u8 reserved_at_10[0x10]; 3657 3658 u8 reserved_at_20[0x10]; 3659 u8 op_mod[0x10]; 3660 3661 u8 reserved_at_40[0x8]; 3662 u8 srqn[0x18]; 3663 3664 u8 reserved_at_60[0x20]; 3665 }; 3666 3667 struct mlx5_ifc_query_sq_out_bits { 3668 u8 status[0x8]; 3669 u8 reserved_at_8[0x18]; 3670 3671 u8 syndrome[0x20]; 3672 3673 u8 reserved_at_40[0xc0]; 3674 3675 struct mlx5_ifc_sqc_bits sq_context; 3676 }; 3677 3678 struct mlx5_ifc_query_sq_in_bits { 3679 u8 opcode[0x10]; 3680 u8 reserved_at_10[0x10]; 3681 3682 u8 reserved_at_20[0x10]; 3683 u8 op_mod[0x10]; 3684 3685 u8 reserved_at_40[0x8]; 3686 u8 sqn[0x18]; 3687 3688 u8 reserved_at_60[0x20]; 3689 }; 3690 3691 struct mlx5_ifc_query_special_contexts_out_bits { 3692 u8 status[0x8]; 3693 u8 reserved_at_8[0x18]; 3694 3695 u8 syndrome[0x20]; 3696 3697 u8 dump_fill_mkey[0x20]; 3698 3699 u8 resd_lkey[0x20]; 3700 3701 u8 null_mkey[0x20]; 3702 3703 u8 reserved_at_a0[0x60]; 3704 }; 3705 3706 struct mlx5_ifc_query_special_contexts_in_bits { 3707 u8 opcode[0x10]; 3708 u8 reserved_at_10[0x10]; 3709 3710 u8 reserved_at_20[0x10]; 3711 u8 op_mod[0x10]; 3712 3713 u8 reserved_at_40[0x40]; 3714 }; 3715 3716 struct mlx5_ifc_query_scheduling_element_out_bits { 3717 u8 opcode[0x10]; 3718 u8 reserved_at_10[0x10]; 3719 3720 u8 reserved_at_20[0x10]; 3721 u8 op_mod[0x10]; 3722 3723 u8 reserved_at_40[0xc0]; 3724 3725 struct mlx5_ifc_scheduling_context_bits scheduling_context; 3726 3727 u8 reserved_at_300[0x100]; 3728 }; 3729 3730 enum { 3731 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 3732 }; 3733 3734 struct mlx5_ifc_query_scheduling_element_in_bits { 3735 u8 opcode[0x10]; 3736 u8 reserved_at_10[0x10]; 3737 3738 u8 reserved_at_20[0x10]; 3739 u8 op_mod[0x10]; 3740 3741 u8 scheduling_hierarchy[0x8]; 3742 u8 reserved_at_48[0x18]; 3743 3744 u8 scheduling_element_id[0x20]; 3745 3746 u8 reserved_at_80[0x180]; 3747 }; 3748 3749 struct mlx5_ifc_query_rqt_out_bits { 3750 u8 status[0x8]; 3751 u8 reserved_at_8[0x18]; 3752 3753 u8 syndrome[0x20]; 3754 3755 u8 reserved_at_40[0xc0]; 3756 3757 struct mlx5_ifc_rqtc_bits rqt_context; 3758 }; 3759 3760 struct mlx5_ifc_query_rqt_in_bits { 3761 u8 opcode[0x10]; 3762 u8 reserved_at_10[0x10]; 3763 3764 u8 reserved_at_20[0x10]; 3765 u8 op_mod[0x10]; 3766 3767 u8 reserved_at_40[0x8]; 3768 u8 rqtn[0x18]; 3769 3770 u8 reserved_at_60[0x20]; 3771 }; 3772 3773 struct mlx5_ifc_query_rq_out_bits { 3774 u8 status[0x8]; 3775 u8 reserved_at_8[0x18]; 3776 3777 u8 syndrome[0x20]; 3778 3779 u8 reserved_at_40[0xc0]; 3780 3781 struct mlx5_ifc_rqc_bits rq_context; 3782 }; 3783 3784 struct mlx5_ifc_query_rq_in_bits { 3785 u8 opcode[0x10]; 3786 u8 reserved_at_10[0x10]; 3787 3788 u8 reserved_at_20[0x10]; 3789 u8 op_mod[0x10]; 3790 3791 u8 reserved_at_40[0x8]; 3792 u8 rqn[0x18]; 3793 3794 u8 reserved_at_60[0x20]; 3795 }; 3796 3797 struct mlx5_ifc_query_roce_address_out_bits { 3798 u8 status[0x8]; 3799 u8 reserved_at_8[0x18]; 3800 3801 u8 syndrome[0x20]; 3802 3803 u8 reserved_at_40[0x40]; 3804 3805 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3806 }; 3807 3808 struct mlx5_ifc_query_roce_address_in_bits { 3809 u8 opcode[0x10]; 3810 u8 reserved_at_10[0x10]; 3811 3812 u8 reserved_at_20[0x10]; 3813 u8 op_mod[0x10]; 3814 3815 u8 roce_address_index[0x10]; 3816 u8 reserved_at_50[0x10]; 3817 3818 u8 reserved_at_60[0x20]; 3819 }; 3820 3821 struct mlx5_ifc_query_rmp_out_bits { 3822 u8 status[0x8]; 3823 u8 reserved_at_8[0x18]; 3824 3825 u8 syndrome[0x20]; 3826 3827 u8 reserved_at_40[0xc0]; 3828 3829 struct mlx5_ifc_rmpc_bits rmp_context; 3830 }; 3831 3832 struct mlx5_ifc_query_rmp_in_bits { 3833 u8 opcode[0x10]; 3834 u8 reserved_at_10[0x10]; 3835 3836 u8 reserved_at_20[0x10]; 3837 u8 op_mod[0x10]; 3838 3839 u8 reserved_at_40[0x8]; 3840 u8 rmpn[0x18]; 3841 3842 u8 reserved_at_60[0x20]; 3843 }; 3844 3845 struct mlx5_ifc_query_qp_out_bits { 3846 u8 status[0x8]; 3847 u8 reserved_at_8[0x18]; 3848 3849 u8 syndrome[0x20]; 3850 3851 u8 reserved_at_40[0x40]; 3852 3853 u8 opt_param_mask[0x20]; 3854 3855 u8 reserved_at_a0[0x20]; 3856 3857 struct mlx5_ifc_qpc_bits qpc; 3858 3859 u8 reserved_at_800[0x80]; 3860 3861 u8 pas[0][0x40]; 3862 }; 3863 3864 struct mlx5_ifc_query_qp_in_bits { 3865 u8 opcode[0x10]; 3866 u8 reserved_at_10[0x10]; 3867 3868 u8 reserved_at_20[0x10]; 3869 u8 op_mod[0x10]; 3870 3871 u8 reserved_at_40[0x8]; 3872 u8 qpn[0x18]; 3873 3874 u8 reserved_at_60[0x20]; 3875 }; 3876 3877 struct mlx5_ifc_query_q_counter_out_bits { 3878 u8 status[0x8]; 3879 u8 reserved_at_8[0x18]; 3880 3881 u8 syndrome[0x20]; 3882 3883 u8 reserved_at_40[0x40]; 3884 3885 u8 rx_write_requests[0x20]; 3886 3887 u8 reserved_at_a0[0x20]; 3888 3889 u8 rx_read_requests[0x20]; 3890 3891 u8 reserved_at_e0[0x20]; 3892 3893 u8 rx_atomic_requests[0x20]; 3894 3895 u8 reserved_at_120[0x20]; 3896 3897 u8 rx_dct_connect[0x20]; 3898 3899 u8 reserved_at_160[0x20]; 3900 3901 u8 out_of_buffer[0x20]; 3902 3903 u8 reserved_at_1a0[0x20]; 3904 3905 u8 out_of_sequence[0x20]; 3906 3907 u8 reserved_at_1e0[0x20]; 3908 3909 u8 duplicate_request[0x20]; 3910 3911 u8 reserved_at_220[0x20]; 3912 3913 u8 rnr_nak_retry_err[0x20]; 3914 3915 u8 reserved_at_260[0x20]; 3916 3917 u8 packet_seq_err[0x20]; 3918 3919 u8 reserved_at_2a0[0x20]; 3920 3921 u8 implied_nak_seq_err[0x20]; 3922 3923 u8 reserved_at_2e0[0x20]; 3924 3925 u8 local_ack_timeout_err[0x20]; 3926 3927 u8 reserved_at_320[0x4e0]; 3928 }; 3929 3930 struct mlx5_ifc_query_q_counter_in_bits { 3931 u8 opcode[0x10]; 3932 u8 reserved_at_10[0x10]; 3933 3934 u8 reserved_at_20[0x10]; 3935 u8 op_mod[0x10]; 3936 3937 u8 reserved_at_40[0x80]; 3938 3939 u8 clear[0x1]; 3940 u8 reserved_at_c1[0x1f]; 3941 3942 u8 reserved_at_e0[0x18]; 3943 u8 counter_set_id[0x8]; 3944 }; 3945 3946 struct mlx5_ifc_query_pages_out_bits { 3947 u8 status[0x8]; 3948 u8 reserved_at_8[0x18]; 3949 3950 u8 syndrome[0x20]; 3951 3952 u8 reserved_at_40[0x10]; 3953 u8 function_id[0x10]; 3954 3955 u8 num_pages[0x20]; 3956 }; 3957 3958 enum { 3959 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 3960 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 3961 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 3962 }; 3963 3964 struct mlx5_ifc_query_pages_in_bits { 3965 u8 opcode[0x10]; 3966 u8 reserved_at_10[0x10]; 3967 3968 u8 reserved_at_20[0x10]; 3969 u8 op_mod[0x10]; 3970 3971 u8 reserved_at_40[0x10]; 3972 u8 function_id[0x10]; 3973 3974 u8 reserved_at_60[0x20]; 3975 }; 3976 3977 struct mlx5_ifc_query_nic_vport_context_out_bits { 3978 u8 status[0x8]; 3979 u8 reserved_at_8[0x18]; 3980 3981 u8 syndrome[0x20]; 3982 3983 u8 reserved_at_40[0x40]; 3984 3985 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 3986 }; 3987 3988 struct mlx5_ifc_query_nic_vport_context_in_bits { 3989 u8 opcode[0x10]; 3990 u8 reserved_at_10[0x10]; 3991 3992 u8 reserved_at_20[0x10]; 3993 u8 op_mod[0x10]; 3994 3995 u8 other_vport[0x1]; 3996 u8 reserved_at_41[0xf]; 3997 u8 vport_number[0x10]; 3998 3999 u8 reserved_at_60[0x5]; 4000 u8 allowed_list_type[0x3]; 4001 u8 reserved_at_68[0x18]; 4002 }; 4003 4004 struct mlx5_ifc_query_mkey_out_bits { 4005 u8 status[0x8]; 4006 u8 reserved_at_8[0x18]; 4007 4008 u8 syndrome[0x20]; 4009 4010 u8 reserved_at_40[0x40]; 4011 4012 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4013 4014 u8 reserved_at_280[0x600]; 4015 4016 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4017 4018 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4019 }; 4020 4021 struct mlx5_ifc_query_mkey_in_bits { 4022 u8 opcode[0x10]; 4023 u8 reserved_at_10[0x10]; 4024 4025 u8 reserved_at_20[0x10]; 4026 u8 op_mod[0x10]; 4027 4028 u8 reserved_at_40[0x8]; 4029 u8 mkey_index[0x18]; 4030 4031 u8 pg_access[0x1]; 4032 u8 reserved_at_61[0x1f]; 4033 }; 4034 4035 struct mlx5_ifc_query_mad_demux_out_bits { 4036 u8 status[0x8]; 4037 u8 reserved_at_8[0x18]; 4038 4039 u8 syndrome[0x20]; 4040 4041 u8 reserved_at_40[0x40]; 4042 4043 u8 mad_dumux_parameters_block[0x20]; 4044 }; 4045 4046 struct mlx5_ifc_query_mad_demux_in_bits { 4047 u8 opcode[0x10]; 4048 u8 reserved_at_10[0x10]; 4049 4050 u8 reserved_at_20[0x10]; 4051 u8 op_mod[0x10]; 4052 4053 u8 reserved_at_40[0x40]; 4054 }; 4055 4056 struct mlx5_ifc_query_l2_table_entry_out_bits { 4057 u8 status[0x8]; 4058 u8 reserved_at_8[0x18]; 4059 4060 u8 syndrome[0x20]; 4061 4062 u8 reserved_at_40[0xa0]; 4063 4064 u8 reserved_at_e0[0x13]; 4065 u8 vlan_valid[0x1]; 4066 u8 vlan[0xc]; 4067 4068 struct mlx5_ifc_mac_address_layout_bits mac_address; 4069 4070 u8 reserved_at_140[0xc0]; 4071 }; 4072 4073 struct mlx5_ifc_query_l2_table_entry_in_bits { 4074 u8 opcode[0x10]; 4075 u8 reserved_at_10[0x10]; 4076 4077 u8 reserved_at_20[0x10]; 4078 u8 op_mod[0x10]; 4079 4080 u8 reserved_at_40[0x60]; 4081 4082 u8 reserved_at_a0[0x8]; 4083 u8 table_index[0x18]; 4084 4085 u8 reserved_at_c0[0x140]; 4086 }; 4087 4088 struct mlx5_ifc_query_issi_out_bits { 4089 u8 status[0x8]; 4090 u8 reserved_at_8[0x18]; 4091 4092 u8 syndrome[0x20]; 4093 4094 u8 reserved_at_40[0x10]; 4095 u8 current_issi[0x10]; 4096 4097 u8 reserved_at_60[0xa0]; 4098 4099 u8 reserved_at_100[76][0x8]; 4100 u8 supported_issi_dw0[0x20]; 4101 }; 4102 4103 struct mlx5_ifc_query_issi_in_bits { 4104 u8 opcode[0x10]; 4105 u8 reserved_at_10[0x10]; 4106 4107 u8 reserved_at_20[0x10]; 4108 u8 op_mod[0x10]; 4109 4110 u8 reserved_at_40[0x40]; 4111 }; 4112 4113 struct mlx5_ifc_set_driver_version_out_bits { 4114 u8 status[0x8]; 4115 u8 reserved_0[0x18]; 4116 4117 u8 syndrome[0x20]; 4118 u8 reserved_1[0x40]; 4119 }; 4120 4121 struct mlx5_ifc_set_driver_version_in_bits { 4122 u8 opcode[0x10]; 4123 u8 reserved_0[0x10]; 4124 4125 u8 reserved_1[0x10]; 4126 u8 op_mod[0x10]; 4127 4128 u8 reserved_2[0x40]; 4129 u8 driver_version[64][0x8]; 4130 }; 4131 4132 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4133 u8 status[0x8]; 4134 u8 reserved_at_8[0x18]; 4135 4136 u8 syndrome[0x20]; 4137 4138 u8 reserved_at_40[0x40]; 4139 4140 struct mlx5_ifc_pkey_bits pkey[0]; 4141 }; 4142 4143 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4144 u8 opcode[0x10]; 4145 u8 reserved_at_10[0x10]; 4146 4147 u8 reserved_at_20[0x10]; 4148 u8 op_mod[0x10]; 4149 4150 u8 other_vport[0x1]; 4151 u8 reserved_at_41[0xb]; 4152 u8 port_num[0x4]; 4153 u8 vport_number[0x10]; 4154 4155 u8 reserved_at_60[0x10]; 4156 u8 pkey_index[0x10]; 4157 }; 4158 4159 enum { 4160 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4161 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4162 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4163 }; 4164 4165 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4166 u8 status[0x8]; 4167 u8 reserved_at_8[0x18]; 4168 4169 u8 syndrome[0x20]; 4170 4171 u8 reserved_at_40[0x20]; 4172 4173 u8 gids_num[0x10]; 4174 u8 reserved_at_70[0x10]; 4175 4176 struct mlx5_ifc_array128_auto_bits gid[0]; 4177 }; 4178 4179 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4180 u8 opcode[0x10]; 4181 u8 reserved_at_10[0x10]; 4182 4183 u8 reserved_at_20[0x10]; 4184 u8 op_mod[0x10]; 4185 4186 u8 other_vport[0x1]; 4187 u8 reserved_at_41[0xb]; 4188 u8 port_num[0x4]; 4189 u8 vport_number[0x10]; 4190 4191 u8 reserved_at_60[0x10]; 4192 u8 gid_index[0x10]; 4193 }; 4194 4195 struct mlx5_ifc_query_hca_vport_context_out_bits { 4196 u8 status[0x8]; 4197 u8 reserved_at_8[0x18]; 4198 4199 u8 syndrome[0x20]; 4200 4201 u8 reserved_at_40[0x40]; 4202 4203 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4204 }; 4205 4206 struct mlx5_ifc_query_hca_vport_context_in_bits { 4207 u8 opcode[0x10]; 4208 u8 reserved_at_10[0x10]; 4209 4210 u8 reserved_at_20[0x10]; 4211 u8 op_mod[0x10]; 4212 4213 u8 other_vport[0x1]; 4214 u8 reserved_at_41[0xb]; 4215 u8 port_num[0x4]; 4216 u8 vport_number[0x10]; 4217 4218 u8 reserved_at_60[0x20]; 4219 }; 4220 4221 struct mlx5_ifc_query_hca_cap_out_bits { 4222 u8 status[0x8]; 4223 u8 reserved_at_8[0x18]; 4224 4225 u8 syndrome[0x20]; 4226 4227 u8 reserved_at_40[0x40]; 4228 4229 union mlx5_ifc_hca_cap_union_bits capability; 4230 }; 4231 4232 struct mlx5_ifc_query_hca_cap_in_bits { 4233 u8 opcode[0x10]; 4234 u8 reserved_at_10[0x10]; 4235 4236 u8 reserved_at_20[0x10]; 4237 u8 op_mod[0x10]; 4238 4239 u8 reserved_at_40[0x40]; 4240 }; 4241 4242 struct mlx5_ifc_query_flow_table_out_bits { 4243 u8 status[0x8]; 4244 u8 reserved_at_8[0x18]; 4245 4246 u8 syndrome[0x20]; 4247 4248 u8 reserved_at_40[0x80]; 4249 4250 u8 reserved_at_c0[0x8]; 4251 u8 level[0x8]; 4252 u8 reserved_at_d0[0x8]; 4253 u8 log_size[0x8]; 4254 4255 u8 reserved_at_e0[0x120]; 4256 }; 4257 4258 struct mlx5_ifc_query_flow_table_in_bits { 4259 u8 opcode[0x10]; 4260 u8 reserved_at_10[0x10]; 4261 4262 u8 reserved_at_20[0x10]; 4263 u8 op_mod[0x10]; 4264 4265 u8 reserved_at_40[0x40]; 4266 4267 u8 table_type[0x8]; 4268 u8 reserved_at_88[0x18]; 4269 4270 u8 reserved_at_a0[0x8]; 4271 u8 table_id[0x18]; 4272 4273 u8 reserved_at_c0[0x140]; 4274 }; 4275 4276 struct mlx5_ifc_query_fte_out_bits { 4277 u8 status[0x8]; 4278 u8 reserved_at_8[0x18]; 4279 4280 u8 syndrome[0x20]; 4281 4282 u8 reserved_at_40[0x1c0]; 4283 4284 struct mlx5_ifc_flow_context_bits flow_context; 4285 }; 4286 4287 struct mlx5_ifc_query_fte_in_bits { 4288 u8 opcode[0x10]; 4289 u8 reserved_at_10[0x10]; 4290 4291 u8 reserved_at_20[0x10]; 4292 u8 op_mod[0x10]; 4293 4294 u8 reserved_at_40[0x40]; 4295 4296 u8 table_type[0x8]; 4297 u8 reserved_at_88[0x18]; 4298 4299 u8 reserved_at_a0[0x8]; 4300 u8 table_id[0x18]; 4301 4302 u8 reserved_at_c0[0x40]; 4303 4304 u8 flow_index[0x20]; 4305 4306 u8 reserved_at_120[0xe0]; 4307 }; 4308 4309 enum { 4310 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4311 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4312 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4313 }; 4314 4315 struct mlx5_ifc_query_flow_group_out_bits { 4316 u8 status[0x8]; 4317 u8 reserved_at_8[0x18]; 4318 4319 u8 syndrome[0x20]; 4320 4321 u8 reserved_at_40[0xa0]; 4322 4323 u8 start_flow_index[0x20]; 4324 4325 u8 reserved_at_100[0x20]; 4326 4327 u8 end_flow_index[0x20]; 4328 4329 u8 reserved_at_140[0xa0]; 4330 4331 u8 reserved_at_1e0[0x18]; 4332 u8 match_criteria_enable[0x8]; 4333 4334 struct mlx5_ifc_fte_match_param_bits match_criteria; 4335 4336 u8 reserved_at_1200[0xe00]; 4337 }; 4338 4339 struct mlx5_ifc_query_flow_group_in_bits { 4340 u8 opcode[0x10]; 4341 u8 reserved_at_10[0x10]; 4342 4343 u8 reserved_at_20[0x10]; 4344 u8 op_mod[0x10]; 4345 4346 u8 reserved_at_40[0x40]; 4347 4348 u8 table_type[0x8]; 4349 u8 reserved_at_88[0x18]; 4350 4351 u8 reserved_at_a0[0x8]; 4352 u8 table_id[0x18]; 4353 4354 u8 group_id[0x20]; 4355 4356 u8 reserved_at_e0[0x120]; 4357 }; 4358 4359 struct mlx5_ifc_query_flow_counter_out_bits { 4360 u8 status[0x8]; 4361 u8 reserved_at_8[0x18]; 4362 4363 u8 syndrome[0x20]; 4364 4365 u8 reserved_at_40[0x40]; 4366 4367 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4368 }; 4369 4370 struct mlx5_ifc_query_flow_counter_in_bits { 4371 u8 opcode[0x10]; 4372 u8 reserved_at_10[0x10]; 4373 4374 u8 reserved_at_20[0x10]; 4375 u8 op_mod[0x10]; 4376 4377 u8 reserved_at_40[0x80]; 4378 4379 u8 clear[0x1]; 4380 u8 reserved_at_c1[0xf]; 4381 u8 num_of_counters[0x10]; 4382 4383 u8 reserved_at_e0[0x10]; 4384 u8 flow_counter_id[0x10]; 4385 }; 4386 4387 struct mlx5_ifc_query_esw_vport_context_out_bits { 4388 u8 status[0x8]; 4389 u8 reserved_at_8[0x18]; 4390 4391 u8 syndrome[0x20]; 4392 4393 u8 reserved_at_40[0x40]; 4394 4395 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4396 }; 4397 4398 struct mlx5_ifc_query_esw_vport_context_in_bits { 4399 u8 opcode[0x10]; 4400 u8 reserved_at_10[0x10]; 4401 4402 u8 reserved_at_20[0x10]; 4403 u8 op_mod[0x10]; 4404 4405 u8 other_vport[0x1]; 4406 u8 reserved_at_41[0xf]; 4407 u8 vport_number[0x10]; 4408 4409 u8 reserved_at_60[0x20]; 4410 }; 4411 4412 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4413 u8 status[0x8]; 4414 u8 reserved_at_8[0x18]; 4415 4416 u8 syndrome[0x20]; 4417 4418 u8 reserved_at_40[0x40]; 4419 }; 4420 4421 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4422 u8 reserved_at_0[0x1c]; 4423 u8 vport_cvlan_insert[0x1]; 4424 u8 vport_svlan_insert[0x1]; 4425 u8 vport_cvlan_strip[0x1]; 4426 u8 vport_svlan_strip[0x1]; 4427 }; 4428 4429 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4430 u8 opcode[0x10]; 4431 u8 reserved_at_10[0x10]; 4432 4433 u8 reserved_at_20[0x10]; 4434 u8 op_mod[0x10]; 4435 4436 u8 other_vport[0x1]; 4437 u8 reserved_at_41[0xf]; 4438 u8 vport_number[0x10]; 4439 4440 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4441 4442 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4443 }; 4444 4445 struct mlx5_ifc_query_eq_out_bits { 4446 u8 status[0x8]; 4447 u8 reserved_at_8[0x18]; 4448 4449 u8 syndrome[0x20]; 4450 4451 u8 reserved_at_40[0x40]; 4452 4453 struct mlx5_ifc_eqc_bits eq_context_entry; 4454 4455 u8 reserved_at_280[0x40]; 4456 4457 u8 event_bitmask[0x40]; 4458 4459 u8 reserved_at_300[0x580]; 4460 4461 u8 pas[0][0x40]; 4462 }; 4463 4464 struct mlx5_ifc_query_eq_in_bits { 4465 u8 opcode[0x10]; 4466 u8 reserved_at_10[0x10]; 4467 4468 u8 reserved_at_20[0x10]; 4469 u8 op_mod[0x10]; 4470 4471 u8 reserved_at_40[0x18]; 4472 u8 eq_number[0x8]; 4473 4474 u8 reserved_at_60[0x20]; 4475 }; 4476 4477 struct mlx5_ifc_encap_header_in_bits { 4478 u8 reserved_at_0[0x5]; 4479 u8 header_type[0x3]; 4480 u8 reserved_at_8[0xe]; 4481 u8 encap_header_size[0xa]; 4482 4483 u8 reserved_at_20[0x10]; 4484 u8 encap_header[2][0x8]; 4485 4486 u8 more_encap_header[0][0x8]; 4487 }; 4488 4489 struct mlx5_ifc_query_encap_header_out_bits { 4490 u8 status[0x8]; 4491 u8 reserved_at_8[0x18]; 4492 4493 u8 syndrome[0x20]; 4494 4495 u8 reserved_at_40[0xa0]; 4496 4497 struct mlx5_ifc_encap_header_in_bits encap_header[0]; 4498 }; 4499 4500 struct mlx5_ifc_query_encap_header_in_bits { 4501 u8 opcode[0x10]; 4502 u8 reserved_at_10[0x10]; 4503 4504 u8 reserved_at_20[0x10]; 4505 u8 op_mod[0x10]; 4506 4507 u8 encap_id[0x20]; 4508 4509 u8 reserved_at_60[0xa0]; 4510 }; 4511 4512 struct mlx5_ifc_alloc_encap_header_out_bits { 4513 u8 status[0x8]; 4514 u8 reserved_at_8[0x18]; 4515 4516 u8 syndrome[0x20]; 4517 4518 u8 encap_id[0x20]; 4519 4520 u8 reserved_at_60[0x20]; 4521 }; 4522 4523 struct mlx5_ifc_alloc_encap_header_in_bits { 4524 u8 opcode[0x10]; 4525 u8 reserved_at_10[0x10]; 4526 4527 u8 reserved_at_20[0x10]; 4528 u8 op_mod[0x10]; 4529 4530 u8 reserved_at_40[0xa0]; 4531 4532 struct mlx5_ifc_encap_header_in_bits encap_header; 4533 }; 4534 4535 struct mlx5_ifc_dealloc_encap_header_out_bits { 4536 u8 status[0x8]; 4537 u8 reserved_at_8[0x18]; 4538 4539 u8 syndrome[0x20]; 4540 4541 u8 reserved_at_40[0x40]; 4542 }; 4543 4544 struct mlx5_ifc_dealloc_encap_header_in_bits { 4545 u8 opcode[0x10]; 4546 u8 reserved_at_10[0x10]; 4547 4548 u8 reserved_20[0x10]; 4549 u8 op_mod[0x10]; 4550 4551 u8 encap_id[0x20]; 4552 4553 u8 reserved_60[0x20]; 4554 }; 4555 4556 struct mlx5_ifc_set_action_in_bits { 4557 u8 action_type[0x4]; 4558 u8 field[0xc]; 4559 u8 reserved_at_10[0x3]; 4560 u8 offset[0x5]; 4561 u8 reserved_at_18[0x3]; 4562 u8 length[0x5]; 4563 4564 u8 data[0x20]; 4565 }; 4566 4567 struct mlx5_ifc_add_action_in_bits { 4568 u8 action_type[0x4]; 4569 u8 field[0xc]; 4570 u8 reserved_at_10[0x10]; 4571 4572 u8 data[0x20]; 4573 }; 4574 4575 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 4576 struct mlx5_ifc_set_action_in_bits set_action_in; 4577 struct mlx5_ifc_add_action_in_bits add_action_in; 4578 u8 reserved_at_0[0x40]; 4579 }; 4580 4581 enum { 4582 MLX5_ACTION_TYPE_SET = 0x1, 4583 MLX5_ACTION_TYPE_ADD = 0x2, 4584 }; 4585 4586 enum { 4587 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 4588 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 4589 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 4590 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 4591 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 4592 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 4593 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 4594 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 4595 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 4596 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 4597 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 4598 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 4599 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 4600 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 4601 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 4602 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 4603 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 4604 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 4605 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 4606 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 4607 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 4608 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 4609 }; 4610 4611 struct mlx5_ifc_alloc_modify_header_context_out_bits { 4612 u8 status[0x8]; 4613 u8 reserved_at_8[0x18]; 4614 4615 u8 syndrome[0x20]; 4616 4617 u8 modify_header_id[0x20]; 4618 4619 u8 reserved_at_60[0x20]; 4620 }; 4621 4622 struct mlx5_ifc_alloc_modify_header_context_in_bits { 4623 u8 opcode[0x10]; 4624 u8 reserved_at_10[0x10]; 4625 4626 u8 reserved_at_20[0x10]; 4627 u8 op_mod[0x10]; 4628 4629 u8 reserved_at_40[0x20]; 4630 4631 u8 table_type[0x8]; 4632 u8 reserved_at_68[0x10]; 4633 u8 num_of_actions[0x8]; 4634 4635 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 4636 }; 4637 4638 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 4639 u8 status[0x8]; 4640 u8 reserved_at_8[0x18]; 4641 4642 u8 syndrome[0x20]; 4643 4644 u8 reserved_at_40[0x40]; 4645 }; 4646 4647 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 4648 u8 opcode[0x10]; 4649 u8 reserved_at_10[0x10]; 4650 4651 u8 reserved_at_20[0x10]; 4652 u8 op_mod[0x10]; 4653 4654 u8 modify_header_id[0x20]; 4655 4656 u8 reserved_at_60[0x20]; 4657 }; 4658 4659 struct mlx5_ifc_query_dct_out_bits { 4660 u8 status[0x8]; 4661 u8 reserved_at_8[0x18]; 4662 4663 u8 syndrome[0x20]; 4664 4665 u8 reserved_at_40[0x40]; 4666 4667 struct mlx5_ifc_dctc_bits dct_context_entry; 4668 4669 u8 reserved_at_280[0x180]; 4670 }; 4671 4672 struct mlx5_ifc_query_dct_in_bits { 4673 u8 opcode[0x10]; 4674 u8 reserved_at_10[0x10]; 4675 4676 u8 reserved_at_20[0x10]; 4677 u8 op_mod[0x10]; 4678 4679 u8 reserved_at_40[0x8]; 4680 u8 dctn[0x18]; 4681 4682 u8 reserved_at_60[0x20]; 4683 }; 4684 4685 struct mlx5_ifc_query_cq_out_bits { 4686 u8 status[0x8]; 4687 u8 reserved_at_8[0x18]; 4688 4689 u8 syndrome[0x20]; 4690 4691 u8 reserved_at_40[0x40]; 4692 4693 struct mlx5_ifc_cqc_bits cq_context; 4694 4695 u8 reserved_at_280[0x600]; 4696 4697 u8 pas[0][0x40]; 4698 }; 4699 4700 struct mlx5_ifc_query_cq_in_bits { 4701 u8 opcode[0x10]; 4702 u8 reserved_at_10[0x10]; 4703 4704 u8 reserved_at_20[0x10]; 4705 u8 op_mod[0x10]; 4706 4707 u8 reserved_at_40[0x8]; 4708 u8 cqn[0x18]; 4709 4710 u8 reserved_at_60[0x20]; 4711 }; 4712 4713 struct mlx5_ifc_query_cong_status_out_bits { 4714 u8 status[0x8]; 4715 u8 reserved_at_8[0x18]; 4716 4717 u8 syndrome[0x20]; 4718 4719 u8 reserved_at_40[0x20]; 4720 4721 u8 enable[0x1]; 4722 u8 tag_enable[0x1]; 4723 u8 reserved_at_62[0x1e]; 4724 }; 4725 4726 struct mlx5_ifc_query_cong_status_in_bits { 4727 u8 opcode[0x10]; 4728 u8 reserved_at_10[0x10]; 4729 4730 u8 reserved_at_20[0x10]; 4731 u8 op_mod[0x10]; 4732 4733 u8 reserved_at_40[0x18]; 4734 u8 priority[0x4]; 4735 u8 cong_protocol[0x4]; 4736 4737 u8 reserved_at_60[0x20]; 4738 }; 4739 4740 struct mlx5_ifc_query_cong_statistics_out_bits { 4741 u8 status[0x8]; 4742 u8 reserved_at_8[0x18]; 4743 4744 u8 syndrome[0x20]; 4745 4746 u8 reserved_at_40[0x40]; 4747 4748 u8 rp_cur_flows[0x20]; 4749 4750 u8 sum_flows[0x20]; 4751 4752 u8 rp_cnp_ignored_high[0x20]; 4753 4754 u8 rp_cnp_ignored_low[0x20]; 4755 4756 u8 rp_cnp_handled_high[0x20]; 4757 4758 u8 rp_cnp_handled_low[0x20]; 4759 4760 u8 reserved_at_140[0x100]; 4761 4762 u8 time_stamp_high[0x20]; 4763 4764 u8 time_stamp_low[0x20]; 4765 4766 u8 accumulators_period[0x20]; 4767 4768 u8 np_ecn_marked_roce_packets_high[0x20]; 4769 4770 u8 np_ecn_marked_roce_packets_low[0x20]; 4771 4772 u8 np_cnp_sent_high[0x20]; 4773 4774 u8 np_cnp_sent_low[0x20]; 4775 4776 u8 reserved_at_320[0x560]; 4777 }; 4778 4779 struct mlx5_ifc_query_cong_statistics_in_bits { 4780 u8 opcode[0x10]; 4781 u8 reserved_at_10[0x10]; 4782 4783 u8 reserved_at_20[0x10]; 4784 u8 op_mod[0x10]; 4785 4786 u8 clear[0x1]; 4787 u8 reserved_at_41[0x1f]; 4788 4789 u8 reserved_at_60[0x20]; 4790 }; 4791 4792 struct mlx5_ifc_query_cong_params_out_bits { 4793 u8 status[0x8]; 4794 u8 reserved_at_8[0x18]; 4795 4796 u8 syndrome[0x20]; 4797 4798 u8 reserved_at_40[0x40]; 4799 4800 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4801 }; 4802 4803 struct mlx5_ifc_query_cong_params_in_bits { 4804 u8 opcode[0x10]; 4805 u8 reserved_at_10[0x10]; 4806 4807 u8 reserved_at_20[0x10]; 4808 u8 op_mod[0x10]; 4809 4810 u8 reserved_at_40[0x1c]; 4811 u8 cong_protocol[0x4]; 4812 4813 u8 reserved_at_60[0x20]; 4814 }; 4815 4816 struct mlx5_ifc_query_adapter_out_bits { 4817 u8 status[0x8]; 4818 u8 reserved_at_8[0x18]; 4819 4820 u8 syndrome[0x20]; 4821 4822 u8 reserved_at_40[0x40]; 4823 4824 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 4825 }; 4826 4827 struct mlx5_ifc_query_adapter_in_bits { 4828 u8 opcode[0x10]; 4829 u8 reserved_at_10[0x10]; 4830 4831 u8 reserved_at_20[0x10]; 4832 u8 op_mod[0x10]; 4833 4834 u8 reserved_at_40[0x40]; 4835 }; 4836 4837 struct mlx5_ifc_qp_2rst_out_bits { 4838 u8 status[0x8]; 4839 u8 reserved_at_8[0x18]; 4840 4841 u8 syndrome[0x20]; 4842 4843 u8 reserved_at_40[0x40]; 4844 }; 4845 4846 struct mlx5_ifc_qp_2rst_in_bits { 4847 u8 opcode[0x10]; 4848 u8 reserved_at_10[0x10]; 4849 4850 u8 reserved_at_20[0x10]; 4851 u8 op_mod[0x10]; 4852 4853 u8 reserved_at_40[0x8]; 4854 u8 qpn[0x18]; 4855 4856 u8 reserved_at_60[0x20]; 4857 }; 4858 4859 struct mlx5_ifc_qp_2err_out_bits { 4860 u8 status[0x8]; 4861 u8 reserved_at_8[0x18]; 4862 4863 u8 syndrome[0x20]; 4864 4865 u8 reserved_at_40[0x40]; 4866 }; 4867 4868 struct mlx5_ifc_qp_2err_in_bits { 4869 u8 opcode[0x10]; 4870 u8 reserved_at_10[0x10]; 4871 4872 u8 reserved_at_20[0x10]; 4873 u8 op_mod[0x10]; 4874 4875 u8 reserved_at_40[0x8]; 4876 u8 qpn[0x18]; 4877 4878 u8 reserved_at_60[0x20]; 4879 }; 4880 4881 struct mlx5_ifc_page_fault_resume_out_bits { 4882 u8 status[0x8]; 4883 u8 reserved_at_8[0x18]; 4884 4885 u8 syndrome[0x20]; 4886 4887 u8 reserved_at_40[0x40]; 4888 }; 4889 4890 struct mlx5_ifc_page_fault_resume_in_bits { 4891 u8 opcode[0x10]; 4892 u8 reserved_at_10[0x10]; 4893 4894 u8 reserved_at_20[0x10]; 4895 u8 op_mod[0x10]; 4896 4897 u8 error[0x1]; 4898 u8 reserved_at_41[0x4]; 4899 u8 page_fault_type[0x3]; 4900 u8 wq_number[0x18]; 4901 4902 u8 reserved_at_60[0x8]; 4903 u8 token[0x18]; 4904 }; 4905 4906 struct mlx5_ifc_nop_out_bits { 4907 u8 status[0x8]; 4908 u8 reserved_at_8[0x18]; 4909 4910 u8 syndrome[0x20]; 4911 4912 u8 reserved_at_40[0x40]; 4913 }; 4914 4915 struct mlx5_ifc_nop_in_bits { 4916 u8 opcode[0x10]; 4917 u8 reserved_at_10[0x10]; 4918 4919 u8 reserved_at_20[0x10]; 4920 u8 op_mod[0x10]; 4921 4922 u8 reserved_at_40[0x40]; 4923 }; 4924 4925 struct mlx5_ifc_modify_vport_state_out_bits { 4926 u8 status[0x8]; 4927 u8 reserved_at_8[0x18]; 4928 4929 u8 syndrome[0x20]; 4930 4931 u8 reserved_at_40[0x40]; 4932 }; 4933 4934 struct mlx5_ifc_modify_vport_state_in_bits { 4935 u8 opcode[0x10]; 4936 u8 reserved_at_10[0x10]; 4937 4938 u8 reserved_at_20[0x10]; 4939 u8 op_mod[0x10]; 4940 4941 u8 other_vport[0x1]; 4942 u8 reserved_at_41[0xf]; 4943 u8 vport_number[0x10]; 4944 4945 u8 reserved_at_60[0x18]; 4946 u8 admin_state[0x4]; 4947 u8 reserved_at_7c[0x4]; 4948 }; 4949 4950 struct mlx5_ifc_modify_tis_out_bits { 4951 u8 status[0x8]; 4952 u8 reserved_at_8[0x18]; 4953 4954 u8 syndrome[0x20]; 4955 4956 u8 reserved_at_40[0x40]; 4957 }; 4958 4959 struct mlx5_ifc_modify_tis_bitmask_bits { 4960 u8 reserved_at_0[0x20]; 4961 4962 u8 reserved_at_20[0x1d]; 4963 u8 lag_tx_port_affinity[0x1]; 4964 u8 strict_lag_tx_port_affinity[0x1]; 4965 u8 prio[0x1]; 4966 }; 4967 4968 struct mlx5_ifc_modify_tis_in_bits { 4969 u8 opcode[0x10]; 4970 u8 reserved_at_10[0x10]; 4971 4972 u8 reserved_at_20[0x10]; 4973 u8 op_mod[0x10]; 4974 4975 u8 reserved_at_40[0x8]; 4976 u8 tisn[0x18]; 4977 4978 u8 reserved_at_60[0x20]; 4979 4980 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 4981 4982 u8 reserved_at_c0[0x40]; 4983 4984 struct mlx5_ifc_tisc_bits ctx; 4985 }; 4986 4987 struct mlx5_ifc_modify_tir_bitmask_bits { 4988 u8 reserved_at_0[0x20]; 4989 4990 u8 reserved_at_20[0x1b]; 4991 u8 self_lb_en[0x1]; 4992 u8 reserved_at_3c[0x1]; 4993 u8 hash[0x1]; 4994 u8 reserved_at_3e[0x1]; 4995 u8 lro[0x1]; 4996 }; 4997 4998 struct mlx5_ifc_modify_tir_out_bits { 4999 u8 status[0x8]; 5000 u8 reserved_at_8[0x18]; 5001 5002 u8 syndrome[0x20]; 5003 5004 u8 reserved_at_40[0x40]; 5005 }; 5006 5007 struct mlx5_ifc_modify_tir_in_bits { 5008 u8 opcode[0x10]; 5009 u8 reserved_at_10[0x10]; 5010 5011 u8 reserved_at_20[0x10]; 5012 u8 op_mod[0x10]; 5013 5014 u8 reserved_at_40[0x8]; 5015 u8 tirn[0x18]; 5016 5017 u8 reserved_at_60[0x20]; 5018 5019 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5020 5021 u8 reserved_at_c0[0x40]; 5022 5023 struct mlx5_ifc_tirc_bits ctx; 5024 }; 5025 5026 struct mlx5_ifc_modify_sq_out_bits { 5027 u8 status[0x8]; 5028 u8 reserved_at_8[0x18]; 5029 5030 u8 syndrome[0x20]; 5031 5032 u8 reserved_at_40[0x40]; 5033 }; 5034 5035 struct mlx5_ifc_modify_sq_in_bits { 5036 u8 opcode[0x10]; 5037 u8 reserved_at_10[0x10]; 5038 5039 u8 reserved_at_20[0x10]; 5040 u8 op_mod[0x10]; 5041 5042 u8 sq_state[0x4]; 5043 u8 reserved_at_44[0x4]; 5044 u8 sqn[0x18]; 5045 5046 u8 reserved_at_60[0x20]; 5047 5048 u8 modify_bitmask[0x40]; 5049 5050 u8 reserved_at_c0[0x40]; 5051 5052 struct mlx5_ifc_sqc_bits ctx; 5053 }; 5054 5055 struct mlx5_ifc_modify_scheduling_element_out_bits { 5056 u8 status[0x8]; 5057 u8 reserved_at_8[0x18]; 5058 5059 u8 syndrome[0x20]; 5060 5061 u8 reserved_at_40[0x1c0]; 5062 }; 5063 5064 enum { 5065 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5066 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5067 }; 5068 5069 struct mlx5_ifc_modify_scheduling_element_in_bits { 5070 u8 opcode[0x10]; 5071 u8 reserved_at_10[0x10]; 5072 5073 u8 reserved_at_20[0x10]; 5074 u8 op_mod[0x10]; 5075 5076 u8 scheduling_hierarchy[0x8]; 5077 u8 reserved_at_48[0x18]; 5078 5079 u8 scheduling_element_id[0x20]; 5080 5081 u8 reserved_at_80[0x20]; 5082 5083 u8 modify_bitmask[0x20]; 5084 5085 u8 reserved_at_c0[0x40]; 5086 5087 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5088 5089 u8 reserved_at_300[0x100]; 5090 }; 5091 5092 struct mlx5_ifc_modify_rqt_out_bits { 5093 u8 status[0x8]; 5094 u8 reserved_at_8[0x18]; 5095 5096 u8 syndrome[0x20]; 5097 5098 u8 reserved_at_40[0x40]; 5099 }; 5100 5101 struct mlx5_ifc_rqt_bitmask_bits { 5102 u8 reserved_at_0[0x20]; 5103 5104 u8 reserved_at_20[0x1f]; 5105 u8 rqn_list[0x1]; 5106 }; 5107 5108 struct mlx5_ifc_modify_rqt_in_bits { 5109 u8 opcode[0x10]; 5110 u8 reserved_at_10[0x10]; 5111 5112 u8 reserved_at_20[0x10]; 5113 u8 op_mod[0x10]; 5114 5115 u8 reserved_at_40[0x8]; 5116 u8 rqtn[0x18]; 5117 5118 u8 reserved_at_60[0x20]; 5119 5120 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5121 5122 u8 reserved_at_c0[0x40]; 5123 5124 struct mlx5_ifc_rqtc_bits ctx; 5125 }; 5126 5127 struct mlx5_ifc_modify_rq_out_bits { 5128 u8 status[0x8]; 5129 u8 reserved_at_8[0x18]; 5130 5131 u8 syndrome[0x20]; 5132 5133 u8 reserved_at_40[0x40]; 5134 }; 5135 5136 enum { 5137 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5138 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5139 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5140 }; 5141 5142 struct mlx5_ifc_modify_rq_in_bits { 5143 u8 opcode[0x10]; 5144 u8 reserved_at_10[0x10]; 5145 5146 u8 reserved_at_20[0x10]; 5147 u8 op_mod[0x10]; 5148 5149 u8 rq_state[0x4]; 5150 u8 reserved_at_44[0x4]; 5151 u8 rqn[0x18]; 5152 5153 u8 reserved_at_60[0x20]; 5154 5155 u8 modify_bitmask[0x40]; 5156 5157 u8 reserved_at_c0[0x40]; 5158 5159 struct mlx5_ifc_rqc_bits ctx; 5160 }; 5161 5162 struct mlx5_ifc_modify_rmp_out_bits { 5163 u8 status[0x8]; 5164 u8 reserved_at_8[0x18]; 5165 5166 u8 syndrome[0x20]; 5167 5168 u8 reserved_at_40[0x40]; 5169 }; 5170 5171 struct mlx5_ifc_rmp_bitmask_bits { 5172 u8 reserved_at_0[0x20]; 5173 5174 u8 reserved_at_20[0x1f]; 5175 u8 lwm[0x1]; 5176 }; 5177 5178 struct mlx5_ifc_modify_rmp_in_bits { 5179 u8 opcode[0x10]; 5180 u8 reserved_at_10[0x10]; 5181 5182 u8 reserved_at_20[0x10]; 5183 u8 op_mod[0x10]; 5184 5185 u8 rmp_state[0x4]; 5186 u8 reserved_at_44[0x4]; 5187 u8 rmpn[0x18]; 5188 5189 u8 reserved_at_60[0x20]; 5190 5191 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5192 5193 u8 reserved_at_c0[0x40]; 5194 5195 struct mlx5_ifc_rmpc_bits ctx; 5196 }; 5197 5198 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5199 u8 status[0x8]; 5200 u8 reserved_at_8[0x18]; 5201 5202 u8 syndrome[0x20]; 5203 5204 u8 reserved_at_40[0x40]; 5205 }; 5206 5207 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5208 u8 reserved_at_0[0x16]; 5209 u8 node_guid[0x1]; 5210 u8 port_guid[0x1]; 5211 u8 min_inline[0x1]; 5212 u8 mtu[0x1]; 5213 u8 change_event[0x1]; 5214 u8 promisc[0x1]; 5215 u8 permanent_address[0x1]; 5216 u8 addresses_list[0x1]; 5217 u8 roce_en[0x1]; 5218 u8 reserved_at_1f[0x1]; 5219 }; 5220 5221 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5222 u8 opcode[0x10]; 5223 u8 reserved_at_10[0x10]; 5224 5225 u8 reserved_at_20[0x10]; 5226 u8 op_mod[0x10]; 5227 5228 u8 other_vport[0x1]; 5229 u8 reserved_at_41[0xf]; 5230 u8 vport_number[0x10]; 5231 5232 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5233 5234 u8 reserved_at_80[0x780]; 5235 5236 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5237 }; 5238 5239 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5240 u8 status[0x8]; 5241 u8 reserved_at_8[0x18]; 5242 5243 u8 syndrome[0x20]; 5244 5245 u8 reserved_at_40[0x40]; 5246 }; 5247 5248 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5249 u8 opcode[0x10]; 5250 u8 reserved_at_10[0x10]; 5251 5252 u8 reserved_at_20[0x10]; 5253 u8 op_mod[0x10]; 5254 5255 u8 other_vport[0x1]; 5256 u8 reserved_at_41[0xb]; 5257 u8 port_num[0x4]; 5258 u8 vport_number[0x10]; 5259 5260 u8 reserved_at_60[0x20]; 5261 5262 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5263 }; 5264 5265 struct mlx5_ifc_modify_cq_out_bits { 5266 u8 status[0x8]; 5267 u8 reserved_at_8[0x18]; 5268 5269 u8 syndrome[0x20]; 5270 5271 u8 reserved_at_40[0x40]; 5272 }; 5273 5274 enum { 5275 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5276 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5277 }; 5278 5279 struct mlx5_ifc_modify_cq_in_bits { 5280 u8 opcode[0x10]; 5281 u8 reserved_at_10[0x10]; 5282 5283 u8 reserved_at_20[0x10]; 5284 u8 op_mod[0x10]; 5285 5286 u8 reserved_at_40[0x8]; 5287 u8 cqn[0x18]; 5288 5289 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5290 5291 struct mlx5_ifc_cqc_bits cq_context; 5292 5293 u8 reserved_at_280[0x600]; 5294 5295 u8 pas[0][0x40]; 5296 }; 5297 5298 struct mlx5_ifc_modify_cong_status_out_bits { 5299 u8 status[0x8]; 5300 u8 reserved_at_8[0x18]; 5301 5302 u8 syndrome[0x20]; 5303 5304 u8 reserved_at_40[0x40]; 5305 }; 5306 5307 struct mlx5_ifc_modify_cong_status_in_bits { 5308 u8 opcode[0x10]; 5309 u8 reserved_at_10[0x10]; 5310 5311 u8 reserved_at_20[0x10]; 5312 u8 op_mod[0x10]; 5313 5314 u8 reserved_at_40[0x18]; 5315 u8 priority[0x4]; 5316 u8 cong_protocol[0x4]; 5317 5318 u8 enable[0x1]; 5319 u8 tag_enable[0x1]; 5320 u8 reserved_at_62[0x1e]; 5321 }; 5322 5323 struct mlx5_ifc_modify_cong_params_out_bits { 5324 u8 status[0x8]; 5325 u8 reserved_at_8[0x18]; 5326 5327 u8 syndrome[0x20]; 5328 5329 u8 reserved_at_40[0x40]; 5330 }; 5331 5332 struct mlx5_ifc_modify_cong_params_in_bits { 5333 u8 opcode[0x10]; 5334 u8 reserved_at_10[0x10]; 5335 5336 u8 reserved_at_20[0x10]; 5337 u8 op_mod[0x10]; 5338 5339 u8 reserved_at_40[0x1c]; 5340 u8 cong_protocol[0x4]; 5341 5342 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5343 5344 u8 reserved_at_80[0x80]; 5345 5346 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5347 }; 5348 5349 struct mlx5_ifc_manage_pages_out_bits { 5350 u8 status[0x8]; 5351 u8 reserved_at_8[0x18]; 5352 5353 u8 syndrome[0x20]; 5354 5355 u8 output_num_entries[0x20]; 5356 5357 u8 reserved_at_60[0x20]; 5358 5359 u8 pas[0][0x40]; 5360 }; 5361 5362 enum { 5363 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5364 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5365 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5366 }; 5367 5368 struct mlx5_ifc_manage_pages_in_bits { 5369 u8 opcode[0x10]; 5370 u8 reserved_at_10[0x10]; 5371 5372 u8 reserved_at_20[0x10]; 5373 u8 op_mod[0x10]; 5374 5375 u8 reserved_at_40[0x10]; 5376 u8 function_id[0x10]; 5377 5378 u8 input_num_entries[0x20]; 5379 5380 u8 pas[0][0x40]; 5381 }; 5382 5383 struct mlx5_ifc_mad_ifc_out_bits { 5384 u8 status[0x8]; 5385 u8 reserved_at_8[0x18]; 5386 5387 u8 syndrome[0x20]; 5388 5389 u8 reserved_at_40[0x40]; 5390 5391 u8 response_mad_packet[256][0x8]; 5392 }; 5393 5394 struct mlx5_ifc_mad_ifc_in_bits { 5395 u8 opcode[0x10]; 5396 u8 reserved_at_10[0x10]; 5397 5398 u8 reserved_at_20[0x10]; 5399 u8 op_mod[0x10]; 5400 5401 u8 remote_lid[0x10]; 5402 u8 reserved_at_50[0x8]; 5403 u8 port[0x8]; 5404 5405 u8 reserved_at_60[0x20]; 5406 5407 u8 mad[256][0x8]; 5408 }; 5409 5410 struct mlx5_ifc_init_hca_out_bits { 5411 u8 status[0x8]; 5412 u8 reserved_at_8[0x18]; 5413 5414 u8 syndrome[0x20]; 5415 5416 u8 reserved_at_40[0x40]; 5417 }; 5418 5419 struct mlx5_ifc_init_hca_in_bits { 5420 u8 opcode[0x10]; 5421 u8 reserved_at_10[0x10]; 5422 5423 u8 reserved_at_20[0x10]; 5424 u8 op_mod[0x10]; 5425 5426 u8 reserved_at_40[0x40]; 5427 }; 5428 5429 struct mlx5_ifc_init2rtr_qp_out_bits { 5430 u8 status[0x8]; 5431 u8 reserved_at_8[0x18]; 5432 5433 u8 syndrome[0x20]; 5434 5435 u8 reserved_at_40[0x40]; 5436 }; 5437 5438 struct mlx5_ifc_init2rtr_qp_in_bits { 5439 u8 opcode[0x10]; 5440 u8 reserved_at_10[0x10]; 5441 5442 u8 reserved_at_20[0x10]; 5443 u8 op_mod[0x10]; 5444 5445 u8 reserved_at_40[0x8]; 5446 u8 qpn[0x18]; 5447 5448 u8 reserved_at_60[0x20]; 5449 5450 u8 opt_param_mask[0x20]; 5451 5452 u8 reserved_at_a0[0x20]; 5453 5454 struct mlx5_ifc_qpc_bits qpc; 5455 5456 u8 reserved_at_800[0x80]; 5457 }; 5458 5459 struct mlx5_ifc_init2init_qp_out_bits { 5460 u8 status[0x8]; 5461 u8 reserved_at_8[0x18]; 5462 5463 u8 syndrome[0x20]; 5464 5465 u8 reserved_at_40[0x40]; 5466 }; 5467 5468 struct mlx5_ifc_init2init_qp_in_bits { 5469 u8 opcode[0x10]; 5470 u8 reserved_at_10[0x10]; 5471 5472 u8 reserved_at_20[0x10]; 5473 u8 op_mod[0x10]; 5474 5475 u8 reserved_at_40[0x8]; 5476 u8 qpn[0x18]; 5477 5478 u8 reserved_at_60[0x20]; 5479 5480 u8 opt_param_mask[0x20]; 5481 5482 u8 reserved_at_a0[0x20]; 5483 5484 struct mlx5_ifc_qpc_bits qpc; 5485 5486 u8 reserved_at_800[0x80]; 5487 }; 5488 5489 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5490 u8 status[0x8]; 5491 u8 reserved_at_8[0x18]; 5492 5493 u8 syndrome[0x20]; 5494 5495 u8 reserved_at_40[0x40]; 5496 5497 u8 packet_headers_log[128][0x8]; 5498 5499 u8 packet_syndrome[64][0x8]; 5500 }; 5501 5502 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5503 u8 opcode[0x10]; 5504 u8 reserved_at_10[0x10]; 5505 5506 u8 reserved_at_20[0x10]; 5507 u8 op_mod[0x10]; 5508 5509 u8 reserved_at_40[0x40]; 5510 }; 5511 5512 struct mlx5_ifc_gen_eqe_in_bits { 5513 u8 opcode[0x10]; 5514 u8 reserved_at_10[0x10]; 5515 5516 u8 reserved_at_20[0x10]; 5517 u8 op_mod[0x10]; 5518 5519 u8 reserved_at_40[0x18]; 5520 u8 eq_number[0x8]; 5521 5522 u8 reserved_at_60[0x20]; 5523 5524 u8 eqe[64][0x8]; 5525 }; 5526 5527 struct mlx5_ifc_gen_eq_out_bits { 5528 u8 status[0x8]; 5529 u8 reserved_at_8[0x18]; 5530 5531 u8 syndrome[0x20]; 5532 5533 u8 reserved_at_40[0x40]; 5534 }; 5535 5536 struct mlx5_ifc_enable_hca_out_bits { 5537 u8 status[0x8]; 5538 u8 reserved_at_8[0x18]; 5539 5540 u8 syndrome[0x20]; 5541 5542 u8 reserved_at_40[0x20]; 5543 }; 5544 5545 struct mlx5_ifc_enable_hca_in_bits { 5546 u8 opcode[0x10]; 5547 u8 reserved_at_10[0x10]; 5548 5549 u8 reserved_at_20[0x10]; 5550 u8 op_mod[0x10]; 5551 5552 u8 reserved_at_40[0x10]; 5553 u8 function_id[0x10]; 5554 5555 u8 reserved_at_60[0x20]; 5556 }; 5557 5558 struct mlx5_ifc_drain_dct_out_bits { 5559 u8 status[0x8]; 5560 u8 reserved_at_8[0x18]; 5561 5562 u8 syndrome[0x20]; 5563 5564 u8 reserved_at_40[0x40]; 5565 }; 5566 5567 struct mlx5_ifc_drain_dct_in_bits { 5568 u8 opcode[0x10]; 5569 u8 reserved_at_10[0x10]; 5570 5571 u8 reserved_at_20[0x10]; 5572 u8 op_mod[0x10]; 5573 5574 u8 reserved_at_40[0x8]; 5575 u8 dctn[0x18]; 5576 5577 u8 reserved_at_60[0x20]; 5578 }; 5579 5580 struct mlx5_ifc_disable_hca_out_bits { 5581 u8 status[0x8]; 5582 u8 reserved_at_8[0x18]; 5583 5584 u8 syndrome[0x20]; 5585 5586 u8 reserved_at_40[0x20]; 5587 }; 5588 5589 struct mlx5_ifc_disable_hca_in_bits { 5590 u8 opcode[0x10]; 5591 u8 reserved_at_10[0x10]; 5592 5593 u8 reserved_at_20[0x10]; 5594 u8 op_mod[0x10]; 5595 5596 u8 reserved_at_40[0x10]; 5597 u8 function_id[0x10]; 5598 5599 u8 reserved_at_60[0x20]; 5600 }; 5601 5602 struct mlx5_ifc_detach_from_mcg_out_bits { 5603 u8 status[0x8]; 5604 u8 reserved_at_8[0x18]; 5605 5606 u8 syndrome[0x20]; 5607 5608 u8 reserved_at_40[0x40]; 5609 }; 5610 5611 struct mlx5_ifc_detach_from_mcg_in_bits { 5612 u8 opcode[0x10]; 5613 u8 reserved_at_10[0x10]; 5614 5615 u8 reserved_at_20[0x10]; 5616 u8 op_mod[0x10]; 5617 5618 u8 reserved_at_40[0x8]; 5619 u8 qpn[0x18]; 5620 5621 u8 reserved_at_60[0x20]; 5622 5623 u8 multicast_gid[16][0x8]; 5624 }; 5625 5626 struct mlx5_ifc_destroy_xrq_out_bits { 5627 u8 status[0x8]; 5628 u8 reserved_at_8[0x18]; 5629 5630 u8 syndrome[0x20]; 5631 5632 u8 reserved_at_40[0x40]; 5633 }; 5634 5635 struct mlx5_ifc_destroy_xrq_in_bits { 5636 u8 opcode[0x10]; 5637 u8 reserved_at_10[0x10]; 5638 5639 u8 reserved_at_20[0x10]; 5640 u8 op_mod[0x10]; 5641 5642 u8 reserved_at_40[0x8]; 5643 u8 xrqn[0x18]; 5644 5645 u8 reserved_at_60[0x20]; 5646 }; 5647 5648 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5649 u8 status[0x8]; 5650 u8 reserved_at_8[0x18]; 5651 5652 u8 syndrome[0x20]; 5653 5654 u8 reserved_at_40[0x40]; 5655 }; 5656 5657 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5658 u8 opcode[0x10]; 5659 u8 reserved_at_10[0x10]; 5660 5661 u8 reserved_at_20[0x10]; 5662 u8 op_mod[0x10]; 5663 5664 u8 reserved_at_40[0x8]; 5665 u8 xrc_srqn[0x18]; 5666 5667 u8 reserved_at_60[0x20]; 5668 }; 5669 5670 struct mlx5_ifc_destroy_tis_out_bits { 5671 u8 status[0x8]; 5672 u8 reserved_at_8[0x18]; 5673 5674 u8 syndrome[0x20]; 5675 5676 u8 reserved_at_40[0x40]; 5677 }; 5678 5679 struct mlx5_ifc_destroy_tis_in_bits { 5680 u8 opcode[0x10]; 5681 u8 reserved_at_10[0x10]; 5682 5683 u8 reserved_at_20[0x10]; 5684 u8 op_mod[0x10]; 5685 5686 u8 reserved_at_40[0x8]; 5687 u8 tisn[0x18]; 5688 5689 u8 reserved_at_60[0x20]; 5690 }; 5691 5692 struct mlx5_ifc_destroy_tir_out_bits { 5693 u8 status[0x8]; 5694 u8 reserved_at_8[0x18]; 5695 5696 u8 syndrome[0x20]; 5697 5698 u8 reserved_at_40[0x40]; 5699 }; 5700 5701 struct mlx5_ifc_destroy_tir_in_bits { 5702 u8 opcode[0x10]; 5703 u8 reserved_at_10[0x10]; 5704 5705 u8 reserved_at_20[0x10]; 5706 u8 op_mod[0x10]; 5707 5708 u8 reserved_at_40[0x8]; 5709 u8 tirn[0x18]; 5710 5711 u8 reserved_at_60[0x20]; 5712 }; 5713 5714 struct mlx5_ifc_destroy_srq_out_bits { 5715 u8 status[0x8]; 5716 u8 reserved_at_8[0x18]; 5717 5718 u8 syndrome[0x20]; 5719 5720 u8 reserved_at_40[0x40]; 5721 }; 5722 5723 struct mlx5_ifc_destroy_srq_in_bits { 5724 u8 opcode[0x10]; 5725 u8 reserved_at_10[0x10]; 5726 5727 u8 reserved_at_20[0x10]; 5728 u8 op_mod[0x10]; 5729 5730 u8 reserved_at_40[0x8]; 5731 u8 srqn[0x18]; 5732 5733 u8 reserved_at_60[0x20]; 5734 }; 5735 5736 struct mlx5_ifc_destroy_sq_out_bits { 5737 u8 status[0x8]; 5738 u8 reserved_at_8[0x18]; 5739 5740 u8 syndrome[0x20]; 5741 5742 u8 reserved_at_40[0x40]; 5743 }; 5744 5745 struct mlx5_ifc_destroy_sq_in_bits { 5746 u8 opcode[0x10]; 5747 u8 reserved_at_10[0x10]; 5748 5749 u8 reserved_at_20[0x10]; 5750 u8 op_mod[0x10]; 5751 5752 u8 reserved_at_40[0x8]; 5753 u8 sqn[0x18]; 5754 5755 u8 reserved_at_60[0x20]; 5756 }; 5757 5758 struct mlx5_ifc_destroy_scheduling_element_out_bits { 5759 u8 status[0x8]; 5760 u8 reserved_at_8[0x18]; 5761 5762 u8 syndrome[0x20]; 5763 5764 u8 reserved_at_40[0x1c0]; 5765 }; 5766 5767 struct mlx5_ifc_destroy_scheduling_element_in_bits { 5768 u8 opcode[0x10]; 5769 u8 reserved_at_10[0x10]; 5770 5771 u8 reserved_at_20[0x10]; 5772 u8 op_mod[0x10]; 5773 5774 u8 scheduling_hierarchy[0x8]; 5775 u8 reserved_at_48[0x18]; 5776 5777 u8 scheduling_element_id[0x20]; 5778 5779 u8 reserved_at_80[0x180]; 5780 }; 5781 5782 struct mlx5_ifc_destroy_rqt_out_bits { 5783 u8 status[0x8]; 5784 u8 reserved_at_8[0x18]; 5785 5786 u8 syndrome[0x20]; 5787 5788 u8 reserved_at_40[0x40]; 5789 }; 5790 5791 struct mlx5_ifc_destroy_rqt_in_bits { 5792 u8 opcode[0x10]; 5793 u8 reserved_at_10[0x10]; 5794 5795 u8 reserved_at_20[0x10]; 5796 u8 op_mod[0x10]; 5797 5798 u8 reserved_at_40[0x8]; 5799 u8 rqtn[0x18]; 5800 5801 u8 reserved_at_60[0x20]; 5802 }; 5803 5804 struct mlx5_ifc_destroy_rq_out_bits { 5805 u8 status[0x8]; 5806 u8 reserved_at_8[0x18]; 5807 5808 u8 syndrome[0x20]; 5809 5810 u8 reserved_at_40[0x40]; 5811 }; 5812 5813 struct mlx5_ifc_destroy_rq_in_bits { 5814 u8 opcode[0x10]; 5815 u8 reserved_at_10[0x10]; 5816 5817 u8 reserved_at_20[0x10]; 5818 u8 op_mod[0x10]; 5819 5820 u8 reserved_at_40[0x8]; 5821 u8 rqn[0x18]; 5822 5823 u8 reserved_at_60[0x20]; 5824 }; 5825 5826 struct mlx5_ifc_destroy_rmp_out_bits { 5827 u8 status[0x8]; 5828 u8 reserved_at_8[0x18]; 5829 5830 u8 syndrome[0x20]; 5831 5832 u8 reserved_at_40[0x40]; 5833 }; 5834 5835 struct mlx5_ifc_destroy_rmp_in_bits { 5836 u8 opcode[0x10]; 5837 u8 reserved_at_10[0x10]; 5838 5839 u8 reserved_at_20[0x10]; 5840 u8 op_mod[0x10]; 5841 5842 u8 reserved_at_40[0x8]; 5843 u8 rmpn[0x18]; 5844 5845 u8 reserved_at_60[0x20]; 5846 }; 5847 5848 struct mlx5_ifc_destroy_qp_out_bits { 5849 u8 status[0x8]; 5850 u8 reserved_at_8[0x18]; 5851 5852 u8 syndrome[0x20]; 5853 5854 u8 reserved_at_40[0x40]; 5855 }; 5856 5857 struct mlx5_ifc_destroy_qp_in_bits { 5858 u8 opcode[0x10]; 5859 u8 reserved_at_10[0x10]; 5860 5861 u8 reserved_at_20[0x10]; 5862 u8 op_mod[0x10]; 5863 5864 u8 reserved_at_40[0x8]; 5865 u8 qpn[0x18]; 5866 5867 u8 reserved_at_60[0x20]; 5868 }; 5869 5870 struct mlx5_ifc_destroy_psv_out_bits { 5871 u8 status[0x8]; 5872 u8 reserved_at_8[0x18]; 5873 5874 u8 syndrome[0x20]; 5875 5876 u8 reserved_at_40[0x40]; 5877 }; 5878 5879 struct mlx5_ifc_destroy_psv_in_bits { 5880 u8 opcode[0x10]; 5881 u8 reserved_at_10[0x10]; 5882 5883 u8 reserved_at_20[0x10]; 5884 u8 op_mod[0x10]; 5885 5886 u8 reserved_at_40[0x8]; 5887 u8 psvn[0x18]; 5888 5889 u8 reserved_at_60[0x20]; 5890 }; 5891 5892 struct mlx5_ifc_destroy_mkey_out_bits { 5893 u8 status[0x8]; 5894 u8 reserved_at_8[0x18]; 5895 5896 u8 syndrome[0x20]; 5897 5898 u8 reserved_at_40[0x40]; 5899 }; 5900 5901 struct mlx5_ifc_destroy_mkey_in_bits { 5902 u8 opcode[0x10]; 5903 u8 reserved_at_10[0x10]; 5904 5905 u8 reserved_at_20[0x10]; 5906 u8 op_mod[0x10]; 5907 5908 u8 reserved_at_40[0x8]; 5909 u8 mkey_index[0x18]; 5910 5911 u8 reserved_at_60[0x20]; 5912 }; 5913 5914 struct mlx5_ifc_destroy_flow_table_out_bits { 5915 u8 status[0x8]; 5916 u8 reserved_at_8[0x18]; 5917 5918 u8 syndrome[0x20]; 5919 5920 u8 reserved_at_40[0x40]; 5921 }; 5922 5923 struct mlx5_ifc_destroy_flow_table_in_bits { 5924 u8 opcode[0x10]; 5925 u8 reserved_at_10[0x10]; 5926 5927 u8 reserved_at_20[0x10]; 5928 u8 op_mod[0x10]; 5929 5930 u8 other_vport[0x1]; 5931 u8 reserved_at_41[0xf]; 5932 u8 vport_number[0x10]; 5933 5934 u8 reserved_at_60[0x20]; 5935 5936 u8 table_type[0x8]; 5937 u8 reserved_at_88[0x18]; 5938 5939 u8 reserved_at_a0[0x8]; 5940 u8 table_id[0x18]; 5941 5942 u8 reserved_at_c0[0x140]; 5943 }; 5944 5945 struct mlx5_ifc_destroy_flow_group_out_bits { 5946 u8 status[0x8]; 5947 u8 reserved_at_8[0x18]; 5948 5949 u8 syndrome[0x20]; 5950 5951 u8 reserved_at_40[0x40]; 5952 }; 5953 5954 struct mlx5_ifc_destroy_flow_group_in_bits { 5955 u8 opcode[0x10]; 5956 u8 reserved_at_10[0x10]; 5957 5958 u8 reserved_at_20[0x10]; 5959 u8 op_mod[0x10]; 5960 5961 u8 other_vport[0x1]; 5962 u8 reserved_at_41[0xf]; 5963 u8 vport_number[0x10]; 5964 5965 u8 reserved_at_60[0x20]; 5966 5967 u8 table_type[0x8]; 5968 u8 reserved_at_88[0x18]; 5969 5970 u8 reserved_at_a0[0x8]; 5971 u8 table_id[0x18]; 5972 5973 u8 group_id[0x20]; 5974 5975 u8 reserved_at_e0[0x120]; 5976 }; 5977 5978 struct mlx5_ifc_destroy_eq_out_bits { 5979 u8 status[0x8]; 5980 u8 reserved_at_8[0x18]; 5981 5982 u8 syndrome[0x20]; 5983 5984 u8 reserved_at_40[0x40]; 5985 }; 5986 5987 struct mlx5_ifc_destroy_eq_in_bits { 5988 u8 opcode[0x10]; 5989 u8 reserved_at_10[0x10]; 5990 5991 u8 reserved_at_20[0x10]; 5992 u8 op_mod[0x10]; 5993 5994 u8 reserved_at_40[0x18]; 5995 u8 eq_number[0x8]; 5996 5997 u8 reserved_at_60[0x20]; 5998 }; 5999 6000 struct mlx5_ifc_destroy_dct_out_bits { 6001 u8 status[0x8]; 6002 u8 reserved_at_8[0x18]; 6003 6004 u8 syndrome[0x20]; 6005 6006 u8 reserved_at_40[0x40]; 6007 }; 6008 6009 struct mlx5_ifc_destroy_dct_in_bits { 6010 u8 opcode[0x10]; 6011 u8 reserved_at_10[0x10]; 6012 6013 u8 reserved_at_20[0x10]; 6014 u8 op_mod[0x10]; 6015 6016 u8 reserved_at_40[0x8]; 6017 u8 dctn[0x18]; 6018 6019 u8 reserved_at_60[0x20]; 6020 }; 6021 6022 struct mlx5_ifc_destroy_cq_out_bits { 6023 u8 status[0x8]; 6024 u8 reserved_at_8[0x18]; 6025 6026 u8 syndrome[0x20]; 6027 6028 u8 reserved_at_40[0x40]; 6029 }; 6030 6031 struct mlx5_ifc_destroy_cq_in_bits { 6032 u8 opcode[0x10]; 6033 u8 reserved_at_10[0x10]; 6034 6035 u8 reserved_at_20[0x10]; 6036 u8 op_mod[0x10]; 6037 6038 u8 reserved_at_40[0x8]; 6039 u8 cqn[0x18]; 6040 6041 u8 reserved_at_60[0x20]; 6042 }; 6043 6044 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6045 u8 status[0x8]; 6046 u8 reserved_at_8[0x18]; 6047 6048 u8 syndrome[0x20]; 6049 6050 u8 reserved_at_40[0x40]; 6051 }; 6052 6053 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6054 u8 opcode[0x10]; 6055 u8 reserved_at_10[0x10]; 6056 6057 u8 reserved_at_20[0x10]; 6058 u8 op_mod[0x10]; 6059 6060 u8 reserved_at_40[0x20]; 6061 6062 u8 reserved_at_60[0x10]; 6063 u8 vxlan_udp_port[0x10]; 6064 }; 6065 6066 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6067 u8 status[0x8]; 6068 u8 reserved_at_8[0x18]; 6069 6070 u8 syndrome[0x20]; 6071 6072 u8 reserved_at_40[0x40]; 6073 }; 6074 6075 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6076 u8 opcode[0x10]; 6077 u8 reserved_at_10[0x10]; 6078 6079 u8 reserved_at_20[0x10]; 6080 u8 op_mod[0x10]; 6081 6082 u8 reserved_at_40[0x60]; 6083 6084 u8 reserved_at_a0[0x8]; 6085 u8 table_index[0x18]; 6086 6087 u8 reserved_at_c0[0x140]; 6088 }; 6089 6090 struct mlx5_ifc_delete_fte_out_bits { 6091 u8 status[0x8]; 6092 u8 reserved_at_8[0x18]; 6093 6094 u8 syndrome[0x20]; 6095 6096 u8 reserved_at_40[0x40]; 6097 }; 6098 6099 struct mlx5_ifc_delete_fte_in_bits { 6100 u8 opcode[0x10]; 6101 u8 reserved_at_10[0x10]; 6102 6103 u8 reserved_at_20[0x10]; 6104 u8 op_mod[0x10]; 6105 6106 u8 other_vport[0x1]; 6107 u8 reserved_at_41[0xf]; 6108 u8 vport_number[0x10]; 6109 6110 u8 reserved_at_60[0x20]; 6111 6112 u8 table_type[0x8]; 6113 u8 reserved_at_88[0x18]; 6114 6115 u8 reserved_at_a0[0x8]; 6116 u8 table_id[0x18]; 6117 6118 u8 reserved_at_c0[0x40]; 6119 6120 u8 flow_index[0x20]; 6121 6122 u8 reserved_at_120[0xe0]; 6123 }; 6124 6125 struct mlx5_ifc_dealloc_xrcd_out_bits { 6126 u8 status[0x8]; 6127 u8 reserved_at_8[0x18]; 6128 6129 u8 syndrome[0x20]; 6130 6131 u8 reserved_at_40[0x40]; 6132 }; 6133 6134 struct mlx5_ifc_dealloc_xrcd_in_bits { 6135 u8 opcode[0x10]; 6136 u8 reserved_at_10[0x10]; 6137 6138 u8 reserved_at_20[0x10]; 6139 u8 op_mod[0x10]; 6140 6141 u8 reserved_at_40[0x8]; 6142 u8 xrcd[0x18]; 6143 6144 u8 reserved_at_60[0x20]; 6145 }; 6146 6147 struct mlx5_ifc_dealloc_uar_out_bits { 6148 u8 status[0x8]; 6149 u8 reserved_at_8[0x18]; 6150 6151 u8 syndrome[0x20]; 6152 6153 u8 reserved_at_40[0x40]; 6154 }; 6155 6156 struct mlx5_ifc_dealloc_uar_in_bits { 6157 u8 opcode[0x10]; 6158 u8 reserved_at_10[0x10]; 6159 6160 u8 reserved_at_20[0x10]; 6161 u8 op_mod[0x10]; 6162 6163 u8 reserved_at_40[0x8]; 6164 u8 uar[0x18]; 6165 6166 u8 reserved_at_60[0x20]; 6167 }; 6168 6169 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6170 u8 status[0x8]; 6171 u8 reserved_at_8[0x18]; 6172 6173 u8 syndrome[0x20]; 6174 6175 u8 reserved_at_40[0x40]; 6176 }; 6177 6178 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6179 u8 opcode[0x10]; 6180 u8 reserved_at_10[0x10]; 6181 6182 u8 reserved_at_20[0x10]; 6183 u8 op_mod[0x10]; 6184 6185 u8 reserved_at_40[0x8]; 6186 u8 transport_domain[0x18]; 6187 6188 u8 reserved_at_60[0x20]; 6189 }; 6190 6191 struct mlx5_ifc_dealloc_q_counter_out_bits { 6192 u8 status[0x8]; 6193 u8 reserved_at_8[0x18]; 6194 6195 u8 syndrome[0x20]; 6196 6197 u8 reserved_at_40[0x40]; 6198 }; 6199 6200 struct mlx5_ifc_dealloc_q_counter_in_bits { 6201 u8 opcode[0x10]; 6202 u8 reserved_at_10[0x10]; 6203 6204 u8 reserved_at_20[0x10]; 6205 u8 op_mod[0x10]; 6206 6207 u8 reserved_at_40[0x18]; 6208 u8 counter_set_id[0x8]; 6209 6210 u8 reserved_at_60[0x20]; 6211 }; 6212 6213 struct mlx5_ifc_dealloc_pd_out_bits { 6214 u8 status[0x8]; 6215 u8 reserved_at_8[0x18]; 6216 6217 u8 syndrome[0x20]; 6218 6219 u8 reserved_at_40[0x40]; 6220 }; 6221 6222 struct mlx5_ifc_dealloc_pd_in_bits { 6223 u8 opcode[0x10]; 6224 u8 reserved_at_10[0x10]; 6225 6226 u8 reserved_at_20[0x10]; 6227 u8 op_mod[0x10]; 6228 6229 u8 reserved_at_40[0x8]; 6230 u8 pd[0x18]; 6231 6232 u8 reserved_at_60[0x20]; 6233 }; 6234 6235 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6236 u8 status[0x8]; 6237 u8 reserved_at_8[0x18]; 6238 6239 u8 syndrome[0x20]; 6240 6241 u8 reserved_at_40[0x40]; 6242 }; 6243 6244 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6245 u8 opcode[0x10]; 6246 u8 reserved_at_10[0x10]; 6247 6248 u8 reserved_at_20[0x10]; 6249 u8 op_mod[0x10]; 6250 6251 u8 reserved_at_40[0x10]; 6252 u8 flow_counter_id[0x10]; 6253 6254 u8 reserved_at_60[0x20]; 6255 }; 6256 6257 struct mlx5_ifc_create_xrq_out_bits { 6258 u8 status[0x8]; 6259 u8 reserved_at_8[0x18]; 6260 6261 u8 syndrome[0x20]; 6262 6263 u8 reserved_at_40[0x8]; 6264 u8 xrqn[0x18]; 6265 6266 u8 reserved_at_60[0x20]; 6267 }; 6268 6269 struct mlx5_ifc_create_xrq_in_bits { 6270 u8 opcode[0x10]; 6271 u8 reserved_at_10[0x10]; 6272 6273 u8 reserved_at_20[0x10]; 6274 u8 op_mod[0x10]; 6275 6276 u8 reserved_at_40[0x40]; 6277 6278 struct mlx5_ifc_xrqc_bits xrq_context; 6279 }; 6280 6281 struct mlx5_ifc_create_xrc_srq_out_bits { 6282 u8 status[0x8]; 6283 u8 reserved_at_8[0x18]; 6284 6285 u8 syndrome[0x20]; 6286 6287 u8 reserved_at_40[0x8]; 6288 u8 xrc_srqn[0x18]; 6289 6290 u8 reserved_at_60[0x20]; 6291 }; 6292 6293 struct mlx5_ifc_create_xrc_srq_in_bits { 6294 u8 opcode[0x10]; 6295 u8 reserved_at_10[0x10]; 6296 6297 u8 reserved_at_20[0x10]; 6298 u8 op_mod[0x10]; 6299 6300 u8 reserved_at_40[0x40]; 6301 6302 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6303 6304 u8 reserved_at_280[0x600]; 6305 6306 u8 pas[0][0x40]; 6307 }; 6308 6309 struct mlx5_ifc_create_tis_out_bits { 6310 u8 status[0x8]; 6311 u8 reserved_at_8[0x18]; 6312 6313 u8 syndrome[0x20]; 6314 6315 u8 reserved_at_40[0x8]; 6316 u8 tisn[0x18]; 6317 6318 u8 reserved_at_60[0x20]; 6319 }; 6320 6321 struct mlx5_ifc_create_tis_in_bits { 6322 u8 opcode[0x10]; 6323 u8 reserved_at_10[0x10]; 6324 6325 u8 reserved_at_20[0x10]; 6326 u8 op_mod[0x10]; 6327 6328 u8 reserved_at_40[0xc0]; 6329 6330 struct mlx5_ifc_tisc_bits ctx; 6331 }; 6332 6333 struct mlx5_ifc_create_tir_out_bits { 6334 u8 status[0x8]; 6335 u8 reserved_at_8[0x18]; 6336 6337 u8 syndrome[0x20]; 6338 6339 u8 reserved_at_40[0x8]; 6340 u8 tirn[0x18]; 6341 6342 u8 reserved_at_60[0x20]; 6343 }; 6344 6345 struct mlx5_ifc_create_tir_in_bits { 6346 u8 opcode[0x10]; 6347 u8 reserved_at_10[0x10]; 6348 6349 u8 reserved_at_20[0x10]; 6350 u8 op_mod[0x10]; 6351 6352 u8 reserved_at_40[0xc0]; 6353 6354 struct mlx5_ifc_tirc_bits ctx; 6355 }; 6356 6357 struct mlx5_ifc_create_srq_out_bits { 6358 u8 status[0x8]; 6359 u8 reserved_at_8[0x18]; 6360 6361 u8 syndrome[0x20]; 6362 6363 u8 reserved_at_40[0x8]; 6364 u8 srqn[0x18]; 6365 6366 u8 reserved_at_60[0x20]; 6367 }; 6368 6369 struct mlx5_ifc_create_srq_in_bits { 6370 u8 opcode[0x10]; 6371 u8 reserved_at_10[0x10]; 6372 6373 u8 reserved_at_20[0x10]; 6374 u8 op_mod[0x10]; 6375 6376 u8 reserved_at_40[0x40]; 6377 6378 struct mlx5_ifc_srqc_bits srq_context_entry; 6379 6380 u8 reserved_at_280[0x600]; 6381 6382 u8 pas[0][0x40]; 6383 }; 6384 6385 struct mlx5_ifc_create_sq_out_bits { 6386 u8 status[0x8]; 6387 u8 reserved_at_8[0x18]; 6388 6389 u8 syndrome[0x20]; 6390 6391 u8 reserved_at_40[0x8]; 6392 u8 sqn[0x18]; 6393 6394 u8 reserved_at_60[0x20]; 6395 }; 6396 6397 struct mlx5_ifc_create_sq_in_bits { 6398 u8 opcode[0x10]; 6399 u8 reserved_at_10[0x10]; 6400 6401 u8 reserved_at_20[0x10]; 6402 u8 op_mod[0x10]; 6403 6404 u8 reserved_at_40[0xc0]; 6405 6406 struct mlx5_ifc_sqc_bits ctx; 6407 }; 6408 6409 struct mlx5_ifc_create_scheduling_element_out_bits { 6410 u8 status[0x8]; 6411 u8 reserved_at_8[0x18]; 6412 6413 u8 syndrome[0x20]; 6414 6415 u8 reserved_at_40[0x40]; 6416 6417 u8 scheduling_element_id[0x20]; 6418 6419 u8 reserved_at_a0[0x160]; 6420 }; 6421 6422 struct mlx5_ifc_create_scheduling_element_in_bits { 6423 u8 opcode[0x10]; 6424 u8 reserved_at_10[0x10]; 6425 6426 u8 reserved_at_20[0x10]; 6427 u8 op_mod[0x10]; 6428 6429 u8 scheduling_hierarchy[0x8]; 6430 u8 reserved_at_48[0x18]; 6431 6432 u8 reserved_at_60[0xa0]; 6433 6434 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6435 6436 u8 reserved_at_300[0x100]; 6437 }; 6438 6439 struct mlx5_ifc_create_rqt_out_bits { 6440 u8 status[0x8]; 6441 u8 reserved_at_8[0x18]; 6442 6443 u8 syndrome[0x20]; 6444 6445 u8 reserved_at_40[0x8]; 6446 u8 rqtn[0x18]; 6447 6448 u8 reserved_at_60[0x20]; 6449 }; 6450 6451 struct mlx5_ifc_create_rqt_in_bits { 6452 u8 opcode[0x10]; 6453 u8 reserved_at_10[0x10]; 6454 6455 u8 reserved_at_20[0x10]; 6456 u8 op_mod[0x10]; 6457 6458 u8 reserved_at_40[0xc0]; 6459 6460 struct mlx5_ifc_rqtc_bits rqt_context; 6461 }; 6462 6463 struct mlx5_ifc_create_rq_out_bits { 6464 u8 status[0x8]; 6465 u8 reserved_at_8[0x18]; 6466 6467 u8 syndrome[0x20]; 6468 6469 u8 reserved_at_40[0x8]; 6470 u8 rqn[0x18]; 6471 6472 u8 reserved_at_60[0x20]; 6473 }; 6474 6475 struct mlx5_ifc_create_rq_in_bits { 6476 u8 opcode[0x10]; 6477 u8 reserved_at_10[0x10]; 6478 6479 u8 reserved_at_20[0x10]; 6480 u8 op_mod[0x10]; 6481 6482 u8 reserved_at_40[0xc0]; 6483 6484 struct mlx5_ifc_rqc_bits ctx; 6485 }; 6486 6487 struct mlx5_ifc_create_rmp_out_bits { 6488 u8 status[0x8]; 6489 u8 reserved_at_8[0x18]; 6490 6491 u8 syndrome[0x20]; 6492 6493 u8 reserved_at_40[0x8]; 6494 u8 rmpn[0x18]; 6495 6496 u8 reserved_at_60[0x20]; 6497 }; 6498 6499 struct mlx5_ifc_create_rmp_in_bits { 6500 u8 opcode[0x10]; 6501 u8 reserved_at_10[0x10]; 6502 6503 u8 reserved_at_20[0x10]; 6504 u8 op_mod[0x10]; 6505 6506 u8 reserved_at_40[0xc0]; 6507 6508 struct mlx5_ifc_rmpc_bits ctx; 6509 }; 6510 6511 struct mlx5_ifc_create_qp_out_bits { 6512 u8 status[0x8]; 6513 u8 reserved_at_8[0x18]; 6514 6515 u8 syndrome[0x20]; 6516 6517 u8 reserved_at_40[0x8]; 6518 u8 qpn[0x18]; 6519 6520 u8 reserved_at_60[0x20]; 6521 }; 6522 6523 struct mlx5_ifc_create_qp_in_bits { 6524 u8 opcode[0x10]; 6525 u8 reserved_at_10[0x10]; 6526 6527 u8 reserved_at_20[0x10]; 6528 u8 op_mod[0x10]; 6529 6530 u8 reserved_at_40[0x40]; 6531 6532 u8 opt_param_mask[0x20]; 6533 6534 u8 reserved_at_a0[0x20]; 6535 6536 struct mlx5_ifc_qpc_bits qpc; 6537 6538 u8 reserved_at_800[0x80]; 6539 6540 u8 pas[0][0x40]; 6541 }; 6542 6543 struct mlx5_ifc_create_psv_out_bits { 6544 u8 status[0x8]; 6545 u8 reserved_at_8[0x18]; 6546 6547 u8 syndrome[0x20]; 6548 6549 u8 reserved_at_40[0x40]; 6550 6551 u8 reserved_at_80[0x8]; 6552 u8 psv0_index[0x18]; 6553 6554 u8 reserved_at_a0[0x8]; 6555 u8 psv1_index[0x18]; 6556 6557 u8 reserved_at_c0[0x8]; 6558 u8 psv2_index[0x18]; 6559 6560 u8 reserved_at_e0[0x8]; 6561 u8 psv3_index[0x18]; 6562 }; 6563 6564 struct mlx5_ifc_create_psv_in_bits { 6565 u8 opcode[0x10]; 6566 u8 reserved_at_10[0x10]; 6567 6568 u8 reserved_at_20[0x10]; 6569 u8 op_mod[0x10]; 6570 6571 u8 num_psv[0x4]; 6572 u8 reserved_at_44[0x4]; 6573 u8 pd[0x18]; 6574 6575 u8 reserved_at_60[0x20]; 6576 }; 6577 6578 struct mlx5_ifc_create_mkey_out_bits { 6579 u8 status[0x8]; 6580 u8 reserved_at_8[0x18]; 6581 6582 u8 syndrome[0x20]; 6583 6584 u8 reserved_at_40[0x8]; 6585 u8 mkey_index[0x18]; 6586 6587 u8 reserved_at_60[0x20]; 6588 }; 6589 6590 struct mlx5_ifc_create_mkey_in_bits { 6591 u8 opcode[0x10]; 6592 u8 reserved_at_10[0x10]; 6593 6594 u8 reserved_at_20[0x10]; 6595 u8 op_mod[0x10]; 6596 6597 u8 reserved_at_40[0x20]; 6598 6599 u8 pg_access[0x1]; 6600 u8 reserved_at_61[0x1f]; 6601 6602 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6603 6604 u8 reserved_at_280[0x80]; 6605 6606 u8 translations_octword_actual_size[0x20]; 6607 6608 u8 reserved_at_320[0x560]; 6609 6610 u8 klm_pas_mtt[0][0x20]; 6611 }; 6612 6613 struct mlx5_ifc_create_flow_table_out_bits { 6614 u8 status[0x8]; 6615 u8 reserved_at_8[0x18]; 6616 6617 u8 syndrome[0x20]; 6618 6619 u8 reserved_at_40[0x8]; 6620 u8 table_id[0x18]; 6621 6622 u8 reserved_at_60[0x20]; 6623 }; 6624 6625 struct mlx5_ifc_create_flow_table_in_bits { 6626 u8 opcode[0x10]; 6627 u8 reserved_at_10[0x10]; 6628 6629 u8 reserved_at_20[0x10]; 6630 u8 op_mod[0x10]; 6631 6632 u8 other_vport[0x1]; 6633 u8 reserved_at_41[0xf]; 6634 u8 vport_number[0x10]; 6635 6636 u8 reserved_at_60[0x20]; 6637 6638 u8 table_type[0x8]; 6639 u8 reserved_at_88[0x18]; 6640 6641 u8 reserved_at_a0[0x20]; 6642 6643 u8 encap_en[0x1]; 6644 u8 decap_en[0x1]; 6645 u8 reserved_at_c2[0x2]; 6646 u8 table_miss_mode[0x4]; 6647 u8 level[0x8]; 6648 u8 reserved_at_d0[0x8]; 6649 u8 log_size[0x8]; 6650 6651 u8 reserved_at_e0[0x8]; 6652 u8 table_miss_id[0x18]; 6653 6654 u8 reserved_at_100[0x8]; 6655 u8 lag_master_next_table_id[0x18]; 6656 6657 u8 reserved_at_120[0x80]; 6658 }; 6659 6660 struct mlx5_ifc_create_flow_group_out_bits { 6661 u8 status[0x8]; 6662 u8 reserved_at_8[0x18]; 6663 6664 u8 syndrome[0x20]; 6665 6666 u8 reserved_at_40[0x8]; 6667 u8 group_id[0x18]; 6668 6669 u8 reserved_at_60[0x20]; 6670 }; 6671 6672 enum { 6673 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6674 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6675 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6676 }; 6677 6678 struct mlx5_ifc_create_flow_group_in_bits { 6679 u8 opcode[0x10]; 6680 u8 reserved_at_10[0x10]; 6681 6682 u8 reserved_at_20[0x10]; 6683 u8 op_mod[0x10]; 6684 6685 u8 other_vport[0x1]; 6686 u8 reserved_at_41[0xf]; 6687 u8 vport_number[0x10]; 6688 6689 u8 reserved_at_60[0x20]; 6690 6691 u8 table_type[0x8]; 6692 u8 reserved_at_88[0x18]; 6693 6694 u8 reserved_at_a0[0x8]; 6695 u8 table_id[0x18]; 6696 6697 u8 reserved_at_c0[0x20]; 6698 6699 u8 start_flow_index[0x20]; 6700 6701 u8 reserved_at_100[0x20]; 6702 6703 u8 end_flow_index[0x20]; 6704 6705 u8 reserved_at_140[0xa0]; 6706 6707 u8 reserved_at_1e0[0x18]; 6708 u8 match_criteria_enable[0x8]; 6709 6710 struct mlx5_ifc_fte_match_param_bits match_criteria; 6711 6712 u8 reserved_at_1200[0xe00]; 6713 }; 6714 6715 struct mlx5_ifc_create_eq_out_bits { 6716 u8 status[0x8]; 6717 u8 reserved_at_8[0x18]; 6718 6719 u8 syndrome[0x20]; 6720 6721 u8 reserved_at_40[0x18]; 6722 u8 eq_number[0x8]; 6723 6724 u8 reserved_at_60[0x20]; 6725 }; 6726 6727 struct mlx5_ifc_create_eq_in_bits { 6728 u8 opcode[0x10]; 6729 u8 reserved_at_10[0x10]; 6730 6731 u8 reserved_at_20[0x10]; 6732 u8 op_mod[0x10]; 6733 6734 u8 reserved_at_40[0x40]; 6735 6736 struct mlx5_ifc_eqc_bits eq_context_entry; 6737 6738 u8 reserved_at_280[0x40]; 6739 6740 u8 event_bitmask[0x40]; 6741 6742 u8 reserved_at_300[0x580]; 6743 6744 u8 pas[0][0x40]; 6745 }; 6746 6747 struct mlx5_ifc_create_dct_out_bits { 6748 u8 status[0x8]; 6749 u8 reserved_at_8[0x18]; 6750 6751 u8 syndrome[0x20]; 6752 6753 u8 reserved_at_40[0x8]; 6754 u8 dctn[0x18]; 6755 6756 u8 reserved_at_60[0x20]; 6757 }; 6758 6759 struct mlx5_ifc_create_dct_in_bits { 6760 u8 opcode[0x10]; 6761 u8 reserved_at_10[0x10]; 6762 6763 u8 reserved_at_20[0x10]; 6764 u8 op_mod[0x10]; 6765 6766 u8 reserved_at_40[0x40]; 6767 6768 struct mlx5_ifc_dctc_bits dct_context_entry; 6769 6770 u8 reserved_at_280[0x180]; 6771 }; 6772 6773 struct mlx5_ifc_create_cq_out_bits { 6774 u8 status[0x8]; 6775 u8 reserved_at_8[0x18]; 6776 6777 u8 syndrome[0x20]; 6778 6779 u8 reserved_at_40[0x8]; 6780 u8 cqn[0x18]; 6781 6782 u8 reserved_at_60[0x20]; 6783 }; 6784 6785 struct mlx5_ifc_create_cq_in_bits { 6786 u8 opcode[0x10]; 6787 u8 reserved_at_10[0x10]; 6788 6789 u8 reserved_at_20[0x10]; 6790 u8 op_mod[0x10]; 6791 6792 u8 reserved_at_40[0x40]; 6793 6794 struct mlx5_ifc_cqc_bits cq_context; 6795 6796 u8 reserved_at_280[0x600]; 6797 6798 u8 pas[0][0x40]; 6799 }; 6800 6801 struct mlx5_ifc_config_int_moderation_out_bits { 6802 u8 status[0x8]; 6803 u8 reserved_at_8[0x18]; 6804 6805 u8 syndrome[0x20]; 6806 6807 u8 reserved_at_40[0x4]; 6808 u8 min_delay[0xc]; 6809 u8 int_vector[0x10]; 6810 6811 u8 reserved_at_60[0x20]; 6812 }; 6813 6814 enum { 6815 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 6816 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 6817 }; 6818 6819 struct mlx5_ifc_config_int_moderation_in_bits { 6820 u8 opcode[0x10]; 6821 u8 reserved_at_10[0x10]; 6822 6823 u8 reserved_at_20[0x10]; 6824 u8 op_mod[0x10]; 6825 6826 u8 reserved_at_40[0x4]; 6827 u8 min_delay[0xc]; 6828 u8 int_vector[0x10]; 6829 6830 u8 reserved_at_60[0x20]; 6831 }; 6832 6833 struct mlx5_ifc_attach_to_mcg_out_bits { 6834 u8 status[0x8]; 6835 u8 reserved_at_8[0x18]; 6836 6837 u8 syndrome[0x20]; 6838 6839 u8 reserved_at_40[0x40]; 6840 }; 6841 6842 struct mlx5_ifc_attach_to_mcg_in_bits { 6843 u8 opcode[0x10]; 6844 u8 reserved_at_10[0x10]; 6845 6846 u8 reserved_at_20[0x10]; 6847 u8 op_mod[0x10]; 6848 6849 u8 reserved_at_40[0x8]; 6850 u8 qpn[0x18]; 6851 6852 u8 reserved_at_60[0x20]; 6853 6854 u8 multicast_gid[16][0x8]; 6855 }; 6856 6857 struct mlx5_ifc_arm_xrq_out_bits { 6858 u8 status[0x8]; 6859 u8 reserved_at_8[0x18]; 6860 6861 u8 syndrome[0x20]; 6862 6863 u8 reserved_at_40[0x40]; 6864 }; 6865 6866 struct mlx5_ifc_arm_xrq_in_bits { 6867 u8 opcode[0x10]; 6868 u8 reserved_at_10[0x10]; 6869 6870 u8 reserved_at_20[0x10]; 6871 u8 op_mod[0x10]; 6872 6873 u8 reserved_at_40[0x8]; 6874 u8 xrqn[0x18]; 6875 6876 u8 reserved_at_60[0x10]; 6877 u8 lwm[0x10]; 6878 }; 6879 6880 struct mlx5_ifc_arm_xrc_srq_out_bits { 6881 u8 status[0x8]; 6882 u8 reserved_at_8[0x18]; 6883 6884 u8 syndrome[0x20]; 6885 6886 u8 reserved_at_40[0x40]; 6887 }; 6888 6889 enum { 6890 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 6891 }; 6892 6893 struct mlx5_ifc_arm_xrc_srq_in_bits { 6894 u8 opcode[0x10]; 6895 u8 reserved_at_10[0x10]; 6896 6897 u8 reserved_at_20[0x10]; 6898 u8 op_mod[0x10]; 6899 6900 u8 reserved_at_40[0x8]; 6901 u8 xrc_srqn[0x18]; 6902 6903 u8 reserved_at_60[0x10]; 6904 u8 lwm[0x10]; 6905 }; 6906 6907 struct mlx5_ifc_arm_rq_out_bits { 6908 u8 status[0x8]; 6909 u8 reserved_at_8[0x18]; 6910 6911 u8 syndrome[0x20]; 6912 6913 u8 reserved_at_40[0x40]; 6914 }; 6915 6916 enum { 6917 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 6918 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 6919 }; 6920 6921 struct mlx5_ifc_arm_rq_in_bits { 6922 u8 opcode[0x10]; 6923 u8 reserved_at_10[0x10]; 6924 6925 u8 reserved_at_20[0x10]; 6926 u8 op_mod[0x10]; 6927 6928 u8 reserved_at_40[0x8]; 6929 u8 srq_number[0x18]; 6930 6931 u8 reserved_at_60[0x10]; 6932 u8 lwm[0x10]; 6933 }; 6934 6935 struct mlx5_ifc_arm_dct_out_bits { 6936 u8 status[0x8]; 6937 u8 reserved_at_8[0x18]; 6938 6939 u8 syndrome[0x20]; 6940 6941 u8 reserved_at_40[0x40]; 6942 }; 6943 6944 struct mlx5_ifc_arm_dct_in_bits { 6945 u8 opcode[0x10]; 6946 u8 reserved_at_10[0x10]; 6947 6948 u8 reserved_at_20[0x10]; 6949 u8 op_mod[0x10]; 6950 6951 u8 reserved_at_40[0x8]; 6952 u8 dct_number[0x18]; 6953 6954 u8 reserved_at_60[0x20]; 6955 }; 6956 6957 struct mlx5_ifc_alloc_xrcd_out_bits { 6958 u8 status[0x8]; 6959 u8 reserved_at_8[0x18]; 6960 6961 u8 syndrome[0x20]; 6962 6963 u8 reserved_at_40[0x8]; 6964 u8 xrcd[0x18]; 6965 6966 u8 reserved_at_60[0x20]; 6967 }; 6968 6969 struct mlx5_ifc_alloc_xrcd_in_bits { 6970 u8 opcode[0x10]; 6971 u8 reserved_at_10[0x10]; 6972 6973 u8 reserved_at_20[0x10]; 6974 u8 op_mod[0x10]; 6975 6976 u8 reserved_at_40[0x40]; 6977 }; 6978 6979 struct mlx5_ifc_alloc_uar_out_bits { 6980 u8 status[0x8]; 6981 u8 reserved_at_8[0x18]; 6982 6983 u8 syndrome[0x20]; 6984 6985 u8 reserved_at_40[0x8]; 6986 u8 uar[0x18]; 6987 6988 u8 reserved_at_60[0x20]; 6989 }; 6990 6991 struct mlx5_ifc_alloc_uar_in_bits { 6992 u8 opcode[0x10]; 6993 u8 reserved_at_10[0x10]; 6994 6995 u8 reserved_at_20[0x10]; 6996 u8 op_mod[0x10]; 6997 6998 u8 reserved_at_40[0x40]; 6999 }; 7000 7001 struct mlx5_ifc_alloc_transport_domain_out_bits { 7002 u8 status[0x8]; 7003 u8 reserved_at_8[0x18]; 7004 7005 u8 syndrome[0x20]; 7006 7007 u8 reserved_at_40[0x8]; 7008 u8 transport_domain[0x18]; 7009 7010 u8 reserved_at_60[0x20]; 7011 }; 7012 7013 struct mlx5_ifc_alloc_transport_domain_in_bits { 7014 u8 opcode[0x10]; 7015 u8 reserved_at_10[0x10]; 7016 7017 u8 reserved_at_20[0x10]; 7018 u8 op_mod[0x10]; 7019 7020 u8 reserved_at_40[0x40]; 7021 }; 7022 7023 struct mlx5_ifc_alloc_q_counter_out_bits { 7024 u8 status[0x8]; 7025 u8 reserved_at_8[0x18]; 7026 7027 u8 syndrome[0x20]; 7028 7029 u8 reserved_at_40[0x18]; 7030 u8 counter_set_id[0x8]; 7031 7032 u8 reserved_at_60[0x20]; 7033 }; 7034 7035 struct mlx5_ifc_alloc_q_counter_in_bits { 7036 u8 opcode[0x10]; 7037 u8 reserved_at_10[0x10]; 7038 7039 u8 reserved_at_20[0x10]; 7040 u8 op_mod[0x10]; 7041 7042 u8 reserved_at_40[0x40]; 7043 }; 7044 7045 struct mlx5_ifc_alloc_pd_out_bits { 7046 u8 status[0x8]; 7047 u8 reserved_at_8[0x18]; 7048 7049 u8 syndrome[0x20]; 7050 7051 u8 reserved_at_40[0x8]; 7052 u8 pd[0x18]; 7053 7054 u8 reserved_at_60[0x20]; 7055 }; 7056 7057 struct mlx5_ifc_alloc_pd_in_bits { 7058 u8 opcode[0x10]; 7059 u8 reserved_at_10[0x10]; 7060 7061 u8 reserved_at_20[0x10]; 7062 u8 op_mod[0x10]; 7063 7064 u8 reserved_at_40[0x40]; 7065 }; 7066 7067 struct mlx5_ifc_alloc_flow_counter_out_bits { 7068 u8 status[0x8]; 7069 u8 reserved_at_8[0x18]; 7070 7071 u8 syndrome[0x20]; 7072 7073 u8 reserved_at_40[0x10]; 7074 u8 flow_counter_id[0x10]; 7075 7076 u8 reserved_at_60[0x20]; 7077 }; 7078 7079 struct mlx5_ifc_alloc_flow_counter_in_bits { 7080 u8 opcode[0x10]; 7081 u8 reserved_at_10[0x10]; 7082 7083 u8 reserved_at_20[0x10]; 7084 u8 op_mod[0x10]; 7085 7086 u8 reserved_at_40[0x40]; 7087 }; 7088 7089 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7090 u8 status[0x8]; 7091 u8 reserved_at_8[0x18]; 7092 7093 u8 syndrome[0x20]; 7094 7095 u8 reserved_at_40[0x40]; 7096 }; 7097 7098 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7099 u8 opcode[0x10]; 7100 u8 reserved_at_10[0x10]; 7101 7102 u8 reserved_at_20[0x10]; 7103 u8 op_mod[0x10]; 7104 7105 u8 reserved_at_40[0x20]; 7106 7107 u8 reserved_at_60[0x10]; 7108 u8 vxlan_udp_port[0x10]; 7109 }; 7110 7111 struct mlx5_ifc_set_rate_limit_out_bits { 7112 u8 status[0x8]; 7113 u8 reserved_at_8[0x18]; 7114 7115 u8 syndrome[0x20]; 7116 7117 u8 reserved_at_40[0x40]; 7118 }; 7119 7120 struct mlx5_ifc_set_rate_limit_in_bits { 7121 u8 opcode[0x10]; 7122 u8 reserved_at_10[0x10]; 7123 7124 u8 reserved_at_20[0x10]; 7125 u8 op_mod[0x10]; 7126 7127 u8 reserved_at_40[0x10]; 7128 u8 rate_limit_index[0x10]; 7129 7130 u8 reserved_at_60[0x20]; 7131 7132 u8 rate_limit[0x20]; 7133 }; 7134 7135 struct mlx5_ifc_access_register_out_bits { 7136 u8 status[0x8]; 7137 u8 reserved_at_8[0x18]; 7138 7139 u8 syndrome[0x20]; 7140 7141 u8 reserved_at_40[0x40]; 7142 7143 u8 register_data[0][0x20]; 7144 }; 7145 7146 enum { 7147 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7148 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7149 }; 7150 7151 struct mlx5_ifc_access_register_in_bits { 7152 u8 opcode[0x10]; 7153 u8 reserved_at_10[0x10]; 7154 7155 u8 reserved_at_20[0x10]; 7156 u8 op_mod[0x10]; 7157 7158 u8 reserved_at_40[0x10]; 7159 u8 register_id[0x10]; 7160 7161 u8 argument[0x20]; 7162 7163 u8 register_data[0][0x20]; 7164 }; 7165 7166 struct mlx5_ifc_sltp_reg_bits { 7167 u8 status[0x4]; 7168 u8 version[0x4]; 7169 u8 local_port[0x8]; 7170 u8 pnat[0x2]; 7171 u8 reserved_at_12[0x2]; 7172 u8 lane[0x4]; 7173 u8 reserved_at_18[0x8]; 7174 7175 u8 reserved_at_20[0x20]; 7176 7177 u8 reserved_at_40[0x7]; 7178 u8 polarity[0x1]; 7179 u8 ob_tap0[0x8]; 7180 u8 ob_tap1[0x8]; 7181 u8 ob_tap2[0x8]; 7182 7183 u8 reserved_at_60[0xc]; 7184 u8 ob_preemp_mode[0x4]; 7185 u8 ob_reg[0x8]; 7186 u8 ob_bias[0x8]; 7187 7188 u8 reserved_at_80[0x20]; 7189 }; 7190 7191 struct mlx5_ifc_slrg_reg_bits { 7192 u8 status[0x4]; 7193 u8 version[0x4]; 7194 u8 local_port[0x8]; 7195 u8 pnat[0x2]; 7196 u8 reserved_at_12[0x2]; 7197 u8 lane[0x4]; 7198 u8 reserved_at_18[0x8]; 7199 7200 u8 time_to_link_up[0x10]; 7201 u8 reserved_at_30[0xc]; 7202 u8 grade_lane_speed[0x4]; 7203 7204 u8 grade_version[0x8]; 7205 u8 grade[0x18]; 7206 7207 u8 reserved_at_60[0x4]; 7208 u8 height_grade_type[0x4]; 7209 u8 height_grade[0x18]; 7210 7211 u8 height_dz[0x10]; 7212 u8 height_dv[0x10]; 7213 7214 u8 reserved_at_a0[0x10]; 7215 u8 height_sigma[0x10]; 7216 7217 u8 reserved_at_c0[0x20]; 7218 7219 u8 reserved_at_e0[0x4]; 7220 u8 phase_grade_type[0x4]; 7221 u8 phase_grade[0x18]; 7222 7223 u8 reserved_at_100[0x8]; 7224 u8 phase_eo_pos[0x8]; 7225 u8 reserved_at_110[0x8]; 7226 u8 phase_eo_neg[0x8]; 7227 7228 u8 ffe_set_tested[0x10]; 7229 u8 test_errors_per_lane[0x10]; 7230 }; 7231 7232 struct mlx5_ifc_pvlc_reg_bits { 7233 u8 reserved_at_0[0x8]; 7234 u8 local_port[0x8]; 7235 u8 reserved_at_10[0x10]; 7236 7237 u8 reserved_at_20[0x1c]; 7238 u8 vl_hw_cap[0x4]; 7239 7240 u8 reserved_at_40[0x1c]; 7241 u8 vl_admin[0x4]; 7242 7243 u8 reserved_at_60[0x1c]; 7244 u8 vl_operational[0x4]; 7245 }; 7246 7247 struct mlx5_ifc_pude_reg_bits { 7248 u8 swid[0x8]; 7249 u8 local_port[0x8]; 7250 u8 reserved_at_10[0x4]; 7251 u8 admin_status[0x4]; 7252 u8 reserved_at_18[0x4]; 7253 u8 oper_status[0x4]; 7254 7255 u8 reserved_at_20[0x60]; 7256 }; 7257 7258 struct mlx5_ifc_ptys_reg_bits { 7259 u8 reserved_at_0[0x1]; 7260 u8 an_disable_admin[0x1]; 7261 u8 an_disable_cap[0x1]; 7262 u8 reserved_at_3[0x5]; 7263 u8 local_port[0x8]; 7264 u8 reserved_at_10[0xd]; 7265 u8 proto_mask[0x3]; 7266 7267 u8 an_status[0x4]; 7268 u8 reserved_at_24[0x3c]; 7269 7270 u8 eth_proto_capability[0x20]; 7271 7272 u8 ib_link_width_capability[0x10]; 7273 u8 ib_proto_capability[0x10]; 7274 7275 u8 reserved_at_a0[0x20]; 7276 7277 u8 eth_proto_admin[0x20]; 7278 7279 u8 ib_link_width_admin[0x10]; 7280 u8 ib_proto_admin[0x10]; 7281 7282 u8 reserved_at_100[0x20]; 7283 7284 u8 eth_proto_oper[0x20]; 7285 7286 u8 ib_link_width_oper[0x10]; 7287 u8 ib_proto_oper[0x10]; 7288 7289 u8 reserved_at_160[0x20]; 7290 7291 u8 eth_proto_lp_advertise[0x20]; 7292 7293 u8 reserved_at_1a0[0x60]; 7294 }; 7295 7296 struct mlx5_ifc_mlcr_reg_bits { 7297 u8 reserved_at_0[0x8]; 7298 u8 local_port[0x8]; 7299 u8 reserved_at_10[0x20]; 7300 7301 u8 beacon_duration[0x10]; 7302 u8 reserved_at_40[0x10]; 7303 7304 u8 beacon_remain[0x10]; 7305 }; 7306 7307 struct mlx5_ifc_ptas_reg_bits { 7308 u8 reserved_at_0[0x20]; 7309 7310 u8 algorithm_options[0x10]; 7311 u8 reserved_at_30[0x4]; 7312 u8 repetitions_mode[0x4]; 7313 u8 num_of_repetitions[0x8]; 7314 7315 u8 grade_version[0x8]; 7316 u8 height_grade_type[0x4]; 7317 u8 phase_grade_type[0x4]; 7318 u8 height_grade_weight[0x8]; 7319 u8 phase_grade_weight[0x8]; 7320 7321 u8 gisim_measure_bits[0x10]; 7322 u8 adaptive_tap_measure_bits[0x10]; 7323 7324 u8 ber_bath_high_error_threshold[0x10]; 7325 u8 ber_bath_mid_error_threshold[0x10]; 7326 7327 u8 ber_bath_low_error_threshold[0x10]; 7328 u8 one_ratio_high_threshold[0x10]; 7329 7330 u8 one_ratio_high_mid_threshold[0x10]; 7331 u8 one_ratio_low_mid_threshold[0x10]; 7332 7333 u8 one_ratio_low_threshold[0x10]; 7334 u8 ndeo_error_threshold[0x10]; 7335 7336 u8 mixer_offset_step_size[0x10]; 7337 u8 reserved_at_110[0x8]; 7338 u8 mix90_phase_for_voltage_bath[0x8]; 7339 7340 u8 mixer_offset_start[0x10]; 7341 u8 mixer_offset_end[0x10]; 7342 7343 u8 reserved_at_140[0x15]; 7344 u8 ber_test_time[0xb]; 7345 }; 7346 7347 struct mlx5_ifc_pspa_reg_bits { 7348 u8 swid[0x8]; 7349 u8 local_port[0x8]; 7350 u8 sub_port[0x8]; 7351 u8 reserved_at_18[0x8]; 7352 7353 u8 reserved_at_20[0x20]; 7354 }; 7355 7356 struct mlx5_ifc_pqdr_reg_bits { 7357 u8 reserved_at_0[0x8]; 7358 u8 local_port[0x8]; 7359 u8 reserved_at_10[0x5]; 7360 u8 prio[0x3]; 7361 u8 reserved_at_18[0x6]; 7362 u8 mode[0x2]; 7363 7364 u8 reserved_at_20[0x20]; 7365 7366 u8 reserved_at_40[0x10]; 7367 u8 min_threshold[0x10]; 7368 7369 u8 reserved_at_60[0x10]; 7370 u8 max_threshold[0x10]; 7371 7372 u8 reserved_at_80[0x10]; 7373 u8 mark_probability_denominator[0x10]; 7374 7375 u8 reserved_at_a0[0x60]; 7376 }; 7377 7378 struct mlx5_ifc_ppsc_reg_bits { 7379 u8 reserved_at_0[0x8]; 7380 u8 local_port[0x8]; 7381 u8 reserved_at_10[0x10]; 7382 7383 u8 reserved_at_20[0x60]; 7384 7385 u8 reserved_at_80[0x1c]; 7386 u8 wrps_admin[0x4]; 7387 7388 u8 reserved_at_a0[0x1c]; 7389 u8 wrps_status[0x4]; 7390 7391 u8 reserved_at_c0[0x8]; 7392 u8 up_threshold[0x8]; 7393 u8 reserved_at_d0[0x8]; 7394 u8 down_threshold[0x8]; 7395 7396 u8 reserved_at_e0[0x20]; 7397 7398 u8 reserved_at_100[0x1c]; 7399 u8 srps_admin[0x4]; 7400 7401 u8 reserved_at_120[0x1c]; 7402 u8 srps_status[0x4]; 7403 7404 u8 reserved_at_140[0x40]; 7405 }; 7406 7407 struct mlx5_ifc_pplr_reg_bits { 7408 u8 reserved_at_0[0x8]; 7409 u8 local_port[0x8]; 7410 u8 reserved_at_10[0x10]; 7411 7412 u8 reserved_at_20[0x8]; 7413 u8 lb_cap[0x8]; 7414 u8 reserved_at_30[0x8]; 7415 u8 lb_en[0x8]; 7416 }; 7417 7418 struct mlx5_ifc_pplm_reg_bits { 7419 u8 reserved_at_0[0x8]; 7420 u8 local_port[0x8]; 7421 u8 reserved_at_10[0x10]; 7422 7423 u8 reserved_at_20[0x20]; 7424 7425 u8 port_profile_mode[0x8]; 7426 u8 static_port_profile[0x8]; 7427 u8 active_port_profile[0x8]; 7428 u8 reserved_at_58[0x8]; 7429 7430 u8 retransmission_active[0x8]; 7431 u8 fec_mode_active[0x18]; 7432 7433 u8 reserved_at_80[0x20]; 7434 }; 7435 7436 struct mlx5_ifc_ppcnt_reg_bits { 7437 u8 swid[0x8]; 7438 u8 local_port[0x8]; 7439 u8 pnat[0x2]; 7440 u8 reserved_at_12[0x8]; 7441 u8 grp[0x6]; 7442 7443 u8 clr[0x1]; 7444 u8 reserved_at_21[0x1c]; 7445 u8 prio_tc[0x3]; 7446 7447 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7448 }; 7449 7450 struct mlx5_ifc_mpcnt_reg_bits { 7451 u8 reserved_at_0[0x8]; 7452 u8 pcie_index[0x8]; 7453 u8 reserved_at_10[0xa]; 7454 u8 grp[0x6]; 7455 7456 u8 clr[0x1]; 7457 u8 reserved_at_21[0x1f]; 7458 7459 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 7460 }; 7461 7462 struct mlx5_ifc_ppad_reg_bits { 7463 u8 reserved_at_0[0x3]; 7464 u8 single_mac[0x1]; 7465 u8 reserved_at_4[0x4]; 7466 u8 local_port[0x8]; 7467 u8 mac_47_32[0x10]; 7468 7469 u8 mac_31_0[0x20]; 7470 7471 u8 reserved_at_40[0x40]; 7472 }; 7473 7474 struct mlx5_ifc_pmtu_reg_bits { 7475 u8 reserved_at_0[0x8]; 7476 u8 local_port[0x8]; 7477 u8 reserved_at_10[0x10]; 7478 7479 u8 max_mtu[0x10]; 7480 u8 reserved_at_30[0x10]; 7481 7482 u8 admin_mtu[0x10]; 7483 u8 reserved_at_50[0x10]; 7484 7485 u8 oper_mtu[0x10]; 7486 u8 reserved_at_70[0x10]; 7487 }; 7488 7489 struct mlx5_ifc_pmpr_reg_bits { 7490 u8 reserved_at_0[0x8]; 7491 u8 module[0x8]; 7492 u8 reserved_at_10[0x10]; 7493 7494 u8 reserved_at_20[0x18]; 7495 u8 attenuation_5g[0x8]; 7496 7497 u8 reserved_at_40[0x18]; 7498 u8 attenuation_7g[0x8]; 7499 7500 u8 reserved_at_60[0x18]; 7501 u8 attenuation_12g[0x8]; 7502 }; 7503 7504 struct mlx5_ifc_pmpe_reg_bits { 7505 u8 reserved_at_0[0x8]; 7506 u8 module[0x8]; 7507 u8 reserved_at_10[0xc]; 7508 u8 module_status[0x4]; 7509 7510 u8 reserved_at_20[0x60]; 7511 }; 7512 7513 struct mlx5_ifc_pmpc_reg_bits { 7514 u8 module_state_updated[32][0x8]; 7515 }; 7516 7517 struct mlx5_ifc_pmlpn_reg_bits { 7518 u8 reserved_at_0[0x4]; 7519 u8 mlpn_status[0x4]; 7520 u8 local_port[0x8]; 7521 u8 reserved_at_10[0x10]; 7522 7523 u8 e[0x1]; 7524 u8 reserved_at_21[0x1f]; 7525 }; 7526 7527 struct mlx5_ifc_pmlp_reg_bits { 7528 u8 rxtx[0x1]; 7529 u8 reserved_at_1[0x7]; 7530 u8 local_port[0x8]; 7531 u8 reserved_at_10[0x8]; 7532 u8 width[0x8]; 7533 7534 u8 lane0_module_mapping[0x20]; 7535 7536 u8 lane1_module_mapping[0x20]; 7537 7538 u8 lane2_module_mapping[0x20]; 7539 7540 u8 lane3_module_mapping[0x20]; 7541 7542 u8 reserved_at_a0[0x160]; 7543 }; 7544 7545 struct mlx5_ifc_pmaos_reg_bits { 7546 u8 reserved_at_0[0x8]; 7547 u8 module[0x8]; 7548 u8 reserved_at_10[0x4]; 7549 u8 admin_status[0x4]; 7550 u8 reserved_at_18[0x4]; 7551 u8 oper_status[0x4]; 7552 7553 u8 ase[0x1]; 7554 u8 ee[0x1]; 7555 u8 reserved_at_22[0x1c]; 7556 u8 e[0x2]; 7557 7558 u8 reserved_at_40[0x40]; 7559 }; 7560 7561 struct mlx5_ifc_plpc_reg_bits { 7562 u8 reserved_at_0[0x4]; 7563 u8 profile_id[0xc]; 7564 u8 reserved_at_10[0x4]; 7565 u8 proto_mask[0x4]; 7566 u8 reserved_at_18[0x8]; 7567 7568 u8 reserved_at_20[0x10]; 7569 u8 lane_speed[0x10]; 7570 7571 u8 reserved_at_40[0x17]; 7572 u8 lpbf[0x1]; 7573 u8 fec_mode_policy[0x8]; 7574 7575 u8 retransmission_capability[0x8]; 7576 u8 fec_mode_capability[0x18]; 7577 7578 u8 retransmission_support_admin[0x8]; 7579 u8 fec_mode_support_admin[0x18]; 7580 7581 u8 retransmission_request_admin[0x8]; 7582 u8 fec_mode_request_admin[0x18]; 7583 7584 u8 reserved_at_c0[0x80]; 7585 }; 7586 7587 struct mlx5_ifc_plib_reg_bits { 7588 u8 reserved_at_0[0x8]; 7589 u8 local_port[0x8]; 7590 u8 reserved_at_10[0x8]; 7591 u8 ib_port[0x8]; 7592 7593 u8 reserved_at_20[0x60]; 7594 }; 7595 7596 struct mlx5_ifc_plbf_reg_bits { 7597 u8 reserved_at_0[0x8]; 7598 u8 local_port[0x8]; 7599 u8 reserved_at_10[0xd]; 7600 u8 lbf_mode[0x3]; 7601 7602 u8 reserved_at_20[0x20]; 7603 }; 7604 7605 struct mlx5_ifc_pipg_reg_bits { 7606 u8 reserved_at_0[0x8]; 7607 u8 local_port[0x8]; 7608 u8 reserved_at_10[0x10]; 7609 7610 u8 dic[0x1]; 7611 u8 reserved_at_21[0x19]; 7612 u8 ipg[0x4]; 7613 u8 reserved_at_3e[0x2]; 7614 }; 7615 7616 struct mlx5_ifc_pifr_reg_bits { 7617 u8 reserved_at_0[0x8]; 7618 u8 local_port[0x8]; 7619 u8 reserved_at_10[0x10]; 7620 7621 u8 reserved_at_20[0xe0]; 7622 7623 u8 port_filter[8][0x20]; 7624 7625 u8 port_filter_update_en[8][0x20]; 7626 }; 7627 7628 struct mlx5_ifc_pfcc_reg_bits { 7629 u8 reserved_at_0[0x8]; 7630 u8 local_port[0x8]; 7631 u8 reserved_at_10[0x10]; 7632 7633 u8 ppan[0x4]; 7634 u8 reserved_at_24[0x4]; 7635 u8 prio_mask_tx[0x8]; 7636 u8 reserved_at_30[0x8]; 7637 u8 prio_mask_rx[0x8]; 7638 7639 u8 pptx[0x1]; 7640 u8 aptx[0x1]; 7641 u8 reserved_at_42[0x6]; 7642 u8 pfctx[0x8]; 7643 u8 reserved_at_50[0x10]; 7644 7645 u8 pprx[0x1]; 7646 u8 aprx[0x1]; 7647 u8 reserved_at_62[0x6]; 7648 u8 pfcrx[0x8]; 7649 u8 reserved_at_70[0x10]; 7650 7651 u8 reserved_at_80[0x80]; 7652 }; 7653 7654 struct mlx5_ifc_pelc_reg_bits { 7655 u8 op[0x4]; 7656 u8 reserved_at_4[0x4]; 7657 u8 local_port[0x8]; 7658 u8 reserved_at_10[0x10]; 7659 7660 u8 op_admin[0x8]; 7661 u8 op_capability[0x8]; 7662 u8 op_request[0x8]; 7663 u8 op_active[0x8]; 7664 7665 u8 admin[0x40]; 7666 7667 u8 capability[0x40]; 7668 7669 u8 request[0x40]; 7670 7671 u8 active[0x40]; 7672 7673 u8 reserved_at_140[0x80]; 7674 }; 7675 7676 struct mlx5_ifc_peir_reg_bits { 7677 u8 reserved_at_0[0x8]; 7678 u8 local_port[0x8]; 7679 u8 reserved_at_10[0x10]; 7680 7681 u8 reserved_at_20[0xc]; 7682 u8 error_count[0x4]; 7683 u8 reserved_at_30[0x10]; 7684 7685 u8 reserved_at_40[0xc]; 7686 u8 lane[0x4]; 7687 u8 reserved_at_50[0x8]; 7688 u8 error_type[0x8]; 7689 }; 7690 7691 struct mlx5_ifc_pcam_enhanced_features_bits { 7692 u8 reserved_at_0[0x7e]; 7693 7694 u8 ppcnt_discard_group[0x1]; 7695 u8 ppcnt_statistical_group[0x1]; 7696 }; 7697 7698 struct mlx5_ifc_pcam_reg_bits { 7699 u8 reserved_at_0[0x8]; 7700 u8 feature_group[0x8]; 7701 u8 reserved_at_10[0x8]; 7702 u8 access_reg_group[0x8]; 7703 7704 u8 reserved_at_20[0x20]; 7705 7706 union { 7707 u8 reserved_at_0[0x80]; 7708 } port_access_reg_cap_mask; 7709 7710 u8 reserved_at_c0[0x80]; 7711 7712 union { 7713 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 7714 u8 reserved_at_0[0x80]; 7715 } feature_cap_mask; 7716 7717 u8 reserved_at_1c0[0xc0]; 7718 }; 7719 7720 struct mlx5_ifc_mcam_enhanced_features_bits { 7721 u8 reserved_at_0[0x7f]; 7722 7723 u8 pcie_performance_group[0x1]; 7724 }; 7725 7726 struct mlx5_ifc_mcam_reg_bits { 7727 u8 reserved_at_0[0x8]; 7728 u8 feature_group[0x8]; 7729 u8 reserved_at_10[0x8]; 7730 u8 access_reg_group[0x8]; 7731 7732 u8 reserved_at_20[0x20]; 7733 7734 union { 7735 u8 reserved_at_0[0x80]; 7736 } mng_access_reg_cap_mask; 7737 7738 u8 reserved_at_c0[0x80]; 7739 7740 union { 7741 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 7742 u8 reserved_at_0[0x80]; 7743 } mng_feature_cap_mask; 7744 7745 u8 reserved_at_1c0[0x80]; 7746 }; 7747 7748 struct mlx5_ifc_pcap_reg_bits { 7749 u8 reserved_at_0[0x8]; 7750 u8 local_port[0x8]; 7751 u8 reserved_at_10[0x10]; 7752 7753 u8 port_capability_mask[4][0x20]; 7754 }; 7755 7756 struct mlx5_ifc_paos_reg_bits { 7757 u8 swid[0x8]; 7758 u8 local_port[0x8]; 7759 u8 reserved_at_10[0x4]; 7760 u8 admin_status[0x4]; 7761 u8 reserved_at_18[0x4]; 7762 u8 oper_status[0x4]; 7763 7764 u8 ase[0x1]; 7765 u8 ee[0x1]; 7766 u8 reserved_at_22[0x1c]; 7767 u8 e[0x2]; 7768 7769 u8 reserved_at_40[0x40]; 7770 }; 7771 7772 struct mlx5_ifc_pamp_reg_bits { 7773 u8 reserved_at_0[0x8]; 7774 u8 opamp_group[0x8]; 7775 u8 reserved_at_10[0xc]; 7776 u8 opamp_group_type[0x4]; 7777 7778 u8 start_index[0x10]; 7779 u8 reserved_at_30[0x4]; 7780 u8 num_of_indices[0xc]; 7781 7782 u8 index_data[18][0x10]; 7783 }; 7784 7785 struct mlx5_ifc_pcmr_reg_bits { 7786 u8 reserved_at_0[0x8]; 7787 u8 local_port[0x8]; 7788 u8 reserved_at_10[0x2e]; 7789 u8 fcs_cap[0x1]; 7790 u8 reserved_at_3f[0x1f]; 7791 u8 fcs_chk[0x1]; 7792 u8 reserved_at_5f[0x1]; 7793 }; 7794 7795 struct mlx5_ifc_lane_2_module_mapping_bits { 7796 u8 reserved_at_0[0x6]; 7797 u8 rx_lane[0x2]; 7798 u8 reserved_at_8[0x6]; 7799 u8 tx_lane[0x2]; 7800 u8 reserved_at_10[0x8]; 7801 u8 module[0x8]; 7802 }; 7803 7804 struct mlx5_ifc_bufferx_reg_bits { 7805 u8 reserved_at_0[0x6]; 7806 u8 lossy[0x1]; 7807 u8 epsb[0x1]; 7808 u8 reserved_at_8[0xc]; 7809 u8 size[0xc]; 7810 7811 u8 xoff_threshold[0x10]; 7812 u8 xon_threshold[0x10]; 7813 }; 7814 7815 struct mlx5_ifc_set_node_in_bits { 7816 u8 node_description[64][0x8]; 7817 }; 7818 7819 struct mlx5_ifc_register_power_settings_bits { 7820 u8 reserved_at_0[0x18]; 7821 u8 power_settings_level[0x8]; 7822 7823 u8 reserved_at_20[0x60]; 7824 }; 7825 7826 struct mlx5_ifc_register_host_endianness_bits { 7827 u8 he[0x1]; 7828 u8 reserved_at_1[0x1f]; 7829 7830 u8 reserved_at_20[0x60]; 7831 }; 7832 7833 struct mlx5_ifc_umr_pointer_desc_argument_bits { 7834 u8 reserved_at_0[0x20]; 7835 7836 u8 mkey[0x20]; 7837 7838 u8 addressh_63_32[0x20]; 7839 7840 u8 addressl_31_0[0x20]; 7841 }; 7842 7843 struct mlx5_ifc_ud_adrs_vector_bits { 7844 u8 dc_key[0x40]; 7845 7846 u8 ext[0x1]; 7847 u8 reserved_at_41[0x7]; 7848 u8 destination_qp_dct[0x18]; 7849 7850 u8 static_rate[0x4]; 7851 u8 sl_eth_prio[0x4]; 7852 u8 fl[0x1]; 7853 u8 mlid[0x7]; 7854 u8 rlid_udp_sport[0x10]; 7855 7856 u8 reserved_at_80[0x20]; 7857 7858 u8 rmac_47_16[0x20]; 7859 7860 u8 rmac_15_0[0x10]; 7861 u8 tclass[0x8]; 7862 u8 hop_limit[0x8]; 7863 7864 u8 reserved_at_e0[0x1]; 7865 u8 grh[0x1]; 7866 u8 reserved_at_e2[0x2]; 7867 u8 src_addr_index[0x8]; 7868 u8 flow_label[0x14]; 7869 7870 u8 rgid_rip[16][0x8]; 7871 }; 7872 7873 struct mlx5_ifc_pages_req_event_bits { 7874 u8 reserved_at_0[0x10]; 7875 u8 function_id[0x10]; 7876 7877 u8 num_pages[0x20]; 7878 7879 u8 reserved_at_40[0xa0]; 7880 }; 7881 7882 struct mlx5_ifc_eqe_bits { 7883 u8 reserved_at_0[0x8]; 7884 u8 event_type[0x8]; 7885 u8 reserved_at_10[0x8]; 7886 u8 event_sub_type[0x8]; 7887 7888 u8 reserved_at_20[0xe0]; 7889 7890 union mlx5_ifc_event_auto_bits event_data; 7891 7892 u8 reserved_at_1e0[0x10]; 7893 u8 signature[0x8]; 7894 u8 reserved_at_1f8[0x7]; 7895 u8 owner[0x1]; 7896 }; 7897 7898 enum { 7899 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 7900 }; 7901 7902 struct mlx5_ifc_cmd_queue_entry_bits { 7903 u8 type[0x8]; 7904 u8 reserved_at_8[0x18]; 7905 7906 u8 input_length[0x20]; 7907 7908 u8 input_mailbox_pointer_63_32[0x20]; 7909 7910 u8 input_mailbox_pointer_31_9[0x17]; 7911 u8 reserved_at_77[0x9]; 7912 7913 u8 command_input_inline_data[16][0x8]; 7914 7915 u8 command_output_inline_data[16][0x8]; 7916 7917 u8 output_mailbox_pointer_63_32[0x20]; 7918 7919 u8 output_mailbox_pointer_31_9[0x17]; 7920 u8 reserved_at_1b7[0x9]; 7921 7922 u8 output_length[0x20]; 7923 7924 u8 token[0x8]; 7925 u8 signature[0x8]; 7926 u8 reserved_at_1f0[0x8]; 7927 u8 status[0x7]; 7928 u8 ownership[0x1]; 7929 }; 7930 7931 struct mlx5_ifc_cmd_out_bits { 7932 u8 status[0x8]; 7933 u8 reserved_at_8[0x18]; 7934 7935 u8 syndrome[0x20]; 7936 7937 u8 command_output[0x20]; 7938 }; 7939 7940 struct mlx5_ifc_cmd_in_bits { 7941 u8 opcode[0x10]; 7942 u8 reserved_at_10[0x10]; 7943 7944 u8 reserved_at_20[0x10]; 7945 u8 op_mod[0x10]; 7946 7947 u8 command[0][0x20]; 7948 }; 7949 7950 struct mlx5_ifc_cmd_if_box_bits { 7951 u8 mailbox_data[512][0x8]; 7952 7953 u8 reserved_at_1000[0x180]; 7954 7955 u8 next_pointer_63_32[0x20]; 7956 7957 u8 next_pointer_31_10[0x16]; 7958 u8 reserved_at_11b6[0xa]; 7959 7960 u8 block_number[0x20]; 7961 7962 u8 reserved_at_11e0[0x8]; 7963 u8 token[0x8]; 7964 u8 ctrl_signature[0x8]; 7965 u8 signature[0x8]; 7966 }; 7967 7968 struct mlx5_ifc_mtt_bits { 7969 u8 ptag_63_32[0x20]; 7970 7971 u8 ptag_31_8[0x18]; 7972 u8 reserved_at_38[0x6]; 7973 u8 wr_en[0x1]; 7974 u8 rd_en[0x1]; 7975 }; 7976 7977 struct mlx5_ifc_query_wol_rol_out_bits { 7978 u8 status[0x8]; 7979 u8 reserved_at_8[0x18]; 7980 7981 u8 syndrome[0x20]; 7982 7983 u8 reserved_at_40[0x10]; 7984 u8 rol_mode[0x8]; 7985 u8 wol_mode[0x8]; 7986 7987 u8 reserved_at_60[0x20]; 7988 }; 7989 7990 struct mlx5_ifc_query_wol_rol_in_bits { 7991 u8 opcode[0x10]; 7992 u8 reserved_at_10[0x10]; 7993 7994 u8 reserved_at_20[0x10]; 7995 u8 op_mod[0x10]; 7996 7997 u8 reserved_at_40[0x40]; 7998 }; 7999 8000 struct mlx5_ifc_set_wol_rol_out_bits { 8001 u8 status[0x8]; 8002 u8 reserved_at_8[0x18]; 8003 8004 u8 syndrome[0x20]; 8005 8006 u8 reserved_at_40[0x40]; 8007 }; 8008 8009 struct mlx5_ifc_set_wol_rol_in_bits { 8010 u8 opcode[0x10]; 8011 u8 reserved_at_10[0x10]; 8012 8013 u8 reserved_at_20[0x10]; 8014 u8 op_mod[0x10]; 8015 8016 u8 rol_mode_valid[0x1]; 8017 u8 wol_mode_valid[0x1]; 8018 u8 reserved_at_42[0xe]; 8019 u8 rol_mode[0x8]; 8020 u8 wol_mode[0x8]; 8021 8022 u8 reserved_at_60[0x20]; 8023 }; 8024 8025 enum { 8026 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8027 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8028 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8029 }; 8030 8031 enum { 8032 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8033 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8034 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8035 }; 8036 8037 enum { 8038 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8039 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8040 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8041 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8042 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8043 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8044 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8045 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8046 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8047 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8048 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8049 }; 8050 8051 struct mlx5_ifc_initial_seg_bits { 8052 u8 fw_rev_minor[0x10]; 8053 u8 fw_rev_major[0x10]; 8054 8055 u8 cmd_interface_rev[0x10]; 8056 u8 fw_rev_subminor[0x10]; 8057 8058 u8 reserved_at_40[0x40]; 8059 8060 u8 cmdq_phy_addr_63_32[0x20]; 8061 8062 u8 cmdq_phy_addr_31_12[0x14]; 8063 u8 reserved_at_b4[0x2]; 8064 u8 nic_interface[0x2]; 8065 u8 log_cmdq_size[0x4]; 8066 u8 log_cmdq_stride[0x4]; 8067 8068 u8 command_doorbell_vector[0x20]; 8069 8070 u8 reserved_at_e0[0xf00]; 8071 8072 u8 initializing[0x1]; 8073 u8 reserved_at_fe1[0x4]; 8074 u8 nic_interface_supported[0x3]; 8075 u8 reserved_at_fe8[0x18]; 8076 8077 struct mlx5_ifc_health_buffer_bits health_buffer; 8078 8079 u8 no_dram_nic_offset[0x20]; 8080 8081 u8 reserved_at_1220[0x6e40]; 8082 8083 u8 reserved_at_8060[0x1f]; 8084 u8 clear_int[0x1]; 8085 8086 u8 health_syndrome[0x8]; 8087 u8 health_counter[0x18]; 8088 8089 u8 reserved_at_80a0[0x17fc0]; 8090 }; 8091 8092 struct mlx5_ifc_mtpps_reg_bits { 8093 u8 reserved_at_0[0xc]; 8094 u8 cap_number_of_pps_pins[0x4]; 8095 u8 reserved_at_10[0x4]; 8096 u8 cap_max_num_of_pps_in_pins[0x4]; 8097 u8 reserved_at_18[0x4]; 8098 u8 cap_max_num_of_pps_out_pins[0x4]; 8099 8100 u8 reserved_at_20[0x24]; 8101 u8 cap_pin_3_mode[0x4]; 8102 u8 reserved_at_48[0x4]; 8103 u8 cap_pin_2_mode[0x4]; 8104 u8 reserved_at_50[0x4]; 8105 u8 cap_pin_1_mode[0x4]; 8106 u8 reserved_at_58[0x4]; 8107 u8 cap_pin_0_mode[0x4]; 8108 8109 u8 reserved_at_60[0x4]; 8110 u8 cap_pin_7_mode[0x4]; 8111 u8 reserved_at_68[0x4]; 8112 u8 cap_pin_6_mode[0x4]; 8113 u8 reserved_at_70[0x4]; 8114 u8 cap_pin_5_mode[0x4]; 8115 u8 reserved_at_78[0x4]; 8116 u8 cap_pin_4_mode[0x4]; 8117 8118 u8 reserved_at_80[0x80]; 8119 8120 u8 enable[0x1]; 8121 u8 reserved_at_101[0xb]; 8122 u8 pattern[0x4]; 8123 u8 reserved_at_110[0x4]; 8124 u8 pin_mode[0x4]; 8125 u8 pin[0x8]; 8126 8127 u8 reserved_at_120[0x20]; 8128 8129 u8 time_stamp[0x40]; 8130 8131 u8 out_pulse_duration[0x10]; 8132 u8 out_periodic_adjustment[0x10]; 8133 8134 u8 reserved_at_1a0[0x60]; 8135 }; 8136 8137 struct mlx5_ifc_mtppse_reg_bits { 8138 u8 reserved_at_0[0x18]; 8139 u8 pin[0x8]; 8140 u8 event_arm[0x1]; 8141 u8 reserved_at_21[0x1b]; 8142 u8 event_generation_mode[0x4]; 8143 u8 reserved_at_40[0x40]; 8144 }; 8145 8146 union mlx5_ifc_ports_control_registers_document_bits { 8147 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8148 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8149 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8150 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8151 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8152 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8153 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8154 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8155 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8156 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8157 struct mlx5_ifc_paos_reg_bits paos_reg; 8158 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8159 struct mlx5_ifc_peir_reg_bits peir_reg; 8160 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8161 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8162 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8163 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8164 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8165 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8166 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8167 struct mlx5_ifc_plib_reg_bits plib_reg; 8168 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8169 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8170 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8171 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8172 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8173 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8174 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8175 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8176 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8177 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8178 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8179 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8180 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8181 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8182 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8183 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8184 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8185 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8186 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8187 struct mlx5_ifc_pude_reg_bits pude_reg; 8188 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8189 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8190 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8191 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8192 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8193 u8 reserved_at_0[0x60e0]; 8194 }; 8195 8196 union mlx5_ifc_debug_enhancements_document_bits { 8197 struct mlx5_ifc_health_buffer_bits health_buffer; 8198 u8 reserved_at_0[0x200]; 8199 }; 8200 8201 union mlx5_ifc_uplink_pci_interface_document_bits { 8202 struct mlx5_ifc_initial_seg_bits initial_seg; 8203 u8 reserved_at_0[0x20060]; 8204 }; 8205 8206 struct mlx5_ifc_set_flow_table_root_out_bits { 8207 u8 status[0x8]; 8208 u8 reserved_at_8[0x18]; 8209 8210 u8 syndrome[0x20]; 8211 8212 u8 reserved_at_40[0x40]; 8213 }; 8214 8215 struct mlx5_ifc_set_flow_table_root_in_bits { 8216 u8 opcode[0x10]; 8217 u8 reserved_at_10[0x10]; 8218 8219 u8 reserved_at_20[0x10]; 8220 u8 op_mod[0x10]; 8221 8222 u8 other_vport[0x1]; 8223 u8 reserved_at_41[0xf]; 8224 u8 vport_number[0x10]; 8225 8226 u8 reserved_at_60[0x20]; 8227 8228 u8 table_type[0x8]; 8229 u8 reserved_at_88[0x18]; 8230 8231 u8 reserved_at_a0[0x8]; 8232 u8 table_id[0x18]; 8233 8234 u8 reserved_at_c0[0x8]; 8235 u8 underlay_qpn[0x18]; 8236 u8 reserved_at_e0[0x120]; 8237 }; 8238 8239 enum { 8240 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8241 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8242 }; 8243 8244 struct mlx5_ifc_modify_flow_table_out_bits { 8245 u8 status[0x8]; 8246 u8 reserved_at_8[0x18]; 8247 8248 u8 syndrome[0x20]; 8249 8250 u8 reserved_at_40[0x40]; 8251 }; 8252 8253 struct mlx5_ifc_modify_flow_table_in_bits { 8254 u8 opcode[0x10]; 8255 u8 reserved_at_10[0x10]; 8256 8257 u8 reserved_at_20[0x10]; 8258 u8 op_mod[0x10]; 8259 8260 u8 other_vport[0x1]; 8261 u8 reserved_at_41[0xf]; 8262 u8 vport_number[0x10]; 8263 8264 u8 reserved_at_60[0x10]; 8265 u8 modify_field_select[0x10]; 8266 8267 u8 table_type[0x8]; 8268 u8 reserved_at_88[0x18]; 8269 8270 u8 reserved_at_a0[0x8]; 8271 u8 table_id[0x18]; 8272 8273 u8 reserved_at_c0[0x4]; 8274 u8 table_miss_mode[0x4]; 8275 u8 reserved_at_c8[0x18]; 8276 8277 u8 reserved_at_e0[0x8]; 8278 u8 table_miss_id[0x18]; 8279 8280 u8 reserved_at_100[0x8]; 8281 u8 lag_master_next_table_id[0x18]; 8282 8283 u8 reserved_at_120[0x80]; 8284 }; 8285 8286 struct mlx5_ifc_ets_tcn_config_reg_bits { 8287 u8 g[0x1]; 8288 u8 b[0x1]; 8289 u8 r[0x1]; 8290 u8 reserved_at_3[0x9]; 8291 u8 group[0x4]; 8292 u8 reserved_at_10[0x9]; 8293 u8 bw_allocation[0x7]; 8294 8295 u8 reserved_at_20[0xc]; 8296 u8 max_bw_units[0x4]; 8297 u8 reserved_at_30[0x8]; 8298 u8 max_bw_value[0x8]; 8299 }; 8300 8301 struct mlx5_ifc_ets_global_config_reg_bits { 8302 u8 reserved_at_0[0x2]; 8303 u8 r[0x1]; 8304 u8 reserved_at_3[0x1d]; 8305 8306 u8 reserved_at_20[0xc]; 8307 u8 max_bw_units[0x4]; 8308 u8 reserved_at_30[0x8]; 8309 u8 max_bw_value[0x8]; 8310 }; 8311 8312 struct mlx5_ifc_qetc_reg_bits { 8313 u8 reserved_at_0[0x8]; 8314 u8 port_number[0x8]; 8315 u8 reserved_at_10[0x30]; 8316 8317 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 8318 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 8319 }; 8320 8321 struct mlx5_ifc_qtct_reg_bits { 8322 u8 reserved_at_0[0x8]; 8323 u8 port_number[0x8]; 8324 u8 reserved_at_10[0xd]; 8325 u8 prio[0x3]; 8326 8327 u8 reserved_at_20[0x1d]; 8328 u8 tclass[0x3]; 8329 }; 8330 8331 struct mlx5_ifc_mcia_reg_bits { 8332 u8 l[0x1]; 8333 u8 reserved_at_1[0x7]; 8334 u8 module[0x8]; 8335 u8 reserved_at_10[0x8]; 8336 u8 status[0x8]; 8337 8338 u8 i2c_device_address[0x8]; 8339 u8 page_number[0x8]; 8340 u8 device_address[0x10]; 8341 8342 u8 reserved_at_40[0x10]; 8343 u8 size[0x10]; 8344 8345 u8 reserved_at_60[0x20]; 8346 8347 u8 dword_0[0x20]; 8348 u8 dword_1[0x20]; 8349 u8 dword_2[0x20]; 8350 u8 dword_3[0x20]; 8351 u8 dword_4[0x20]; 8352 u8 dword_5[0x20]; 8353 u8 dword_6[0x20]; 8354 u8 dword_7[0x20]; 8355 u8 dword_8[0x20]; 8356 u8 dword_9[0x20]; 8357 u8 dword_10[0x20]; 8358 u8 dword_11[0x20]; 8359 }; 8360 8361 struct mlx5_ifc_dcbx_param_bits { 8362 u8 dcbx_cee_cap[0x1]; 8363 u8 dcbx_ieee_cap[0x1]; 8364 u8 dcbx_standby_cap[0x1]; 8365 u8 reserved_at_0[0x5]; 8366 u8 port_number[0x8]; 8367 u8 reserved_at_10[0xa]; 8368 u8 max_application_table_size[6]; 8369 u8 reserved_at_20[0x15]; 8370 u8 version_oper[0x3]; 8371 u8 reserved_at_38[5]; 8372 u8 version_admin[0x3]; 8373 u8 willing_admin[0x1]; 8374 u8 reserved_at_41[0x3]; 8375 u8 pfc_cap_oper[0x4]; 8376 u8 reserved_at_48[0x4]; 8377 u8 pfc_cap_admin[0x4]; 8378 u8 reserved_at_50[0x4]; 8379 u8 num_of_tc_oper[0x4]; 8380 u8 reserved_at_58[0x4]; 8381 u8 num_of_tc_admin[0x4]; 8382 u8 remote_willing[0x1]; 8383 u8 reserved_at_61[3]; 8384 u8 remote_pfc_cap[4]; 8385 u8 reserved_at_68[0x14]; 8386 u8 remote_num_of_tc[0x4]; 8387 u8 reserved_at_80[0x18]; 8388 u8 error[0x8]; 8389 u8 reserved_at_a0[0x160]; 8390 }; 8391 8392 struct mlx5_ifc_lagc_bits { 8393 u8 reserved_at_0[0x1d]; 8394 u8 lag_state[0x3]; 8395 8396 u8 reserved_at_20[0x14]; 8397 u8 tx_remap_affinity_2[0x4]; 8398 u8 reserved_at_38[0x4]; 8399 u8 tx_remap_affinity_1[0x4]; 8400 }; 8401 8402 struct mlx5_ifc_create_lag_out_bits { 8403 u8 status[0x8]; 8404 u8 reserved_at_8[0x18]; 8405 8406 u8 syndrome[0x20]; 8407 8408 u8 reserved_at_40[0x40]; 8409 }; 8410 8411 struct mlx5_ifc_create_lag_in_bits { 8412 u8 opcode[0x10]; 8413 u8 reserved_at_10[0x10]; 8414 8415 u8 reserved_at_20[0x10]; 8416 u8 op_mod[0x10]; 8417 8418 struct mlx5_ifc_lagc_bits ctx; 8419 }; 8420 8421 struct mlx5_ifc_modify_lag_out_bits { 8422 u8 status[0x8]; 8423 u8 reserved_at_8[0x18]; 8424 8425 u8 syndrome[0x20]; 8426 8427 u8 reserved_at_40[0x40]; 8428 }; 8429 8430 struct mlx5_ifc_modify_lag_in_bits { 8431 u8 opcode[0x10]; 8432 u8 reserved_at_10[0x10]; 8433 8434 u8 reserved_at_20[0x10]; 8435 u8 op_mod[0x10]; 8436 8437 u8 reserved_at_40[0x20]; 8438 u8 field_select[0x20]; 8439 8440 struct mlx5_ifc_lagc_bits ctx; 8441 }; 8442 8443 struct mlx5_ifc_query_lag_out_bits { 8444 u8 status[0x8]; 8445 u8 reserved_at_8[0x18]; 8446 8447 u8 syndrome[0x20]; 8448 8449 u8 reserved_at_40[0x40]; 8450 8451 struct mlx5_ifc_lagc_bits ctx; 8452 }; 8453 8454 struct mlx5_ifc_query_lag_in_bits { 8455 u8 opcode[0x10]; 8456 u8 reserved_at_10[0x10]; 8457 8458 u8 reserved_at_20[0x10]; 8459 u8 op_mod[0x10]; 8460 8461 u8 reserved_at_40[0x40]; 8462 }; 8463 8464 struct mlx5_ifc_destroy_lag_out_bits { 8465 u8 status[0x8]; 8466 u8 reserved_at_8[0x18]; 8467 8468 u8 syndrome[0x20]; 8469 8470 u8 reserved_at_40[0x40]; 8471 }; 8472 8473 struct mlx5_ifc_destroy_lag_in_bits { 8474 u8 opcode[0x10]; 8475 u8 reserved_at_10[0x10]; 8476 8477 u8 reserved_at_20[0x10]; 8478 u8 op_mod[0x10]; 8479 8480 u8 reserved_at_40[0x40]; 8481 }; 8482 8483 struct mlx5_ifc_create_vport_lag_out_bits { 8484 u8 status[0x8]; 8485 u8 reserved_at_8[0x18]; 8486 8487 u8 syndrome[0x20]; 8488 8489 u8 reserved_at_40[0x40]; 8490 }; 8491 8492 struct mlx5_ifc_create_vport_lag_in_bits { 8493 u8 opcode[0x10]; 8494 u8 reserved_at_10[0x10]; 8495 8496 u8 reserved_at_20[0x10]; 8497 u8 op_mod[0x10]; 8498 8499 u8 reserved_at_40[0x40]; 8500 }; 8501 8502 struct mlx5_ifc_destroy_vport_lag_out_bits { 8503 u8 status[0x8]; 8504 u8 reserved_at_8[0x18]; 8505 8506 u8 syndrome[0x20]; 8507 8508 u8 reserved_at_40[0x40]; 8509 }; 8510 8511 struct mlx5_ifc_destroy_vport_lag_in_bits { 8512 u8 opcode[0x10]; 8513 u8 reserved_at_10[0x10]; 8514 8515 u8 reserved_at_20[0x10]; 8516 u8 op_mod[0x10]; 8517 8518 u8 reserved_at_40[0x40]; 8519 }; 8520 8521 #endif /* MLX5_IFC_H */ 8522