1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 enum { 36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb 60 }; 61 62 enum { 63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 67 }; 68 69 enum { 70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 72 }; 73 74 enum { 75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 77 MLX5_CMD_OP_INIT_HCA = 0x102, 78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 79 MLX5_CMD_OP_ENABLE_HCA = 0x104, 80 MLX5_CMD_OP_DISABLE_HCA = 0x105, 81 MLX5_CMD_OP_QUERY_PAGES = 0x107, 82 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 83 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 85 MLX5_CMD_OP_SET_ISSI = 0x10b, 86 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 87 MLX5_CMD_OP_CREATE_MKEY = 0x200, 88 MLX5_CMD_OP_QUERY_MKEY = 0x201, 89 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 90 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 91 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 92 MLX5_CMD_OP_CREATE_EQ = 0x301, 93 MLX5_CMD_OP_DESTROY_EQ = 0x302, 94 MLX5_CMD_OP_QUERY_EQ = 0x303, 95 MLX5_CMD_OP_GEN_EQE = 0x304, 96 MLX5_CMD_OP_CREATE_CQ = 0x400, 97 MLX5_CMD_OP_DESTROY_CQ = 0x401, 98 MLX5_CMD_OP_QUERY_CQ = 0x402, 99 MLX5_CMD_OP_MODIFY_CQ = 0x403, 100 MLX5_CMD_OP_CREATE_QP = 0x500, 101 MLX5_CMD_OP_DESTROY_QP = 0x501, 102 MLX5_CMD_OP_RST2INIT_QP = 0x502, 103 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 104 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 105 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 106 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 107 MLX5_CMD_OP_2ERR_QP = 0x507, 108 MLX5_CMD_OP_2RST_QP = 0x50a, 109 MLX5_CMD_OP_QUERY_QP = 0x50b, 110 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 111 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 112 MLX5_CMD_OP_CREATE_PSV = 0x600, 113 MLX5_CMD_OP_DESTROY_PSV = 0x601, 114 MLX5_CMD_OP_CREATE_SRQ = 0x700, 115 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 116 MLX5_CMD_OP_QUERY_SRQ = 0x702, 117 MLX5_CMD_OP_ARM_RQ = 0x703, 118 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 119 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 120 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 121 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 122 MLX5_CMD_OP_CREATE_DCT = 0x710, 123 MLX5_CMD_OP_DESTROY_DCT = 0x711, 124 MLX5_CMD_OP_DRAIN_DCT = 0x712, 125 MLX5_CMD_OP_QUERY_DCT = 0x713, 126 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 127 MLX5_CMD_OP_CREATE_XRQ = 0x717, 128 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 129 MLX5_CMD_OP_QUERY_XRQ = 0x719, 130 MLX5_CMD_OP_ARM_XRQ = 0x71a, 131 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 132 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 133 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 134 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 135 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 136 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 137 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 138 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 139 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 140 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 141 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 142 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 143 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 144 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 145 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 146 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 147 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 148 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 149 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 150 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 151 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 152 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 153 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 154 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 155 MLX5_CMD_OP_ALLOC_PD = 0x800, 156 MLX5_CMD_OP_DEALLOC_PD = 0x801, 157 MLX5_CMD_OP_ALLOC_UAR = 0x802, 158 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 159 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 160 MLX5_CMD_OP_ACCESS_REG = 0x805, 161 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 162 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 163 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 164 MLX5_CMD_OP_MAD_IFC = 0x50d, 165 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 166 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 167 MLX5_CMD_OP_NOP = 0x80d, 168 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 169 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 170 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 171 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 172 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 173 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 174 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 175 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 176 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 177 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 178 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 179 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 180 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 181 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 182 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 183 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 184 MLX5_CMD_OP_CREATE_LAG = 0x840, 185 MLX5_CMD_OP_MODIFY_LAG = 0x841, 186 MLX5_CMD_OP_QUERY_LAG = 0x842, 187 MLX5_CMD_OP_DESTROY_LAG = 0x843, 188 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 189 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 190 MLX5_CMD_OP_CREATE_TIR = 0x900, 191 MLX5_CMD_OP_MODIFY_TIR = 0x901, 192 MLX5_CMD_OP_DESTROY_TIR = 0x902, 193 MLX5_CMD_OP_QUERY_TIR = 0x903, 194 MLX5_CMD_OP_CREATE_SQ = 0x904, 195 MLX5_CMD_OP_MODIFY_SQ = 0x905, 196 MLX5_CMD_OP_DESTROY_SQ = 0x906, 197 MLX5_CMD_OP_QUERY_SQ = 0x907, 198 MLX5_CMD_OP_CREATE_RQ = 0x908, 199 MLX5_CMD_OP_MODIFY_RQ = 0x909, 200 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 201 MLX5_CMD_OP_QUERY_RQ = 0x90b, 202 MLX5_CMD_OP_CREATE_RMP = 0x90c, 203 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 204 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 205 MLX5_CMD_OP_QUERY_RMP = 0x90f, 206 MLX5_CMD_OP_CREATE_TIS = 0x912, 207 MLX5_CMD_OP_MODIFY_TIS = 0x913, 208 MLX5_CMD_OP_DESTROY_TIS = 0x914, 209 MLX5_CMD_OP_QUERY_TIS = 0x915, 210 MLX5_CMD_OP_CREATE_RQT = 0x916, 211 MLX5_CMD_OP_MODIFY_RQT = 0x917, 212 MLX5_CMD_OP_DESTROY_RQT = 0x918, 213 MLX5_CMD_OP_QUERY_RQT = 0x919, 214 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 215 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 216 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 217 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 218 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 219 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 220 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 221 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 222 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 223 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 224 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 225 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 226 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 227 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 228 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 229 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 230 MLX5_CMD_OP_MAX 231 }; 232 233 struct mlx5_ifc_flow_table_fields_supported_bits { 234 u8 outer_dmac[0x1]; 235 u8 outer_smac[0x1]; 236 u8 outer_ether_type[0x1]; 237 u8 reserved_at_3[0x1]; 238 u8 outer_first_prio[0x1]; 239 u8 outer_first_cfi[0x1]; 240 u8 outer_first_vid[0x1]; 241 u8 reserved_at_7[0x1]; 242 u8 outer_second_prio[0x1]; 243 u8 outer_second_cfi[0x1]; 244 u8 outer_second_vid[0x1]; 245 u8 reserved_at_b[0x1]; 246 u8 outer_sip[0x1]; 247 u8 outer_dip[0x1]; 248 u8 outer_frag[0x1]; 249 u8 outer_ip_protocol[0x1]; 250 u8 outer_ip_ecn[0x1]; 251 u8 outer_ip_dscp[0x1]; 252 u8 outer_udp_sport[0x1]; 253 u8 outer_udp_dport[0x1]; 254 u8 outer_tcp_sport[0x1]; 255 u8 outer_tcp_dport[0x1]; 256 u8 outer_tcp_flags[0x1]; 257 u8 outer_gre_protocol[0x1]; 258 u8 outer_gre_key[0x1]; 259 u8 outer_vxlan_vni[0x1]; 260 u8 reserved_at_1a[0x5]; 261 u8 source_eswitch_port[0x1]; 262 263 u8 inner_dmac[0x1]; 264 u8 inner_smac[0x1]; 265 u8 inner_ether_type[0x1]; 266 u8 reserved_at_23[0x1]; 267 u8 inner_first_prio[0x1]; 268 u8 inner_first_cfi[0x1]; 269 u8 inner_first_vid[0x1]; 270 u8 reserved_at_27[0x1]; 271 u8 inner_second_prio[0x1]; 272 u8 inner_second_cfi[0x1]; 273 u8 inner_second_vid[0x1]; 274 u8 reserved_at_2b[0x1]; 275 u8 inner_sip[0x1]; 276 u8 inner_dip[0x1]; 277 u8 inner_frag[0x1]; 278 u8 inner_ip_protocol[0x1]; 279 u8 inner_ip_ecn[0x1]; 280 u8 inner_ip_dscp[0x1]; 281 u8 inner_udp_sport[0x1]; 282 u8 inner_udp_dport[0x1]; 283 u8 inner_tcp_sport[0x1]; 284 u8 inner_tcp_dport[0x1]; 285 u8 inner_tcp_flags[0x1]; 286 u8 reserved_at_37[0x9]; 287 288 u8 reserved_at_40[0x40]; 289 }; 290 291 struct mlx5_ifc_flow_table_prop_layout_bits { 292 u8 ft_support[0x1]; 293 u8 reserved_at_1[0x1]; 294 u8 flow_counter[0x1]; 295 u8 flow_modify_en[0x1]; 296 u8 modify_root[0x1]; 297 u8 identified_miss_table_mode[0x1]; 298 u8 flow_table_modify[0x1]; 299 u8 encap[0x1]; 300 u8 decap[0x1]; 301 u8 reserved_at_9[0x17]; 302 303 u8 reserved_at_20[0x2]; 304 u8 log_max_ft_size[0x6]; 305 u8 reserved_at_28[0x10]; 306 u8 max_ft_level[0x8]; 307 308 u8 reserved_at_40[0x20]; 309 310 u8 reserved_at_60[0x18]; 311 u8 log_max_ft_num[0x8]; 312 313 u8 reserved_at_80[0x18]; 314 u8 log_max_destination[0x8]; 315 316 u8 reserved_at_a0[0x18]; 317 u8 log_max_flow[0x8]; 318 319 u8 reserved_at_c0[0x40]; 320 321 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 322 323 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 324 }; 325 326 struct mlx5_ifc_odp_per_transport_service_cap_bits { 327 u8 send[0x1]; 328 u8 receive[0x1]; 329 u8 write[0x1]; 330 u8 read[0x1]; 331 u8 atomic[0x1]; 332 u8 srq_receive[0x1]; 333 u8 reserved_at_6[0x1a]; 334 }; 335 336 struct mlx5_ifc_ipv4_layout_bits { 337 u8 reserved_at_0[0x60]; 338 339 u8 ipv4[0x20]; 340 }; 341 342 struct mlx5_ifc_ipv6_layout_bits { 343 u8 ipv6[16][0x8]; 344 }; 345 346 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 347 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 348 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 349 u8 reserved_at_0[0x80]; 350 }; 351 352 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 353 u8 smac_47_16[0x20]; 354 355 u8 smac_15_0[0x10]; 356 u8 ethertype[0x10]; 357 358 u8 dmac_47_16[0x20]; 359 360 u8 dmac_15_0[0x10]; 361 u8 first_prio[0x3]; 362 u8 first_cfi[0x1]; 363 u8 first_vid[0xc]; 364 365 u8 ip_protocol[0x8]; 366 u8 ip_dscp[0x6]; 367 u8 ip_ecn[0x2]; 368 u8 vlan_tag[0x1]; 369 u8 reserved_at_91[0x1]; 370 u8 frag[0x1]; 371 u8 reserved_at_93[0x4]; 372 u8 tcp_flags[0x9]; 373 374 u8 tcp_sport[0x10]; 375 u8 tcp_dport[0x10]; 376 377 u8 reserved_at_c0[0x20]; 378 379 u8 udp_sport[0x10]; 380 u8 udp_dport[0x10]; 381 382 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 383 384 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 385 }; 386 387 struct mlx5_ifc_fte_match_set_misc_bits { 388 u8 reserved_at_0[0x8]; 389 u8 source_sqn[0x18]; 390 391 u8 reserved_at_20[0x10]; 392 u8 source_port[0x10]; 393 394 u8 outer_second_prio[0x3]; 395 u8 outer_second_cfi[0x1]; 396 u8 outer_second_vid[0xc]; 397 u8 inner_second_prio[0x3]; 398 u8 inner_second_cfi[0x1]; 399 u8 inner_second_vid[0xc]; 400 401 u8 outer_second_vlan_tag[0x1]; 402 u8 inner_second_vlan_tag[0x1]; 403 u8 reserved_at_62[0xe]; 404 u8 gre_protocol[0x10]; 405 406 u8 gre_key_h[0x18]; 407 u8 gre_key_l[0x8]; 408 409 u8 vxlan_vni[0x18]; 410 u8 reserved_at_b8[0x8]; 411 412 u8 reserved_at_c0[0x20]; 413 414 u8 reserved_at_e0[0xc]; 415 u8 outer_ipv6_flow_label[0x14]; 416 417 u8 reserved_at_100[0xc]; 418 u8 inner_ipv6_flow_label[0x14]; 419 420 u8 reserved_at_120[0xe0]; 421 }; 422 423 struct mlx5_ifc_cmd_pas_bits { 424 u8 pa_h[0x20]; 425 426 u8 pa_l[0x14]; 427 u8 reserved_at_34[0xc]; 428 }; 429 430 struct mlx5_ifc_uint64_bits { 431 u8 hi[0x20]; 432 433 u8 lo[0x20]; 434 }; 435 436 enum { 437 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 438 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 439 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 440 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 441 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 442 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 443 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 444 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 445 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 446 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 447 }; 448 449 struct mlx5_ifc_ads_bits { 450 u8 fl[0x1]; 451 u8 free_ar[0x1]; 452 u8 reserved_at_2[0xe]; 453 u8 pkey_index[0x10]; 454 455 u8 reserved_at_20[0x8]; 456 u8 grh[0x1]; 457 u8 mlid[0x7]; 458 u8 rlid[0x10]; 459 460 u8 ack_timeout[0x5]; 461 u8 reserved_at_45[0x3]; 462 u8 src_addr_index[0x8]; 463 u8 reserved_at_50[0x4]; 464 u8 stat_rate[0x4]; 465 u8 hop_limit[0x8]; 466 467 u8 reserved_at_60[0x4]; 468 u8 tclass[0x8]; 469 u8 flow_label[0x14]; 470 471 u8 rgid_rip[16][0x8]; 472 473 u8 reserved_at_100[0x4]; 474 u8 f_dscp[0x1]; 475 u8 f_ecn[0x1]; 476 u8 reserved_at_106[0x1]; 477 u8 f_eth_prio[0x1]; 478 u8 ecn[0x2]; 479 u8 dscp[0x6]; 480 u8 udp_sport[0x10]; 481 482 u8 dei_cfi[0x1]; 483 u8 eth_prio[0x3]; 484 u8 sl[0x4]; 485 u8 port[0x8]; 486 u8 rmac_47_32[0x10]; 487 488 u8 rmac_31_0[0x20]; 489 }; 490 491 struct mlx5_ifc_flow_table_nic_cap_bits { 492 u8 nic_rx_multi_path_tirs[0x1]; 493 u8 nic_rx_multi_path_tirs_fts[0x1]; 494 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 495 u8 reserved_at_3[0x1fd]; 496 497 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 498 499 u8 reserved_at_400[0x200]; 500 501 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 502 503 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 504 505 u8 reserved_at_a00[0x200]; 506 507 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 508 509 u8 reserved_at_e00[0x7200]; 510 }; 511 512 struct mlx5_ifc_flow_table_eswitch_cap_bits { 513 u8 reserved_at_0[0x200]; 514 515 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 516 517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 518 519 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 520 521 u8 reserved_at_800[0x7800]; 522 }; 523 524 struct mlx5_ifc_e_switch_cap_bits { 525 u8 vport_svlan_strip[0x1]; 526 u8 vport_cvlan_strip[0x1]; 527 u8 vport_svlan_insert[0x1]; 528 u8 vport_cvlan_insert_if_not_exist[0x1]; 529 u8 vport_cvlan_insert_overwrite[0x1]; 530 u8 reserved_at_5[0x19]; 531 u8 nic_vport_node_guid_modify[0x1]; 532 u8 nic_vport_port_guid_modify[0x1]; 533 534 u8 vxlan_encap_decap[0x1]; 535 u8 nvgre_encap_decap[0x1]; 536 u8 reserved_at_22[0x9]; 537 u8 log_max_encap_headers[0x5]; 538 u8 reserved_2b[0x6]; 539 u8 max_encap_header_size[0xa]; 540 541 u8 reserved_40[0x7c0]; 542 543 }; 544 545 struct mlx5_ifc_qos_cap_bits { 546 u8 packet_pacing[0x1]; 547 u8 esw_scheduling[0x1]; 548 u8 reserved_at_2[0x1e]; 549 550 u8 reserved_at_20[0x20]; 551 552 u8 packet_pacing_max_rate[0x20]; 553 554 u8 packet_pacing_min_rate[0x20]; 555 556 u8 reserved_at_80[0x10]; 557 u8 packet_pacing_rate_table_size[0x10]; 558 559 u8 esw_element_type[0x10]; 560 u8 esw_tsar_type[0x10]; 561 562 u8 reserved_at_c0[0x10]; 563 u8 max_qos_para_vport[0x10]; 564 565 u8 max_tsar_bw_share[0x20]; 566 567 u8 reserved_at_100[0x700]; 568 }; 569 570 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 571 u8 csum_cap[0x1]; 572 u8 vlan_cap[0x1]; 573 u8 lro_cap[0x1]; 574 u8 lro_psh_flag[0x1]; 575 u8 lro_time_stamp[0x1]; 576 u8 reserved_at_5[0x3]; 577 u8 self_lb_en_modifiable[0x1]; 578 u8 reserved_at_9[0x2]; 579 u8 max_lso_cap[0x5]; 580 u8 multi_pkt_send_wqe[0x2]; 581 u8 wqe_inline_mode[0x2]; 582 u8 rss_ind_tbl_cap[0x4]; 583 u8 reg_umr_sq[0x1]; 584 u8 scatter_fcs[0x1]; 585 u8 reserved_at_1a[0x1]; 586 u8 tunnel_lso_const_out_ip_id[0x1]; 587 u8 reserved_at_1c[0x2]; 588 u8 tunnel_statless_gre[0x1]; 589 u8 tunnel_stateless_vxlan[0x1]; 590 591 u8 reserved_at_20[0x20]; 592 593 u8 reserved_at_40[0x10]; 594 u8 lro_min_mss_size[0x10]; 595 596 u8 reserved_at_60[0x120]; 597 598 u8 lro_timer_supported_periods[4][0x20]; 599 600 u8 reserved_at_200[0x600]; 601 }; 602 603 struct mlx5_ifc_roce_cap_bits { 604 u8 roce_apm[0x1]; 605 u8 reserved_at_1[0x1f]; 606 607 u8 reserved_at_20[0x60]; 608 609 u8 reserved_at_80[0xc]; 610 u8 l3_type[0x4]; 611 u8 reserved_at_90[0x8]; 612 u8 roce_version[0x8]; 613 614 u8 reserved_at_a0[0x10]; 615 u8 r_roce_dest_udp_port[0x10]; 616 617 u8 r_roce_max_src_udp_port[0x10]; 618 u8 r_roce_min_src_udp_port[0x10]; 619 620 u8 reserved_at_e0[0x10]; 621 u8 roce_address_table_size[0x10]; 622 623 u8 reserved_at_100[0x700]; 624 }; 625 626 enum { 627 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 628 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 629 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 630 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 631 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 632 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 633 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 634 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 635 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 636 }; 637 638 enum { 639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 640 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 644 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 645 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 646 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 648 }; 649 650 struct mlx5_ifc_atomic_caps_bits { 651 u8 reserved_at_0[0x40]; 652 653 u8 atomic_req_8B_endianess_mode[0x2]; 654 u8 reserved_at_42[0x4]; 655 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 656 657 u8 reserved_at_47[0x19]; 658 659 u8 reserved_at_60[0x20]; 660 661 u8 reserved_at_80[0x10]; 662 u8 atomic_operations[0x10]; 663 664 u8 reserved_at_a0[0x10]; 665 u8 atomic_size_qp[0x10]; 666 667 u8 reserved_at_c0[0x10]; 668 u8 atomic_size_dc[0x10]; 669 670 u8 reserved_at_e0[0x720]; 671 }; 672 673 struct mlx5_ifc_odp_cap_bits { 674 u8 reserved_at_0[0x40]; 675 676 u8 sig[0x1]; 677 u8 reserved_at_41[0x1f]; 678 679 u8 reserved_at_60[0x20]; 680 681 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 682 683 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 684 685 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 686 687 u8 reserved_at_e0[0x720]; 688 }; 689 690 struct mlx5_ifc_calc_op { 691 u8 reserved_at_0[0x10]; 692 u8 reserved_at_10[0x9]; 693 u8 op_swap_endianness[0x1]; 694 u8 op_min[0x1]; 695 u8 op_xor[0x1]; 696 u8 op_or[0x1]; 697 u8 op_and[0x1]; 698 u8 op_max[0x1]; 699 u8 op_add[0x1]; 700 }; 701 702 struct mlx5_ifc_vector_calc_cap_bits { 703 u8 calc_matrix[0x1]; 704 u8 reserved_at_1[0x1f]; 705 u8 reserved_at_20[0x8]; 706 u8 max_vec_count[0x8]; 707 u8 reserved_at_30[0xd]; 708 u8 max_chunk_size[0x3]; 709 struct mlx5_ifc_calc_op calc0; 710 struct mlx5_ifc_calc_op calc1; 711 struct mlx5_ifc_calc_op calc2; 712 struct mlx5_ifc_calc_op calc3; 713 714 u8 reserved_at_e0[0x720]; 715 }; 716 717 enum { 718 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 719 MLX5_WQ_TYPE_CYCLIC = 0x1, 720 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 721 }; 722 723 enum { 724 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 725 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 726 }; 727 728 enum { 729 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 730 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 731 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 732 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 733 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 734 }; 735 736 enum { 737 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 738 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 739 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 740 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 741 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 742 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 743 }; 744 745 enum { 746 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 747 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 748 }; 749 750 enum { 751 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 752 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 753 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 754 }; 755 756 enum { 757 MLX5_CAP_PORT_TYPE_IB = 0x0, 758 MLX5_CAP_PORT_TYPE_ETH = 0x1, 759 }; 760 761 struct mlx5_ifc_cmd_hca_cap_bits { 762 u8 reserved_at_0[0x80]; 763 764 u8 log_max_srq_sz[0x8]; 765 u8 log_max_qp_sz[0x8]; 766 u8 reserved_at_90[0xb]; 767 u8 log_max_qp[0x5]; 768 769 u8 reserved_at_a0[0xb]; 770 u8 log_max_srq[0x5]; 771 u8 reserved_at_b0[0x10]; 772 773 u8 reserved_at_c0[0x8]; 774 u8 log_max_cq_sz[0x8]; 775 u8 reserved_at_d0[0xb]; 776 u8 log_max_cq[0x5]; 777 778 u8 log_max_eq_sz[0x8]; 779 u8 reserved_at_e8[0x2]; 780 u8 log_max_mkey[0x6]; 781 u8 reserved_at_f0[0xc]; 782 u8 log_max_eq[0x4]; 783 784 u8 max_indirection[0x8]; 785 u8 fixed_buffer_size[0x1]; 786 u8 log_max_mrw_sz[0x7]; 787 u8 reserved_at_110[0x2]; 788 u8 log_max_bsf_list_size[0x6]; 789 u8 umr_extended_translation_offset[0x1]; 790 u8 null_mkey[0x1]; 791 u8 log_max_klm_list_size[0x6]; 792 793 u8 reserved_at_120[0xa]; 794 u8 log_max_ra_req_dc[0x6]; 795 u8 reserved_at_130[0xa]; 796 u8 log_max_ra_res_dc[0x6]; 797 798 u8 reserved_at_140[0xa]; 799 u8 log_max_ra_req_qp[0x6]; 800 u8 reserved_at_150[0xa]; 801 u8 log_max_ra_res_qp[0x6]; 802 803 u8 pad_cap[0x1]; 804 u8 cc_query_allowed[0x1]; 805 u8 cc_modify_allowed[0x1]; 806 u8 reserved_at_163[0xd]; 807 u8 gid_table_size[0x10]; 808 809 u8 out_of_seq_cnt[0x1]; 810 u8 vport_counters[0x1]; 811 u8 retransmission_q_counters[0x1]; 812 u8 reserved_at_183[0x1]; 813 u8 modify_rq_counter_set_id[0x1]; 814 u8 reserved_at_185[0x1]; 815 u8 max_qp_cnt[0xa]; 816 u8 pkey_table_size[0x10]; 817 818 u8 vport_group_manager[0x1]; 819 u8 vhca_group_manager[0x1]; 820 u8 ib_virt[0x1]; 821 u8 eth_virt[0x1]; 822 u8 reserved_at_1a4[0x1]; 823 u8 ets[0x1]; 824 u8 nic_flow_table[0x1]; 825 u8 eswitch_flow_table[0x1]; 826 u8 early_vf_enable[0x1]; 827 u8 reserved_at_1a9[0x2]; 828 u8 local_ca_ack_delay[0x5]; 829 u8 port_module_event[0x1]; 830 u8 reserved_at_1b1[0x1]; 831 u8 ports_check[0x1]; 832 u8 reserved_at_1b3[0x1]; 833 u8 disable_link_up[0x1]; 834 u8 beacon_led[0x1]; 835 u8 port_type[0x2]; 836 u8 num_ports[0x8]; 837 838 u8 reserved_at_1c0[0x3]; 839 u8 log_max_msg[0x5]; 840 u8 reserved_at_1c8[0x4]; 841 u8 max_tc[0x4]; 842 u8 reserved_at_1d0[0x1]; 843 u8 dcbx[0x1]; 844 u8 reserved_at_1d2[0x4]; 845 u8 rol_s[0x1]; 846 u8 rol_g[0x1]; 847 u8 reserved_at_1d8[0x1]; 848 u8 wol_s[0x1]; 849 u8 wol_g[0x1]; 850 u8 wol_a[0x1]; 851 u8 wol_b[0x1]; 852 u8 wol_m[0x1]; 853 u8 wol_u[0x1]; 854 u8 wol_p[0x1]; 855 856 u8 stat_rate_support[0x10]; 857 u8 reserved_at_1f0[0xc]; 858 u8 cqe_version[0x4]; 859 860 u8 compact_address_vector[0x1]; 861 u8 striding_rq[0x1]; 862 u8 reserved_at_202[0x2]; 863 u8 ipoib_basic_offloads[0x1]; 864 u8 reserved_at_205[0xa]; 865 u8 drain_sigerr[0x1]; 866 u8 cmdif_checksum[0x2]; 867 u8 sigerr_cqe[0x1]; 868 u8 reserved_at_213[0x1]; 869 u8 wq_signature[0x1]; 870 u8 sctr_data_cqe[0x1]; 871 u8 reserved_at_216[0x1]; 872 u8 sho[0x1]; 873 u8 tph[0x1]; 874 u8 rf[0x1]; 875 u8 dct[0x1]; 876 u8 qos[0x1]; 877 u8 eth_net_offloads[0x1]; 878 u8 roce[0x1]; 879 u8 atomic[0x1]; 880 u8 reserved_at_21f[0x1]; 881 882 u8 cq_oi[0x1]; 883 u8 cq_resize[0x1]; 884 u8 cq_moderation[0x1]; 885 u8 reserved_at_223[0x3]; 886 u8 cq_eq_remap[0x1]; 887 u8 pg[0x1]; 888 u8 block_lb_mc[0x1]; 889 u8 reserved_at_229[0x1]; 890 u8 scqe_break_moderation[0x1]; 891 u8 cq_period_start_from_cqe[0x1]; 892 u8 cd[0x1]; 893 u8 reserved_at_22d[0x1]; 894 u8 apm[0x1]; 895 u8 vector_calc[0x1]; 896 u8 umr_ptr_rlky[0x1]; 897 u8 imaicl[0x1]; 898 u8 reserved_at_232[0x4]; 899 u8 qkv[0x1]; 900 u8 pkv[0x1]; 901 u8 set_deth_sqpn[0x1]; 902 u8 reserved_at_239[0x3]; 903 u8 xrc[0x1]; 904 u8 ud[0x1]; 905 u8 uc[0x1]; 906 u8 rc[0x1]; 907 908 u8 reserved_at_240[0xa]; 909 u8 uar_sz[0x6]; 910 u8 reserved_at_250[0x8]; 911 u8 log_pg_sz[0x8]; 912 913 u8 bf[0x1]; 914 u8 driver_version[0x1]; 915 u8 pad_tx_eth_packet[0x1]; 916 u8 reserved_at_263[0x8]; 917 u8 log_bf_reg_size[0x5]; 918 919 u8 reserved_at_270[0xb]; 920 u8 lag_master[0x1]; 921 u8 num_lag_ports[0x4]; 922 923 u8 reserved_at_280[0x10]; 924 u8 max_wqe_sz_sq[0x10]; 925 926 u8 reserved_at_2a0[0x10]; 927 u8 max_wqe_sz_rq[0x10]; 928 929 u8 reserved_at_2c0[0x10]; 930 u8 max_wqe_sz_sq_dc[0x10]; 931 932 u8 reserved_at_2e0[0x7]; 933 u8 max_qp_mcg[0x19]; 934 935 u8 reserved_at_300[0x18]; 936 u8 log_max_mcg[0x8]; 937 938 u8 reserved_at_320[0x3]; 939 u8 log_max_transport_domain[0x5]; 940 u8 reserved_at_328[0x3]; 941 u8 log_max_pd[0x5]; 942 u8 reserved_at_330[0xb]; 943 u8 log_max_xrcd[0x5]; 944 945 u8 reserved_at_340[0x8]; 946 u8 log_max_flow_counter_bulk[0x8]; 947 u8 max_flow_counter[0x10]; 948 949 950 u8 reserved_at_360[0x3]; 951 u8 log_max_rq[0x5]; 952 u8 reserved_at_368[0x3]; 953 u8 log_max_sq[0x5]; 954 u8 reserved_at_370[0x3]; 955 u8 log_max_tir[0x5]; 956 u8 reserved_at_378[0x3]; 957 u8 log_max_tis[0x5]; 958 959 u8 basic_cyclic_rcv_wqe[0x1]; 960 u8 reserved_at_381[0x2]; 961 u8 log_max_rmp[0x5]; 962 u8 reserved_at_388[0x3]; 963 u8 log_max_rqt[0x5]; 964 u8 reserved_at_390[0x3]; 965 u8 log_max_rqt_size[0x5]; 966 u8 reserved_at_398[0x3]; 967 u8 log_max_tis_per_sq[0x5]; 968 969 u8 reserved_at_3a0[0x3]; 970 u8 log_max_stride_sz_rq[0x5]; 971 u8 reserved_at_3a8[0x3]; 972 u8 log_min_stride_sz_rq[0x5]; 973 u8 reserved_at_3b0[0x3]; 974 u8 log_max_stride_sz_sq[0x5]; 975 u8 reserved_at_3b8[0x3]; 976 u8 log_min_stride_sz_sq[0x5]; 977 978 u8 reserved_at_3c0[0x1b]; 979 u8 log_max_wq_sz[0x5]; 980 981 u8 nic_vport_change_event[0x1]; 982 u8 reserved_at_3e1[0xa]; 983 u8 log_max_vlan_list[0x5]; 984 u8 reserved_at_3f0[0x3]; 985 u8 log_max_current_mc_list[0x5]; 986 u8 reserved_at_3f8[0x3]; 987 u8 log_max_current_uc_list[0x5]; 988 989 u8 reserved_at_400[0x80]; 990 991 u8 reserved_at_480[0x3]; 992 u8 log_max_l2_table[0x5]; 993 u8 reserved_at_488[0x8]; 994 u8 log_uar_page_sz[0x10]; 995 996 u8 reserved_at_4a0[0x20]; 997 u8 device_frequency_mhz[0x20]; 998 u8 device_frequency_khz[0x20]; 999 1000 u8 reserved_at_500[0x80]; 1001 1002 u8 reserved_at_580[0x3f]; 1003 u8 cqe_compression[0x1]; 1004 1005 u8 cqe_compression_timeout[0x10]; 1006 u8 cqe_compression_max_num[0x10]; 1007 1008 u8 reserved_at_5e0[0x10]; 1009 u8 tag_matching[0x1]; 1010 u8 rndv_offload_rc[0x1]; 1011 u8 rndv_offload_dc[0x1]; 1012 u8 log_tag_matching_list_sz[0x5]; 1013 u8 reserved_at_5f8[0x3]; 1014 u8 log_max_xrq[0x5]; 1015 1016 u8 reserved_at_600[0x200]; 1017 }; 1018 1019 enum mlx5_flow_destination_type { 1020 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1021 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1022 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1023 1024 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1025 }; 1026 1027 struct mlx5_ifc_dest_format_struct_bits { 1028 u8 destination_type[0x8]; 1029 u8 destination_id[0x18]; 1030 1031 u8 reserved_at_20[0x20]; 1032 }; 1033 1034 struct mlx5_ifc_flow_counter_list_bits { 1035 u8 clear[0x1]; 1036 u8 num_of_counters[0xf]; 1037 u8 flow_counter_id[0x10]; 1038 1039 u8 reserved_at_20[0x20]; 1040 }; 1041 1042 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1043 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1044 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1045 u8 reserved_at_0[0x40]; 1046 }; 1047 1048 struct mlx5_ifc_fte_match_param_bits { 1049 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1050 1051 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1052 1053 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1054 1055 u8 reserved_at_600[0xa00]; 1056 }; 1057 1058 enum { 1059 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1060 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1061 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1062 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1063 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1064 }; 1065 1066 struct mlx5_ifc_rx_hash_field_select_bits { 1067 u8 l3_prot_type[0x1]; 1068 u8 l4_prot_type[0x1]; 1069 u8 selected_fields[0x1e]; 1070 }; 1071 1072 enum { 1073 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1074 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1075 }; 1076 1077 enum { 1078 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1079 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1080 }; 1081 1082 struct mlx5_ifc_wq_bits { 1083 u8 wq_type[0x4]; 1084 u8 wq_signature[0x1]; 1085 u8 end_padding_mode[0x2]; 1086 u8 cd_slave[0x1]; 1087 u8 reserved_at_8[0x18]; 1088 1089 u8 hds_skip_first_sge[0x1]; 1090 u8 log2_hds_buf_size[0x3]; 1091 u8 reserved_at_24[0x7]; 1092 u8 page_offset[0x5]; 1093 u8 lwm[0x10]; 1094 1095 u8 reserved_at_40[0x8]; 1096 u8 pd[0x18]; 1097 1098 u8 reserved_at_60[0x8]; 1099 u8 uar_page[0x18]; 1100 1101 u8 dbr_addr[0x40]; 1102 1103 u8 hw_counter[0x20]; 1104 1105 u8 sw_counter[0x20]; 1106 1107 u8 reserved_at_100[0xc]; 1108 u8 log_wq_stride[0x4]; 1109 u8 reserved_at_110[0x3]; 1110 u8 log_wq_pg_sz[0x5]; 1111 u8 reserved_at_118[0x3]; 1112 u8 log_wq_sz[0x5]; 1113 1114 u8 reserved_at_120[0x15]; 1115 u8 log_wqe_num_of_strides[0x3]; 1116 u8 two_byte_shift_en[0x1]; 1117 u8 reserved_at_139[0x4]; 1118 u8 log_wqe_stride_size[0x3]; 1119 1120 u8 reserved_at_140[0x4c0]; 1121 1122 struct mlx5_ifc_cmd_pas_bits pas[0]; 1123 }; 1124 1125 struct mlx5_ifc_rq_num_bits { 1126 u8 reserved_at_0[0x8]; 1127 u8 rq_num[0x18]; 1128 }; 1129 1130 struct mlx5_ifc_mac_address_layout_bits { 1131 u8 reserved_at_0[0x10]; 1132 u8 mac_addr_47_32[0x10]; 1133 1134 u8 mac_addr_31_0[0x20]; 1135 }; 1136 1137 struct mlx5_ifc_vlan_layout_bits { 1138 u8 reserved_at_0[0x14]; 1139 u8 vlan[0x0c]; 1140 1141 u8 reserved_at_20[0x20]; 1142 }; 1143 1144 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1145 u8 reserved_at_0[0xa0]; 1146 1147 u8 min_time_between_cnps[0x20]; 1148 1149 u8 reserved_at_c0[0x12]; 1150 u8 cnp_dscp[0x6]; 1151 u8 reserved_at_d8[0x5]; 1152 u8 cnp_802p_prio[0x3]; 1153 1154 u8 reserved_at_e0[0x720]; 1155 }; 1156 1157 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1158 u8 reserved_at_0[0x60]; 1159 1160 u8 reserved_at_60[0x4]; 1161 u8 clamp_tgt_rate[0x1]; 1162 u8 reserved_at_65[0x3]; 1163 u8 clamp_tgt_rate_after_time_inc[0x1]; 1164 u8 reserved_at_69[0x17]; 1165 1166 u8 reserved_at_80[0x20]; 1167 1168 u8 rpg_time_reset[0x20]; 1169 1170 u8 rpg_byte_reset[0x20]; 1171 1172 u8 rpg_threshold[0x20]; 1173 1174 u8 rpg_max_rate[0x20]; 1175 1176 u8 rpg_ai_rate[0x20]; 1177 1178 u8 rpg_hai_rate[0x20]; 1179 1180 u8 rpg_gd[0x20]; 1181 1182 u8 rpg_min_dec_fac[0x20]; 1183 1184 u8 rpg_min_rate[0x20]; 1185 1186 u8 reserved_at_1c0[0xe0]; 1187 1188 u8 rate_to_set_on_first_cnp[0x20]; 1189 1190 u8 dce_tcp_g[0x20]; 1191 1192 u8 dce_tcp_rtt[0x20]; 1193 1194 u8 rate_reduce_monitor_period[0x20]; 1195 1196 u8 reserved_at_320[0x20]; 1197 1198 u8 initial_alpha_value[0x20]; 1199 1200 u8 reserved_at_360[0x4a0]; 1201 }; 1202 1203 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1204 u8 reserved_at_0[0x80]; 1205 1206 u8 rppp_max_rps[0x20]; 1207 1208 u8 rpg_time_reset[0x20]; 1209 1210 u8 rpg_byte_reset[0x20]; 1211 1212 u8 rpg_threshold[0x20]; 1213 1214 u8 rpg_max_rate[0x20]; 1215 1216 u8 rpg_ai_rate[0x20]; 1217 1218 u8 rpg_hai_rate[0x20]; 1219 1220 u8 rpg_gd[0x20]; 1221 1222 u8 rpg_min_dec_fac[0x20]; 1223 1224 u8 rpg_min_rate[0x20]; 1225 1226 u8 reserved_at_1c0[0x640]; 1227 }; 1228 1229 enum { 1230 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1231 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1232 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1233 }; 1234 1235 struct mlx5_ifc_resize_field_select_bits { 1236 u8 resize_field_select[0x20]; 1237 }; 1238 1239 enum { 1240 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1241 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1242 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1243 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1244 }; 1245 1246 struct mlx5_ifc_modify_field_select_bits { 1247 u8 modify_field_select[0x20]; 1248 }; 1249 1250 struct mlx5_ifc_field_select_r_roce_np_bits { 1251 u8 field_select_r_roce_np[0x20]; 1252 }; 1253 1254 struct mlx5_ifc_field_select_r_roce_rp_bits { 1255 u8 field_select_r_roce_rp[0x20]; 1256 }; 1257 1258 enum { 1259 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1260 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1261 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1262 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1263 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1264 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1265 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1266 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1267 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1268 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1269 }; 1270 1271 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1272 u8 field_select_8021qaurp[0x20]; 1273 }; 1274 1275 struct mlx5_ifc_phys_layer_cntrs_bits { 1276 u8 time_since_last_clear_high[0x20]; 1277 1278 u8 time_since_last_clear_low[0x20]; 1279 1280 u8 symbol_errors_high[0x20]; 1281 1282 u8 symbol_errors_low[0x20]; 1283 1284 u8 sync_headers_errors_high[0x20]; 1285 1286 u8 sync_headers_errors_low[0x20]; 1287 1288 u8 edpl_bip_errors_lane0_high[0x20]; 1289 1290 u8 edpl_bip_errors_lane0_low[0x20]; 1291 1292 u8 edpl_bip_errors_lane1_high[0x20]; 1293 1294 u8 edpl_bip_errors_lane1_low[0x20]; 1295 1296 u8 edpl_bip_errors_lane2_high[0x20]; 1297 1298 u8 edpl_bip_errors_lane2_low[0x20]; 1299 1300 u8 edpl_bip_errors_lane3_high[0x20]; 1301 1302 u8 edpl_bip_errors_lane3_low[0x20]; 1303 1304 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1305 1306 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1307 1308 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1309 1310 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1311 1312 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1313 1314 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1315 1316 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1317 1318 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1319 1320 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1321 1322 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1323 1324 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1325 1326 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1327 1328 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1329 1330 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1331 1332 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1333 1334 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1335 1336 u8 rs_fec_corrected_blocks_high[0x20]; 1337 1338 u8 rs_fec_corrected_blocks_low[0x20]; 1339 1340 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1341 1342 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1343 1344 u8 rs_fec_no_errors_blocks_high[0x20]; 1345 1346 u8 rs_fec_no_errors_blocks_low[0x20]; 1347 1348 u8 rs_fec_single_error_blocks_high[0x20]; 1349 1350 u8 rs_fec_single_error_blocks_low[0x20]; 1351 1352 u8 rs_fec_corrected_symbols_total_high[0x20]; 1353 1354 u8 rs_fec_corrected_symbols_total_low[0x20]; 1355 1356 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1357 1358 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1359 1360 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1361 1362 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1363 1364 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1365 1366 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1367 1368 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1369 1370 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1371 1372 u8 link_down_events[0x20]; 1373 1374 u8 successful_recovery_events[0x20]; 1375 1376 u8 reserved_at_640[0x180]; 1377 }; 1378 1379 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1380 u8 symbol_error_counter[0x10]; 1381 1382 u8 link_error_recovery_counter[0x8]; 1383 1384 u8 link_downed_counter[0x8]; 1385 1386 u8 port_rcv_errors[0x10]; 1387 1388 u8 port_rcv_remote_physical_errors[0x10]; 1389 1390 u8 port_rcv_switch_relay_errors[0x10]; 1391 1392 u8 port_xmit_discards[0x10]; 1393 1394 u8 port_xmit_constraint_errors[0x8]; 1395 1396 u8 port_rcv_constraint_errors[0x8]; 1397 1398 u8 reserved_at_70[0x8]; 1399 1400 u8 link_overrun_errors[0x8]; 1401 1402 u8 reserved_at_80[0x10]; 1403 1404 u8 vl_15_dropped[0x10]; 1405 1406 u8 reserved_at_a0[0xa0]; 1407 }; 1408 1409 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1410 u8 transmit_queue_high[0x20]; 1411 1412 u8 transmit_queue_low[0x20]; 1413 1414 u8 reserved_at_40[0x780]; 1415 }; 1416 1417 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1418 u8 rx_octets_high[0x20]; 1419 1420 u8 rx_octets_low[0x20]; 1421 1422 u8 reserved_at_40[0xc0]; 1423 1424 u8 rx_frames_high[0x20]; 1425 1426 u8 rx_frames_low[0x20]; 1427 1428 u8 tx_octets_high[0x20]; 1429 1430 u8 tx_octets_low[0x20]; 1431 1432 u8 reserved_at_180[0xc0]; 1433 1434 u8 tx_frames_high[0x20]; 1435 1436 u8 tx_frames_low[0x20]; 1437 1438 u8 rx_pause_high[0x20]; 1439 1440 u8 rx_pause_low[0x20]; 1441 1442 u8 rx_pause_duration_high[0x20]; 1443 1444 u8 rx_pause_duration_low[0x20]; 1445 1446 u8 tx_pause_high[0x20]; 1447 1448 u8 tx_pause_low[0x20]; 1449 1450 u8 tx_pause_duration_high[0x20]; 1451 1452 u8 tx_pause_duration_low[0x20]; 1453 1454 u8 rx_pause_transition_high[0x20]; 1455 1456 u8 rx_pause_transition_low[0x20]; 1457 1458 u8 reserved_at_3c0[0x400]; 1459 }; 1460 1461 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1462 u8 port_transmit_wait_high[0x20]; 1463 1464 u8 port_transmit_wait_low[0x20]; 1465 1466 u8 reserved_at_40[0x780]; 1467 }; 1468 1469 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1470 u8 dot3stats_alignment_errors_high[0x20]; 1471 1472 u8 dot3stats_alignment_errors_low[0x20]; 1473 1474 u8 dot3stats_fcs_errors_high[0x20]; 1475 1476 u8 dot3stats_fcs_errors_low[0x20]; 1477 1478 u8 dot3stats_single_collision_frames_high[0x20]; 1479 1480 u8 dot3stats_single_collision_frames_low[0x20]; 1481 1482 u8 dot3stats_multiple_collision_frames_high[0x20]; 1483 1484 u8 dot3stats_multiple_collision_frames_low[0x20]; 1485 1486 u8 dot3stats_sqe_test_errors_high[0x20]; 1487 1488 u8 dot3stats_sqe_test_errors_low[0x20]; 1489 1490 u8 dot3stats_deferred_transmissions_high[0x20]; 1491 1492 u8 dot3stats_deferred_transmissions_low[0x20]; 1493 1494 u8 dot3stats_late_collisions_high[0x20]; 1495 1496 u8 dot3stats_late_collisions_low[0x20]; 1497 1498 u8 dot3stats_excessive_collisions_high[0x20]; 1499 1500 u8 dot3stats_excessive_collisions_low[0x20]; 1501 1502 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1503 1504 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1505 1506 u8 dot3stats_carrier_sense_errors_high[0x20]; 1507 1508 u8 dot3stats_carrier_sense_errors_low[0x20]; 1509 1510 u8 dot3stats_frame_too_longs_high[0x20]; 1511 1512 u8 dot3stats_frame_too_longs_low[0x20]; 1513 1514 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1515 1516 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1517 1518 u8 dot3stats_symbol_errors_high[0x20]; 1519 1520 u8 dot3stats_symbol_errors_low[0x20]; 1521 1522 u8 dot3control_in_unknown_opcodes_high[0x20]; 1523 1524 u8 dot3control_in_unknown_opcodes_low[0x20]; 1525 1526 u8 dot3in_pause_frames_high[0x20]; 1527 1528 u8 dot3in_pause_frames_low[0x20]; 1529 1530 u8 dot3out_pause_frames_high[0x20]; 1531 1532 u8 dot3out_pause_frames_low[0x20]; 1533 1534 u8 reserved_at_400[0x3c0]; 1535 }; 1536 1537 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1538 u8 ether_stats_drop_events_high[0x20]; 1539 1540 u8 ether_stats_drop_events_low[0x20]; 1541 1542 u8 ether_stats_octets_high[0x20]; 1543 1544 u8 ether_stats_octets_low[0x20]; 1545 1546 u8 ether_stats_pkts_high[0x20]; 1547 1548 u8 ether_stats_pkts_low[0x20]; 1549 1550 u8 ether_stats_broadcast_pkts_high[0x20]; 1551 1552 u8 ether_stats_broadcast_pkts_low[0x20]; 1553 1554 u8 ether_stats_multicast_pkts_high[0x20]; 1555 1556 u8 ether_stats_multicast_pkts_low[0x20]; 1557 1558 u8 ether_stats_crc_align_errors_high[0x20]; 1559 1560 u8 ether_stats_crc_align_errors_low[0x20]; 1561 1562 u8 ether_stats_undersize_pkts_high[0x20]; 1563 1564 u8 ether_stats_undersize_pkts_low[0x20]; 1565 1566 u8 ether_stats_oversize_pkts_high[0x20]; 1567 1568 u8 ether_stats_oversize_pkts_low[0x20]; 1569 1570 u8 ether_stats_fragments_high[0x20]; 1571 1572 u8 ether_stats_fragments_low[0x20]; 1573 1574 u8 ether_stats_jabbers_high[0x20]; 1575 1576 u8 ether_stats_jabbers_low[0x20]; 1577 1578 u8 ether_stats_collisions_high[0x20]; 1579 1580 u8 ether_stats_collisions_low[0x20]; 1581 1582 u8 ether_stats_pkts64octets_high[0x20]; 1583 1584 u8 ether_stats_pkts64octets_low[0x20]; 1585 1586 u8 ether_stats_pkts65to127octets_high[0x20]; 1587 1588 u8 ether_stats_pkts65to127octets_low[0x20]; 1589 1590 u8 ether_stats_pkts128to255octets_high[0x20]; 1591 1592 u8 ether_stats_pkts128to255octets_low[0x20]; 1593 1594 u8 ether_stats_pkts256to511octets_high[0x20]; 1595 1596 u8 ether_stats_pkts256to511octets_low[0x20]; 1597 1598 u8 ether_stats_pkts512to1023octets_high[0x20]; 1599 1600 u8 ether_stats_pkts512to1023octets_low[0x20]; 1601 1602 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1603 1604 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1605 1606 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1607 1608 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1609 1610 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1611 1612 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1613 1614 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1615 1616 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1617 1618 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1619 1620 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1621 1622 u8 reserved_at_540[0x280]; 1623 }; 1624 1625 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1626 u8 if_in_octets_high[0x20]; 1627 1628 u8 if_in_octets_low[0x20]; 1629 1630 u8 if_in_ucast_pkts_high[0x20]; 1631 1632 u8 if_in_ucast_pkts_low[0x20]; 1633 1634 u8 if_in_discards_high[0x20]; 1635 1636 u8 if_in_discards_low[0x20]; 1637 1638 u8 if_in_errors_high[0x20]; 1639 1640 u8 if_in_errors_low[0x20]; 1641 1642 u8 if_in_unknown_protos_high[0x20]; 1643 1644 u8 if_in_unknown_protos_low[0x20]; 1645 1646 u8 if_out_octets_high[0x20]; 1647 1648 u8 if_out_octets_low[0x20]; 1649 1650 u8 if_out_ucast_pkts_high[0x20]; 1651 1652 u8 if_out_ucast_pkts_low[0x20]; 1653 1654 u8 if_out_discards_high[0x20]; 1655 1656 u8 if_out_discards_low[0x20]; 1657 1658 u8 if_out_errors_high[0x20]; 1659 1660 u8 if_out_errors_low[0x20]; 1661 1662 u8 if_in_multicast_pkts_high[0x20]; 1663 1664 u8 if_in_multicast_pkts_low[0x20]; 1665 1666 u8 if_in_broadcast_pkts_high[0x20]; 1667 1668 u8 if_in_broadcast_pkts_low[0x20]; 1669 1670 u8 if_out_multicast_pkts_high[0x20]; 1671 1672 u8 if_out_multicast_pkts_low[0x20]; 1673 1674 u8 if_out_broadcast_pkts_high[0x20]; 1675 1676 u8 if_out_broadcast_pkts_low[0x20]; 1677 1678 u8 reserved_at_340[0x480]; 1679 }; 1680 1681 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1682 u8 a_frames_transmitted_ok_high[0x20]; 1683 1684 u8 a_frames_transmitted_ok_low[0x20]; 1685 1686 u8 a_frames_received_ok_high[0x20]; 1687 1688 u8 a_frames_received_ok_low[0x20]; 1689 1690 u8 a_frame_check_sequence_errors_high[0x20]; 1691 1692 u8 a_frame_check_sequence_errors_low[0x20]; 1693 1694 u8 a_alignment_errors_high[0x20]; 1695 1696 u8 a_alignment_errors_low[0x20]; 1697 1698 u8 a_octets_transmitted_ok_high[0x20]; 1699 1700 u8 a_octets_transmitted_ok_low[0x20]; 1701 1702 u8 a_octets_received_ok_high[0x20]; 1703 1704 u8 a_octets_received_ok_low[0x20]; 1705 1706 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1707 1708 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1709 1710 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1711 1712 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1713 1714 u8 a_multicast_frames_received_ok_high[0x20]; 1715 1716 u8 a_multicast_frames_received_ok_low[0x20]; 1717 1718 u8 a_broadcast_frames_received_ok_high[0x20]; 1719 1720 u8 a_broadcast_frames_received_ok_low[0x20]; 1721 1722 u8 a_in_range_length_errors_high[0x20]; 1723 1724 u8 a_in_range_length_errors_low[0x20]; 1725 1726 u8 a_out_of_range_length_field_high[0x20]; 1727 1728 u8 a_out_of_range_length_field_low[0x20]; 1729 1730 u8 a_frame_too_long_errors_high[0x20]; 1731 1732 u8 a_frame_too_long_errors_low[0x20]; 1733 1734 u8 a_symbol_error_during_carrier_high[0x20]; 1735 1736 u8 a_symbol_error_during_carrier_low[0x20]; 1737 1738 u8 a_mac_control_frames_transmitted_high[0x20]; 1739 1740 u8 a_mac_control_frames_transmitted_low[0x20]; 1741 1742 u8 a_mac_control_frames_received_high[0x20]; 1743 1744 u8 a_mac_control_frames_received_low[0x20]; 1745 1746 u8 a_unsupported_opcodes_received_high[0x20]; 1747 1748 u8 a_unsupported_opcodes_received_low[0x20]; 1749 1750 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1751 1752 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1753 1754 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1755 1756 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1757 1758 u8 reserved_at_4c0[0x300]; 1759 }; 1760 1761 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 1762 u8 life_time_counter_high[0x20]; 1763 1764 u8 life_time_counter_low[0x20]; 1765 1766 u8 rx_errors[0x20]; 1767 1768 u8 tx_errors[0x20]; 1769 1770 u8 l0_to_recovery_eieos[0x20]; 1771 1772 u8 l0_to_recovery_ts[0x20]; 1773 1774 u8 l0_to_recovery_framing[0x20]; 1775 1776 u8 l0_to_recovery_retrain[0x20]; 1777 1778 u8 crc_error_dllp[0x20]; 1779 1780 u8 crc_error_tlp[0x20]; 1781 1782 u8 reserved_at_140[0x680]; 1783 }; 1784 1785 struct mlx5_ifc_pcie_tas_cntrs_grp_data_layout_bits { 1786 u8 life_time_counter_high[0x20]; 1787 1788 u8 life_time_counter_low[0x20]; 1789 1790 u8 time_to_boot_image_start[0x20]; 1791 1792 u8 time_to_link_image[0x20]; 1793 1794 u8 calibration_time[0x20]; 1795 1796 u8 time_to_first_perst[0x20]; 1797 1798 u8 time_to_detect_state[0x20]; 1799 1800 u8 time_to_l0[0x20]; 1801 1802 u8 time_to_crs_en[0x20]; 1803 1804 u8 time_to_plastic_image_start[0x20]; 1805 1806 u8 time_to_iron_image_start[0x20]; 1807 1808 u8 perst_handler[0x20]; 1809 1810 u8 times_in_l1[0x20]; 1811 1812 u8 times_in_l23[0x20]; 1813 1814 u8 dl_down[0x20]; 1815 1816 u8 config_cycle1usec[0x20]; 1817 1818 u8 config_cycle2to7usec[0x20]; 1819 1820 u8 config_cycle_8to15usec[0x20]; 1821 1822 u8 config_cycle_16_to_63usec[0x20]; 1823 1824 u8 config_cycle_64usec[0x20]; 1825 1826 u8 correctable_err_msg_sent[0x20]; 1827 1828 u8 non_fatal_err_msg_sent[0x20]; 1829 1830 u8 fatal_err_msg_sent[0x20]; 1831 1832 u8 reserved_at_2e0[0x4e0]; 1833 }; 1834 1835 struct mlx5_ifc_cmd_inter_comp_event_bits { 1836 u8 command_completion_vector[0x20]; 1837 1838 u8 reserved_at_20[0xc0]; 1839 }; 1840 1841 struct mlx5_ifc_stall_vl_event_bits { 1842 u8 reserved_at_0[0x18]; 1843 u8 port_num[0x1]; 1844 u8 reserved_at_19[0x3]; 1845 u8 vl[0x4]; 1846 1847 u8 reserved_at_20[0xa0]; 1848 }; 1849 1850 struct mlx5_ifc_db_bf_congestion_event_bits { 1851 u8 event_subtype[0x8]; 1852 u8 reserved_at_8[0x8]; 1853 u8 congestion_level[0x8]; 1854 u8 reserved_at_18[0x8]; 1855 1856 u8 reserved_at_20[0xa0]; 1857 }; 1858 1859 struct mlx5_ifc_gpio_event_bits { 1860 u8 reserved_at_0[0x60]; 1861 1862 u8 gpio_event_hi[0x20]; 1863 1864 u8 gpio_event_lo[0x20]; 1865 1866 u8 reserved_at_a0[0x40]; 1867 }; 1868 1869 struct mlx5_ifc_port_state_change_event_bits { 1870 u8 reserved_at_0[0x40]; 1871 1872 u8 port_num[0x4]; 1873 u8 reserved_at_44[0x1c]; 1874 1875 u8 reserved_at_60[0x80]; 1876 }; 1877 1878 struct mlx5_ifc_dropped_packet_logged_bits { 1879 u8 reserved_at_0[0xe0]; 1880 }; 1881 1882 enum { 1883 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1884 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1885 }; 1886 1887 struct mlx5_ifc_cq_error_bits { 1888 u8 reserved_at_0[0x8]; 1889 u8 cqn[0x18]; 1890 1891 u8 reserved_at_20[0x20]; 1892 1893 u8 reserved_at_40[0x18]; 1894 u8 syndrome[0x8]; 1895 1896 u8 reserved_at_60[0x80]; 1897 }; 1898 1899 struct mlx5_ifc_rdma_page_fault_event_bits { 1900 u8 bytes_committed[0x20]; 1901 1902 u8 r_key[0x20]; 1903 1904 u8 reserved_at_40[0x10]; 1905 u8 packet_len[0x10]; 1906 1907 u8 rdma_op_len[0x20]; 1908 1909 u8 rdma_va[0x40]; 1910 1911 u8 reserved_at_c0[0x5]; 1912 u8 rdma[0x1]; 1913 u8 write[0x1]; 1914 u8 requestor[0x1]; 1915 u8 qp_number[0x18]; 1916 }; 1917 1918 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1919 u8 bytes_committed[0x20]; 1920 1921 u8 reserved_at_20[0x10]; 1922 u8 wqe_index[0x10]; 1923 1924 u8 reserved_at_40[0x10]; 1925 u8 len[0x10]; 1926 1927 u8 reserved_at_60[0x60]; 1928 1929 u8 reserved_at_c0[0x5]; 1930 u8 rdma[0x1]; 1931 u8 write_read[0x1]; 1932 u8 requestor[0x1]; 1933 u8 qpn[0x18]; 1934 }; 1935 1936 struct mlx5_ifc_qp_events_bits { 1937 u8 reserved_at_0[0xa0]; 1938 1939 u8 type[0x8]; 1940 u8 reserved_at_a8[0x18]; 1941 1942 u8 reserved_at_c0[0x8]; 1943 u8 qpn_rqn_sqn[0x18]; 1944 }; 1945 1946 struct mlx5_ifc_dct_events_bits { 1947 u8 reserved_at_0[0xc0]; 1948 1949 u8 reserved_at_c0[0x8]; 1950 u8 dct_number[0x18]; 1951 }; 1952 1953 struct mlx5_ifc_comp_event_bits { 1954 u8 reserved_at_0[0xc0]; 1955 1956 u8 reserved_at_c0[0x8]; 1957 u8 cq_number[0x18]; 1958 }; 1959 1960 enum { 1961 MLX5_QPC_STATE_RST = 0x0, 1962 MLX5_QPC_STATE_INIT = 0x1, 1963 MLX5_QPC_STATE_RTR = 0x2, 1964 MLX5_QPC_STATE_RTS = 0x3, 1965 MLX5_QPC_STATE_SQER = 0x4, 1966 MLX5_QPC_STATE_ERR = 0x6, 1967 MLX5_QPC_STATE_SQD = 0x7, 1968 MLX5_QPC_STATE_SUSPENDED = 0x9, 1969 }; 1970 1971 enum { 1972 MLX5_QPC_ST_RC = 0x0, 1973 MLX5_QPC_ST_UC = 0x1, 1974 MLX5_QPC_ST_UD = 0x2, 1975 MLX5_QPC_ST_XRC = 0x3, 1976 MLX5_QPC_ST_DCI = 0x5, 1977 MLX5_QPC_ST_QP0 = 0x7, 1978 MLX5_QPC_ST_QP1 = 0x8, 1979 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1980 MLX5_QPC_ST_REG_UMR = 0xc, 1981 }; 1982 1983 enum { 1984 MLX5_QPC_PM_STATE_ARMED = 0x0, 1985 MLX5_QPC_PM_STATE_REARM = 0x1, 1986 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1987 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 1988 }; 1989 1990 enum { 1991 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1992 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1993 }; 1994 1995 enum { 1996 MLX5_QPC_MTU_256_BYTES = 0x1, 1997 MLX5_QPC_MTU_512_BYTES = 0x2, 1998 MLX5_QPC_MTU_1K_BYTES = 0x3, 1999 MLX5_QPC_MTU_2K_BYTES = 0x4, 2000 MLX5_QPC_MTU_4K_BYTES = 0x5, 2001 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2002 }; 2003 2004 enum { 2005 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2006 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2007 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2008 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2009 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2010 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2011 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2012 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2013 }; 2014 2015 enum { 2016 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2017 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2018 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2019 }; 2020 2021 enum { 2022 MLX5_QPC_CS_RES_DISABLE = 0x0, 2023 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2024 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2025 }; 2026 2027 struct mlx5_ifc_qpc_bits { 2028 u8 state[0x4]; 2029 u8 lag_tx_port_affinity[0x4]; 2030 u8 st[0x8]; 2031 u8 reserved_at_10[0x3]; 2032 u8 pm_state[0x2]; 2033 u8 reserved_at_15[0x7]; 2034 u8 end_padding_mode[0x2]; 2035 u8 reserved_at_1e[0x2]; 2036 2037 u8 wq_signature[0x1]; 2038 u8 block_lb_mc[0x1]; 2039 u8 atomic_like_write_en[0x1]; 2040 u8 latency_sensitive[0x1]; 2041 u8 reserved_at_24[0x1]; 2042 u8 drain_sigerr[0x1]; 2043 u8 reserved_at_26[0x2]; 2044 u8 pd[0x18]; 2045 2046 u8 mtu[0x3]; 2047 u8 log_msg_max[0x5]; 2048 u8 reserved_at_48[0x1]; 2049 u8 log_rq_size[0x4]; 2050 u8 log_rq_stride[0x3]; 2051 u8 no_sq[0x1]; 2052 u8 log_sq_size[0x4]; 2053 u8 reserved_at_55[0x6]; 2054 u8 rlky[0x1]; 2055 u8 ulp_stateless_offload_mode[0x4]; 2056 2057 u8 counter_set_id[0x8]; 2058 u8 uar_page[0x18]; 2059 2060 u8 reserved_at_80[0x8]; 2061 u8 user_index[0x18]; 2062 2063 u8 reserved_at_a0[0x3]; 2064 u8 log_page_size[0x5]; 2065 u8 remote_qpn[0x18]; 2066 2067 struct mlx5_ifc_ads_bits primary_address_path; 2068 2069 struct mlx5_ifc_ads_bits secondary_address_path; 2070 2071 u8 log_ack_req_freq[0x4]; 2072 u8 reserved_at_384[0x4]; 2073 u8 log_sra_max[0x3]; 2074 u8 reserved_at_38b[0x2]; 2075 u8 retry_count[0x3]; 2076 u8 rnr_retry[0x3]; 2077 u8 reserved_at_393[0x1]; 2078 u8 fre[0x1]; 2079 u8 cur_rnr_retry[0x3]; 2080 u8 cur_retry_count[0x3]; 2081 u8 reserved_at_39b[0x5]; 2082 2083 u8 reserved_at_3a0[0x20]; 2084 2085 u8 reserved_at_3c0[0x8]; 2086 u8 next_send_psn[0x18]; 2087 2088 u8 reserved_at_3e0[0x8]; 2089 u8 cqn_snd[0x18]; 2090 2091 u8 reserved_at_400[0x8]; 2092 u8 deth_sqpn[0x18]; 2093 2094 u8 reserved_at_420[0x20]; 2095 2096 u8 reserved_at_440[0x8]; 2097 u8 last_acked_psn[0x18]; 2098 2099 u8 reserved_at_460[0x8]; 2100 u8 ssn[0x18]; 2101 2102 u8 reserved_at_480[0x8]; 2103 u8 log_rra_max[0x3]; 2104 u8 reserved_at_48b[0x1]; 2105 u8 atomic_mode[0x4]; 2106 u8 rre[0x1]; 2107 u8 rwe[0x1]; 2108 u8 rae[0x1]; 2109 u8 reserved_at_493[0x1]; 2110 u8 page_offset[0x6]; 2111 u8 reserved_at_49a[0x3]; 2112 u8 cd_slave_receive[0x1]; 2113 u8 cd_slave_send[0x1]; 2114 u8 cd_master[0x1]; 2115 2116 u8 reserved_at_4a0[0x3]; 2117 u8 min_rnr_nak[0x5]; 2118 u8 next_rcv_psn[0x18]; 2119 2120 u8 reserved_at_4c0[0x8]; 2121 u8 xrcd[0x18]; 2122 2123 u8 reserved_at_4e0[0x8]; 2124 u8 cqn_rcv[0x18]; 2125 2126 u8 dbr_addr[0x40]; 2127 2128 u8 q_key[0x20]; 2129 2130 u8 reserved_at_560[0x5]; 2131 u8 rq_type[0x3]; 2132 u8 srqn_rmpn_xrqn[0x18]; 2133 2134 u8 reserved_at_580[0x8]; 2135 u8 rmsn[0x18]; 2136 2137 u8 hw_sq_wqebb_counter[0x10]; 2138 u8 sw_sq_wqebb_counter[0x10]; 2139 2140 u8 hw_rq_counter[0x20]; 2141 2142 u8 sw_rq_counter[0x20]; 2143 2144 u8 reserved_at_600[0x20]; 2145 2146 u8 reserved_at_620[0xf]; 2147 u8 cgs[0x1]; 2148 u8 cs_req[0x8]; 2149 u8 cs_res[0x8]; 2150 2151 u8 dc_access_key[0x40]; 2152 2153 u8 reserved_at_680[0xc0]; 2154 }; 2155 2156 struct mlx5_ifc_roce_addr_layout_bits { 2157 u8 source_l3_address[16][0x8]; 2158 2159 u8 reserved_at_80[0x3]; 2160 u8 vlan_valid[0x1]; 2161 u8 vlan_id[0xc]; 2162 u8 source_mac_47_32[0x10]; 2163 2164 u8 source_mac_31_0[0x20]; 2165 2166 u8 reserved_at_c0[0x14]; 2167 u8 roce_l3_type[0x4]; 2168 u8 roce_version[0x8]; 2169 2170 u8 reserved_at_e0[0x20]; 2171 }; 2172 2173 union mlx5_ifc_hca_cap_union_bits { 2174 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2175 struct mlx5_ifc_odp_cap_bits odp_cap; 2176 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2177 struct mlx5_ifc_roce_cap_bits roce_cap; 2178 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2179 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2180 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2181 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2182 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2183 struct mlx5_ifc_qos_cap_bits qos_cap; 2184 u8 reserved_at_0[0x8000]; 2185 }; 2186 2187 enum { 2188 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2189 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2190 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2191 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2192 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10, 2193 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2194 }; 2195 2196 struct mlx5_ifc_flow_context_bits { 2197 u8 reserved_at_0[0x20]; 2198 2199 u8 group_id[0x20]; 2200 2201 u8 reserved_at_40[0x8]; 2202 u8 flow_tag[0x18]; 2203 2204 u8 reserved_at_60[0x10]; 2205 u8 action[0x10]; 2206 2207 u8 reserved_at_80[0x8]; 2208 u8 destination_list_size[0x18]; 2209 2210 u8 reserved_at_a0[0x8]; 2211 u8 flow_counter_list_size[0x18]; 2212 2213 u8 encap_id[0x20]; 2214 2215 u8 reserved_at_e0[0x120]; 2216 2217 struct mlx5_ifc_fte_match_param_bits match_value; 2218 2219 u8 reserved_at_1200[0x600]; 2220 2221 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2222 }; 2223 2224 enum { 2225 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2226 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2227 }; 2228 2229 struct mlx5_ifc_xrc_srqc_bits { 2230 u8 state[0x4]; 2231 u8 log_xrc_srq_size[0x4]; 2232 u8 reserved_at_8[0x18]; 2233 2234 u8 wq_signature[0x1]; 2235 u8 cont_srq[0x1]; 2236 u8 reserved_at_22[0x1]; 2237 u8 rlky[0x1]; 2238 u8 basic_cyclic_rcv_wqe[0x1]; 2239 u8 log_rq_stride[0x3]; 2240 u8 xrcd[0x18]; 2241 2242 u8 page_offset[0x6]; 2243 u8 reserved_at_46[0x2]; 2244 u8 cqn[0x18]; 2245 2246 u8 reserved_at_60[0x20]; 2247 2248 u8 user_index_equal_xrc_srqn[0x1]; 2249 u8 reserved_at_81[0x1]; 2250 u8 log_page_size[0x6]; 2251 u8 user_index[0x18]; 2252 2253 u8 reserved_at_a0[0x20]; 2254 2255 u8 reserved_at_c0[0x8]; 2256 u8 pd[0x18]; 2257 2258 u8 lwm[0x10]; 2259 u8 wqe_cnt[0x10]; 2260 2261 u8 reserved_at_100[0x40]; 2262 2263 u8 db_record_addr_h[0x20]; 2264 2265 u8 db_record_addr_l[0x1e]; 2266 u8 reserved_at_17e[0x2]; 2267 2268 u8 reserved_at_180[0x80]; 2269 }; 2270 2271 struct mlx5_ifc_traffic_counter_bits { 2272 u8 packets[0x40]; 2273 2274 u8 octets[0x40]; 2275 }; 2276 2277 struct mlx5_ifc_tisc_bits { 2278 u8 strict_lag_tx_port_affinity[0x1]; 2279 u8 reserved_at_1[0x3]; 2280 u8 lag_tx_port_affinity[0x04]; 2281 2282 u8 reserved_at_8[0x4]; 2283 u8 prio[0x4]; 2284 u8 reserved_at_10[0x10]; 2285 2286 u8 reserved_at_20[0x100]; 2287 2288 u8 reserved_at_120[0x8]; 2289 u8 transport_domain[0x18]; 2290 2291 u8 reserved_at_140[0x3c0]; 2292 }; 2293 2294 enum { 2295 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2296 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2297 }; 2298 2299 enum { 2300 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2301 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2302 }; 2303 2304 enum { 2305 MLX5_RX_HASH_FN_NONE = 0x0, 2306 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2307 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2308 }; 2309 2310 enum { 2311 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 2312 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 2313 }; 2314 2315 struct mlx5_ifc_tirc_bits { 2316 u8 reserved_at_0[0x20]; 2317 2318 u8 disp_type[0x4]; 2319 u8 reserved_at_24[0x1c]; 2320 2321 u8 reserved_at_40[0x40]; 2322 2323 u8 reserved_at_80[0x4]; 2324 u8 lro_timeout_period_usecs[0x10]; 2325 u8 lro_enable_mask[0x4]; 2326 u8 lro_max_ip_payload_size[0x8]; 2327 2328 u8 reserved_at_a0[0x40]; 2329 2330 u8 reserved_at_e0[0x8]; 2331 u8 inline_rqn[0x18]; 2332 2333 u8 rx_hash_symmetric[0x1]; 2334 u8 reserved_at_101[0x1]; 2335 u8 tunneled_offload_en[0x1]; 2336 u8 reserved_at_103[0x5]; 2337 u8 indirect_table[0x18]; 2338 2339 u8 rx_hash_fn[0x4]; 2340 u8 reserved_at_124[0x2]; 2341 u8 self_lb_block[0x2]; 2342 u8 transport_domain[0x18]; 2343 2344 u8 rx_hash_toeplitz_key[10][0x20]; 2345 2346 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2347 2348 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2349 2350 u8 reserved_at_2c0[0x4c0]; 2351 }; 2352 2353 enum { 2354 MLX5_SRQC_STATE_GOOD = 0x0, 2355 MLX5_SRQC_STATE_ERROR = 0x1, 2356 }; 2357 2358 struct mlx5_ifc_srqc_bits { 2359 u8 state[0x4]; 2360 u8 log_srq_size[0x4]; 2361 u8 reserved_at_8[0x18]; 2362 2363 u8 wq_signature[0x1]; 2364 u8 cont_srq[0x1]; 2365 u8 reserved_at_22[0x1]; 2366 u8 rlky[0x1]; 2367 u8 reserved_at_24[0x1]; 2368 u8 log_rq_stride[0x3]; 2369 u8 xrcd[0x18]; 2370 2371 u8 page_offset[0x6]; 2372 u8 reserved_at_46[0x2]; 2373 u8 cqn[0x18]; 2374 2375 u8 reserved_at_60[0x20]; 2376 2377 u8 reserved_at_80[0x2]; 2378 u8 log_page_size[0x6]; 2379 u8 reserved_at_88[0x18]; 2380 2381 u8 reserved_at_a0[0x20]; 2382 2383 u8 reserved_at_c0[0x8]; 2384 u8 pd[0x18]; 2385 2386 u8 lwm[0x10]; 2387 u8 wqe_cnt[0x10]; 2388 2389 u8 reserved_at_100[0x40]; 2390 2391 u8 dbr_addr[0x40]; 2392 2393 u8 reserved_at_180[0x80]; 2394 }; 2395 2396 enum { 2397 MLX5_SQC_STATE_RST = 0x0, 2398 MLX5_SQC_STATE_RDY = 0x1, 2399 MLX5_SQC_STATE_ERR = 0x3, 2400 }; 2401 2402 struct mlx5_ifc_sqc_bits { 2403 u8 rlky[0x1]; 2404 u8 cd_master[0x1]; 2405 u8 fre[0x1]; 2406 u8 flush_in_error_en[0x1]; 2407 u8 reserved_at_4[0x1]; 2408 u8 min_wqe_inline_mode[0x3]; 2409 u8 state[0x4]; 2410 u8 reg_umr[0x1]; 2411 u8 reserved_at_d[0x13]; 2412 2413 u8 reserved_at_20[0x8]; 2414 u8 user_index[0x18]; 2415 2416 u8 reserved_at_40[0x8]; 2417 u8 cqn[0x18]; 2418 2419 u8 reserved_at_60[0x90]; 2420 2421 u8 packet_pacing_rate_limit_index[0x10]; 2422 u8 tis_lst_sz[0x10]; 2423 u8 reserved_at_110[0x10]; 2424 2425 u8 reserved_at_120[0x40]; 2426 2427 u8 reserved_at_160[0x8]; 2428 u8 tis_num_0[0x18]; 2429 2430 struct mlx5_ifc_wq_bits wq; 2431 }; 2432 2433 enum { 2434 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2435 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2436 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2437 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2438 }; 2439 2440 struct mlx5_ifc_scheduling_context_bits { 2441 u8 element_type[0x8]; 2442 u8 reserved_at_8[0x18]; 2443 2444 u8 element_attributes[0x20]; 2445 2446 u8 parent_element_id[0x20]; 2447 2448 u8 reserved_at_60[0x40]; 2449 2450 u8 bw_share[0x20]; 2451 2452 u8 max_average_bw[0x20]; 2453 2454 u8 reserved_at_e0[0x120]; 2455 }; 2456 2457 struct mlx5_ifc_rqtc_bits { 2458 u8 reserved_at_0[0xa0]; 2459 2460 u8 reserved_at_a0[0x10]; 2461 u8 rqt_max_size[0x10]; 2462 2463 u8 reserved_at_c0[0x10]; 2464 u8 rqt_actual_size[0x10]; 2465 2466 u8 reserved_at_e0[0x6a0]; 2467 2468 struct mlx5_ifc_rq_num_bits rq_num[0]; 2469 }; 2470 2471 enum { 2472 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2473 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2474 }; 2475 2476 enum { 2477 MLX5_RQC_STATE_RST = 0x0, 2478 MLX5_RQC_STATE_RDY = 0x1, 2479 MLX5_RQC_STATE_ERR = 0x3, 2480 }; 2481 2482 struct mlx5_ifc_rqc_bits { 2483 u8 rlky[0x1]; 2484 u8 reserved_at_1[0x1]; 2485 u8 scatter_fcs[0x1]; 2486 u8 vsd[0x1]; 2487 u8 mem_rq_type[0x4]; 2488 u8 state[0x4]; 2489 u8 reserved_at_c[0x1]; 2490 u8 flush_in_error_en[0x1]; 2491 u8 reserved_at_e[0x12]; 2492 2493 u8 reserved_at_20[0x8]; 2494 u8 user_index[0x18]; 2495 2496 u8 reserved_at_40[0x8]; 2497 u8 cqn[0x18]; 2498 2499 u8 counter_set_id[0x8]; 2500 u8 reserved_at_68[0x18]; 2501 2502 u8 reserved_at_80[0x8]; 2503 u8 rmpn[0x18]; 2504 2505 u8 reserved_at_a0[0xe0]; 2506 2507 struct mlx5_ifc_wq_bits wq; 2508 }; 2509 2510 enum { 2511 MLX5_RMPC_STATE_RDY = 0x1, 2512 MLX5_RMPC_STATE_ERR = 0x3, 2513 }; 2514 2515 struct mlx5_ifc_rmpc_bits { 2516 u8 reserved_at_0[0x8]; 2517 u8 state[0x4]; 2518 u8 reserved_at_c[0x14]; 2519 2520 u8 basic_cyclic_rcv_wqe[0x1]; 2521 u8 reserved_at_21[0x1f]; 2522 2523 u8 reserved_at_40[0x140]; 2524 2525 struct mlx5_ifc_wq_bits wq; 2526 }; 2527 2528 struct mlx5_ifc_nic_vport_context_bits { 2529 u8 reserved_at_0[0x5]; 2530 u8 min_wqe_inline_mode[0x3]; 2531 u8 reserved_at_8[0x17]; 2532 u8 roce_en[0x1]; 2533 2534 u8 arm_change_event[0x1]; 2535 u8 reserved_at_21[0x1a]; 2536 u8 event_on_mtu[0x1]; 2537 u8 event_on_promisc_change[0x1]; 2538 u8 event_on_vlan_change[0x1]; 2539 u8 event_on_mc_address_change[0x1]; 2540 u8 event_on_uc_address_change[0x1]; 2541 2542 u8 reserved_at_40[0xf0]; 2543 2544 u8 mtu[0x10]; 2545 2546 u8 system_image_guid[0x40]; 2547 u8 port_guid[0x40]; 2548 u8 node_guid[0x40]; 2549 2550 u8 reserved_at_200[0x140]; 2551 u8 qkey_violation_counter[0x10]; 2552 u8 reserved_at_350[0x430]; 2553 2554 u8 promisc_uc[0x1]; 2555 u8 promisc_mc[0x1]; 2556 u8 promisc_all[0x1]; 2557 u8 reserved_at_783[0x2]; 2558 u8 allowed_list_type[0x3]; 2559 u8 reserved_at_788[0xc]; 2560 u8 allowed_list_size[0xc]; 2561 2562 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2563 2564 u8 reserved_at_7e0[0x20]; 2565 2566 u8 current_uc_mac_address[0][0x40]; 2567 }; 2568 2569 enum { 2570 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2571 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2572 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2573 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2574 }; 2575 2576 struct mlx5_ifc_mkc_bits { 2577 u8 reserved_at_0[0x1]; 2578 u8 free[0x1]; 2579 u8 reserved_at_2[0xd]; 2580 u8 small_fence_on_rdma_read_response[0x1]; 2581 u8 umr_en[0x1]; 2582 u8 a[0x1]; 2583 u8 rw[0x1]; 2584 u8 rr[0x1]; 2585 u8 lw[0x1]; 2586 u8 lr[0x1]; 2587 u8 access_mode[0x2]; 2588 u8 reserved_at_18[0x8]; 2589 2590 u8 qpn[0x18]; 2591 u8 mkey_7_0[0x8]; 2592 2593 u8 reserved_at_40[0x20]; 2594 2595 u8 length64[0x1]; 2596 u8 bsf_en[0x1]; 2597 u8 sync_umr[0x1]; 2598 u8 reserved_at_63[0x2]; 2599 u8 expected_sigerr_count[0x1]; 2600 u8 reserved_at_66[0x1]; 2601 u8 en_rinval[0x1]; 2602 u8 pd[0x18]; 2603 2604 u8 start_addr[0x40]; 2605 2606 u8 len[0x40]; 2607 2608 u8 bsf_octword_size[0x20]; 2609 2610 u8 reserved_at_120[0x80]; 2611 2612 u8 translations_octword_size[0x20]; 2613 2614 u8 reserved_at_1c0[0x1b]; 2615 u8 log_page_size[0x5]; 2616 2617 u8 reserved_at_1e0[0x20]; 2618 }; 2619 2620 struct mlx5_ifc_pkey_bits { 2621 u8 reserved_at_0[0x10]; 2622 u8 pkey[0x10]; 2623 }; 2624 2625 struct mlx5_ifc_array128_auto_bits { 2626 u8 array128_auto[16][0x8]; 2627 }; 2628 2629 struct mlx5_ifc_hca_vport_context_bits { 2630 u8 field_select[0x20]; 2631 2632 u8 reserved_at_20[0xe0]; 2633 2634 u8 sm_virt_aware[0x1]; 2635 u8 has_smi[0x1]; 2636 u8 has_raw[0x1]; 2637 u8 grh_required[0x1]; 2638 u8 reserved_at_104[0xc]; 2639 u8 port_physical_state[0x4]; 2640 u8 vport_state_policy[0x4]; 2641 u8 port_state[0x4]; 2642 u8 vport_state[0x4]; 2643 2644 u8 reserved_at_120[0x20]; 2645 2646 u8 system_image_guid[0x40]; 2647 2648 u8 port_guid[0x40]; 2649 2650 u8 node_guid[0x40]; 2651 2652 u8 cap_mask1[0x20]; 2653 2654 u8 cap_mask1_field_select[0x20]; 2655 2656 u8 cap_mask2[0x20]; 2657 2658 u8 cap_mask2_field_select[0x20]; 2659 2660 u8 reserved_at_280[0x80]; 2661 2662 u8 lid[0x10]; 2663 u8 reserved_at_310[0x4]; 2664 u8 init_type_reply[0x4]; 2665 u8 lmc[0x3]; 2666 u8 subnet_timeout[0x5]; 2667 2668 u8 sm_lid[0x10]; 2669 u8 sm_sl[0x4]; 2670 u8 reserved_at_334[0xc]; 2671 2672 u8 qkey_violation_counter[0x10]; 2673 u8 pkey_violation_counter[0x10]; 2674 2675 u8 reserved_at_360[0xca0]; 2676 }; 2677 2678 struct mlx5_ifc_esw_vport_context_bits { 2679 u8 reserved_at_0[0x3]; 2680 u8 vport_svlan_strip[0x1]; 2681 u8 vport_cvlan_strip[0x1]; 2682 u8 vport_svlan_insert[0x1]; 2683 u8 vport_cvlan_insert[0x2]; 2684 u8 reserved_at_8[0x18]; 2685 2686 u8 reserved_at_20[0x20]; 2687 2688 u8 svlan_cfi[0x1]; 2689 u8 svlan_pcp[0x3]; 2690 u8 svlan_id[0xc]; 2691 u8 cvlan_cfi[0x1]; 2692 u8 cvlan_pcp[0x3]; 2693 u8 cvlan_id[0xc]; 2694 2695 u8 reserved_at_60[0x7a0]; 2696 }; 2697 2698 enum { 2699 MLX5_EQC_STATUS_OK = 0x0, 2700 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2701 }; 2702 2703 enum { 2704 MLX5_EQC_ST_ARMED = 0x9, 2705 MLX5_EQC_ST_FIRED = 0xa, 2706 }; 2707 2708 struct mlx5_ifc_eqc_bits { 2709 u8 status[0x4]; 2710 u8 reserved_at_4[0x9]; 2711 u8 ec[0x1]; 2712 u8 oi[0x1]; 2713 u8 reserved_at_f[0x5]; 2714 u8 st[0x4]; 2715 u8 reserved_at_18[0x8]; 2716 2717 u8 reserved_at_20[0x20]; 2718 2719 u8 reserved_at_40[0x14]; 2720 u8 page_offset[0x6]; 2721 u8 reserved_at_5a[0x6]; 2722 2723 u8 reserved_at_60[0x3]; 2724 u8 log_eq_size[0x5]; 2725 u8 uar_page[0x18]; 2726 2727 u8 reserved_at_80[0x20]; 2728 2729 u8 reserved_at_a0[0x18]; 2730 u8 intr[0x8]; 2731 2732 u8 reserved_at_c0[0x3]; 2733 u8 log_page_size[0x5]; 2734 u8 reserved_at_c8[0x18]; 2735 2736 u8 reserved_at_e0[0x60]; 2737 2738 u8 reserved_at_140[0x8]; 2739 u8 consumer_counter[0x18]; 2740 2741 u8 reserved_at_160[0x8]; 2742 u8 producer_counter[0x18]; 2743 2744 u8 reserved_at_180[0x80]; 2745 }; 2746 2747 enum { 2748 MLX5_DCTC_STATE_ACTIVE = 0x0, 2749 MLX5_DCTC_STATE_DRAINING = 0x1, 2750 MLX5_DCTC_STATE_DRAINED = 0x2, 2751 }; 2752 2753 enum { 2754 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2755 MLX5_DCTC_CS_RES_NA = 0x1, 2756 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2757 }; 2758 2759 enum { 2760 MLX5_DCTC_MTU_256_BYTES = 0x1, 2761 MLX5_DCTC_MTU_512_BYTES = 0x2, 2762 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2763 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2764 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2765 }; 2766 2767 struct mlx5_ifc_dctc_bits { 2768 u8 reserved_at_0[0x4]; 2769 u8 state[0x4]; 2770 u8 reserved_at_8[0x18]; 2771 2772 u8 reserved_at_20[0x8]; 2773 u8 user_index[0x18]; 2774 2775 u8 reserved_at_40[0x8]; 2776 u8 cqn[0x18]; 2777 2778 u8 counter_set_id[0x8]; 2779 u8 atomic_mode[0x4]; 2780 u8 rre[0x1]; 2781 u8 rwe[0x1]; 2782 u8 rae[0x1]; 2783 u8 atomic_like_write_en[0x1]; 2784 u8 latency_sensitive[0x1]; 2785 u8 rlky[0x1]; 2786 u8 free_ar[0x1]; 2787 u8 reserved_at_73[0xd]; 2788 2789 u8 reserved_at_80[0x8]; 2790 u8 cs_res[0x8]; 2791 u8 reserved_at_90[0x3]; 2792 u8 min_rnr_nak[0x5]; 2793 u8 reserved_at_98[0x8]; 2794 2795 u8 reserved_at_a0[0x8]; 2796 u8 srqn_xrqn[0x18]; 2797 2798 u8 reserved_at_c0[0x8]; 2799 u8 pd[0x18]; 2800 2801 u8 tclass[0x8]; 2802 u8 reserved_at_e8[0x4]; 2803 u8 flow_label[0x14]; 2804 2805 u8 dc_access_key[0x40]; 2806 2807 u8 reserved_at_140[0x5]; 2808 u8 mtu[0x3]; 2809 u8 port[0x8]; 2810 u8 pkey_index[0x10]; 2811 2812 u8 reserved_at_160[0x8]; 2813 u8 my_addr_index[0x8]; 2814 u8 reserved_at_170[0x8]; 2815 u8 hop_limit[0x8]; 2816 2817 u8 dc_access_key_violation_count[0x20]; 2818 2819 u8 reserved_at_1a0[0x14]; 2820 u8 dei_cfi[0x1]; 2821 u8 eth_prio[0x3]; 2822 u8 ecn[0x2]; 2823 u8 dscp[0x6]; 2824 2825 u8 reserved_at_1c0[0x40]; 2826 }; 2827 2828 enum { 2829 MLX5_CQC_STATUS_OK = 0x0, 2830 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2831 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2832 }; 2833 2834 enum { 2835 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 2836 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 2837 }; 2838 2839 enum { 2840 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 2841 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 2842 MLX5_CQC_ST_FIRED = 0xa, 2843 }; 2844 2845 enum { 2846 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2847 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2848 MLX5_CQ_PERIOD_NUM_MODES 2849 }; 2850 2851 struct mlx5_ifc_cqc_bits { 2852 u8 status[0x4]; 2853 u8 reserved_at_4[0x4]; 2854 u8 cqe_sz[0x3]; 2855 u8 cc[0x1]; 2856 u8 reserved_at_c[0x1]; 2857 u8 scqe_break_moderation_en[0x1]; 2858 u8 oi[0x1]; 2859 u8 cq_period_mode[0x2]; 2860 u8 cqe_comp_en[0x1]; 2861 u8 mini_cqe_res_format[0x2]; 2862 u8 st[0x4]; 2863 u8 reserved_at_18[0x8]; 2864 2865 u8 reserved_at_20[0x20]; 2866 2867 u8 reserved_at_40[0x14]; 2868 u8 page_offset[0x6]; 2869 u8 reserved_at_5a[0x6]; 2870 2871 u8 reserved_at_60[0x3]; 2872 u8 log_cq_size[0x5]; 2873 u8 uar_page[0x18]; 2874 2875 u8 reserved_at_80[0x4]; 2876 u8 cq_period[0xc]; 2877 u8 cq_max_count[0x10]; 2878 2879 u8 reserved_at_a0[0x18]; 2880 u8 c_eqn[0x8]; 2881 2882 u8 reserved_at_c0[0x3]; 2883 u8 log_page_size[0x5]; 2884 u8 reserved_at_c8[0x18]; 2885 2886 u8 reserved_at_e0[0x20]; 2887 2888 u8 reserved_at_100[0x8]; 2889 u8 last_notified_index[0x18]; 2890 2891 u8 reserved_at_120[0x8]; 2892 u8 last_solicit_index[0x18]; 2893 2894 u8 reserved_at_140[0x8]; 2895 u8 consumer_counter[0x18]; 2896 2897 u8 reserved_at_160[0x8]; 2898 u8 producer_counter[0x18]; 2899 2900 u8 reserved_at_180[0x40]; 2901 2902 u8 dbr_addr[0x40]; 2903 }; 2904 2905 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2906 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2907 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2908 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2909 u8 reserved_at_0[0x800]; 2910 }; 2911 2912 struct mlx5_ifc_query_adapter_param_block_bits { 2913 u8 reserved_at_0[0xc0]; 2914 2915 u8 reserved_at_c0[0x8]; 2916 u8 ieee_vendor_id[0x18]; 2917 2918 u8 reserved_at_e0[0x10]; 2919 u8 vsd_vendor_id[0x10]; 2920 2921 u8 vsd[208][0x8]; 2922 2923 u8 vsd_contd_psid[16][0x8]; 2924 }; 2925 2926 enum { 2927 MLX5_XRQC_STATE_GOOD = 0x0, 2928 MLX5_XRQC_STATE_ERROR = 0x1, 2929 }; 2930 2931 enum { 2932 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 2933 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 2934 }; 2935 2936 enum { 2937 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 2938 }; 2939 2940 struct mlx5_ifc_tag_matching_topology_context_bits { 2941 u8 log_matching_list_sz[0x4]; 2942 u8 reserved_at_4[0xc]; 2943 u8 append_next_index[0x10]; 2944 2945 u8 sw_phase_cnt[0x10]; 2946 u8 hw_phase_cnt[0x10]; 2947 2948 u8 reserved_at_40[0x40]; 2949 }; 2950 2951 struct mlx5_ifc_xrqc_bits { 2952 u8 state[0x4]; 2953 u8 rlkey[0x1]; 2954 u8 reserved_at_5[0xf]; 2955 u8 topology[0x4]; 2956 u8 reserved_at_18[0x4]; 2957 u8 offload[0x4]; 2958 2959 u8 reserved_at_20[0x8]; 2960 u8 user_index[0x18]; 2961 2962 u8 reserved_at_40[0x8]; 2963 u8 cqn[0x18]; 2964 2965 u8 reserved_at_60[0xa0]; 2966 2967 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 2968 2969 u8 reserved_at_180[0x880]; 2970 2971 struct mlx5_ifc_wq_bits wq; 2972 }; 2973 2974 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2975 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2976 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2977 u8 reserved_at_0[0x20]; 2978 }; 2979 2980 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2981 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2982 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2983 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2984 u8 reserved_at_0[0x20]; 2985 }; 2986 2987 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 2988 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 2989 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 2990 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 2991 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 2992 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 2993 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 2994 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 2995 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 2996 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 2997 u8 reserved_at_0[0x7c0]; 2998 }; 2999 3000 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3001 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3002 struct mlx5_ifc_pcie_tas_cntrs_grp_data_layout_bits pcie_tas_cntrs_grp_data_layout; 3003 u8 reserved_at_0[0x7c0]; 3004 }; 3005 3006 union mlx5_ifc_event_auto_bits { 3007 struct mlx5_ifc_comp_event_bits comp_event; 3008 struct mlx5_ifc_dct_events_bits dct_events; 3009 struct mlx5_ifc_qp_events_bits qp_events; 3010 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3011 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3012 struct mlx5_ifc_cq_error_bits cq_error; 3013 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3014 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3015 struct mlx5_ifc_gpio_event_bits gpio_event; 3016 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3017 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3018 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3019 u8 reserved_at_0[0xe0]; 3020 }; 3021 3022 struct mlx5_ifc_health_buffer_bits { 3023 u8 reserved_at_0[0x100]; 3024 3025 u8 assert_existptr[0x20]; 3026 3027 u8 assert_callra[0x20]; 3028 3029 u8 reserved_at_140[0x40]; 3030 3031 u8 fw_version[0x20]; 3032 3033 u8 hw_id[0x20]; 3034 3035 u8 reserved_at_1c0[0x20]; 3036 3037 u8 irisc_index[0x8]; 3038 u8 synd[0x8]; 3039 u8 ext_synd[0x10]; 3040 }; 3041 3042 struct mlx5_ifc_register_loopback_control_bits { 3043 u8 no_lb[0x1]; 3044 u8 reserved_at_1[0x7]; 3045 u8 port[0x8]; 3046 u8 reserved_at_10[0x10]; 3047 3048 u8 reserved_at_20[0x60]; 3049 }; 3050 3051 struct mlx5_ifc_vport_tc_element_bits { 3052 u8 traffic_class[0x4]; 3053 u8 reserved_at_4[0xc]; 3054 u8 vport_number[0x10]; 3055 }; 3056 3057 struct mlx5_ifc_vport_element_bits { 3058 u8 reserved_at_0[0x10]; 3059 u8 vport_number[0x10]; 3060 }; 3061 3062 enum { 3063 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3064 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3065 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3066 }; 3067 3068 struct mlx5_ifc_tsar_element_bits { 3069 u8 reserved_at_0[0x8]; 3070 u8 tsar_type[0x8]; 3071 u8 reserved_at_10[0x10]; 3072 }; 3073 3074 struct mlx5_ifc_teardown_hca_out_bits { 3075 u8 status[0x8]; 3076 u8 reserved_at_8[0x18]; 3077 3078 u8 syndrome[0x20]; 3079 3080 u8 reserved_at_40[0x40]; 3081 }; 3082 3083 enum { 3084 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3085 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1, 3086 }; 3087 3088 struct mlx5_ifc_teardown_hca_in_bits { 3089 u8 opcode[0x10]; 3090 u8 reserved_at_10[0x10]; 3091 3092 u8 reserved_at_20[0x10]; 3093 u8 op_mod[0x10]; 3094 3095 u8 reserved_at_40[0x10]; 3096 u8 profile[0x10]; 3097 3098 u8 reserved_at_60[0x20]; 3099 }; 3100 3101 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3102 u8 status[0x8]; 3103 u8 reserved_at_8[0x18]; 3104 3105 u8 syndrome[0x20]; 3106 3107 u8 reserved_at_40[0x40]; 3108 }; 3109 3110 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3111 u8 opcode[0x10]; 3112 u8 reserved_at_10[0x10]; 3113 3114 u8 reserved_at_20[0x10]; 3115 u8 op_mod[0x10]; 3116 3117 u8 reserved_at_40[0x8]; 3118 u8 qpn[0x18]; 3119 3120 u8 reserved_at_60[0x20]; 3121 3122 u8 opt_param_mask[0x20]; 3123 3124 u8 reserved_at_a0[0x20]; 3125 3126 struct mlx5_ifc_qpc_bits qpc; 3127 3128 u8 reserved_at_800[0x80]; 3129 }; 3130 3131 struct mlx5_ifc_sqd2rts_qp_out_bits { 3132 u8 status[0x8]; 3133 u8 reserved_at_8[0x18]; 3134 3135 u8 syndrome[0x20]; 3136 3137 u8 reserved_at_40[0x40]; 3138 }; 3139 3140 struct mlx5_ifc_sqd2rts_qp_in_bits { 3141 u8 opcode[0x10]; 3142 u8 reserved_at_10[0x10]; 3143 3144 u8 reserved_at_20[0x10]; 3145 u8 op_mod[0x10]; 3146 3147 u8 reserved_at_40[0x8]; 3148 u8 qpn[0x18]; 3149 3150 u8 reserved_at_60[0x20]; 3151 3152 u8 opt_param_mask[0x20]; 3153 3154 u8 reserved_at_a0[0x20]; 3155 3156 struct mlx5_ifc_qpc_bits qpc; 3157 3158 u8 reserved_at_800[0x80]; 3159 }; 3160 3161 struct mlx5_ifc_set_roce_address_out_bits { 3162 u8 status[0x8]; 3163 u8 reserved_at_8[0x18]; 3164 3165 u8 syndrome[0x20]; 3166 3167 u8 reserved_at_40[0x40]; 3168 }; 3169 3170 struct mlx5_ifc_set_roce_address_in_bits { 3171 u8 opcode[0x10]; 3172 u8 reserved_at_10[0x10]; 3173 3174 u8 reserved_at_20[0x10]; 3175 u8 op_mod[0x10]; 3176 3177 u8 roce_address_index[0x10]; 3178 u8 reserved_at_50[0x10]; 3179 3180 u8 reserved_at_60[0x20]; 3181 3182 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3183 }; 3184 3185 struct mlx5_ifc_set_mad_demux_out_bits { 3186 u8 status[0x8]; 3187 u8 reserved_at_8[0x18]; 3188 3189 u8 syndrome[0x20]; 3190 3191 u8 reserved_at_40[0x40]; 3192 }; 3193 3194 enum { 3195 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3196 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3197 }; 3198 3199 struct mlx5_ifc_set_mad_demux_in_bits { 3200 u8 opcode[0x10]; 3201 u8 reserved_at_10[0x10]; 3202 3203 u8 reserved_at_20[0x10]; 3204 u8 op_mod[0x10]; 3205 3206 u8 reserved_at_40[0x20]; 3207 3208 u8 reserved_at_60[0x6]; 3209 u8 demux_mode[0x2]; 3210 u8 reserved_at_68[0x18]; 3211 }; 3212 3213 struct mlx5_ifc_set_l2_table_entry_out_bits { 3214 u8 status[0x8]; 3215 u8 reserved_at_8[0x18]; 3216 3217 u8 syndrome[0x20]; 3218 3219 u8 reserved_at_40[0x40]; 3220 }; 3221 3222 struct mlx5_ifc_set_l2_table_entry_in_bits { 3223 u8 opcode[0x10]; 3224 u8 reserved_at_10[0x10]; 3225 3226 u8 reserved_at_20[0x10]; 3227 u8 op_mod[0x10]; 3228 3229 u8 reserved_at_40[0x60]; 3230 3231 u8 reserved_at_a0[0x8]; 3232 u8 table_index[0x18]; 3233 3234 u8 reserved_at_c0[0x20]; 3235 3236 u8 reserved_at_e0[0x13]; 3237 u8 vlan_valid[0x1]; 3238 u8 vlan[0xc]; 3239 3240 struct mlx5_ifc_mac_address_layout_bits mac_address; 3241 3242 u8 reserved_at_140[0xc0]; 3243 }; 3244 3245 struct mlx5_ifc_set_issi_out_bits { 3246 u8 status[0x8]; 3247 u8 reserved_at_8[0x18]; 3248 3249 u8 syndrome[0x20]; 3250 3251 u8 reserved_at_40[0x40]; 3252 }; 3253 3254 struct mlx5_ifc_set_issi_in_bits { 3255 u8 opcode[0x10]; 3256 u8 reserved_at_10[0x10]; 3257 3258 u8 reserved_at_20[0x10]; 3259 u8 op_mod[0x10]; 3260 3261 u8 reserved_at_40[0x10]; 3262 u8 current_issi[0x10]; 3263 3264 u8 reserved_at_60[0x20]; 3265 }; 3266 3267 struct mlx5_ifc_set_hca_cap_out_bits { 3268 u8 status[0x8]; 3269 u8 reserved_at_8[0x18]; 3270 3271 u8 syndrome[0x20]; 3272 3273 u8 reserved_at_40[0x40]; 3274 }; 3275 3276 struct mlx5_ifc_set_hca_cap_in_bits { 3277 u8 opcode[0x10]; 3278 u8 reserved_at_10[0x10]; 3279 3280 u8 reserved_at_20[0x10]; 3281 u8 op_mod[0x10]; 3282 3283 u8 reserved_at_40[0x40]; 3284 3285 union mlx5_ifc_hca_cap_union_bits capability; 3286 }; 3287 3288 enum { 3289 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3290 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3291 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3292 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3293 }; 3294 3295 struct mlx5_ifc_set_fte_out_bits { 3296 u8 status[0x8]; 3297 u8 reserved_at_8[0x18]; 3298 3299 u8 syndrome[0x20]; 3300 3301 u8 reserved_at_40[0x40]; 3302 }; 3303 3304 struct mlx5_ifc_set_fte_in_bits { 3305 u8 opcode[0x10]; 3306 u8 reserved_at_10[0x10]; 3307 3308 u8 reserved_at_20[0x10]; 3309 u8 op_mod[0x10]; 3310 3311 u8 other_vport[0x1]; 3312 u8 reserved_at_41[0xf]; 3313 u8 vport_number[0x10]; 3314 3315 u8 reserved_at_60[0x20]; 3316 3317 u8 table_type[0x8]; 3318 u8 reserved_at_88[0x18]; 3319 3320 u8 reserved_at_a0[0x8]; 3321 u8 table_id[0x18]; 3322 3323 u8 reserved_at_c0[0x18]; 3324 u8 modify_enable_mask[0x8]; 3325 3326 u8 reserved_at_e0[0x20]; 3327 3328 u8 flow_index[0x20]; 3329 3330 u8 reserved_at_120[0xe0]; 3331 3332 struct mlx5_ifc_flow_context_bits flow_context; 3333 }; 3334 3335 struct mlx5_ifc_rts2rts_qp_out_bits { 3336 u8 status[0x8]; 3337 u8 reserved_at_8[0x18]; 3338 3339 u8 syndrome[0x20]; 3340 3341 u8 reserved_at_40[0x40]; 3342 }; 3343 3344 struct mlx5_ifc_rts2rts_qp_in_bits { 3345 u8 opcode[0x10]; 3346 u8 reserved_at_10[0x10]; 3347 3348 u8 reserved_at_20[0x10]; 3349 u8 op_mod[0x10]; 3350 3351 u8 reserved_at_40[0x8]; 3352 u8 qpn[0x18]; 3353 3354 u8 reserved_at_60[0x20]; 3355 3356 u8 opt_param_mask[0x20]; 3357 3358 u8 reserved_at_a0[0x20]; 3359 3360 struct mlx5_ifc_qpc_bits qpc; 3361 3362 u8 reserved_at_800[0x80]; 3363 }; 3364 3365 struct mlx5_ifc_rtr2rts_qp_out_bits { 3366 u8 status[0x8]; 3367 u8 reserved_at_8[0x18]; 3368 3369 u8 syndrome[0x20]; 3370 3371 u8 reserved_at_40[0x40]; 3372 }; 3373 3374 struct mlx5_ifc_rtr2rts_qp_in_bits { 3375 u8 opcode[0x10]; 3376 u8 reserved_at_10[0x10]; 3377 3378 u8 reserved_at_20[0x10]; 3379 u8 op_mod[0x10]; 3380 3381 u8 reserved_at_40[0x8]; 3382 u8 qpn[0x18]; 3383 3384 u8 reserved_at_60[0x20]; 3385 3386 u8 opt_param_mask[0x20]; 3387 3388 u8 reserved_at_a0[0x20]; 3389 3390 struct mlx5_ifc_qpc_bits qpc; 3391 3392 u8 reserved_at_800[0x80]; 3393 }; 3394 3395 struct mlx5_ifc_rst2init_qp_out_bits { 3396 u8 status[0x8]; 3397 u8 reserved_at_8[0x18]; 3398 3399 u8 syndrome[0x20]; 3400 3401 u8 reserved_at_40[0x40]; 3402 }; 3403 3404 struct mlx5_ifc_rst2init_qp_in_bits { 3405 u8 opcode[0x10]; 3406 u8 reserved_at_10[0x10]; 3407 3408 u8 reserved_at_20[0x10]; 3409 u8 op_mod[0x10]; 3410 3411 u8 reserved_at_40[0x8]; 3412 u8 qpn[0x18]; 3413 3414 u8 reserved_at_60[0x20]; 3415 3416 u8 opt_param_mask[0x20]; 3417 3418 u8 reserved_at_a0[0x20]; 3419 3420 struct mlx5_ifc_qpc_bits qpc; 3421 3422 u8 reserved_at_800[0x80]; 3423 }; 3424 3425 struct mlx5_ifc_query_xrq_out_bits { 3426 u8 status[0x8]; 3427 u8 reserved_at_8[0x18]; 3428 3429 u8 syndrome[0x20]; 3430 3431 u8 reserved_at_40[0x40]; 3432 3433 struct mlx5_ifc_xrqc_bits xrq_context; 3434 }; 3435 3436 struct mlx5_ifc_query_xrq_in_bits { 3437 u8 opcode[0x10]; 3438 u8 reserved_at_10[0x10]; 3439 3440 u8 reserved_at_20[0x10]; 3441 u8 op_mod[0x10]; 3442 3443 u8 reserved_at_40[0x8]; 3444 u8 xrqn[0x18]; 3445 3446 u8 reserved_at_60[0x20]; 3447 }; 3448 3449 struct mlx5_ifc_query_xrc_srq_out_bits { 3450 u8 status[0x8]; 3451 u8 reserved_at_8[0x18]; 3452 3453 u8 syndrome[0x20]; 3454 3455 u8 reserved_at_40[0x40]; 3456 3457 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3458 3459 u8 reserved_at_280[0x600]; 3460 3461 u8 pas[0][0x40]; 3462 }; 3463 3464 struct mlx5_ifc_query_xrc_srq_in_bits { 3465 u8 opcode[0x10]; 3466 u8 reserved_at_10[0x10]; 3467 3468 u8 reserved_at_20[0x10]; 3469 u8 op_mod[0x10]; 3470 3471 u8 reserved_at_40[0x8]; 3472 u8 xrc_srqn[0x18]; 3473 3474 u8 reserved_at_60[0x20]; 3475 }; 3476 3477 enum { 3478 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3479 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3480 }; 3481 3482 struct mlx5_ifc_query_vport_state_out_bits { 3483 u8 status[0x8]; 3484 u8 reserved_at_8[0x18]; 3485 3486 u8 syndrome[0x20]; 3487 3488 u8 reserved_at_40[0x20]; 3489 3490 u8 reserved_at_60[0x18]; 3491 u8 admin_state[0x4]; 3492 u8 state[0x4]; 3493 }; 3494 3495 enum { 3496 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3497 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3498 }; 3499 3500 struct mlx5_ifc_query_vport_state_in_bits { 3501 u8 opcode[0x10]; 3502 u8 reserved_at_10[0x10]; 3503 3504 u8 reserved_at_20[0x10]; 3505 u8 op_mod[0x10]; 3506 3507 u8 other_vport[0x1]; 3508 u8 reserved_at_41[0xf]; 3509 u8 vport_number[0x10]; 3510 3511 u8 reserved_at_60[0x20]; 3512 }; 3513 3514 struct mlx5_ifc_query_vport_counter_out_bits { 3515 u8 status[0x8]; 3516 u8 reserved_at_8[0x18]; 3517 3518 u8 syndrome[0x20]; 3519 3520 u8 reserved_at_40[0x40]; 3521 3522 struct mlx5_ifc_traffic_counter_bits received_errors; 3523 3524 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3525 3526 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3527 3528 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3529 3530 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3531 3532 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3533 3534 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3535 3536 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3537 3538 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3539 3540 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3541 3542 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3543 3544 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3545 3546 u8 reserved_at_680[0xa00]; 3547 }; 3548 3549 enum { 3550 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3551 }; 3552 3553 struct mlx5_ifc_query_vport_counter_in_bits { 3554 u8 opcode[0x10]; 3555 u8 reserved_at_10[0x10]; 3556 3557 u8 reserved_at_20[0x10]; 3558 u8 op_mod[0x10]; 3559 3560 u8 other_vport[0x1]; 3561 u8 reserved_at_41[0xb]; 3562 u8 port_num[0x4]; 3563 u8 vport_number[0x10]; 3564 3565 u8 reserved_at_60[0x60]; 3566 3567 u8 clear[0x1]; 3568 u8 reserved_at_c1[0x1f]; 3569 3570 u8 reserved_at_e0[0x20]; 3571 }; 3572 3573 struct mlx5_ifc_query_tis_out_bits { 3574 u8 status[0x8]; 3575 u8 reserved_at_8[0x18]; 3576 3577 u8 syndrome[0x20]; 3578 3579 u8 reserved_at_40[0x40]; 3580 3581 struct mlx5_ifc_tisc_bits tis_context; 3582 }; 3583 3584 struct mlx5_ifc_query_tis_in_bits { 3585 u8 opcode[0x10]; 3586 u8 reserved_at_10[0x10]; 3587 3588 u8 reserved_at_20[0x10]; 3589 u8 op_mod[0x10]; 3590 3591 u8 reserved_at_40[0x8]; 3592 u8 tisn[0x18]; 3593 3594 u8 reserved_at_60[0x20]; 3595 }; 3596 3597 struct mlx5_ifc_query_tir_out_bits { 3598 u8 status[0x8]; 3599 u8 reserved_at_8[0x18]; 3600 3601 u8 syndrome[0x20]; 3602 3603 u8 reserved_at_40[0xc0]; 3604 3605 struct mlx5_ifc_tirc_bits tir_context; 3606 }; 3607 3608 struct mlx5_ifc_query_tir_in_bits { 3609 u8 opcode[0x10]; 3610 u8 reserved_at_10[0x10]; 3611 3612 u8 reserved_at_20[0x10]; 3613 u8 op_mod[0x10]; 3614 3615 u8 reserved_at_40[0x8]; 3616 u8 tirn[0x18]; 3617 3618 u8 reserved_at_60[0x20]; 3619 }; 3620 3621 struct mlx5_ifc_query_srq_out_bits { 3622 u8 status[0x8]; 3623 u8 reserved_at_8[0x18]; 3624 3625 u8 syndrome[0x20]; 3626 3627 u8 reserved_at_40[0x40]; 3628 3629 struct mlx5_ifc_srqc_bits srq_context_entry; 3630 3631 u8 reserved_at_280[0x600]; 3632 3633 u8 pas[0][0x40]; 3634 }; 3635 3636 struct mlx5_ifc_query_srq_in_bits { 3637 u8 opcode[0x10]; 3638 u8 reserved_at_10[0x10]; 3639 3640 u8 reserved_at_20[0x10]; 3641 u8 op_mod[0x10]; 3642 3643 u8 reserved_at_40[0x8]; 3644 u8 srqn[0x18]; 3645 3646 u8 reserved_at_60[0x20]; 3647 }; 3648 3649 struct mlx5_ifc_query_sq_out_bits { 3650 u8 status[0x8]; 3651 u8 reserved_at_8[0x18]; 3652 3653 u8 syndrome[0x20]; 3654 3655 u8 reserved_at_40[0xc0]; 3656 3657 struct mlx5_ifc_sqc_bits sq_context; 3658 }; 3659 3660 struct mlx5_ifc_query_sq_in_bits { 3661 u8 opcode[0x10]; 3662 u8 reserved_at_10[0x10]; 3663 3664 u8 reserved_at_20[0x10]; 3665 u8 op_mod[0x10]; 3666 3667 u8 reserved_at_40[0x8]; 3668 u8 sqn[0x18]; 3669 3670 u8 reserved_at_60[0x20]; 3671 }; 3672 3673 struct mlx5_ifc_query_special_contexts_out_bits { 3674 u8 status[0x8]; 3675 u8 reserved_at_8[0x18]; 3676 3677 u8 syndrome[0x20]; 3678 3679 u8 dump_fill_mkey[0x20]; 3680 3681 u8 resd_lkey[0x20]; 3682 3683 u8 null_mkey[0x20]; 3684 3685 u8 reserved_at_a0[0x60]; 3686 }; 3687 3688 struct mlx5_ifc_query_special_contexts_in_bits { 3689 u8 opcode[0x10]; 3690 u8 reserved_at_10[0x10]; 3691 3692 u8 reserved_at_20[0x10]; 3693 u8 op_mod[0x10]; 3694 3695 u8 reserved_at_40[0x40]; 3696 }; 3697 3698 struct mlx5_ifc_query_scheduling_element_out_bits { 3699 u8 opcode[0x10]; 3700 u8 reserved_at_10[0x10]; 3701 3702 u8 reserved_at_20[0x10]; 3703 u8 op_mod[0x10]; 3704 3705 u8 reserved_at_40[0xc0]; 3706 3707 struct mlx5_ifc_scheduling_context_bits scheduling_context; 3708 3709 u8 reserved_at_300[0x100]; 3710 }; 3711 3712 enum { 3713 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 3714 }; 3715 3716 struct mlx5_ifc_query_scheduling_element_in_bits { 3717 u8 opcode[0x10]; 3718 u8 reserved_at_10[0x10]; 3719 3720 u8 reserved_at_20[0x10]; 3721 u8 op_mod[0x10]; 3722 3723 u8 scheduling_hierarchy[0x8]; 3724 u8 reserved_at_48[0x18]; 3725 3726 u8 scheduling_element_id[0x20]; 3727 3728 u8 reserved_at_80[0x180]; 3729 }; 3730 3731 struct mlx5_ifc_query_rqt_out_bits { 3732 u8 status[0x8]; 3733 u8 reserved_at_8[0x18]; 3734 3735 u8 syndrome[0x20]; 3736 3737 u8 reserved_at_40[0xc0]; 3738 3739 struct mlx5_ifc_rqtc_bits rqt_context; 3740 }; 3741 3742 struct mlx5_ifc_query_rqt_in_bits { 3743 u8 opcode[0x10]; 3744 u8 reserved_at_10[0x10]; 3745 3746 u8 reserved_at_20[0x10]; 3747 u8 op_mod[0x10]; 3748 3749 u8 reserved_at_40[0x8]; 3750 u8 rqtn[0x18]; 3751 3752 u8 reserved_at_60[0x20]; 3753 }; 3754 3755 struct mlx5_ifc_query_rq_out_bits { 3756 u8 status[0x8]; 3757 u8 reserved_at_8[0x18]; 3758 3759 u8 syndrome[0x20]; 3760 3761 u8 reserved_at_40[0xc0]; 3762 3763 struct mlx5_ifc_rqc_bits rq_context; 3764 }; 3765 3766 struct mlx5_ifc_query_rq_in_bits { 3767 u8 opcode[0x10]; 3768 u8 reserved_at_10[0x10]; 3769 3770 u8 reserved_at_20[0x10]; 3771 u8 op_mod[0x10]; 3772 3773 u8 reserved_at_40[0x8]; 3774 u8 rqn[0x18]; 3775 3776 u8 reserved_at_60[0x20]; 3777 }; 3778 3779 struct mlx5_ifc_query_roce_address_out_bits { 3780 u8 status[0x8]; 3781 u8 reserved_at_8[0x18]; 3782 3783 u8 syndrome[0x20]; 3784 3785 u8 reserved_at_40[0x40]; 3786 3787 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3788 }; 3789 3790 struct mlx5_ifc_query_roce_address_in_bits { 3791 u8 opcode[0x10]; 3792 u8 reserved_at_10[0x10]; 3793 3794 u8 reserved_at_20[0x10]; 3795 u8 op_mod[0x10]; 3796 3797 u8 roce_address_index[0x10]; 3798 u8 reserved_at_50[0x10]; 3799 3800 u8 reserved_at_60[0x20]; 3801 }; 3802 3803 struct mlx5_ifc_query_rmp_out_bits { 3804 u8 status[0x8]; 3805 u8 reserved_at_8[0x18]; 3806 3807 u8 syndrome[0x20]; 3808 3809 u8 reserved_at_40[0xc0]; 3810 3811 struct mlx5_ifc_rmpc_bits rmp_context; 3812 }; 3813 3814 struct mlx5_ifc_query_rmp_in_bits { 3815 u8 opcode[0x10]; 3816 u8 reserved_at_10[0x10]; 3817 3818 u8 reserved_at_20[0x10]; 3819 u8 op_mod[0x10]; 3820 3821 u8 reserved_at_40[0x8]; 3822 u8 rmpn[0x18]; 3823 3824 u8 reserved_at_60[0x20]; 3825 }; 3826 3827 struct mlx5_ifc_query_qp_out_bits { 3828 u8 status[0x8]; 3829 u8 reserved_at_8[0x18]; 3830 3831 u8 syndrome[0x20]; 3832 3833 u8 reserved_at_40[0x40]; 3834 3835 u8 opt_param_mask[0x20]; 3836 3837 u8 reserved_at_a0[0x20]; 3838 3839 struct mlx5_ifc_qpc_bits qpc; 3840 3841 u8 reserved_at_800[0x80]; 3842 3843 u8 pas[0][0x40]; 3844 }; 3845 3846 struct mlx5_ifc_query_qp_in_bits { 3847 u8 opcode[0x10]; 3848 u8 reserved_at_10[0x10]; 3849 3850 u8 reserved_at_20[0x10]; 3851 u8 op_mod[0x10]; 3852 3853 u8 reserved_at_40[0x8]; 3854 u8 qpn[0x18]; 3855 3856 u8 reserved_at_60[0x20]; 3857 }; 3858 3859 struct mlx5_ifc_query_q_counter_out_bits { 3860 u8 status[0x8]; 3861 u8 reserved_at_8[0x18]; 3862 3863 u8 syndrome[0x20]; 3864 3865 u8 reserved_at_40[0x40]; 3866 3867 u8 rx_write_requests[0x20]; 3868 3869 u8 reserved_at_a0[0x20]; 3870 3871 u8 rx_read_requests[0x20]; 3872 3873 u8 reserved_at_e0[0x20]; 3874 3875 u8 rx_atomic_requests[0x20]; 3876 3877 u8 reserved_at_120[0x20]; 3878 3879 u8 rx_dct_connect[0x20]; 3880 3881 u8 reserved_at_160[0x20]; 3882 3883 u8 out_of_buffer[0x20]; 3884 3885 u8 reserved_at_1a0[0x20]; 3886 3887 u8 out_of_sequence[0x20]; 3888 3889 u8 reserved_at_1e0[0x20]; 3890 3891 u8 duplicate_request[0x20]; 3892 3893 u8 reserved_at_220[0x20]; 3894 3895 u8 rnr_nak_retry_err[0x20]; 3896 3897 u8 reserved_at_260[0x20]; 3898 3899 u8 packet_seq_err[0x20]; 3900 3901 u8 reserved_at_2a0[0x20]; 3902 3903 u8 implied_nak_seq_err[0x20]; 3904 3905 u8 reserved_at_2e0[0x20]; 3906 3907 u8 local_ack_timeout_err[0x20]; 3908 3909 u8 reserved_at_320[0x4e0]; 3910 }; 3911 3912 struct mlx5_ifc_query_q_counter_in_bits { 3913 u8 opcode[0x10]; 3914 u8 reserved_at_10[0x10]; 3915 3916 u8 reserved_at_20[0x10]; 3917 u8 op_mod[0x10]; 3918 3919 u8 reserved_at_40[0x80]; 3920 3921 u8 clear[0x1]; 3922 u8 reserved_at_c1[0x1f]; 3923 3924 u8 reserved_at_e0[0x18]; 3925 u8 counter_set_id[0x8]; 3926 }; 3927 3928 struct mlx5_ifc_query_pages_out_bits { 3929 u8 status[0x8]; 3930 u8 reserved_at_8[0x18]; 3931 3932 u8 syndrome[0x20]; 3933 3934 u8 reserved_at_40[0x10]; 3935 u8 function_id[0x10]; 3936 3937 u8 num_pages[0x20]; 3938 }; 3939 3940 enum { 3941 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 3942 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 3943 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 3944 }; 3945 3946 struct mlx5_ifc_query_pages_in_bits { 3947 u8 opcode[0x10]; 3948 u8 reserved_at_10[0x10]; 3949 3950 u8 reserved_at_20[0x10]; 3951 u8 op_mod[0x10]; 3952 3953 u8 reserved_at_40[0x10]; 3954 u8 function_id[0x10]; 3955 3956 u8 reserved_at_60[0x20]; 3957 }; 3958 3959 struct mlx5_ifc_query_nic_vport_context_out_bits { 3960 u8 status[0x8]; 3961 u8 reserved_at_8[0x18]; 3962 3963 u8 syndrome[0x20]; 3964 3965 u8 reserved_at_40[0x40]; 3966 3967 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 3968 }; 3969 3970 struct mlx5_ifc_query_nic_vport_context_in_bits { 3971 u8 opcode[0x10]; 3972 u8 reserved_at_10[0x10]; 3973 3974 u8 reserved_at_20[0x10]; 3975 u8 op_mod[0x10]; 3976 3977 u8 other_vport[0x1]; 3978 u8 reserved_at_41[0xf]; 3979 u8 vport_number[0x10]; 3980 3981 u8 reserved_at_60[0x5]; 3982 u8 allowed_list_type[0x3]; 3983 u8 reserved_at_68[0x18]; 3984 }; 3985 3986 struct mlx5_ifc_query_mkey_out_bits { 3987 u8 status[0x8]; 3988 u8 reserved_at_8[0x18]; 3989 3990 u8 syndrome[0x20]; 3991 3992 u8 reserved_at_40[0x40]; 3993 3994 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 3995 3996 u8 reserved_at_280[0x600]; 3997 3998 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 3999 4000 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4001 }; 4002 4003 struct mlx5_ifc_query_mkey_in_bits { 4004 u8 opcode[0x10]; 4005 u8 reserved_at_10[0x10]; 4006 4007 u8 reserved_at_20[0x10]; 4008 u8 op_mod[0x10]; 4009 4010 u8 reserved_at_40[0x8]; 4011 u8 mkey_index[0x18]; 4012 4013 u8 pg_access[0x1]; 4014 u8 reserved_at_61[0x1f]; 4015 }; 4016 4017 struct mlx5_ifc_query_mad_demux_out_bits { 4018 u8 status[0x8]; 4019 u8 reserved_at_8[0x18]; 4020 4021 u8 syndrome[0x20]; 4022 4023 u8 reserved_at_40[0x40]; 4024 4025 u8 mad_dumux_parameters_block[0x20]; 4026 }; 4027 4028 struct mlx5_ifc_query_mad_demux_in_bits { 4029 u8 opcode[0x10]; 4030 u8 reserved_at_10[0x10]; 4031 4032 u8 reserved_at_20[0x10]; 4033 u8 op_mod[0x10]; 4034 4035 u8 reserved_at_40[0x40]; 4036 }; 4037 4038 struct mlx5_ifc_query_l2_table_entry_out_bits { 4039 u8 status[0x8]; 4040 u8 reserved_at_8[0x18]; 4041 4042 u8 syndrome[0x20]; 4043 4044 u8 reserved_at_40[0xa0]; 4045 4046 u8 reserved_at_e0[0x13]; 4047 u8 vlan_valid[0x1]; 4048 u8 vlan[0xc]; 4049 4050 struct mlx5_ifc_mac_address_layout_bits mac_address; 4051 4052 u8 reserved_at_140[0xc0]; 4053 }; 4054 4055 struct mlx5_ifc_query_l2_table_entry_in_bits { 4056 u8 opcode[0x10]; 4057 u8 reserved_at_10[0x10]; 4058 4059 u8 reserved_at_20[0x10]; 4060 u8 op_mod[0x10]; 4061 4062 u8 reserved_at_40[0x60]; 4063 4064 u8 reserved_at_a0[0x8]; 4065 u8 table_index[0x18]; 4066 4067 u8 reserved_at_c0[0x140]; 4068 }; 4069 4070 struct mlx5_ifc_query_issi_out_bits { 4071 u8 status[0x8]; 4072 u8 reserved_at_8[0x18]; 4073 4074 u8 syndrome[0x20]; 4075 4076 u8 reserved_at_40[0x10]; 4077 u8 current_issi[0x10]; 4078 4079 u8 reserved_at_60[0xa0]; 4080 4081 u8 reserved_at_100[76][0x8]; 4082 u8 supported_issi_dw0[0x20]; 4083 }; 4084 4085 struct mlx5_ifc_query_issi_in_bits { 4086 u8 opcode[0x10]; 4087 u8 reserved_at_10[0x10]; 4088 4089 u8 reserved_at_20[0x10]; 4090 u8 op_mod[0x10]; 4091 4092 u8 reserved_at_40[0x40]; 4093 }; 4094 4095 struct mlx5_ifc_set_driver_version_out_bits { 4096 u8 status[0x8]; 4097 u8 reserved_0[0x18]; 4098 4099 u8 syndrome[0x20]; 4100 u8 reserved_1[0x40]; 4101 }; 4102 4103 struct mlx5_ifc_set_driver_version_in_bits { 4104 u8 opcode[0x10]; 4105 u8 reserved_0[0x10]; 4106 4107 u8 reserved_1[0x10]; 4108 u8 op_mod[0x10]; 4109 4110 u8 reserved_2[0x40]; 4111 u8 driver_version[64][0x8]; 4112 }; 4113 4114 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4115 u8 status[0x8]; 4116 u8 reserved_at_8[0x18]; 4117 4118 u8 syndrome[0x20]; 4119 4120 u8 reserved_at_40[0x40]; 4121 4122 struct mlx5_ifc_pkey_bits pkey[0]; 4123 }; 4124 4125 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4126 u8 opcode[0x10]; 4127 u8 reserved_at_10[0x10]; 4128 4129 u8 reserved_at_20[0x10]; 4130 u8 op_mod[0x10]; 4131 4132 u8 other_vport[0x1]; 4133 u8 reserved_at_41[0xb]; 4134 u8 port_num[0x4]; 4135 u8 vport_number[0x10]; 4136 4137 u8 reserved_at_60[0x10]; 4138 u8 pkey_index[0x10]; 4139 }; 4140 4141 enum { 4142 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4143 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4144 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4145 }; 4146 4147 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4148 u8 status[0x8]; 4149 u8 reserved_at_8[0x18]; 4150 4151 u8 syndrome[0x20]; 4152 4153 u8 reserved_at_40[0x20]; 4154 4155 u8 gids_num[0x10]; 4156 u8 reserved_at_70[0x10]; 4157 4158 struct mlx5_ifc_array128_auto_bits gid[0]; 4159 }; 4160 4161 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4162 u8 opcode[0x10]; 4163 u8 reserved_at_10[0x10]; 4164 4165 u8 reserved_at_20[0x10]; 4166 u8 op_mod[0x10]; 4167 4168 u8 other_vport[0x1]; 4169 u8 reserved_at_41[0xb]; 4170 u8 port_num[0x4]; 4171 u8 vport_number[0x10]; 4172 4173 u8 reserved_at_60[0x10]; 4174 u8 gid_index[0x10]; 4175 }; 4176 4177 struct mlx5_ifc_query_hca_vport_context_out_bits { 4178 u8 status[0x8]; 4179 u8 reserved_at_8[0x18]; 4180 4181 u8 syndrome[0x20]; 4182 4183 u8 reserved_at_40[0x40]; 4184 4185 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4186 }; 4187 4188 struct mlx5_ifc_query_hca_vport_context_in_bits { 4189 u8 opcode[0x10]; 4190 u8 reserved_at_10[0x10]; 4191 4192 u8 reserved_at_20[0x10]; 4193 u8 op_mod[0x10]; 4194 4195 u8 other_vport[0x1]; 4196 u8 reserved_at_41[0xb]; 4197 u8 port_num[0x4]; 4198 u8 vport_number[0x10]; 4199 4200 u8 reserved_at_60[0x20]; 4201 }; 4202 4203 struct mlx5_ifc_query_hca_cap_out_bits { 4204 u8 status[0x8]; 4205 u8 reserved_at_8[0x18]; 4206 4207 u8 syndrome[0x20]; 4208 4209 u8 reserved_at_40[0x40]; 4210 4211 union mlx5_ifc_hca_cap_union_bits capability; 4212 }; 4213 4214 struct mlx5_ifc_query_hca_cap_in_bits { 4215 u8 opcode[0x10]; 4216 u8 reserved_at_10[0x10]; 4217 4218 u8 reserved_at_20[0x10]; 4219 u8 op_mod[0x10]; 4220 4221 u8 reserved_at_40[0x40]; 4222 }; 4223 4224 struct mlx5_ifc_query_flow_table_out_bits { 4225 u8 status[0x8]; 4226 u8 reserved_at_8[0x18]; 4227 4228 u8 syndrome[0x20]; 4229 4230 u8 reserved_at_40[0x80]; 4231 4232 u8 reserved_at_c0[0x8]; 4233 u8 level[0x8]; 4234 u8 reserved_at_d0[0x8]; 4235 u8 log_size[0x8]; 4236 4237 u8 reserved_at_e0[0x120]; 4238 }; 4239 4240 struct mlx5_ifc_query_flow_table_in_bits { 4241 u8 opcode[0x10]; 4242 u8 reserved_at_10[0x10]; 4243 4244 u8 reserved_at_20[0x10]; 4245 u8 op_mod[0x10]; 4246 4247 u8 reserved_at_40[0x40]; 4248 4249 u8 table_type[0x8]; 4250 u8 reserved_at_88[0x18]; 4251 4252 u8 reserved_at_a0[0x8]; 4253 u8 table_id[0x18]; 4254 4255 u8 reserved_at_c0[0x140]; 4256 }; 4257 4258 struct mlx5_ifc_query_fte_out_bits { 4259 u8 status[0x8]; 4260 u8 reserved_at_8[0x18]; 4261 4262 u8 syndrome[0x20]; 4263 4264 u8 reserved_at_40[0x1c0]; 4265 4266 struct mlx5_ifc_flow_context_bits flow_context; 4267 }; 4268 4269 struct mlx5_ifc_query_fte_in_bits { 4270 u8 opcode[0x10]; 4271 u8 reserved_at_10[0x10]; 4272 4273 u8 reserved_at_20[0x10]; 4274 u8 op_mod[0x10]; 4275 4276 u8 reserved_at_40[0x40]; 4277 4278 u8 table_type[0x8]; 4279 u8 reserved_at_88[0x18]; 4280 4281 u8 reserved_at_a0[0x8]; 4282 u8 table_id[0x18]; 4283 4284 u8 reserved_at_c0[0x40]; 4285 4286 u8 flow_index[0x20]; 4287 4288 u8 reserved_at_120[0xe0]; 4289 }; 4290 4291 enum { 4292 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4293 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4294 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4295 }; 4296 4297 struct mlx5_ifc_query_flow_group_out_bits { 4298 u8 status[0x8]; 4299 u8 reserved_at_8[0x18]; 4300 4301 u8 syndrome[0x20]; 4302 4303 u8 reserved_at_40[0xa0]; 4304 4305 u8 start_flow_index[0x20]; 4306 4307 u8 reserved_at_100[0x20]; 4308 4309 u8 end_flow_index[0x20]; 4310 4311 u8 reserved_at_140[0xa0]; 4312 4313 u8 reserved_at_1e0[0x18]; 4314 u8 match_criteria_enable[0x8]; 4315 4316 struct mlx5_ifc_fte_match_param_bits match_criteria; 4317 4318 u8 reserved_at_1200[0xe00]; 4319 }; 4320 4321 struct mlx5_ifc_query_flow_group_in_bits { 4322 u8 opcode[0x10]; 4323 u8 reserved_at_10[0x10]; 4324 4325 u8 reserved_at_20[0x10]; 4326 u8 op_mod[0x10]; 4327 4328 u8 reserved_at_40[0x40]; 4329 4330 u8 table_type[0x8]; 4331 u8 reserved_at_88[0x18]; 4332 4333 u8 reserved_at_a0[0x8]; 4334 u8 table_id[0x18]; 4335 4336 u8 group_id[0x20]; 4337 4338 u8 reserved_at_e0[0x120]; 4339 }; 4340 4341 struct mlx5_ifc_query_flow_counter_out_bits { 4342 u8 status[0x8]; 4343 u8 reserved_at_8[0x18]; 4344 4345 u8 syndrome[0x20]; 4346 4347 u8 reserved_at_40[0x40]; 4348 4349 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4350 }; 4351 4352 struct mlx5_ifc_query_flow_counter_in_bits { 4353 u8 opcode[0x10]; 4354 u8 reserved_at_10[0x10]; 4355 4356 u8 reserved_at_20[0x10]; 4357 u8 op_mod[0x10]; 4358 4359 u8 reserved_at_40[0x80]; 4360 4361 u8 clear[0x1]; 4362 u8 reserved_at_c1[0xf]; 4363 u8 num_of_counters[0x10]; 4364 4365 u8 reserved_at_e0[0x10]; 4366 u8 flow_counter_id[0x10]; 4367 }; 4368 4369 struct mlx5_ifc_query_esw_vport_context_out_bits { 4370 u8 status[0x8]; 4371 u8 reserved_at_8[0x18]; 4372 4373 u8 syndrome[0x20]; 4374 4375 u8 reserved_at_40[0x40]; 4376 4377 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4378 }; 4379 4380 struct mlx5_ifc_query_esw_vport_context_in_bits { 4381 u8 opcode[0x10]; 4382 u8 reserved_at_10[0x10]; 4383 4384 u8 reserved_at_20[0x10]; 4385 u8 op_mod[0x10]; 4386 4387 u8 other_vport[0x1]; 4388 u8 reserved_at_41[0xf]; 4389 u8 vport_number[0x10]; 4390 4391 u8 reserved_at_60[0x20]; 4392 }; 4393 4394 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4395 u8 status[0x8]; 4396 u8 reserved_at_8[0x18]; 4397 4398 u8 syndrome[0x20]; 4399 4400 u8 reserved_at_40[0x40]; 4401 }; 4402 4403 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4404 u8 reserved_at_0[0x1c]; 4405 u8 vport_cvlan_insert[0x1]; 4406 u8 vport_svlan_insert[0x1]; 4407 u8 vport_cvlan_strip[0x1]; 4408 u8 vport_svlan_strip[0x1]; 4409 }; 4410 4411 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4412 u8 opcode[0x10]; 4413 u8 reserved_at_10[0x10]; 4414 4415 u8 reserved_at_20[0x10]; 4416 u8 op_mod[0x10]; 4417 4418 u8 other_vport[0x1]; 4419 u8 reserved_at_41[0xf]; 4420 u8 vport_number[0x10]; 4421 4422 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4423 4424 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4425 }; 4426 4427 struct mlx5_ifc_query_eq_out_bits { 4428 u8 status[0x8]; 4429 u8 reserved_at_8[0x18]; 4430 4431 u8 syndrome[0x20]; 4432 4433 u8 reserved_at_40[0x40]; 4434 4435 struct mlx5_ifc_eqc_bits eq_context_entry; 4436 4437 u8 reserved_at_280[0x40]; 4438 4439 u8 event_bitmask[0x40]; 4440 4441 u8 reserved_at_300[0x580]; 4442 4443 u8 pas[0][0x40]; 4444 }; 4445 4446 struct mlx5_ifc_query_eq_in_bits { 4447 u8 opcode[0x10]; 4448 u8 reserved_at_10[0x10]; 4449 4450 u8 reserved_at_20[0x10]; 4451 u8 op_mod[0x10]; 4452 4453 u8 reserved_at_40[0x18]; 4454 u8 eq_number[0x8]; 4455 4456 u8 reserved_at_60[0x20]; 4457 }; 4458 4459 struct mlx5_ifc_encap_header_in_bits { 4460 u8 reserved_at_0[0x5]; 4461 u8 header_type[0x3]; 4462 u8 reserved_at_8[0xe]; 4463 u8 encap_header_size[0xa]; 4464 4465 u8 reserved_at_20[0x10]; 4466 u8 encap_header[2][0x8]; 4467 4468 u8 more_encap_header[0][0x8]; 4469 }; 4470 4471 struct mlx5_ifc_query_encap_header_out_bits { 4472 u8 status[0x8]; 4473 u8 reserved_at_8[0x18]; 4474 4475 u8 syndrome[0x20]; 4476 4477 u8 reserved_at_40[0xa0]; 4478 4479 struct mlx5_ifc_encap_header_in_bits encap_header[0]; 4480 }; 4481 4482 struct mlx5_ifc_query_encap_header_in_bits { 4483 u8 opcode[0x10]; 4484 u8 reserved_at_10[0x10]; 4485 4486 u8 reserved_at_20[0x10]; 4487 u8 op_mod[0x10]; 4488 4489 u8 encap_id[0x20]; 4490 4491 u8 reserved_at_60[0xa0]; 4492 }; 4493 4494 struct mlx5_ifc_alloc_encap_header_out_bits { 4495 u8 status[0x8]; 4496 u8 reserved_at_8[0x18]; 4497 4498 u8 syndrome[0x20]; 4499 4500 u8 encap_id[0x20]; 4501 4502 u8 reserved_at_60[0x20]; 4503 }; 4504 4505 struct mlx5_ifc_alloc_encap_header_in_bits { 4506 u8 opcode[0x10]; 4507 u8 reserved_at_10[0x10]; 4508 4509 u8 reserved_at_20[0x10]; 4510 u8 op_mod[0x10]; 4511 4512 u8 reserved_at_40[0xa0]; 4513 4514 struct mlx5_ifc_encap_header_in_bits encap_header; 4515 }; 4516 4517 struct mlx5_ifc_dealloc_encap_header_out_bits { 4518 u8 status[0x8]; 4519 u8 reserved_at_8[0x18]; 4520 4521 u8 syndrome[0x20]; 4522 4523 u8 reserved_at_40[0x40]; 4524 }; 4525 4526 struct mlx5_ifc_dealloc_encap_header_in_bits { 4527 u8 opcode[0x10]; 4528 u8 reserved_at_10[0x10]; 4529 4530 u8 reserved_20[0x10]; 4531 u8 op_mod[0x10]; 4532 4533 u8 encap_id[0x20]; 4534 4535 u8 reserved_60[0x20]; 4536 }; 4537 4538 struct mlx5_ifc_query_dct_out_bits { 4539 u8 status[0x8]; 4540 u8 reserved_at_8[0x18]; 4541 4542 u8 syndrome[0x20]; 4543 4544 u8 reserved_at_40[0x40]; 4545 4546 struct mlx5_ifc_dctc_bits dct_context_entry; 4547 4548 u8 reserved_at_280[0x180]; 4549 }; 4550 4551 struct mlx5_ifc_query_dct_in_bits { 4552 u8 opcode[0x10]; 4553 u8 reserved_at_10[0x10]; 4554 4555 u8 reserved_at_20[0x10]; 4556 u8 op_mod[0x10]; 4557 4558 u8 reserved_at_40[0x8]; 4559 u8 dctn[0x18]; 4560 4561 u8 reserved_at_60[0x20]; 4562 }; 4563 4564 struct mlx5_ifc_query_cq_out_bits { 4565 u8 status[0x8]; 4566 u8 reserved_at_8[0x18]; 4567 4568 u8 syndrome[0x20]; 4569 4570 u8 reserved_at_40[0x40]; 4571 4572 struct mlx5_ifc_cqc_bits cq_context; 4573 4574 u8 reserved_at_280[0x600]; 4575 4576 u8 pas[0][0x40]; 4577 }; 4578 4579 struct mlx5_ifc_query_cq_in_bits { 4580 u8 opcode[0x10]; 4581 u8 reserved_at_10[0x10]; 4582 4583 u8 reserved_at_20[0x10]; 4584 u8 op_mod[0x10]; 4585 4586 u8 reserved_at_40[0x8]; 4587 u8 cqn[0x18]; 4588 4589 u8 reserved_at_60[0x20]; 4590 }; 4591 4592 struct mlx5_ifc_query_cong_status_out_bits { 4593 u8 status[0x8]; 4594 u8 reserved_at_8[0x18]; 4595 4596 u8 syndrome[0x20]; 4597 4598 u8 reserved_at_40[0x20]; 4599 4600 u8 enable[0x1]; 4601 u8 tag_enable[0x1]; 4602 u8 reserved_at_62[0x1e]; 4603 }; 4604 4605 struct mlx5_ifc_query_cong_status_in_bits { 4606 u8 opcode[0x10]; 4607 u8 reserved_at_10[0x10]; 4608 4609 u8 reserved_at_20[0x10]; 4610 u8 op_mod[0x10]; 4611 4612 u8 reserved_at_40[0x18]; 4613 u8 priority[0x4]; 4614 u8 cong_protocol[0x4]; 4615 4616 u8 reserved_at_60[0x20]; 4617 }; 4618 4619 struct mlx5_ifc_query_cong_statistics_out_bits { 4620 u8 status[0x8]; 4621 u8 reserved_at_8[0x18]; 4622 4623 u8 syndrome[0x20]; 4624 4625 u8 reserved_at_40[0x40]; 4626 4627 u8 cur_flows[0x20]; 4628 4629 u8 sum_flows[0x20]; 4630 4631 u8 cnp_ignored_high[0x20]; 4632 4633 u8 cnp_ignored_low[0x20]; 4634 4635 u8 cnp_handled_high[0x20]; 4636 4637 u8 cnp_handled_low[0x20]; 4638 4639 u8 reserved_at_140[0x100]; 4640 4641 u8 time_stamp_high[0x20]; 4642 4643 u8 time_stamp_low[0x20]; 4644 4645 u8 accumulators_period[0x20]; 4646 4647 u8 ecn_marked_roce_packets_high[0x20]; 4648 4649 u8 ecn_marked_roce_packets_low[0x20]; 4650 4651 u8 cnps_sent_high[0x20]; 4652 4653 u8 cnps_sent_low[0x20]; 4654 4655 u8 reserved_at_320[0x560]; 4656 }; 4657 4658 struct mlx5_ifc_query_cong_statistics_in_bits { 4659 u8 opcode[0x10]; 4660 u8 reserved_at_10[0x10]; 4661 4662 u8 reserved_at_20[0x10]; 4663 u8 op_mod[0x10]; 4664 4665 u8 clear[0x1]; 4666 u8 reserved_at_41[0x1f]; 4667 4668 u8 reserved_at_60[0x20]; 4669 }; 4670 4671 struct mlx5_ifc_query_cong_params_out_bits { 4672 u8 status[0x8]; 4673 u8 reserved_at_8[0x18]; 4674 4675 u8 syndrome[0x20]; 4676 4677 u8 reserved_at_40[0x40]; 4678 4679 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4680 }; 4681 4682 struct mlx5_ifc_query_cong_params_in_bits { 4683 u8 opcode[0x10]; 4684 u8 reserved_at_10[0x10]; 4685 4686 u8 reserved_at_20[0x10]; 4687 u8 op_mod[0x10]; 4688 4689 u8 reserved_at_40[0x1c]; 4690 u8 cong_protocol[0x4]; 4691 4692 u8 reserved_at_60[0x20]; 4693 }; 4694 4695 struct mlx5_ifc_query_adapter_out_bits { 4696 u8 status[0x8]; 4697 u8 reserved_at_8[0x18]; 4698 4699 u8 syndrome[0x20]; 4700 4701 u8 reserved_at_40[0x40]; 4702 4703 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 4704 }; 4705 4706 struct mlx5_ifc_query_adapter_in_bits { 4707 u8 opcode[0x10]; 4708 u8 reserved_at_10[0x10]; 4709 4710 u8 reserved_at_20[0x10]; 4711 u8 op_mod[0x10]; 4712 4713 u8 reserved_at_40[0x40]; 4714 }; 4715 4716 struct mlx5_ifc_qp_2rst_out_bits { 4717 u8 status[0x8]; 4718 u8 reserved_at_8[0x18]; 4719 4720 u8 syndrome[0x20]; 4721 4722 u8 reserved_at_40[0x40]; 4723 }; 4724 4725 struct mlx5_ifc_qp_2rst_in_bits { 4726 u8 opcode[0x10]; 4727 u8 reserved_at_10[0x10]; 4728 4729 u8 reserved_at_20[0x10]; 4730 u8 op_mod[0x10]; 4731 4732 u8 reserved_at_40[0x8]; 4733 u8 qpn[0x18]; 4734 4735 u8 reserved_at_60[0x20]; 4736 }; 4737 4738 struct mlx5_ifc_qp_2err_out_bits { 4739 u8 status[0x8]; 4740 u8 reserved_at_8[0x18]; 4741 4742 u8 syndrome[0x20]; 4743 4744 u8 reserved_at_40[0x40]; 4745 }; 4746 4747 struct mlx5_ifc_qp_2err_in_bits { 4748 u8 opcode[0x10]; 4749 u8 reserved_at_10[0x10]; 4750 4751 u8 reserved_at_20[0x10]; 4752 u8 op_mod[0x10]; 4753 4754 u8 reserved_at_40[0x8]; 4755 u8 qpn[0x18]; 4756 4757 u8 reserved_at_60[0x20]; 4758 }; 4759 4760 struct mlx5_ifc_page_fault_resume_out_bits { 4761 u8 status[0x8]; 4762 u8 reserved_at_8[0x18]; 4763 4764 u8 syndrome[0x20]; 4765 4766 u8 reserved_at_40[0x40]; 4767 }; 4768 4769 struct mlx5_ifc_page_fault_resume_in_bits { 4770 u8 opcode[0x10]; 4771 u8 reserved_at_10[0x10]; 4772 4773 u8 reserved_at_20[0x10]; 4774 u8 op_mod[0x10]; 4775 4776 u8 error[0x1]; 4777 u8 reserved_at_41[0x4]; 4778 u8 page_fault_type[0x3]; 4779 u8 wq_number[0x18]; 4780 4781 u8 reserved_at_60[0x8]; 4782 u8 token[0x18]; 4783 }; 4784 4785 struct mlx5_ifc_nop_out_bits { 4786 u8 status[0x8]; 4787 u8 reserved_at_8[0x18]; 4788 4789 u8 syndrome[0x20]; 4790 4791 u8 reserved_at_40[0x40]; 4792 }; 4793 4794 struct mlx5_ifc_nop_in_bits { 4795 u8 opcode[0x10]; 4796 u8 reserved_at_10[0x10]; 4797 4798 u8 reserved_at_20[0x10]; 4799 u8 op_mod[0x10]; 4800 4801 u8 reserved_at_40[0x40]; 4802 }; 4803 4804 struct mlx5_ifc_modify_vport_state_out_bits { 4805 u8 status[0x8]; 4806 u8 reserved_at_8[0x18]; 4807 4808 u8 syndrome[0x20]; 4809 4810 u8 reserved_at_40[0x40]; 4811 }; 4812 4813 struct mlx5_ifc_modify_vport_state_in_bits { 4814 u8 opcode[0x10]; 4815 u8 reserved_at_10[0x10]; 4816 4817 u8 reserved_at_20[0x10]; 4818 u8 op_mod[0x10]; 4819 4820 u8 other_vport[0x1]; 4821 u8 reserved_at_41[0xf]; 4822 u8 vport_number[0x10]; 4823 4824 u8 reserved_at_60[0x18]; 4825 u8 admin_state[0x4]; 4826 u8 reserved_at_7c[0x4]; 4827 }; 4828 4829 struct mlx5_ifc_modify_tis_out_bits { 4830 u8 status[0x8]; 4831 u8 reserved_at_8[0x18]; 4832 4833 u8 syndrome[0x20]; 4834 4835 u8 reserved_at_40[0x40]; 4836 }; 4837 4838 struct mlx5_ifc_modify_tis_bitmask_bits { 4839 u8 reserved_at_0[0x20]; 4840 4841 u8 reserved_at_20[0x1d]; 4842 u8 lag_tx_port_affinity[0x1]; 4843 u8 strict_lag_tx_port_affinity[0x1]; 4844 u8 prio[0x1]; 4845 }; 4846 4847 struct mlx5_ifc_modify_tis_in_bits { 4848 u8 opcode[0x10]; 4849 u8 reserved_at_10[0x10]; 4850 4851 u8 reserved_at_20[0x10]; 4852 u8 op_mod[0x10]; 4853 4854 u8 reserved_at_40[0x8]; 4855 u8 tisn[0x18]; 4856 4857 u8 reserved_at_60[0x20]; 4858 4859 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 4860 4861 u8 reserved_at_c0[0x40]; 4862 4863 struct mlx5_ifc_tisc_bits ctx; 4864 }; 4865 4866 struct mlx5_ifc_modify_tir_bitmask_bits { 4867 u8 reserved_at_0[0x20]; 4868 4869 u8 reserved_at_20[0x1b]; 4870 u8 self_lb_en[0x1]; 4871 u8 reserved_at_3c[0x1]; 4872 u8 hash[0x1]; 4873 u8 reserved_at_3e[0x1]; 4874 u8 lro[0x1]; 4875 }; 4876 4877 struct mlx5_ifc_modify_tir_out_bits { 4878 u8 status[0x8]; 4879 u8 reserved_at_8[0x18]; 4880 4881 u8 syndrome[0x20]; 4882 4883 u8 reserved_at_40[0x40]; 4884 }; 4885 4886 struct mlx5_ifc_modify_tir_in_bits { 4887 u8 opcode[0x10]; 4888 u8 reserved_at_10[0x10]; 4889 4890 u8 reserved_at_20[0x10]; 4891 u8 op_mod[0x10]; 4892 4893 u8 reserved_at_40[0x8]; 4894 u8 tirn[0x18]; 4895 4896 u8 reserved_at_60[0x20]; 4897 4898 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 4899 4900 u8 reserved_at_c0[0x40]; 4901 4902 struct mlx5_ifc_tirc_bits ctx; 4903 }; 4904 4905 struct mlx5_ifc_modify_sq_out_bits { 4906 u8 status[0x8]; 4907 u8 reserved_at_8[0x18]; 4908 4909 u8 syndrome[0x20]; 4910 4911 u8 reserved_at_40[0x40]; 4912 }; 4913 4914 struct mlx5_ifc_modify_sq_in_bits { 4915 u8 opcode[0x10]; 4916 u8 reserved_at_10[0x10]; 4917 4918 u8 reserved_at_20[0x10]; 4919 u8 op_mod[0x10]; 4920 4921 u8 sq_state[0x4]; 4922 u8 reserved_at_44[0x4]; 4923 u8 sqn[0x18]; 4924 4925 u8 reserved_at_60[0x20]; 4926 4927 u8 modify_bitmask[0x40]; 4928 4929 u8 reserved_at_c0[0x40]; 4930 4931 struct mlx5_ifc_sqc_bits ctx; 4932 }; 4933 4934 struct mlx5_ifc_modify_scheduling_element_out_bits { 4935 u8 status[0x8]; 4936 u8 reserved_at_8[0x18]; 4937 4938 u8 syndrome[0x20]; 4939 4940 u8 reserved_at_40[0x1c0]; 4941 }; 4942 4943 enum { 4944 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 4945 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 4946 }; 4947 4948 struct mlx5_ifc_modify_scheduling_element_in_bits { 4949 u8 opcode[0x10]; 4950 u8 reserved_at_10[0x10]; 4951 4952 u8 reserved_at_20[0x10]; 4953 u8 op_mod[0x10]; 4954 4955 u8 scheduling_hierarchy[0x8]; 4956 u8 reserved_at_48[0x18]; 4957 4958 u8 scheduling_element_id[0x20]; 4959 4960 u8 reserved_at_80[0x20]; 4961 4962 u8 modify_bitmask[0x20]; 4963 4964 u8 reserved_at_c0[0x40]; 4965 4966 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4967 4968 u8 reserved_at_300[0x100]; 4969 }; 4970 4971 struct mlx5_ifc_modify_rqt_out_bits { 4972 u8 status[0x8]; 4973 u8 reserved_at_8[0x18]; 4974 4975 u8 syndrome[0x20]; 4976 4977 u8 reserved_at_40[0x40]; 4978 }; 4979 4980 struct mlx5_ifc_rqt_bitmask_bits { 4981 u8 reserved_at_0[0x20]; 4982 4983 u8 reserved_at_20[0x1f]; 4984 u8 rqn_list[0x1]; 4985 }; 4986 4987 struct mlx5_ifc_modify_rqt_in_bits { 4988 u8 opcode[0x10]; 4989 u8 reserved_at_10[0x10]; 4990 4991 u8 reserved_at_20[0x10]; 4992 u8 op_mod[0x10]; 4993 4994 u8 reserved_at_40[0x8]; 4995 u8 rqtn[0x18]; 4996 4997 u8 reserved_at_60[0x20]; 4998 4999 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5000 5001 u8 reserved_at_c0[0x40]; 5002 5003 struct mlx5_ifc_rqtc_bits ctx; 5004 }; 5005 5006 struct mlx5_ifc_modify_rq_out_bits { 5007 u8 status[0x8]; 5008 u8 reserved_at_8[0x18]; 5009 5010 u8 syndrome[0x20]; 5011 5012 u8 reserved_at_40[0x40]; 5013 }; 5014 5015 enum { 5016 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5017 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5018 }; 5019 5020 struct mlx5_ifc_modify_rq_in_bits { 5021 u8 opcode[0x10]; 5022 u8 reserved_at_10[0x10]; 5023 5024 u8 reserved_at_20[0x10]; 5025 u8 op_mod[0x10]; 5026 5027 u8 rq_state[0x4]; 5028 u8 reserved_at_44[0x4]; 5029 u8 rqn[0x18]; 5030 5031 u8 reserved_at_60[0x20]; 5032 5033 u8 modify_bitmask[0x40]; 5034 5035 u8 reserved_at_c0[0x40]; 5036 5037 struct mlx5_ifc_rqc_bits ctx; 5038 }; 5039 5040 struct mlx5_ifc_modify_rmp_out_bits { 5041 u8 status[0x8]; 5042 u8 reserved_at_8[0x18]; 5043 5044 u8 syndrome[0x20]; 5045 5046 u8 reserved_at_40[0x40]; 5047 }; 5048 5049 struct mlx5_ifc_rmp_bitmask_bits { 5050 u8 reserved_at_0[0x20]; 5051 5052 u8 reserved_at_20[0x1f]; 5053 u8 lwm[0x1]; 5054 }; 5055 5056 struct mlx5_ifc_modify_rmp_in_bits { 5057 u8 opcode[0x10]; 5058 u8 reserved_at_10[0x10]; 5059 5060 u8 reserved_at_20[0x10]; 5061 u8 op_mod[0x10]; 5062 5063 u8 rmp_state[0x4]; 5064 u8 reserved_at_44[0x4]; 5065 u8 rmpn[0x18]; 5066 5067 u8 reserved_at_60[0x20]; 5068 5069 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5070 5071 u8 reserved_at_c0[0x40]; 5072 5073 struct mlx5_ifc_rmpc_bits ctx; 5074 }; 5075 5076 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5077 u8 status[0x8]; 5078 u8 reserved_at_8[0x18]; 5079 5080 u8 syndrome[0x20]; 5081 5082 u8 reserved_at_40[0x40]; 5083 }; 5084 5085 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5086 u8 reserved_at_0[0x16]; 5087 u8 node_guid[0x1]; 5088 u8 port_guid[0x1]; 5089 u8 min_inline[0x1]; 5090 u8 mtu[0x1]; 5091 u8 change_event[0x1]; 5092 u8 promisc[0x1]; 5093 u8 permanent_address[0x1]; 5094 u8 addresses_list[0x1]; 5095 u8 roce_en[0x1]; 5096 u8 reserved_at_1f[0x1]; 5097 }; 5098 5099 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5100 u8 opcode[0x10]; 5101 u8 reserved_at_10[0x10]; 5102 5103 u8 reserved_at_20[0x10]; 5104 u8 op_mod[0x10]; 5105 5106 u8 other_vport[0x1]; 5107 u8 reserved_at_41[0xf]; 5108 u8 vport_number[0x10]; 5109 5110 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5111 5112 u8 reserved_at_80[0x780]; 5113 5114 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5115 }; 5116 5117 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5118 u8 status[0x8]; 5119 u8 reserved_at_8[0x18]; 5120 5121 u8 syndrome[0x20]; 5122 5123 u8 reserved_at_40[0x40]; 5124 }; 5125 5126 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5127 u8 opcode[0x10]; 5128 u8 reserved_at_10[0x10]; 5129 5130 u8 reserved_at_20[0x10]; 5131 u8 op_mod[0x10]; 5132 5133 u8 other_vport[0x1]; 5134 u8 reserved_at_41[0xb]; 5135 u8 port_num[0x4]; 5136 u8 vport_number[0x10]; 5137 5138 u8 reserved_at_60[0x20]; 5139 5140 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5141 }; 5142 5143 struct mlx5_ifc_modify_cq_out_bits { 5144 u8 status[0x8]; 5145 u8 reserved_at_8[0x18]; 5146 5147 u8 syndrome[0x20]; 5148 5149 u8 reserved_at_40[0x40]; 5150 }; 5151 5152 enum { 5153 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5154 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5155 }; 5156 5157 struct mlx5_ifc_modify_cq_in_bits { 5158 u8 opcode[0x10]; 5159 u8 reserved_at_10[0x10]; 5160 5161 u8 reserved_at_20[0x10]; 5162 u8 op_mod[0x10]; 5163 5164 u8 reserved_at_40[0x8]; 5165 u8 cqn[0x18]; 5166 5167 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5168 5169 struct mlx5_ifc_cqc_bits cq_context; 5170 5171 u8 reserved_at_280[0x600]; 5172 5173 u8 pas[0][0x40]; 5174 }; 5175 5176 struct mlx5_ifc_modify_cong_status_out_bits { 5177 u8 status[0x8]; 5178 u8 reserved_at_8[0x18]; 5179 5180 u8 syndrome[0x20]; 5181 5182 u8 reserved_at_40[0x40]; 5183 }; 5184 5185 struct mlx5_ifc_modify_cong_status_in_bits { 5186 u8 opcode[0x10]; 5187 u8 reserved_at_10[0x10]; 5188 5189 u8 reserved_at_20[0x10]; 5190 u8 op_mod[0x10]; 5191 5192 u8 reserved_at_40[0x18]; 5193 u8 priority[0x4]; 5194 u8 cong_protocol[0x4]; 5195 5196 u8 enable[0x1]; 5197 u8 tag_enable[0x1]; 5198 u8 reserved_at_62[0x1e]; 5199 }; 5200 5201 struct mlx5_ifc_modify_cong_params_out_bits { 5202 u8 status[0x8]; 5203 u8 reserved_at_8[0x18]; 5204 5205 u8 syndrome[0x20]; 5206 5207 u8 reserved_at_40[0x40]; 5208 }; 5209 5210 struct mlx5_ifc_modify_cong_params_in_bits { 5211 u8 opcode[0x10]; 5212 u8 reserved_at_10[0x10]; 5213 5214 u8 reserved_at_20[0x10]; 5215 u8 op_mod[0x10]; 5216 5217 u8 reserved_at_40[0x1c]; 5218 u8 cong_protocol[0x4]; 5219 5220 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5221 5222 u8 reserved_at_80[0x80]; 5223 5224 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5225 }; 5226 5227 struct mlx5_ifc_manage_pages_out_bits { 5228 u8 status[0x8]; 5229 u8 reserved_at_8[0x18]; 5230 5231 u8 syndrome[0x20]; 5232 5233 u8 output_num_entries[0x20]; 5234 5235 u8 reserved_at_60[0x20]; 5236 5237 u8 pas[0][0x40]; 5238 }; 5239 5240 enum { 5241 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5242 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5243 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5244 }; 5245 5246 struct mlx5_ifc_manage_pages_in_bits { 5247 u8 opcode[0x10]; 5248 u8 reserved_at_10[0x10]; 5249 5250 u8 reserved_at_20[0x10]; 5251 u8 op_mod[0x10]; 5252 5253 u8 reserved_at_40[0x10]; 5254 u8 function_id[0x10]; 5255 5256 u8 input_num_entries[0x20]; 5257 5258 u8 pas[0][0x40]; 5259 }; 5260 5261 struct mlx5_ifc_mad_ifc_out_bits { 5262 u8 status[0x8]; 5263 u8 reserved_at_8[0x18]; 5264 5265 u8 syndrome[0x20]; 5266 5267 u8 reserved_at_40[0x40]; 5268 5269 u8 response_mad_packet[256][0x8]; 5270 }; 5271 5272 struct mlx5_ifc_mad_ifc_in_bits { 5273 u8 opcode[0x10]; 5274 u8 reserved_at_10[0x10]; 5275 5276 u8 reserved_at_20[0x10]; 5277 u8 op_mod[0x10]; 5278 5279 u8 remote_lid[0x10]; 5280 u8 reserved_at_50[0x8]; 5281 u8 port[0x8]; 5282 5283 u8 reserved_at_60[0x20]; 5284 5285 u8 mad[256][0x8]; 5286 }; 5287 5288 struct mlx5_ifc_init_hca_out_bits { 5289 u8 status[0x8]; 5290 u8 reserved_at_8[0x18]; 5291 5292 u8 syndrome[0x20]; 5293 5294 u8 reserved_at_40[0x40]; 5295 }; 5296 5297 struct mlx5_ifc_init_hca_in_bits { 5298 u8 opcode[0x10]; 5299 u8 reserved_at_10[0x10]; 5300 5301 u8 reserved_at_20[0x10]; 5302 u8 op_mod[0x10]; 5303 5304 u8 reserved_at_40[0x40]; 5305 }; 5306 5307 struct mlx5_ifc_init2rtr_qp_out_bits { 5308 u8 status[0x8]; 5309 u8 reserved_at_8[0x18]; 5310 5311 u8 syndrome[0x20]; 5312 5313 u8 reserved_at_40[0x40]; 5314 }; 5315 5316 struct mlx5_ifc_init2rtr_qp_in_bits { 5317 u8 opcode[0x10]; 5318 u8 reserved_at_10[0x10]; 5319 5320 u8 reserved_at_20[0x10]; 5321 u8 op_mod[0x10]; 5322 5323 u8 reserved_at_40[0x8]; 5324 u8 qpn[0x18]; 5325 5326 u8 reserved_at_60[0x20]; 5327 5328 u8 opt_param_mask[0x20]; 5329 5330 u8 reserved_at_a0[0x20]; 5331 5332 struct mlx5_ifc_qpc_bits qpc; 5333 5334 u8 reserved_at_800[0x80]; 5335 }; 5336 5337 struct mlx5_ifc_init2init_qp_out_bits { 5338 u8 status[0x8]; 5339 u8 reserved_at_8[0x18]; 5340 5341 u8 syndrome[0x20]; 5342 5343 u8 reserved_at_40[0x40]; 5344 }; 5345 5346 struct mlx5_ifc_init2init_qp_in_bits { 5347 u8 opcode[0x10]; 5348 u8 reserved_at_10[0x10]; 5349 5350 u8 reserved_at_20[0x10]; 5351 u8 op_mod[0x10]; 5352 5353 u8 reserved_at_40[0x8]; 5354 u8 qpn[0x18]; 5355 5356 u8 reserved_at_60[0x20]; 5357 5358 u8 opt_param_mask[0x20]; 5359 5360 u8 reserved_at_a0[0x20]; 5361 5362 struct mlx5_ifc_qpc_bits qpc; 5363 5364 u8 reserved_at_800[0x80]; 5365 }; 5366 5367 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5368 u8 status[0x8]; 5369 u8 reserved_at_8[0x18]; 5370 5371 u8 syndrome[0x20]; 5372 5373 u8 reserved_at_40[0x40]; 5374 5375 u8 packet_headers_log[128][0x8]; 5376 5377 u8 packet_syndrome[64][0x8]; 5378 }; 5379 5380 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5381 u8 opcode[0x10]; 5382 u8 reserved_at_10[0x10]; 5383 5384 u8 reserved_at_20[0x10]; 5385 u8 op_mod[0x10]; 5386 5387 u8 reserved_at_40[0x40]; 5388 }; 5389 5390 struct mlx5_ifc_gen_eqe_in_bits { 5391 u8 opcode[0x10]; 5392 u8 reserved_at_10[0x10]; 5393 5394 u8 reserved_at_20[0x10]; 5395 u8 op_mod[0x10]; 5396 5397 u8 reserved_at_40[0x18]; 5398 u8 eq_number[0x8]; 5399 5400 u8 reserved_at_60[0x20]; 5401 5402 u8 eqe[64][0x8]; 5403 }; 5404 5405 struct mlx5_ifc_gen_eq_out_bits { 5406 u8 status[0x8]; 5407 u8 reserved_at_8[0x18]; 5408 5409 u8 syndrome[0x20]; 5410 5411 u8 reserved_at_40[0x40]; 5412 }; 5413 5414 struct mlx5_ifc_enable_hca_out_bits { 5415 u8 status[0x8]; 5416 u8 reserved_at_8[0x18]; 5417 5418 u8 syndrome[0x20]; 5419 5420 u8 reserved_at_40[0x20]; 5421 }; 5422 5423 struct mlx5_ifc_enable_hca_in_bits { 5424 u8 opcode[0x10]; 5425 u8 reserved_at_10[0x10]; 5426 5427 u8 reserved_at_20[0x10]; 5428 u8 op_mod[0x10]; 5429 5430 u8 reserved_at_40[0x10]; 5431 u8 function_id[0x10]; 5432 5433 u8 reserved_at_60[0x20]; 5434 }; 5435 5436 struct mlx5_ifc_drain_dct_out_bits { 5437 u8 status[0x8]; 5438 u8 reserved_at_8[0x18]; 5439 5440 u8 syndrome[0x20]; 5441 5442 u8 reserved_at_40[0x40]; 5443 }; 5444 5445 struct mlx5_ifc_drain_dct_in_bits { 5446 u8 opcode[0x10]; 5447 u8 reserved_at_10[0x10]; 5448 5449 u8 reserved_at_20[0x10]; 5450 u8 op_mod[0x10]; 5451 5452 u8 reserved_at_40[0x8]; 5453 u8 dctn[0x18]; 5454 5455 u8 reserved_at_60[0x20]; 5456 }; 5457 5458 struct mlx5_ifc_disable_hca_out_bits { 5459 u8 status[0x8]; 5460 u8 reserved_at_8[0x18]; 5461 5462 u8 syndrome[0x20]; 5463 5464 u8 reserved_at_40[0x20]; 5465 }; 5466 5467 struct mlx5_ifc_disable_hca_in_bits { 5468 u8 opcode[0x10]; 5469 u8 reserved_at_10[0x10]; 5470 5471 u8 reserved_at_20[0x10]; 5472 u8 op_mod[0x10]; 5473 5474 u8 reserved_at_40[0x10]; 5475 u8 function_id[0x10]; 5476 5477 u8 reserved_at_60[0x20]; 5478 }; 5479 5480 struct mlx5_ifc_detach_from_mcg_out_bits { 5481 u8 status[0x8]; 5482 u8 reserved_at_8[0x18]; 5483 5484 u8 syndrome[0x20]; 5485 5486 u8 reserved_at_40[0x40]; 5487 }; 5488 5489 struct mlx5_ifc_detach_from_mcg_in_bits { 5490 u8 opcode[0x10]; 5491 u8 reserved_at_10[0x10]; 5492 5493 u8 reserved_at_20[0x10]; 5494 u8 op_mod[0x10]; 5495 5496 u8 reserved_at_40[0x8]; 5497 u8 qpn[0x18]; 5498 5499 u8 reserved_at_60[0x20]; 5500 5501 u8 multicast_gid[16][0x8]; 5502 }; 5503 5504 struct mlx5_ifc_destroy_xrq_out_bits { 5505 u8 status[0x8]; 5506 u8 reserved_at_8[0x18]; 5507 5508 u8 syndrome[0x20]; 5509 5510 u8 reserved_at_40[0x40]; 5511 }; 5512 5513 struct mlx5_ifc_destroy_xrq_in_bits { 5514 u8 opcode[0x10]; 5515 u8 reserved_at_10[0x10]; 5516 5517 u8 reserved_at_20[0x10]; 5518 u8 op_mod[0x10]; 5519 5520 u8 reserved_at_40[0x8]; 5521 u8 xrqn[0x18]; 5522 5523 u8 reserved_at_60[0x20]; 5524 }; 5525 5526 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5527 u8 status[0x8]; 5528 u8 reserved_at_8[0x18]; 5529 5530 u8 syndrome[0x20]; 5531 5532 u8 reserved_at_40[0x40]; 5533 }; 5534 5535 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5536 u8 opcode[0x10]; 5537 u8 reserved_at_10[0x10]; 5538 5539 u8 reserved_at_20[0x10]; 5540 u8 op_mod[0x10]; 5541 5542 u8 reserved_at_40[0x8]; 5543 u8 xrc_srqn[0x18]; 5544 5545 u8 reserved_at_60[0x20]; 5546 }; 5547 5548 struct mlx5_ifc_destroy_tis_out_bits { 5549 u8 status[0x8]; 5550 u8 reserved_at_8[0x18]; 5551 5552 u8 syndrome[0x20]; 5553 5554 u8 reserved_at_40[0x40]; 5555 }; 5556 5557 struct mlx5_ifc_destroy_tis_in_bits { 5558 u8 opcode[0x10]; 5559 u8 reserved_at_10[0x10]; 5560 5561 u8 reserved_at_20[0x10]; 5562 u8 op_mod[0x10]; 5563 5564 u8 reserved_at_40[0x8]; 5565 u8 tisn[0x18]; 5566 5567 u8 reserved_at_60[0x20]; 5568 }; 5569 5570 struct mlx5_ifc_destroy_tir_out_bits { 5571 u8 status[0x8]; 5572 u8 reserved_at_8[0x18]; 5573 5574 u8 syndrome[0x20]; 5575 5576 u8 reserved_at_40[0x40]; 5577 }; 5578 5579 struct mlx5_ifc_destroy_tir_in_bits { 5580 u8 opcode[0x10]; 5581 u8 reserved_at_10[0x10]; 5582 5583 u8 reserved_at_20[0x10]; 5584 u8 op_mod[0x10]; 5585 5586 u8 reserved_at_40[0x8]; 5587 u8 tirn[0x18]; 5588 5589 u8 reserved_at_60[0x20]; 5590 }; 5591 5592 struct mlx5_ifc_destroy_srq_out_bits { 5593 u8 status[0x8]; 5594 u8 reserved_at_8[0x18]; 5595 5596 u8 syndrome[0x20]; 5597 5598 u8 reserved_at_40[0x40]; 5599 }; 5600 5601 struct mlx5_ifc_destroy_srq_in_bits { 5602 u8 opcode[0x10]; 5603 u8 reserved_at_10[0x10]; 5604 5605 u8 reserved_at_20[0x10]; 5606 u8 op_mod[0x10]; 5607 5608 u8 reserved_at_40[0x8]; 5609 u8 srqn[0x18]; 5610 5611 u8 reserved_at_60[0x20]; 5612 }; 5613 5614 struct mlx5_ifc_destroy_sq_out_bits { 5615 u8 status[0x8]; 5616 u8 reserved_at_8[0x18]; 5617 5618 u8 syndrome[0x20]; 5619 5620 u8 reserved_at_40[0x40]; 5621 }; 5622 5623 struct mlx5_ifc_destroy_sq_in_bits { 5624 u8 opcode[0x10]; 5625 u8 reserved_at_10[0x10]; 5626 5627 u8 reserved_at_20[0x10]; 5628 u8 op_mod[0x10]; 5629 5630 u8 reserved_at_40[0x8]; 5631 u8 sqn[0x18]; 5632 5633 u8 reserved_at_60[0x20]; 5634 }; 5635 5636 struct mlx5_ifc_destroy_scheduling_element_out_bits { 5637 u8 status[0x8]; 5638 u8 reserved_at_8[0x18]; 5639 5640 u8 syndrome[0x20]; 5641 5642 u8 reserved_at_40[0x1c0]; 5643 }; 5644 5645 struct mlx5_ifc_destroy_scheduling_element_in_bits { 5646 u8 opcode[0x10]; 5647 u8 reserved_at_10[0x10]; 5648 5649 u8 reserved_at_20[0x10]; 5650 u8 op_mod[0x10]; 5651 5652 u8 scheduling_hierarchy[0x8]; 5653 u8 reserved_at_48[0x18]; 5654 5655 u8 scheduling_element_id[0x20]; 5656 5657 u8 reserved_at_80[0x180]; 5658 }; 5659 5660 struct mlx5_ifc_destroy_rqt_out_bits { 5661 u8 status[0x8]; 5662 u8 reserved_at_8[0x18]; 5663 5664 u8 syndrome[0x20]; 5665 5666 u8 reserved_at_40[0x40]; 5667 }; 5668 5669 struct mlx5_ifc_destroy_rqt_in_bits { 5670 u8 opcode[0x10]; 5671 u8 reserved_at_10[0x10]; 5672 5673 u8 reserved_at_20[0x10]; 5674 u8 op_mod[0x10]; 5675 5676 u8 reserved_at_40[0x8]; 5677 u8 rqtn[0x18]; 5678 5679 u8 reserved_at_60[0x20]; 5680 }; 5681 5682 struct mlx5_ifc_destroy_rq_out_bits { 5683 u8 status[0x8]; 5684 u8 reserved_at_8[0x18]; 5685 5686 u8 syndrome[0x20]; 5687 5688 u8 reserved_at_40[0x40]; 5689 }; 5690 5691 struct mlx5_ifc_destroy_rq_in_bits { 5692 u8 opcode[0x10]; 5693 u8 reserved_at_10[0x10]; 5694 5695 u8 reserved_at_20[0x10]; 5696 u8 op_mod[0x10]; 5697 5698 u8 reserved_at_40[0x8]; 5699 u8 rqn[0x18]; 5700 5701 u8 reserved_at_60[0x20]; 5702 }; 5703 5704 struct mlx5_ifc_destroy_rmp_out_bits { 5705 u8 status[0x8]; 5706 u8 reserved_at_8[0x18]; 5707 5708 u8 syndrome[0x20]; 5709 5710 u8 reserved_at_40[0x40]; 5711 }; 5712 5713 struct mlx5_ifc_destroy_rmp_in_bits { 5714 u8 opcode[0x10]; 5715 u8 reserved_at_10[0x10]; 5716 5717 u8 reserved_at_20[0x10]; 5718 u8 op_mod[0x10]; 5719 5720 u8 reserved_at_40[0x8]; 5721 u8 rmpn[0x18]; 5722 5723 u8 reserved_at_60[0x20]; 5724 }; 5725 5726 struct mlx5_ifc_destroy_qp_out_bits { 5727 u8 status[0x8]; 5728 u8 reserved_at_8[0x18]; 5729 5730 u8 syndrome[0x20]; 5731 5732 u8 reserved_at_40[0x40]; 5733 }; 5734 5735 struct mlx5_ifc_destroy_qp_in_bits { 5736 u8 opcode[0x10]; 5737 u8 reserved_at_10[0x10]; 5738 5739 u8 reserved_at_20[0x10]; 5740 u8 op_mod[0x10]; 5741 5742 u8 reserved_at_40[0x8]; 5743 u8 qpn[0x18]; 5744 5745 u8 reserved_at_60[0x20]; 5746 }; 5747 5748 struct mlx5_ifc_destroy_psv_out_bits { 5749 u8 status[0x8]; 5750 u8 reserved_at_8[0x18]; 5751 5752 u8 syndrome[0x20]; 5753 5754 u8 reserved_at_40[0x40]; 5755 }; 5756 5757 struct mlx5_ifc_destroy_psv_in_bits { 5758 u8 opcode[0x10]; 5759 u8 reserved_at_10[0x10]; 5760 5761 u8 reserved_at_20[0x10]; 5762 u8 op_mod[0x10]; 5763 5764 u8 reserved_at_40[0x8]; 5765 u8 psvn[0x18]; 5766 5767 u8 reserved_at_60[0x20]; 5768 }; 5769 5770 struct mlx5_ifc_destroy_mkey_out_bits { 5771 u8 status[0x8]; 5772 u8 reserved_at_8[0x18]; 5773 5774 u8 syndrome[0x20]; 5775 5776 u8 reserved_at_40[0x40]; 5777 }; 5778 5779 struct mlx5_ifc_destroy_mkey_in_bits { 5780 u8 opcode[0x10]; 5781 u8 reserved_at_10[0x10]; 5782 5783 u8 reserved_at_20[0x10]; 5784 u8 op_mod[0x10]; 5785 5786 u8 reserved_at_40[0x8]; 5787 u8 mkey_index[0x18]; 5788 5789 u8 reserved_at_60[0x20]; 5790 }; 5791 5792 struct mlx5_ifc_destroy_flow_table_out_bits { 5793 u8 status[0x8]; 5794 u8 reserved_at_8[0x18]; 5795 5796 u8 syndrome[0x20]; 5797 5798 u8 reserved_at_40[0x40]; 5799 }; 5800 5801 struct mlx5_ifc_destroy_flow_table_in_bits { 5802 u8 opcode[0x10]; 5803 u8 reserved_at_10[0x10]; 5804 5805 u8 reserved_at_20[0x10]; 5806 u8 op_mod[0x10]; 5807 5808 u8 other_vport[0x1]; 5809 u8 reserved_at_41[0xf]; 5810 u8 vport_number[0x10]; 5811 5812 u8 reserved_at_60[0x20]; 5813 5814 u8 table_type[0x8]; 5815 u8 reserved_at_88[0x18]; 5816 5817 u8 reserved_at_a0[0x8]; 5818 u8 table_id[0x18]; 5819 5820 u8 reserved_at_c0[0x140]; 5821 }; 5822 5823 struct mlx5_ifc_destroy_flow_group_out_bits { 5824 u8 status[0x8]; 5825 u8 reserved_at_8[0x18]; 5826 5827 u8 syndrome[0x20]; 5828 5829 u8 reserved_at_40[0x40]; 5830 }; 5831 5832 struct mlx5_ifc_destroy_flow_group_in_bits { 5833 u8 opcode[0x10]; 5834 u8 reserved_at_10[0x10]; 5835 5836 u8 reserved_at_20[0x10]; 5837 u8 op_mod[0x10]; 5838 5839 u8 other_vport[0x1]; 5840 u8 reserved_at_41[0xf]; 5841 u8 vport_number[0x10]; 5842 5843 u8 reserved_at_60[0x20]; 5844 5845 u8 table_type[0x8]; 5846 u8 reserved_at_88[0x18]; 5847 5848 u8 reserved_at_a0[0x8]; 5849 u8 table_id[0x18]; 5850 5851 u8 group_id[0x20]; 5852 5853 u8 reserved_at_e0[0x120]; 5854 }; 5855 5856 struct mlx5_ifc_destroy_eq_out_bits { 5857 u8 status[0x8]; 5858 u8 reserved_at_8[0x18]; 5859 5860 u8 syndrome[0x20]; 5861 5862 u8 reserved_at_40[0x40]; 5863 }; 5864 5865 struct mlx5_ifc_destroy_eq_in_bits { 5866 u8 opcode[0x10]; 5867 u8 reserved_at_10[0x10]; 5868 5869 u8 reserved_at_20[0x10]; 5870 u8 op_mod[0x10]; 5871 5872 u8 reserved_at_40[0x18]; 5873 u8 eq_number[0x8]; 5874 5875 u8 reserved_at_60[0x20]; 5876 }; 5877 5878 struct mlx5_ifc_destroy_dct_out_bits { 5879 u8 status[0x8]; 5880 u8 reserved_at_8[0x18]; 5881 5882 u8 syndrome[0x20]; 5883 5884 u8 reserved_at_40[0x40]; 5885 }; 5886 5887 struct mlx5_ifc_destroy_dct_in_bits { 5888 u8 opcode[0x10]; 5889 u8 reserved_at_10[0x10]; 5890 5891 u8 reserved_at_20[0x10]; 5892 u8 op_mod[0x10]; 5893 5894 u8 reserved_at_40[0x8]; 5895 u8 dctn[0x18]; 5896 5897 u8 reserved_at_60[0x20]; 5898 }; 5899 5900 struct mlx5_ifc_destroy_cq_out_bits { 5901 u8 status[0x8]; 5902 u8 reserved_at_8[0x18]; 5903 5904 u8 syndrome[0x20]; 5905 5906 u8 reserved_at_40[0x40]; 5907 }; 5908 5909 struct mlx5_ifc_destroy_cq_in_bits { 5910 u8 opcode[0x10]; 5911 u8 reserved_at_10[0x10]; 5912 5913 u8 reserved_at_20[0x10]; 5914 u8 op_mod[0x10]; 5915 5916 u8 reserved_at_40[0x8]; 5917 u8 cqn[0x18]; 5918 5919 u8 reserved_at_60[0x20]; 5920 }; 5921 5922 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 5923 u8 status[0x8]; 5924 u8 reserved_at_8[0x18]; 5925 5926 u8 syndrome[0x20]; 5927 5928 u8 reserved_at_40[0x40]; 5929 }; 5930 5931 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 5932 u8 opcode[0x10]; 5933 u8 reserved_at_10[0x10]; 5934 5935 u8 reserved_at_20[0x10]; 5936 u8 op_mod[0x10]; 5937 5938 u8 reserved_at_40[0x20]; 5939 5940 u8 reserved_at_60[0x10]; 5941 u8 vxlan_udp_port[0x10]; 5942 }; 5943 5944 struct mlx5_ifc_delete_l2_table_entry_out_bits { 5945 u8 status[0x8]; 5946 u8 reserved_at_8[0x18]; 5947 5948 u8 syndrome[0x20]; 5949 5950 u8 reserved_at_40[0x40]; 5951 }; 5952 5953 struct mlx5_ifc_delete_l2_table_entry_in_bits { 5954 u8 opcode[0x10]; 5955 u8 reserved_at_10[0x10]; 5956 5957 u8 reserved_at_20[0x10]; 5958 u8 op_mod[0x10]; 5959 5960 u8 reserved_at_40[0x60]; 5961 5962 u8 reserved_at_a0[0x8]; 5963 u8 table_index[0x18]; 5964 5965 u8 reserved_at_c0[0x140]; 5966 }; 5967 5968 struct mlx5_ifc_delete_fte_out_bits { 5969 u8 status[0x8]; 5970 u8 reserved_at_8[0x18]; 5971 5972 u8 syndrome[0x20]; 5973 5974 u8 reserved_at_40[0x40]; 5975 }; 5976 5977 struct mlx5_ifc_delete_fte_in_bits { 5978 u8 opcode[0x10]; 5979 u8 reserved_at_10[0x10]; 5980 5981 u8 reserved_at_20[0x10]; 5982 u8 op_mod[0x10]; 5983 5984 u8 other_vport[0x1]; 5985 u8 reserved_at_41[0xf]; 5986 u8 vport_number[0x10]; 5987 5988 u8 reserved_at_60[0x20]; 5989 5990 u8 table_type[0x8]; 5991 u8 reserved_at_88[0x18]; 5992 5993 u8 reserved_at_a0[0x8]; 5994 u8 table_id[0x18]; 5995 5996 u8 reserved_at_c0[0x40]; 5997 5998 u8 flow_index[0x20]; 5999 6000 u8 reserved_at_120[0xe0]; 6001 }; 6002 6003 struct mlx5_ifc_dealloc_xrcd_out_bits { 6004 u8 status[0x8]; 6005 u8 reserved_at_8[0x18]; 6006 6007 u8 syndrome[0x20]; 6008 6009 u8 reserved_at_40[0x40]; 6010 }; 6011 6012 struct mlx5_ifc_dealloc_xrcd_in_bits { 6013 u8 opcode[0x10]; 6014 u8 reserved_at_10[0x10]; 6015 6016 u8 reserved_at_20[0x10]; 6017 u8 op_mod[0x10]; 6018 6019 u8 reserved_at_40[0x8]; 6020 u8 xrcd[0x18]; 6021 6022 u8 reserved_at_60[0x20]; 6023 }; 6024 6025 struct mlx5_ifc_dealloc_uar_out_bits { 6026 u8 status[0x8]; 6027 u8 reserved_at_8[0x18]; 6028 6029 u8 syndrome[0x20]; 6030 6031 u8 reserved_at_40[0x40]; 6032 }; 6033 6034 struct mlx5_ifc_dealloc_uar_in_bits { 6035 u8 opcode[0x10]; 6036 u8 reserved_at_10[0x10]; 6037 6038 u8 reserved_at_20[0x10]; 6039 u8 op_mod[0x10]; 6040 6041 u8 reserved_at_40[0x8]; 6042 u8 uar[0x18]; 6043 6044 u8 reserved_at_60[0x20]; 6045 }; 6046 6047 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6048 u8 status[0x8]; 6049 u8 reserved_at_8[0x18]; 6050 6051 u8 syndrome[0x20]; 6052 6053 u8 reserved_at_40[0x40]; 6054 }; 6055 6056 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6057 u8 opcode[0x10]; 6058 u8 reserved_at_10[0x10]; 6059 6060 u8 reserved_at_20[0x10]; 6061 u8 op_mod[0x10]; 6062 6063 u8 reserved_at_40[0x8]; 6064 u8 transport_domain[0x18]; 6065 6066 u8 reserved_at_60[0x20]; 6067 }; 6068 6069 struct mlx5_ifc_dealloc_q_counter_out_bits { 6070 u8 status[0x8]; 6071 u8 reserved_at_8[0x18]; 6072 6073 u8 syndrome[0x20]; 6074 6075 u8 reserved_at_40[0x40]; 6076 }; 6077 6078 struct mlx5_ifc_dealloc_q_counter_in_bits { 6079 u8 opcode[0x10]; 6080 u8 reserved_at_10[0x10]; 6081 6082 u8 reserved_at_20[0x10]; 6083 u8 op_mod[0x10]; 6084 6085 u8 reserved_at_40[0x18]; 6086 u8 counter_set_id[0x8]; 6087 6088 u8 reserved_at_60[0x20]; 6089 }; 6090 6091 struct mlx5_ifc_dealloc_pd_out_bits { 6092 u8 status[0x8]; 6093 u8 reserved_at_8[0x18]; 6094 6095 u8 syndrome[0x20]; 6096 6097 u8 reserved_at_40[0x40]; 6098 }; 6099 6100 struct mlx5_ifc_dealloc_pd_in_bits { 6101 u8 opcode[0x10]; 6102 u8 reserved_at_10[0x10]; 6103 6104 u8 reserved_at_20[0x10]; 6105 u8 op_mod[0x10]; 6106 6107 u8 reserved_at_40[0x8]; 6108 u8 pd[0x18]; 6109 6110 u8 reserved_at_60[0x20]; 6111 }; 6112 6113 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6114 u8 status[0x8]; 6115 u8 reserved_at_8[0x18]; 6116 6117 u8 syndrome[0x20]; 6118 6119 u8 reserved_at_40[0x40]; 6120 }; 6121 6122 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6123 u8 opcode[0x10]; 6124 u8 reserved_at_10[0x10]; 6125 6126 u8 reserved_at_20[0x10]; 6127 u8 op_mod[0x10]; 6128 6129 u8 reserved_at_40[0x10]; 6130 u8 flow_counter_id[0x10]; 6131 6132 u8 reserved_at_60[0x20]; 6133 }; 6134 6135 struct mlx5_ifc_create_xrq_out_bits { 6136 u8 status[0x8]; 6137 u8 reserved_at_8[0x18]; 6138 6139 u8 syndrome[0x20]; 6140 6141 u8 reserved_at_40[0x8]; 6142 u8 xrqn[0x18]; 6143 6144 u8 reserved_at_60[0x20]; 6145 }; 6146 6147 struct mlx5_ifc_create_xrq_in_bits { 6148 u8 opcode[0x10]; 6149 u8 reserved_at_10[0x10]; 6150 6151 u8 reserved_at_20[0x10]; 6152 u8 op_mod[0x10]; 6153 6154 u8 reserved_at_40[0x40]; 6155 6156 struct mlx5_ifc_xrqc_bits xrq_context; 6157 }; 6158 6159 struct mlx5_ifc_create_xrc_srq_out_bits { 6160 u8 status[0x8]; 6161 u8 reserved_at_8[0x18]; 6162 6163 u8 syndrome[0x20]; 6164 6165 u8 reserved_at_40[0x8]; 6166 u8 xrc_srqn[0x18]; 6167 6168 u8 reserved_at_60[0x20]; 6169 }; 6170 6171 struct mlx5_ifc_create_xrc_srq_in_bits { 6172 u8 opcode[0x10]; 6173 u8 reserved_at_10[0x10]; 6174 6175 u8 reserved_at_20[0x10]; 6176 u8 op_mod[0x10]; 6177 6178 u8 reserved_at_40[0x40]; 6179 6180 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6181 6182 u8 reserved_at_280[0x600]; 6183 6184 u8 pas[0][0x40]; 6185 }; 6186 6187 struct mlx5_ifc_create_tis_out_bits { 6188 u8 status[0x8]; 6189 u8 reserved_at_8[0x18]; 6190 6191 u8 syndrome[0x20]; 6192 6193 u8 reserved_at_40[0x8]; 6194 u8 tisn[0x18]; 6195 6196 u8 reserved_at_60[0x20]; 6197 }; 6198 6199 struct mlx5_ifc_create_tis_in_bits { 6200 u8 opcode[0x10]; 6201 u8 reserved_at_10[0x10]; 6202 6203 u8 reserved_at_20[0x10]; 6204 u8 op_mod[0x10]; 6205 6206 u8 reserved_at_40[0xc0]; 6207 6208 struct mlx5_ifc_tisc_bits ctx; 6209 }; 6210 6211 struct mlx5_ifc_create_tir_out_bits { 6212 u8 status[0x8]; 6213 u8 reserved_at_8[0x18]; 6214 6215 u8 syndrome[0x20]; 6216 6217 u8 reserved_at_40[0x8]; 6218 u8 tirn[0x18]; 6219 6220 u8 reserved_at_60[0x20]; 6221 }; 6222 6223 struct mlx5_ifc_create_tir_in_bits { 6224 u8 opcode[0x10]; 6225 u8 reserved_at_10[0x10]; 6226 6227 u8 reserved_at_20[0x10]; 6228 u8 op_mod[0x10]; 6229 6230 u8 reserved_at_40[0xc0]; 6231 6232 struct mlx5_ifc_tirc_bits ctx; 6233 }; 6234 6235 struct mlx5_ifc_create_srq_out_bits { 6236 u8 status[0x8]; 6237 u8 reserved_at_8[0x18]; 6238 6239 u8 syndrome[0x20]; 6240 6241 u8 reserved_at_40[0x8]; 6242 u8 srqn[0x18]; 6243 6244 u8 reserved_at_60[0x20]; 6245 }; 6246 6247 struct mlx5_ifc_create_srq_in_bits { 6248 u8 opcode[0x10]; 6249 u8 reserved_at_10[0x10]; 6250 6251 u8 reserved_at_20[0x10]; 6252 u8 op_mod[0x10]; 6253 6254 u8 reserved_at_40[0x40]; 6255 6256 struct mlx5_ifc_srqc_bits srq_context_entry; 6257 6258 u8 reserved_at_280[0x600]; 6259 6260 u8 pas[0][0x40]; 6261 }; 6262 6263 struct mlx5_ifc_create_sq_out_bits { 6264 u8 status[0x8]; 6265 u8 reserved_at_8[0x18]; 6266 6267 u8 syndrome[0x20]; 6268 6269 u8 reserved_at_40[0x8]; 6270 u8 sqn[0x18]; 6271 6272 u8 reserved_at_60[0x20]; 6273 }; 6274 6275 struct mlx5_ifc_create_sq_in_bits { 6276 u8 opcode[0x10]; 6277 u8 reserved_at_10[0x10]; 6278 6279 u8 reserved_at_20[0x10]; 6280 u8 op_mod[0x10]; 6281 6282 u8 reserved_at_40[0xc0]; 6283 6284 struct mlx5_ifc_sqc_bits ctx; 6285 }; 6286 6287 struct mlx5_ifc_create_scheduling_element_out_bits { 6288 u8 status[0x8]; 6289 u8 reserved_at_8[0x18]; 6290 6291 u8 syndrome[0x20]; 6292 6293 u8 reserved_at_40[0x40]; 6294 6295 u8 scheduling_element_id[0x20]; 6296 6297 u8 reserved_at_a0[0x160]; 6298 }; 6299 6300 struct mlx5_ifc_create_scheduling_element_in_bits { 6301 u8 opcode[0x10]; 6302 u8 reserved_at_10[0x10]; 6303 6304 u8 reserved_at_20[0x10]; 6305 u8 op_mod[0x10]; 6306 6307 u8 scheduling_hierarchy[0x8]; 6308 u8 reserved_at_48[0x18]; 6309 6310 u8 reserved_at_60[0xa0]; 6311 6312 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6313 6314 u8 reserved_at_300[0x100]; 6315 }; 6316 6317 struct mlx5_ifc_create_rqt_out_bits { 6318 u8 status[0x8]; 6319 u8 reserved_at_8[0x18]; 6320 6321 u8 syndrome[0x20]; 6322 6323 u8 reserved_at_40[0x8]; 6324 u8 rqtn[0x18]; 6325 6326 u8 reserved_at_60[0x20]; 6327 }; 6328 6329 struct mlx5_ifc_create_rqt_in_bits { 6330 u8 opcode[0x10]; 6331 u8 reserved_at_10[0x10]; 6332 6333 u8 reserved_at_20[0x10]; 6334 u8 op_mod[0x10]; 6335 6336 u8 reserved_at_40[0xc0]; 6337 6338 struct mlx5_ifc_rqtc_bits rqt_context; 6339 }; 6340 6341 struct mlx5_ifc_create_rq_out_bits { 6342 u8 status[0x8]; 6343 u8 reserved_at_8[0x18]; 6344 6345 u8 syndrome[0x20]; 6346 6347 u8 reserved_at_40[0x8]; 6348 u8 rqn[0x18]; 6349 6350 u8 reserved_at_60[0x20]; 6351 }; 6352 6353 struct mlx5_ifc_create_rq_in_bits { 6354 u8 opcode[0x10]; 6355 u8 reserved_at_10[0x10]; 6356 6357 u8 reserved_at_20[0x10]; 6358 u8 op_mod[0x10]; 6359 6360 u8 reserved_at_40[0xc0]; 6361 6362 struct mlx5_ifc_rqc_bits ctx; 6363 }; 6364 6365 struct mlx5_ifc_create_rmp_out_bits { 6366 u8 status[0x8]; 6367 u8 reserved_at_8[0x18]; 6368 6369 u8 syndrome[0x20]; 6370 6371 u8 reserved_at_40[0x8]; 6372 u8 rmpn[0x18]; 6373 6374 u8 reserved_at_60[0x20]; 6375 }; 6376 6377 struct mlx5_ifc_create_rmp_in_bits { 6378 u8 opcode[0x10]; 6379 u8 reserved_at_10[0x10]; 6380 6381 u8 reserved_at_20[0x10]; 6382 u8 op_mod[0x10]; 6383 6384 u8 reserved_at_40[0xc0]; 6385 6386 struct mlx5_ifc_rmpc_bits ctx; 6387 }; 6388 6389 struct mlx5_ifc_create_qp_out_bits { 6390 u8 status[0x8]; 6391 u8 reserved_at_8[0x18]; 6392 6393 u8 syndrome[0x20]; 6394 6395 u8 reserved_at_40[0x8]; 6396 u8 qpn[0x18]; 6397 6398 u8 reserved_at_60[0x20]; 6399 }; 6400 6401 struct mlx5_ifc_create_qp_in_bits { 6402 u8 opcode[0x10]; 6403 u8 reserved_at_10[0x10]; 6404 6405 u8 reserved_at_20[0x10]; 6406 u8 op_mod[0x10]; 6407 6408 u8 reserved_at_40[0x40]; 6409 6410 u8 opt_param_mask[0x20]; 6411 6412 u8 reserved_at_a0[0x20]; 6413 6414 struct mlx5_ifc_qpc_bits qpc; 6415 6416 u8 reserved_at_800[0x80]; 6417 6418 u8 pas[0][0x40]; 6419 }; 6420 6421 struct mlx5_ifc_create_psv_out_bits { 6422 u8 status[0x8]; 6423 u8 reserved_at_8[0x18]; 6424 6425 u8 syndrome[0x20]; 6426 6427 u8 reserved_at_40[0x40]; 6428 6429 u8 reserved_at_80[0x8]; 6430 u8 psv0_index[0x18]; 6431 6432 u8 reserved_at_a0[0x8]; 6433 u8 psv1_index[0x18]; 6434 6435 u8 reserved_at_c0[0x8]; 6436 u8 psv2_index[0x18]; 6437 6438 u8 reserved_at_e0[0x8]; 6439 u8 psv3_index[0x18]; 6440 }; 6441 6442 struct mlx5_ifc_create_psv_in_bits { 6443 u8 opcode[0x10]; 6444 u8 reserved_at_10[0x10]; 6445 6446 u8 reserved_at_20[0x10]; 6447 u8 op_mod[0x10]; 6448 6449 u8 num_psv[0x4]; 6450 u8 reserved_at_44[0x4]; 6451 u8 pd[0x18]; 6452 6453 u8 reserved_at_60[0x20]; 6454 }; 6455 6456 struct mlx5_ifc_create_mkey_out_bits { 6457 u8 status[0x8]; 6458 u8 reserved_at_8[0x18]; 6459 6460 u8 syndrome[0x20]; 6461 6462 u8 reserved_at_40[0x8]; 6463 u8 mkey_index[0x18]; 6464 6465 u8 reserved_at_60[0x20]; 6466 }; 6467 6468 struct mlx5_ifc_create_mkey_in_bits { 6469 u8 opcode[0x10]; 6470 u8 reserved_at_10[0x10]; 6471 6472 u8 reserved_at_20[0x10]; 6473 u8 op_mod[0x10]; 6474 6475 u8 reserved_at_40[0x20]; 6476 6477 u8 pg_access[0x1]; 6478 u8 reserved_at_61[0x1f]; 6479 6480 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6481 6482 u8 reserved_at_280[0x80]; 6483 6484 u8 translations_octword_actual_size[0x20]; 6485 6486 u8 reserved_at_320[0x560]; 6487 6488 u8 klm_pas_mtt[0][0x20]; 6489 }; 6490 6491 struct mlx5_ifc_create_flow_table_out_bits { 6492 u8 status[0x8]; 6493 u8 reserved_at_8[0x18]; 6494 6495 u8 syndrome[0x20]; 6496 6497 u8 reserved_at_40[0x8]; 6498 u8 table_id[0x18]; 6499 6500 u8 reserved_at_60[0x20]; 6501 }; 6502 6503 struct mlx5_ifc_create_flow_table_in_bits { 6504 u8 opcode[0x10]; 6505 u8 reserved_at_10[0x10]; 6506 6507 u8 reserved_at_20[0x10]; 6508 u8 op_mod[0x10]; 6509 6510 u8 other_vport[0x1]; 6511 u8 reserved_at_41[0xf]; 6512 u8 vport_number[0x10]; 6513 6514 u8 reserved_at_60[0x20]; 6515 6516 u8 table_type[0x8]; 6517 u8 reserved_at_88[0x18]; 6518 6519 u8 reserved_at_a0[0x20]; 6520 6521 u8 encap_en[0x1]; 6522 u8 decap_en[0x1]; 6523 u8 reserved_at_c2[0x2]; 6524 u8 table_miss_mode[0x4]; 6525 u8 level[0x8]; 6526 u8 reserved_at_d0[0x8]; 6527 u8 log_size[0x8]; 6528 6529 u8 reserved_at_e0[0x8]; 6530 u8 table_miss_id[0x18]; 6531 6532 u8 reserved_at_100[0x8]; 6533 u8 lag_master_next_table_id[0x18]; 6534 6535 u8 reserved_at_120[0x80]; 6536 }; 6537 6538 struct mlx5_ifc_create_flow_group_out_bits { 6539 u8 status[0x8]; 6540 u8 reserved_at_8[0x18]; 6541 6542 u8 syndrome[0x20]; 6543 6544 u8 reserved_at_40[0x8]; 6545 u8 group_id[0x18]; 6546 6547 u8 reserved_at_60[0x20]; 6548 }; 6549 6550 enum { 6551 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6552 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6553 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6554 }; 6555 6556 struct mlx5_ifc_create_flow_group_in_bits { 6557 u8 opcode[0x10]; 6558 u8 reserved_at_10[0x10]; 6559 6560 u8 reserved_at_20[0x10]; 6561 u8 op_mod[0x10]; 6562 6563 u8 other_vport[0x1]; 6564 u8 reserved_at_41[0xf]; 6565 u8 vport_number[0x10]; 6566 6567 u8 reserved_at_60[0x20]; 6568 6569 u8 table_type[0x8]; 6570 u8 reserved_at_88[0x18]; 6571 6572 u8 reserved_at_a0[0x8]; 6573 u8 table_id[0x18]; 6574 6575 u8 reserved_at_c0[0x20]; 6576 6577 u8 start_flow_index[0x20]; 6578 6579 u8 reserved_at_100[0x20]; 6580 6581 u8 end_flow_index[0x20]; 6582 6583 u8 reserved_at_140[0xa0]; 6584 6585 u8 reserved_at_1e0[0x18]; 6586 u8 match_criteria_enable[0x8]; 6587 6588 struct mlx5_ifc_fte_match_param_bits match_criteria; 6589 6590 u8 reserved_at_1200[0xe00]; 6591 }; 6592 6593 struct mlx5_ifc_create_eq_out_bits { 6594 u8 status[0x8]; 6595 u8 reserved_at_8[0x18]; 6596 6597 u8 syndrome[0x20]; 6598 6599 u8 reserved_at_40[0x18]; 6600 u8 eq_number[0x8]; 6601 6602 u8 reserved_at_60[0x20]; 6603 }; 6604 6605 struct mlx5_ifc_create_eq_in_bits { 6606 u8 opcode[0x10]; 6607 u8 reserved_at_10[0x10]; 6608 6609 u8 reserved_at_20[0x10]; 6610 u8 op_mod[0x10]; 6611 6612 u8 reserved_at_40[0x40]; 6613 6614 struct mlx5_ifc_eqc_bits eq_context_entry; 6615 6616 u8 reserved_at_280[0x40]; 6617 6618 u8 event_bitmask[0x40]; 6619 6620 u8 reserved_at_300[0x580]; 6621 6622 u8 pas[0][0x40]; 6623 }; 6624 6625 struct mlx5_ifc_create_dct_out_bits { 6626 u8 status[0x8]; 6627 u8 reserved_at_8[0x18]; 6628 6629 u8 syndrome[0x20]; 6630 6631 u8 reserved_at_40[0x8]; 6632 u8 dctn[0x18]; 6633 6634 u8 reserved_at_60[0x20]; 6635 }; 6636 6637 struct mlx5_ifc_create_dct_in_bits { 6638 u8 opcode[0x10]; 6639 u8 reserved_at_10[0x10]; 6640 6641 u8 reserved_at_20[0x10]; 6642 u8 op_mod[0x10]; 6643 6644 u8 reserved_at_40[0x40]; 6645 6646 struct mlx5_ifc_dctc_bits dct_context_entry; 6647 6648 u8 reserved_at_280[0x180]; 6649 }; 6650 6651 struct mlx5_ifc_create_cq_out_bits { 6652 u8 status[0x8]; 6653 u8 reserved_at_8[0x18]; 6654 6655 u8 syndrome[0x20]; 6656 6657 u8 reserved_at_40[0x8]; 6658 u8 cqn[0x18]; 6659 6660 u8 reserved_at_60[0x20]; 6661 }; 6662 6663 struct mlx5_ifc_create_cq_in_bits { 6664 u8 opcode[0x10]; 6665 u8 reserved_at_10[0x10]; 6666 6667 u8 reserved_at_20[0x10]; 6668 u8 op_mod[0x10]; 6669 6670 u8 reserved_at_40[0x40]; 6671 6672 struct mlx5_ifc_cqc_bits cq_context; 6673 6674 u8 reserved_at_280[0x600]; 6675 6676 u8 pas[0][0x40]; 6677 }; 6678 6679 struct mlx5_ifc_config_int_moderation_out_bits { 6680 u8 status[0x8]; 6681 u8 reserved_at_8[0x18]; 6682 6683 u8 syndrome[0x20]; 6684 6685 u8 reserved_at_40[0x4]; 6686 u8 min_delay[0xc]; 6687 u8 int_vector[0x10]; 6688 6689 u8 reserved_at_60[0x20]; 6690 }; 6691 6692 enum { 6693 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 6694 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 6695 }; 6696 6697 struct mlx5_ifc_config_int_moderation_in_bits { 6698 u8 opcode[0x10]; 6699 u8 reserved_at_10[0x10]; 6700 6701 u8 reserved_at_20[0x10]; 6702 u8 op_mod[0x10]; 6703 6704 u8 reserved_at_40[0x4]; 6705 u8 min_delay[0xc]; 6706 u8 int_vector[0x10]; 6707 6708 u8 reserved_at_60[0x20]; 6709 }; 6710 6711 struct mlx5_ifc_attach_to_mcg_out_bits { 6712 u8 status[0x8]; 6713 u8 reserved_at_8[0x18]; 6714 6715 u8 syndrome[0x20]; 6716 6717 u8 reserved_at_40[0x40]; 6718 }; 6719 6720 struct mlx5_ifc_attach_to_mcg_in_bits { 6721 u8 opcode[0x10]; 6722 u8 reserved_at_10[0x10]; 6723 6724 u8 reserved_at_20[0x10]; 6725 u8 op_mod[0x10]; 6726 6727 u8 reserved_at_40[0x8]; 6728 u8 qpn[0x18]; 6729 6730 u8 reserved_at_60[0x20]; 6731 6732 u8 multicast_gid[16][0x8]; 6733 }; 6734 6735 struct mlx5_ifc_arm_xrq_out_bits { 6736 u8 status[0x8]; 6737 u8 reserved_at_8[0x18]; 6738 6739 u8 syndrome[0x20]; 6740 6741 u8 reserved_at_40[0x40]; 6742 }; 6743 6744 struct mlx5_ifc_arm_xrq_in_bits { 6745 u8 opcode[0x10]; 6746 u8 reserved_at_10[0x10]; 6747 6748 u8 reserved_at_20[0x10]; 6749 u8 op_mod[0x10]; 6750 6751 u8 reserved_at_40[0x8]; 6752 u8 xrqn[0x18]; 6753 6754 u8 reserved_at_60[0x10]; 6755 u8 lwm[0x10]; 6756 }; 6757 6758 struct mlx5_ifc_arm_xrc_srq_out_bits { 6759 u8 status[0x8]; 6760 u8 reserved_at_8[0x18]; 6761 6762 u8 syndrome[0x20]; 6763 6764 u8 reserved_at_40[0x40]; 6765 }; 6766 6767 enum { 6768 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 6769 }; 6770 6771 struct mlx5_ifc_arm_xrc_srq_in_bits { 6772 u8 opcode[0x10]; 6773 u8 reserved_at_10[0x10]; 6774 6775 u8 reserved_at_20[0x10]; 6776 u8 op_mod[0x10]; 6777 6778 u8 reserved_at_40[0x8]; 6779 u8 xrc_srqn[0x18]; 6780 6781 u8 reserved_at_60[0x10]; 6782 u8 lwm[0x10]; 6783 }; 6784 6785 struct mlx5_ifc_arm_rq_out_bits { 6786 u8 status[0x8]; 6787 u8 reserved_at_8[0x18]; 6788 6789 u8 syndrome[0x20]; 6790 6791 u8 reserved_at_40[0x40]; 6792 }; 6793 6794 enum { 6795 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 6796 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 6797 }; 6798 6799 struct mlx5_ifc_arm_rq_in_bits { 6800 u8 opcode[0x10]; 6801 u8 reserved_at_10[0x10]; 6802 6803 u8 reserved_at_20[0x10]; 6804 u8 op_mod[0x10]; 6805 6806 u8 reserved_at_40[0x8]; 6807 u8 srq_number[0x18]; 6808 6809 u8 reserved_at_60[0x10]; 6810 u8 lwm[0x10]; 6811 }; 6812 6813 struct mlx5_ifc_arm_dct_out_bits { 6814 u8 status[0x8]; 6815 u8 reserved_at_8[0x18]; 6816 6817 u8 syndrome[0x20]; 6818 6819 u8 reserved_at_40[0x40]; 6820 }; 6821 6822 struct mlx5_ifc_arm_dct_in_bits { 6823 u8 opcode[0x10]; 6824 u8 reserved_at_10[0x10]; 6825 6826 u8 reserved_at_20[0x10]; 6827 u8 op_mod[0x10]; 6828 6829 u8 reserved_at_40[0x8]; 6830 u8 dct_number[0x18]; 6831 6832 u8 reserved_at_60[0x20]; 6833 }; 6834 6835 struct mlx5_ifc_alloc_xrcd_out_bits { 6836 u8 status[0x8]; 6837 u8 reserved_at_8[0x18]; 6838 6839 u8 syndrome[0x20]; 6840 6841 u8 reserved_at_40[0x8]; 6842 u8 xrcd[0x18]; 6843 6844 u8 reserved_at_60[0x20]; 6845 }; 6846 6847 struct mlx5_ifc_alloc_xrcd_in_bits { 6848 u8 opcode[0x10]; 6849 u8 reserved_at_10[0x10]; 6850 6851 u8 reserved_at_20[0x10]; 6852 u8 op_mod[0x10]; 6853 6854 u8 reserved_at_40[0x40]; 6855 }; 6856 6857 struct mlx5_ifc_alloc_uar_out_bits { 6858 u8 status[0x8]; 6859 u8 reserved_at_8[0x18]; 6860 6861 u8 syndrome[0x20]; 6862 6863 u8 reserved_at_40[0x8]; 6864 u8 uar[0x18]; 6865 6866 u8 reserved_at_60[0x20]; 6867 }; 6868 6869 struct mlx5_ifc_alloc_uar_in_bits { 6870 u8 opcode[0x10]; 6871 u8 reserved_at_10[0x10]; 6872 6873 u8 reserved_at_20[0x10]; 6874 u8 op_mod[0x10]; 6875 6876 u8 reserved_at_40[0x40]; 6877 }; 6878 6879 struct mlx5_ifc_alloc_transport_domain_out_bits { 6880 u8 status[0x8]; 6881 u8 reserved_at_8[0x18]; 6882 6883 u8 syndrome[0x20]; 6884 6885 u8 reserved_at_40[0x8]; 6886 u8 transport_domain[0x18]; 6887 6888 u8 reserved_at_60[0x20]; 6889 }; 6890 6891 struct mlx5_ifc_alloc_transport_domain_in_bits { 6892 u8 opcode[0x10]; 6893 u8 reserved_at_10[0x10]; 6894 6895 u8 reserved_at_20[0x10]; 6896 u8 op_mod[0x10]; 6897 6898 u8 reserved_at_40[0x40]; 6899 }; 6900 6901 struct mlx5_ifc_alloc_q_counter_out_bits { 6902 u8 status[0x8]; 6903 u8 reserved_at_8[0x18]; 6904 6905 u8 syndrome[0x20]; 6906 6907 u8 reserved_at_40[0x18]; 6908 u8 counter_set_id[0x8]; 6909 6910 u8 reserved_at_60[0x20]; 6911 }; 6912 6913 struct mlx5_ifc_alloc_q_counter_in_bits { 6914 u8 opcode[0x10]; 6915 u8 reserved_at_10[0x10]; 6916 6917 u8 reserved_at_20[0x10]; 6918 u8 op_mod[0x10]; 6919 6920 u8 reserved_at_40[0x40]; 6921 }; 6922 6923 struct mlx5_ifc_alloc_pd_out_bits { 6924 u8 status[0x8]; 6925 u8 reserved_at_8[0x18]; 6926 6927 u8 syndrome[0x20]; 6928 6929 u8 reserved_at_40[0x8]; 6930 u8 pd[0x18]; 6931 6932 u8 reserved_at_60[0x20]; 6933 }; 6934 6935 struct mlx5_ifc_alloc_pd_in_bits { 6936 u8 opcode[0x10]; 6937 u8 reserved_at_10[0x10]; 6938 6939 u8 reserved_at_20[0x10]; 6940 u8 op_mod[0x10]; 6941 6942 u8 reserved_at_40[0x40]; 6943 }; 6944 6945 struct mlx5_ifc_alloc_flow_counter_out_bits { 6946 u8 status[0x8]; 6947 u8 reserved_at_8[0x18]; 6948 6949 u8 syndrome[0x20]; 6950 6951 u8 reserved_at_40[0x10]; 6952 u8 flow_counter_id[0x10]; 6953 6954 u8 reserved_at_60[0x20]; 6955 }; 6956 6957 struct mlx5_ifc_alloc_flow_counter_in_bits { 6958 u8 opcode[0x10]; 6959 u8 reserved_at_10[0x10]; 6960 6961 u8 reserved_at_20[0x10]; 6962 u8 op_mod[0x10]; 6963 6964 u8 reserved_at_40[0x40]; 6965 }; 6966 6967 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 6968 u8 status[0x8]; 6969 u8 reserved_at_8[0x18]; 6970 6971 u8 syndrome[0x20]; 6972 6973 u8 reserved_at_40[0x40]; 6974 }; 6975 6976 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 6977 u8 opcode[0x10]; 6978 u8 reserved_at_10[0x10]; 6979 6980 u8 reserved_at_20[0x10]; 6981 u8 op_mod[0x10]; 6982 6983 u8 reserved_at_40[0x20]; 6984 6985 u8 reserved_at_60[0x10]; 6986 u8 vxlan_udp_port[0x10]; 6987 }; 6988 6989 struct mlx5_ifc_set_rate_limit_out_bits { 6990 u8 status[0x8]; 6991 u8 reserved_at_8[0x18]; 6992 6993 u8 syndrome[0x20]; 6994 6995 u8 reserved_at_40[0x40]; 6996 }; 6997 6998 struct mlx5_ifc_set_rate_limit_in_bits { 6999 u8 opcode[0x10]; 7000 u8 reserved_at_10[0x10]; 7001 7002 u8 reserved_at_20[0x10]; 7003 u8 op_mod[0x10]; 7004 7005 u8 reserved_at_40[0x10]; 7006 u8 rate_limit_index[0x10]; 7007 7008 u8 reserved_at_60[0x20]; 7009 7010 u8 rate_limit[0x20]; 7011 }; 7012 7013 struct mlx5_ifc_access_register_out_bits { 7014 u8 status[0x8]; 7015 u8 reserved_at_8[0x18]; 7016 7017 u8 syndrome[0x20]; 7018 7019 u8 reserved_at_40[0x40]; 7020 7021 u8 register_data[0][0x20]; 7022 }; 7023 7024 enum { 7025 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7026 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7027 }; 7028 7029 struct mlx5_ifc_access_register_in_bits { 7030 u8 opcode[0x10]; 7031 u8 reserved_at_10[0x10]; 7032 7033 u8 reserved_at_20[0x10]; 7034 u8 op_mod[0x10]; 7035 7036 u8 reserved_at_40[0x10]; 7037 u8 register_id[0x10]; 7038 7039 u8 argument[0x20]; 7040 7041 u8 register_data[0][0x20]; 7042 }; 7043 7044 struct mlx5_ifc_sltp_reg_bits { 7045 u8 status[0x4]; 7046 u8 version[0x4]; 7047 u8 local_port[0x8]; 7048 u8 pnat[0x2]; 7049 u8 reserved_at_12[0x2]; 7050 u8 lane[0x4]; 7051 u8 reserved_at_18[0x8]; 7052 7053 u8 reserved_at_20[0x20]; 7054 7055 u8 reserved_at_40[0x7]; 7056 u8 polarity[0x1]; 7057 u8 ob_tap0[0x8]; 7058 u8 ob_tap1[0x8]; 7059 u8 ob_tap2[0x8]; 7060 7061 u8 reserved_at_60[0xc]; 7062 u8 ob_preemp_mode[0x4]; 7063 u8 ob_reg[0x8]; 7064 u8 ob_bias[0x8]; 7065 7066 u8 reserved_at_80[0x20]; 7067 }; 7068 7069 struct mlx5_ifc_slrg_reg_bits { 7070 u8 status[0x4]; 7071 u8 version[0x4]; 7072 u8 local_port[0x8]; 7073 u8 pnat[0x2]; 7074 u8 reserved_at_12[0x2]; 7075 u8 lane[0x4]; 7076 u8 reserved_at_18[0x8]; 7077 7078 u8 time_to_link_up[0x10]; 7079 u8 reserved_at_30[0xc]; 7080 u8 grade_lane_speed[0x4]; 7081 7082 u8 grade_version[0x8]; 7083 u8 grade[0x18]; 7084 7085 u8 reserved_at_60[0x4]; 7086 u8 height_grade_type[0x4]; 7087 u8 height_grade[0x18]; 7088 7089 u8 height_dz[0x10]; 7090 u8 height_dv[0x10]; 7091 7092 u8 reserved_at_a0[0x10]; 7093 u8 height_sigma[0x10]; 7094 7095 u8 reserved_at_c0[0x20]; 7096 7097 u8 reserved_at_e0[0x4]; 7098 u8 phase_grade_type[0x4]; 7099 u8 phase_grade[0x18]; 7100 7101 u8 reserved_at_100[0x8]; 7102 u8 phase_eo_pos[0x8]; 7103 u8 reserved_at_110[0x8]; 7104 u8 phase_eo_neg[0x8]; 7105 7106 u8 ffe_set_tested[0x10]; 7107 u8 test_errors_per_lane[0x10]; 7108 }; 7109 7110 struct mlx5_ifc_pvlc_reg_bits { 7111 u8 reserved_at_0[0x8]; 7112 u8 local_port[0x8]; 7113 u8 reserved_at_10[0x10]; 7114 7115 u8 reserved_at_20[0x1c]; 7116 u8 vl_hw_cap[0x4]; 7117 7118 u8 reserved_at_40[0x1c]; 7119 u8 vl_admin[0x4]; 7120 7121 u8 reserved_at_60[0x1c]; 7122 u8 vl_operational[0x4]; 7123 }; 7124 7125 struct mlx5_ifc_pude_reg_bits { 7126 u8 swid[0x8]; 7127 u8 local_port[0x8]; 7128 u8 reserved_at_10[0x4]; 7129 u8 admin_status[0x4]; 7130 u8 reserved_at_18[0x4]; 7131 u8 oper_status[0x4]; 7132 7133 u8 reserved_at_20[0x60]; 7134 }; 7135 7136 struct mlx5_ifc_ptys_reg_bits { 7137 u8 reserved_at_0[0x1]; 7138 u8 an_disable_admin[0x1]; 7139 u8 an_disable_cap[0x1]; 7140 u8 reserved_at_3[0x5]; 7141 u8 local_port[0x8]; 7142 u8 reserved_at_10[0xd]; 7143 u8 proto_mask[0x3]; 7144 7145 u8 an_status[0x4]; 7146 u8 reserved_at_24[0x3c]; 7147 7148 u8 eth_proto_capability[0x20]; 7149 7150 u8 ib_link_width_capability[0x10]; 7151 u8 ib_proto_capability[0x10]; 7152 7153 u8 reserved_at_a0[0x20]; 7154 7155 u8 eth_proto_admin[0x20]; 7156 7157 u8 ib_link_width_admin[0x10]; 7158 u8 ib_proto_admin[0x10]; 7159 7160 u8 reserved_at_100[0x20]; 7161 7162 u8 eth_proto_oper[0x20]; 7163 7164 u8 ib_link_width_oper[0x10]; 7165 u8 ib_proto_oper[0x10]; 7166 7167 u8 reserved_at_160[0x20]; 7168 7169 u8 eth_proto_lp_advertise[0x20]; 7170 7171 u8 reserved_at_1a0[0x60]; 7172 }; 7173 7174 struct mlx5_ifc_mlcr_reg_bits { 7175 u8 reserved_at_0[0x8]; 7176 u8 local_port[0x8]; 7177 u8 reserved_at_10[0x20]; 7178 7179 u8 beacon_duration[0x10]; 7180 u8 reserved_at_40[0x10]; 7181 7182 u8 beacon_remain[0x10]; 7183 }; 7184 7185 struct mlx5_ifc_ptas_reg_bits { 7186 u8 reserved_at_0[0x20]; 7187 7188 u8 algorithm_options[0x10]; 7189 u8 reserved_at_30[0x4]; 7190 u8 repetitions_mode[0x4]; 7191 u8 num_of_repetitions[0x8]; 7192 7193 u8 grade_version[0x8]; 7194 u8 height_grade_type[0x4]; 7195 u8 phase_grade_type[0x4]; 7196 u8 height_grade_weight[0x8]; 7197 u8 phase_grade_weight[0x8]; 7198 7199 u8 gisim_measure_bits[0x10]; 7200 u8 adaptive_tap_measure_bits[0x10]; 7201 7202 u8 ber_bath_high_error_threshold[0x10]; 7203 u8 ber_bath_mid_error_threshold[0x10]; 7204 7205 u8 ber_bath_low_error_threshold[0x10]; 7206 u8 one_ratio_high_threshold[0x10]; 7207 7208 u8 one_ratio_high_mid_threshold[0x10]; 7209 u8 one_ratio_low_mid_threshold[0x10]; 7210 7211 u8 one_ratio_low_threshold[0x10]; 7212 u8 ndeo_error_threshold[0x10]; 7213 7214 u8 mixer_offset_step_size[0x10]; 7215 u8 reserved_at_110[0x8]; 7216 u8 mix90_phase_for_voltage_bath[0x8]; 7217 7218 u8 mixer_offset_start[0x10]; 7219 u8 mixer_offset_end[0x10]; 7220 7221 u8 reserved_at_140[0x15]; 7222 u8 ber_test_time[0xb]; 7223 }; 7224 7225 struct mlx5_ifc_pspa_reg_bits { 7226 u8 swid[0x8]; 7227 u8 local_port[0x8]; 7228 u8 sub_port[0x8]; 7229 u8 reserved_at_18[0x8]; 7230 7231 u8 reserved_at_20[0x20]; 7232 }; 7233 7234 struct mlx5_ifc_pqdr_reg_bits { 7235 u8 reserved_at_0[0x8]; 7236 u8 local_port[0x8]; 7237 u8 reserved_at_10[0x5]; 7238 u8 prio[0x3]; 7239 u8 reserved_at_18[0x6]; 7240 u8 mode[0x2]; 7241 7242 u8 reserved_at_20[0x20]; 7243 7244 u8 reserved_at_40[0x10]; 7245 u8 min_threshold[0x10]; 7246 7247 u8 reserved_at_60[0x10]; 7248 u8 max_threshold[0x10]; 7249 7250 u8 reserved_at_80[0x10]; 7251 u8 mark_probability_denominator[0x10]; 7252 7253 u8 reserved_at_a0[0x60]; 7254 }; 7255 7256 struct mlx5_ifc_ppsc_reg_bits { 7257 u8 reserved_at_0[0x8]; 7258 u8 local_port[0x8]; 7259 u8 reserved_at_10[0x10]; 7260 7261 u8 reserved_at_20[0x60]; 7262 7263 u8 reserved_at_80[0x1c]; 7264 u8 wrps_admin[0x4]; 7265 7266 u8 reserved_at_a0[0x1c]; 7267 u8 wrps_status[0x4]; 7268 7269 u8 reserved_at_c0[0x8]; 7270 u8 up_threshold[0x8]; 7271 u8 reserved_at_d0[0x8]; 7272 u8 down_threshold[0x8]; 7273 7274 u8 reserved_at_e0[0x20]; 7275 7276 u8 reserved_at_100[0x1c]; 7277 u8 srps_admin[0x4]; 7278 7279 u8 reserved_at_120[0x1c]; 7280 u8 srps_status[0x4]; 7281 7282 u8 reserved_at_140[0x40]; 7283 }; 7284 7285 struct mlx5_ifc_pplr_reg_bits { 7286 u8 reserved_at_0[0x8]; 7287 u8 local_port[0x8]; 7288 u8 reserved_at_10[0x10]; 7289 7290 u8 reserved_at_20[0x8]; 7291 u8 lb_cap[0x8]; 7292 u8 reserved_at_30[0x8]; 7293 u8 lb_en[0x8]; 7294 }; 7295 7296 struct mlx5_ifc_pplm_reg_bits { 7297 u8 reserved_at_0[0x8]; 7298 u8 local_port[0x8]; 7299 u8 reserved_at_10[0x10]; 7300 7301 u8 reserved_at_20[0x20]; 7302 7303 u8 port_profile_mode[0x8]; 7304 u8 static_port_profile[0x8]; 7305 u8 active_port_profile[0x8]; 7306 u8 reserved_at_58[0x8]; 7307 7308 u8 retransmission_active[0x8]; 7309 u8 fec_mode_active[0x18]; 7310 7311 u8 reserved_at_80[0x20]; 7312 }; 7313 7314 struct mlx5_ifc_ppcnt_reg_bits { 7315 u8 swid[0x8]; 7316 u8 local_port[0x8]; 7317 u8 pnat[0x2]; 7318 u8 reserved_at_12[0x8]; 7319 u8 grp[0x6]; 7320 7321 u8 clr[0x1]; 7322 u8 reserved_at_21[0x1c]; 7323 u8 prio_tc[0x3]; 7324 7325 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7326 }; 7327 7328 struct mlx5_ifc_mpcnt_reg_bits { 7329 u8 reserved_at_0[0x8]; 7330 u8 pcie_index[0x8]; 7331 u8 reserved_at_10[0xa]; 7332 u8 grp[0x6]; 7333 7334 u8 clr[0x1]; 7335 u8 reserved_at_21[0x1f]; 7336 7337 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 7338 }; 7339 7340 struct mlx5_ifc_ppad_reg_bits { 7341 u8 reserved_at_0[0x3]; 7342 u8 single_mac[0x1]; 7343 u8 reserved_at_4[0x4]; 7344 u8 local_port[0x8]; 7345 u8 mac_47_32[0x10]; 7346 7347 u8 mac_31_0[0x20]; 7348 7349 u8 reserved_at_40[0x40]; 7350 }; 7351 7352 struct mlx5_ifc_pmtu_reg_bits { 7353 u8 reserved_at_0[0x8]; 7354 u8 local_port[0x8]; 7355 u8 reserved_at_10[0x10]; 7356 7357 u8 max_mtu[0x10]; 7358 u8 reserved_at_30[0x10]; 7359 7360 u8 admin_mtu[0x10]; 7361 u8 reserved_at_50[0x10]; 7362 7363 u8 oper_mtu[0x10]; 7364 u8 reserved_at_70[0x10]; 7365 }; 7366 7367 struct mlx5_ifc_pmpr_reg_bits { 7368 u8 reserved_at_0[0x8]; 7369 u8 module[0x8]; 7370 u8 reserved_at_10[0x10]; 7371 7372 u8 reserved_at_20[0x18]; 7373 u8 attenuation_5g[0x8]; 7374 7375 u8 reserved_at_40[0x18]; 7376 u8 attenuation_7g[0x8]; 7377 7378 u8 reserved_at_60[0x18]; 7379 u8 attenuation_12g[0x8]; 7380 }; 7381 7382 struct mlx5_ifc_pmpe_reg_bits { 7383 u8 reserved_at_0[0x8]; 7384 u8 module[0x8]; 7385 u8 reserved_at_10[0xc]; 7386 u8 module_status[0x4]; 7387 7388 u8 reserved_at_20[0x60]; 7389 }; 7390 7391 struct mlx5_ifc_pmpc_reg_bits { 7392 u8 module_state_updated[32][0x8]; 7393 }; 7394 7395 struct mlx5_ifc_pmlpn_reg_bits { 7396 u8 reserved_at_0[0x4]; 7397 u8 mlpn_status[0x4]; 7398 u8 local_port[0x8]; 7399 u8 reserved_at_10[0x10]; 7400 7401 u8 e[0x1]; 7402 u8 reserved_at_21[0x1f]; 7403 }; 7404 7405 struct mlx5_ifc_pmlp_reg_bits { 7406 u8 rxtx[0x1]; 7407 u8 reserved_at_1[0x7]; 7408 u8 local_port[0x8]; 7409 u8 reserved_at_10[0x8]; 7410 u8 width[0x8]; 7411 7412 u8 lane0_module_mapping[0x20]; 7413 7414 u8 lane1_module_mapping[0x20]; 7415 7416 u8 lane2_module_mapping[0x20]; 7417 7418 u8 lane3_module_mapping[0x20]; 7419 7420 u8 reserved_at_a0[0x160]; 7421 }; 7422 7423 struct mlx5_ifc_pmaos_reg_bits { 7424 u8 reserved_at_0[0x8]; 7425 u8 module[0x8]; 7426 u8 reserved_at_10[0x4]; 7427 u8 admin_status[0x4]; 7428 u8 reserved_at_18[0x4]; 7429 u8 oper_status[0x4]; 7430 7431 u8 ase[0x1]; 7432 u8 ee[0x1]; 7433 u8 reserved_at_22[0x1c]; 7434 u8 e[0x2]; 7435 7436 u8 reserved_at_40[0x40]; 7437 }; 7438 7439 struct mlx5_ifc_plpc_reg_bits { 7440 u8 reserved_at_0[0x4]; 7441 u8 profile_id[0xc]; 7442 u8 reserved_at_10[0x4]; 7443 u8 proto_mask[0x4]; 7444 u8 reserved_at_18[0x8]; 7445 7446 u8 reserved_at_20[0x10]; 7447 u8 lane_speed[0x10]; 7448 7449 u8 reserved_at_40[0x17]; 7450 u8 lpbf[0x1]; 7451 u8 fec_mode_policy[0x8]; 7452 7453 u8 retransmission_capability[0x8]; 7454 u8 fec_mode_capability[0x18]; 7455 7456 u8 retransmission_support_admin[0x8]; 7457 u8 fec_mode_support_admin[0x18]; 7458 7459 u8 retransmission_request_admin[0x8]; 7460 u8 fec_mode_request_admin[0x18]; 7461 7462 u8 reserved_at_c0[0x80]; 7463 }; 7464 7465 struct mlx5_ifc_plib_reg_bits { 7466 u8 reserved_at_0[0x8]; 7467 u8 local_port[0x8]; 7468 u8 reserved_at_10[0x8]; 7469 u8 ib_port[0x8]; 7470 7471 u8 reserved_at_20[0x60]; 7472 }; 7473 7474 struct mlx5_ifc_plbf_reg_bits { 7475 u8 reserved_at_0[0x8]; 7476 u8 local_port[0x8]; 7477 u8 reserved_at_10[0xd]; 7478 u8 lbf_mode[0x3]; 7479 7480 u8 reserved_at_20[0x20]; 7481 }; 7482 7483 struct mlx5_ifc_pipg_reg_bits { 7484 u8 reserved_at_0[0x8]; 7485 u8 local_port[0x8]; 7486 u8 reserved_at_10[0x10]; 7487 7488 u8 dic[0x1]; 7489 u8 reserved_at_21[0x19]; 7490 u8 ipg[0x4]; 7491 u8 reserved_at_3e[0x2]; 7492 }; 7493 7494 struct mlx5_ifc_pifr_reg_bits { 7495 u8 reserved_at_0[0x8]; 7496 u8 local_port[0x8]; 7497 u8 reserved_at_10[0x10]; 7498 7499 u8 reserved_at_20[0xe0]; 7500 7501 u8 port_filter[8][0x20]; 7502 7503 u8 port_filter_update_en[8][0x20]; 7504 }; 7505 7506 struct mlx5_ifc_pfcc_reg_bits { 7507 u8 reserved_at_0[0x8]; 7508 u8 local_port[0x8]; 7509 u8 reserved_at_10[0x10]; 7510 7511 u8 ppan[0x4]; 7512 u8 reserved_at_24[0x4]; 7513 u8 prio_mask_tx[0x8]; 7514 u8 reserved_at_30[0x8]; 7515 u8 prio_mask_rx[0x8]; 7516 7517 u8 pptx[0x1]; 7518 u8 aptx[0x1]; 7519 u8 reserved_at_42[0x6]; 7520 u8 pfctx[0x8]; 7521 u8 reserved_at_50[0x10]; 7522 7523 u8 pprx[0x1]; 7524 u8 aprx[0x1]; 7525 u8 reserved_at_62[0x6]; 7526 u8 pfcrx[0x8]; 7527 u8 reserved_at_70[0x10]; 7528 7529 u8 reserved_at_80[0x80]; 7530 }; 7531 7532 struct mlx5_ifc_pelc_reg_bits { 7533 u8 op[0x4]; 7534 u8 reserved_at_4[0x4]; 7535 u8 local_port[0x8]; 7536 u8 reserved_at_10[0x10]; 7537 7538 u8 op_admin[0x8]; 7539 u8 op_capability[0x8]; 7540 u8 op_request[0x8]; 7541 u8 op_active[0x8]; 7542 7543 u8 admin[0x40]; 7544 7545 u8 capability[0x40]; 7546 7547 u8 request[0x40]; 7548 7549 u8 active[0x40]; 7550 7551 u8 reserved_at_140[0x80]; 7552 }; 7553 7554 struct mlx5_ifc_peir_reg_bits { 7555 u8 reserved_at_0[0x8]; 7556 u8 local_port[0x8]; 7557 u8 reserved_at_10[0x10]; 7558 7559 u8 reserved_at_20[0xc]; 7560 u8 error_count[0x4]; 7561 u8 reserved_at_30[0x10]; 7562 7563 u8 reserved_at_40[0xc]; 7564 u8 lane[0x4]; 7565 u8 reserved_at_50[0x8]; 7566 u8 error_type[0x8]; 7567 }; 7568 7569 struct mlx5_ifc_pcap_reg_bits { 7570 u8 reserved_at_0[0x8]; 7571 u8 local_port[0x8]; 7572 u8 reserved_at_10[0x10]; 7573 7574 u8 port_capability_mask[4][0x20]; 7575 }; 7576 7577 struct mlx5_ifc_paos_reg_bits { 7578 u8 swid[0x8]; 7579 u8 local_port[0x8]; 7580 u8 reserved_at_10[0x4]; 7581 u8 admin_status[0x4]; 7582 u8 reserved_at_18[0x4]; 7583 u8 oper_status[0x4]; 7584 7585 u8 ase[0x1]; 7586 u8 ee[0x1]; 7587 u8 reserved_at_22[0x1c]; 7588 u8 e[0x2]; 7589 7590 u8 reserved_at_40[0x40]; 7591 }; 7592 7593 struct mlx5_ifc_pamp_reg_bits { 7594 u8 reserved_at_0[0x8]; 7595 u8 opamp_group[0x8]; 7596 u8 reserved_at_10[0xc]; 7597 u8 opamp_group_type[0x4]; 7598 7599 u8 start_index[0x10]; 7600 u8 reserved_at_30[0x4]; 7601 u8 num_of_indices[0xc]; 7602 7603 u8 index_data[18][0x10]; 7604 }; 7605 7606 struct mlx5_ifc_pcmr_reg_bits { 7607 u8 reserved_at_0[0x8]; 7608 u8 local_port[0x8]; 7609 u8 reserved_at_10[0x2e]; 7610 u8 fcs_cap[0x1]; 7611 u8 reserved_at_3f[0x1f]; 7612 u8 fcs_chk[0x1]; 7613 u8 reserved_at_5f[0x1]; 7614 }; 7615 7616 struct mlx5_ifc_lane_2_module_mapping_bits { 7617 u8 reserved_at_0[0x6]; 7618 u8 rx_lane[0x2]; 7619 u8 reserved_at_8[0x6]; 7620 u8 tx_lane[0x2]; 7621 u8 reserved_at_10[0x8]; 7622 u8 module[0x8]; 7623 }; 7624 7625 struct mlx5_ifc_bufferx_reg_bits { 7626 u8 reserved_at_0[0x6]; 7627 u8 lossy[0x1]; 7628 u8 epsb[0x1]; 7629 u8 reserved_at_8[0xc]; 7630 u8 size[0xc]; 7631 7632 u8 xoff_threshold[0x10]; 7633 u8 xon_threshold[0x10]; 7634 }; 7635 7636 struct mlx5_ifc_set_node_in_bits { 7637 u8 node_description[64][0x8]; 7638 }; 7639 7640 struct mlx5_ifc_register_power_settings_bits { 7641 u8 reserved_at_0[0x18]; 7642 u8 power_settings_level[0x8]; 7643 7644 u8 reserved_at_20[0x60]; 7645 }; 7646 7647 struct mlx5_ifc_register_host_endianness_bits { 7648 u8 he[0x1]; 7649 u8 reserved_at_1[0x1f]; 7650 7651 u8 reserved_at_20[0x60]; 7652 }; 7653 7654 struct mlx5_ifc_umr_pointer_desc_argument_bits { 7655 u8 reserved_at_0[0x20]; 7656 7657 u8 mkey[0x20]; 7658 7659 u8 addressh_63_32[0x20]; 7660 7661 u8 addressl_31_0[0x20]; 7662 }; 7663 7664 struct mlx5_ifc_ud_adrs_vector_bits { 7665 u8 dc_key[0x40]; 7666 7667 u8 ext[0x1]; 7668 u8 reserved_at_41[0x7]; 7669 u8 destination_qp_dct[0x18]; 7670 7671 u8 static_rate[0x4]; 7672 u8 sl_eth_prio[0x4]; 7673 u8 fl[0x1]; 7674 u8 mlid[0x7]; 7675 u8 rlid_udp_sport[0x10]; 7676 7677 u8 reserved_at_80[0x20]; 7678 7679 u8 rmac_47_16[0x20]; 7680 7681 u8 rmac_15_0[0x10]; 7682 u8 tclass[0x8]; 7683 u8 hop_limit[0x8]; 7684 7685 u8 reserved_at_e0[0x1]; 7686 u8 grh[0x1]; 7687 u8 reserved_at_e2[0x2]; 7688 u8 src_addr_index[0x8]; 7689 u8 flow_label[0x14]; 7690 7691 u8 rgid_rip[16][0x8]; 7692 }; 7693 7694 struct mlx5_ifc_pages_req_event_bits { 7695 u8 reserved_at_0[0x10]; 7696 u8 function_id[0x10]; 7697 7698 u8 num_pages[0x20]; 7699 7700 u8 reserved_at_40[0xa0]; 7701 }; 7702 7703 struct mlx5_ifc_eqe_bits { 7704 u8 reserved_at_0[0x8]; 7705 u8 event_type[0x8]; 7706 u8 reserved_at_10[0x8]; 7707 u8 event_sub_type[0x8]; 7708 7709 u8 reserved_at_20[0xe0]; 7710 7711 union mlx5_ifc_event_auto_bits event_data; 7712 7713 u8 reserved_at_1e0[0x10]; 7714 u8 signature[0x8]; 7715 u8 reserved_at_1f8[0x7]; 7716 u8 owner[0x1]; 7717 }; 7718 7719 enum { 7720 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 7721 }; 7722 7723 struct mlx5_ifc_cmd_queue_entry_bits { 7724 u8 type[0x8]; 7725 u8 reserved_at_8[0x18]; 7726 7727 u8 input_length[0x20]; 7728 7729 u8 input_mailbox_pointer_63_32[0x20]; 7730 7731 u8 input_mailbox_pointer_31_9[0x17]; 7732 u8 reserved_at_77[0x9]; 7733 7734 u8 command_input_inline_data[16][0x8]; 7735 7736 u8 command_output_inline_data[16][0x8]; 7737 7738 u8 output_mailbox_pointer_63_32[0x20]; 7739 7740 u8 output_mailbox_pointer_31_9[0x17]; 7741 u8 reserved_at_1b7[0x9]; 7742 7743 u8 output_length[0x20]; 7744 7745 u8 token[0x8]; 7746 u8 signature[0x8]; 7747 u8 reserved_at_1f0[0x8]; 7748 u8 status[0x7]; 7749 u8 ownership[0x1]; 7750 }; 7751 7752 struct mlx5_ifc_cmd_out_bits { 7753 u8 status[0x8]; 7754 u8 reserved_at_8[0x18]; 7755 7756 u8 syndrome[0x20]; 7757 7758 u8 command_output[0x20]; 7759 }; 7760 7761 struct mlx5_ifc_cmd_in_bits { 7762 u8 opcode[0x10]; 7763 u8 reserved_at_10[0x10]; 7764 7765 u8 reserved_at_20[0x10]; 7766 u8 op_mod[0x10]; 7767 7768 u8 command[0][0x20]; 7769 }; 7770 7771 struct mlx5_ifc_cmd_if_box_bits { 7772 u8 mailbox_data[512][0x8]; 7773 7774 u8 reserved_at_1000[0x180]; 7775 7776 u8 next_pointer_63_32[0x20]; 7777 7778 u8 next_pointer_31_10[0x16]; 7779 u8 reserved_at_11b6[0xa]; 7780 7781 u8 block_number[0x20]; 7782 7783 u8 reserved_at_11e0[0x8]; 7784 u8 token[0x8]; 7785 u8 ctrl_signature[0x8]; 7786 u8 signature[0x8]; 7787 }; 7788 7789 struct mlx5_ifc_mtt_bits { 7790 u8 ptag_63_32[0x20]; 7791 7792 u8 ptag_31_8[0x18]; 7793 u8 reserved_at_38[0x6]; 7794 u8 wr_en[0x1]; 7795 u8 rd_en[0x1]; 7796 }; 7797 7798 struct mlx5_ifc_query_wol_rol_out_bits { 7799 u8 status[0x8]; 7800 u8 reserved_at_8[0x18]; 7801 7802 u8 syndrome[0x20]; 7803 7804 u8 reserved_at_40[0x10]; 7805 u8 rol_mode[0x8]; 7806 u8 wol_mode[0x8]; 7807 7808 u8 reserved_at_60[0x20]; 7809 }; 7810 7811 struct mlx5_ifc_query_wol_rol_in_bits { 7812 u8 opcode[0x10]; 7813 u8 reserved_at_10[0x10]; 7814 7815 u8 reserved_at_20[0x10]; 7816 u8 op_mod[0x10]; 7817 7818 u8 reserved_at_40[0x40]; 7819 }; 7820 7821 struct mlx5_ifc_set_wol_rol_out_bits { 7822 u8 status[0x8]; 7823 u8 reserved_at_8[0x18]; 7824 7825 u8 syndrome[0x20]; 7826 7827 u8 reserved_at_40[0x40]; 7828 }; 7829 7830 struct mlx5_ifc_set_wol_rol_in_bits { 7831 u8 opcode[0x10]; 7832 u8 reserved_at_10[0x10]; 7833 7834 u8 reserved_at_20[0x10]; 7835 u8 op_mod[0x10]; 7836 7837 u8 rol_mode_valid[0x1]; 7838 u8 wol_mode_valid[0x1]; 7839 u8 reserved_at_42[0xe]; 7840 u8 rol_mode[0x8]; 7841 u8 wol_mode[0x8]; 7842 7843 u8 reserved_at_60[0x20]; 7844 }; 7845 7846 enum { 7847 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 7848 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 7849 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 7850 }; 7851 7852 enum { 7853 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 7854 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 7855 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 7856 }; 7857 7858 enum { 7859 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 7860 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 7861 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 7862 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 7863 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 7864 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 7865 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 7866 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 7867 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 7868 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 7869 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 7870 }; 7871 7872 struct mlx5_ifc_initial_seg_bits { 7873 u8 fw_rev_minor[0x10]; 7874 u8 fw_rev_major[0x10]; 7875 7876 u8 cmd_interface_rev[0x10]; 7877 u8 fw_rev_subminor[0x10]; 7878 7879 u8 reserved_at_40[0x40]; 7880 7881 u8 cmdq_phy_addr_63_32[0x20]; 7882 7883 u8 cmdq_phy_addr_31_12[0x14]; 7884 u8 reserved_at_b4[0x2]; 7885 u8 nic_interface[0x2]; 7886 u8 log_cmdq_size[0x4]; 7887 u8 log_cmdq_stride[0x4]; 7888 7889 u8 command_doorbell_vector[0x20]; 7890 7891 u8 reserved_at_e0[0xf00]; 7892 7893 u8 initializing[0x1]; 7894 u8 reserved_at_fe1[0x4]; 7895 u8 nic_interface_supported[0x3]; 7896 u8 reserved_at_fe8[0x18]; 7897 7898 struct mlx5_ifc_health_buffer_bits health_buffer; 7899 7900 u8 no_dram_nic_offset[0x20]; 7901 7902 u8 reserved_at_1220[0x6e40]; 7903 7904 u8 reserved_at_8060[0x1f]; 7905 u8 clear_int[0x1]; 7906 7907 u8 health_syndrome[0x8]; 7908 u8 health_counter[0x18]; 7909 7910 u8 reserved_at_80a0[0x17fc0]; 7911 }; 7912 7913 union mlx5_ifc_ports_control_registers_document_bits { 7914 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 7915 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 7916 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 7917 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 7918 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 7919 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 7920 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 7921 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 7922 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 7923 struct mlx5_ifc_pamp_reg_bits pamp_reg; 7924 struct mlx5_ifc_paos_reg_bits paos_reg; 7925 struct mlx5_ifc_pcap_reg_bits pcap_reg; 7926 struct mlx5_ifc_peir_reg_bits peir_reg; 7927 struct mlx5_ifc_pelc_reg_bits pelc_reg; 7928 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 7929 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 7930 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 7931 struct mlx5_ifc_pifr_reg_bits pifr_reg; 7932 struct mlx5_ifc_pipg_reg_bits pipg_reg; 7933 struct mlx5_ifc_plbf_reg_bits plbf_reg; 7934 struct mlx5_ifc_plib_reg_bits plib_reg; 7935 struct mlx5_ifc_plpc_reg_bits plpc_reg; 7936 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 7937 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 7938 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 7939 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 7940 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 7941 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 7942 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 7943 struct mlx5_ifc_ppad_reg_bits ppad_reg; 7944 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 7945 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 7946 struct mlx5_ifc_pplm_reg_bits pplm_reg; 7947 struct mlx5_ifc_pplr_reg_bits pplr_reg; 7948 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 7949 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 7950 struct mlx5_ifc_pspa_reg_bits pspa_reg; 7951 struct mlx5_ifc_ptas_reg_bits ptas_reg; 7952 struct mlx5_ifc_ptys_reg_bits ptys_reg; 7953 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 7954 struct mlx5_ifc_pude_reg_bits pude_reg; 7955 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 7956 struct mlx5_ifc_slrg_reg_bits slrg_reg; 7957 struct mlx5_ifc_sltp_reg_bits sltp_reg; 7958 u8 reserved_at_0[0x60e0]; 7959 }; 7960 7961 union mlx5_ifc_debug_enhancements_document_bits { 7962 struct mlx5_ifc_health_buffer_bits health_buffer; 7963 u8 reserved_at_0[0x200]; 7964 }; 7965 7966 union mlx5_ifc_uplink_pci_interface_document_bits { 7967 struct mlx5_ifc_initial_seg_bits initial_seg; 7968 u8 reserved_at_0[0x20060]; 7969 }; 7970 7971 struct mlx5_ifc_set_flow_table_root_out_bits { 7972 u8 status[0x8]; 7973 u8 reserved_at_8[0x18]; 7974 7975 u8 syndrome[0x20]; 7976 7977 u8 reserved_at_40[0x40]; 7978 }; 7979 7980 struct mlx5_ifc_set_flow_table_root_in_bits { 7981 u8 opcode[0x10]; 7982 u8 reserved_at_10[0x10]; 7983 7984 u8 reserved_at_20[0x10]; 7985 u8 op_mod[0x10]; 7986 7987 u8 other_vport[0x1]; 7988 u8 reserved_at_41[0xf]; 7989 u8 vport_number[0x10]; 7990 7991 u8 reserved_at_60[0x20]; 7992 7993 u8 table_type[0x8]; 7994 u8 reserved_at_88[0x18]; 7995 7996 u8 reserved_at_a0[0x8]; 7997 u8 table_id[0x18]; 7998 7999 u8 reserved_at_c0[0x140]; 8000 }; 8001 8002 enum { 8003 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8004 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8005 }; 8006 8007 struct mlx5_ifc_modify_flow_table_out_bits { 8008 u8 status[0x8]; 8009 u8 reserved_at_8[0x18]; 8010 8011 u8 syndrome[0x20]; 8012 8013 u8 reserved_at_40[0x40]; 8014 }; 8015 8016 struct mlx5_ifc_modify_flow_table_in_bits { 8017 u8 opcode[0x10]; 8018 u8 reserved_at_10[0x10]; 8019 8020 u8 reserved_at_20[0x10]; 8021 u8 op_mod[0x10]; 8022 8023 u8 other_vport[0x1]; 8024 u8 reserved_at_41[0xf]; 8025 u8 vport_number[0x10]; 8026 8027 u8 reserved_at_60[0x10]; 8028 u8 modify_field_select[0x10]; 8029 8030 u8 table_type[0x8]; 8031 u8 reserved_at_88[0x18]; 8032 8033 u8 reserved_at_a0[0x8]; 8034 u8 table_id[0x18]; 8035 8036 u8 reserved_at_c0[0x4]; 8037 u8 table_miss_mode[0x4]; 8038 u8 reserved_at_c8[0x18]; 8039 8040 u8 reserved_at_e0[0x8]; 8041 u8 table_miss_id[0x18]; 8042 8043 u8 reserved_at_100[0x8]; 8044 u8 lag_master_next_table_id[0x18]; 8045 8046 u8 reserved_at_120[0x80]; 8047 }; 8048 8049 struct mlx5_ifc_ets_tcn_config_reg_bits { 8050 u8 g[0x1]; 8051 u8 b[0x1]; 8052 u8 r[0x1]; 8053 u8 reserved_at_3[0x9]; 8054 u8 group[0x4]; 8055 u8 reserved_at_10[0x9]; 8056 u8 bw_allocation[0x7]; 8057 8058 u8 reserved_at_20[0xc]; 8059 u8 max_bw_units[0x4]; 8060 u8 reserved_at_30[0x8]; 8061 u8 max_bw_value[0x8]; 8062 }; 8063 8064 struct mlx5_ifc_ets_global_config_reg_bits { 8065 u8 reserved_at_0[0x2]; 8066 u8 r[0x1]; 8067 u8 reserved_at_3[0x1d]; 8068 8069 u8 reserved_at_20[0xc]; 8070 u8 max_bw_units[0x4]; 8071 u8 reserved_at_30[0x8]; 8072 u8 max_bw_value[0x8]; 8073 }; 8074 8075 struct mlx5_ifc_qetc_reg_bits { 8076 u8 reserved_at_0[0x8]; 8077 u8 port_number[0x8]; 8078 u8 reserved_at_10[0x30]; 8079 8080 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 8081 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 8082 }; 8083 8084 struct mlx5_ifc_qtct_reg_bits { 8085 u8 reserved_at_0[0x8]; 8086 u8 port_number[0x8]; 8087 u8 reserved_at_10[0xd]; 8088 u8 prio[0x3]; 8089 8090 u8 reserved_at_20[0x1d]; 8091 u8 tclass[0x3]; 8092 }; 8093 8094 struct mlx5_ifc_mcia_reg_bits { 8095 u8 l[0x1]; 8096 u8 reserved_at_1[0x7]; 8097 u8 module[0x8]; 8098 u8 reserved_at_10[0x8]; 8099 u8 status[0x8]; 8100 8101 u8 i2c_device_address[0x8]; 8102 u8 page_number[0x8]; 8103 u8 device_address[0x10]; 8104 8105 u8 reserved_at_40[0x10]; 8106 u8 size[0x10]; 8107 8108 u8 reserved_at_60[0x20]; 8109 8110 u8 dword_0[0x20]; 8111 u8 dword_1[0x20]; 8112 u8 dword_2[0x20]; 8113 u8 dword_3[0x20]; 8114 u8 dword_4[0x20]; 8115 u8 dword_5[0x20]; 8116 u8 dword_6[0x20]; 8117 u8 dword_7[0x20]; 8118 u8 dword_8[0x20]; 8119 u8 dword_9[0x20]; 8120 u8 dword_10[0x20]; 8121 u8 dword_11[0x20]; 8122 }; 8123 8124 struct mlx5_ifc_dcbx_param_bits { 8125 u8 dcbx_cee_cap[0x1]; 8126 u8 dcbx_ieee_cap[0x1]; 8127 u8 dcbx_standby_cap[0x1]; 8128 u8 reserved_at_0[0x5]; 8129 u8 port_number[0x8]; 8130 u8 reserved_at_10[0xa]; 8131 u8 max_application_table_size[6]; 8132 u8 reserved_at_20[0x15]; 8133 u8 version_oper[0x3]; 8134 u8 reserved_at_38[5]; 8135 u8 version_admin[0x3]; 8136 u8 willing_admin[0x1]; 8137 u8 reserved_at_41[0x3]; 8138 u8 pfc_cap_oper[0x4]; 8139 u8 reserved_at_48[0x4]; 8140 u8 pfc_cap_admin[0x4]; 8141 u8 reserved_at_50[0x4]; 8142 u8 num_of_tc_oper[0x4]; 8143 u8 reserved_at_58[0x4]; 8144 u8 num_of_tc_admin[0x4]; 8145 u8 remote_willing[0x1]; 8146 u8 reserved_at_61[3]; 8147 u8 remote_pfc_cap[4]; 8148 u8 reserved_at_68[0x14]; 8149 u8 remote_num_of_tc[0x4]; 8150 u8 reserved_at_80[0x18]; 8151 u8 error[0x8]; 8152 u8 reserved_at_a0[0x160]; 8153 }; 8154 8155 struct mlx5_ifc_lagc_bits { 8156 u8 reserved_at_0[0x1d]; 8157 u8 lag_state[0x3]; 8158 8159 u8 reserved_at_20[0x14]; 8160 u8 tx_remap_affinity_2[0x4]; 8161 u8 reserved_at_38[0x4]; 8162 u8 tx_remap_affinity_1[0x4]; 8163 }; 8164 8165 struct mlx5_ifc_create_lag_out_bits { 8166 u8 status[0x8]; 8167 u8 reserved_at_8[0x18]; 8168 8169 u8 syndrome[0x20]; 8170 8171 u8 reserved_at_40[0x40]; 8172 }; 8173 8174 struct mlx5_ifc_create_lag_in_bits { 8175 u8 opcode[0x10]; 8176 u8 reserved_at_10[0x10]; 8177 8178 u8 reserved_at_20[0x10]; 8179 u8 op_mod[0x10]; 8180 8181 struct mlx5_ifc_lagc_bits ctx; 8182 }; 8183 8184 struct mlx5_ifc_modify_lag_out_bits { 8185 u8 status[0x8]; 8186 u8 reserved_at_8[0x18]; 8187 8188 u8 syndrome[0x20]; 8189 8190 u8 reserved_at_40[0x40]; 8191 }; 8192 8193 struct mlx5_ifc_modify_lag_in_bits { 8194 u8 opcode[0x10]; 8195 u8 reserved_at_10[0x10]; 8196 8197 u8 reserved_at_20[0x10]; 8198 u8 op_mod[0x10]; 8199 8200 u8 reserved_at_40[0x20]; 8201 u8 field_select[0x20]; 8202 8203 struct mlx5_ifc_lagc_bits ctx; 8204 }; 8205 8206 struct mlx5_ifc_query_lag_out_bits { 8207 u8 status[0x8]; 8208 u8 reserved_at_8[0x18]; 8209 8210 u8 syndrome[0x20]; 8211 8212 u8 reserved_at_40[0x40]; 8213 8214 struct mlx5_ifc_lagc_bits ctx; 8215 }; 8216 8217 struct mlx5_ifc_query_lag_in_bits { 8218 u8 opcode[0x10]; 8219 u8 reserved_at_10[0x10]; 8220 8221 u8 reserved_at_20[0x10]; 8222 u8 op_mod[0x10]; 8223 8224 u8 reserved_at_40[0x40]; 8225 }; 8226 8227 struct mlx5_ifc_destroy_lag_out_bits { 8228 u8 status[0x8]; 8229 u8 reserved_at_8[0x18]; 8230 8231 u8 syndrome[0x20]; 8232 8233 u8 reserved_at_40[0x40]; 8234 }; 8235 8236 struct mlx5_ifc_destroy_lag_in_bits { 8237 u8 opcode[0x10]; 8238 u8 reserved_at_10[0x10]; 8239 8240 u8 reserved_at_20[0x10]; 8241 u8 op_mod[0x10]; 8242 8243 u8 reserved_at_40[0x40]; 8244 }; 8245 8246 struct mlx5_ifc_create_vport_lag_out_bits { 8247 u8 status[0x8]; 8248 u8 reserved_at_8[0x18]; 8249 8250 u8 syndrome[0x20]; 8251 8252 u8 reserved_at_40[0x40]; 8253 }; 8254 8255 struct mlx5_ifc_create_vport_lag_in_bits { 8256 u8 opcode[0x10]; 8257 u8 reserved_at_10[0x10]; 8258 8259 u8 reserved_at_20[0x10]; 8260 u8 op_mod[0x10]; 8261 8262 u8 reserved_at_40[0x40]; 8263 }; 8264 8265 struct mlx5_ifc_destroy_vport_lag_out_bits { 8266 u8 status[0x8]; 8267 u8 reserved_at_8[0x18]; 8268 8269 u8 syndrome[0x20]; 8270 8271 u8 reserved_at_40[0x40]; 8272 }; 8273 8274 struct mlx5_ifc_destroy_vport_lag_in_bits { 8275 u8 opcode[0x10]; 8276 u8 reserved_at_10[0x10]; 8277 8278 u8 reserved_at_20[0x10]; 8279 u8 op_mod[0x10]; 8280 8281 u8 reserved_at_40[0x40]; 8282 }; 8283 8284 #endif /* MLX5_IFC_H */ 8285