1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 enum { 36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb 60 }; 61 62 enum { 63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 67 }; 68 69 enum { 70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 72 }; 73 74 enum { 75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 77 MLX5_CMD_OP_INIT_HCA = 0x102, 78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 79 MLX5_CMD_OP_ENABLE_HCA = 0x104, 80 MLX5_CMD_OP_DISABLE_HCA = 0x105, 81 MLX5_CMD_OP_QUERY_PAGES = 0x107, 82 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 83 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 85 MLX5_CMD_OP_SET_ISSI = 0x10b, 86 MLX5_CMD_OP_CREATE_MKEY = 0x200, 87 MLX5_CMD_OP_QUERY_MKEY = 0x201, 88 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 91 MLX5_CMD_OP_CREATE_EQ = 0x301, 92 MLX5_CMD_OP_DESTROY_EQ = 0x302, 93 MLX5_CMD_OP_QUERY_EQ = 0x303, 94 MLX5_CMD_OP_GEN_EQE = 0x304, 95 MLX5_CMD_OP_CREATE_CQ = 0x400, 96 MLX5_CMD_OP_DESTROY_CQ = 0x401, 97 MLX5_CMD_OP_QUERY_CQ = 0x402, 98 MLX5_CMD_OP_MODIFY_CQ = 0x403, 99 MLX5_CMD_OP_CREATE_QP = 0x500, 100 MLX5_CMD_OP_DESTROY_QP = 0x501, 101 MLX5_CMD_OP_RST2INIT_QP = 0x502, 102 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 103 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 104 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 106 MLX5_CMD_OP_2ERR_QP = 0x507, 107 MLX5_CMD_OP_2RST_QP = 0x50a, 108 MLX5_CMD_OP_QUERY_QP = 0x50b, 109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 111 MLX5_CMD_OP_CREATE_PSV = 0x600, 112 MLX5_CMD_OP_DESTROY_PSV = 0x601, 113 MLX5_CMD_OP_CREATE_SRQ = 0x700, 114 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 115 MLX5_CMD_OP_QUERY_SRQ = 0x702, 116 MLX5_CMD_OP_ARM_RQ = 0x703, 117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 121 MLX5_CMD_OP_CREATE_DCT = 0x710, 122 MLX5_CMD_OP_DESTROY_DCT = 0x711, 123 MLX5_CMD_OP_DRAIN_DCT = 0x712, 124 MLX5_CMD_OP_QUERY_DCT = 0x713, 125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 126 MLX5_CMD_OP_CREATE_XRQ = 0x717, 127 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 128 MLX5_CMD_OP_QUERY_XRQ = 0x719, 129 MLX5_CMD_OP_ARM_XRQ = 0x71a, 130 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 131 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 132 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 133 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 134 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 135 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 136 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 137 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 138 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 139 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 140 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 141 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 142 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 143 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 144 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 145 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 146 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 147 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 148 MLX5_CMD_OP_ALLOC_PD = 0x800, 149 MLX5_CMD_OP_DEALLOC_PD = 0x801, 150 MLX5_CMD_OP_ALLOC_UAR = 0x802, 151 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 152 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 153 MLX5_CMD_OP_ACCESS_REG = 0x805, 154 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 155 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 156 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 157 MLX5_CMD_OP_MAD_IFC = 0x50d, 158 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 159 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 160 MLX5_CMD_OP_NOP = 0x80d, 161 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 162 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 163 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 164 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 165 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 166 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 167 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 168 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 169 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 170 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 171 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 172 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 173 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 174 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 175 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 176 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 177 MLX5_CMD_OP_CREATE_LAG = 0x840, 178 MLX5_CMD_OP_MODIFY_LAG = 0x841, 179 MLX5_CMD_OP_QUERY_LAG = 0x842, 180 MLX5_CMD_OP_DESTROY_LAG = 0x843, 181 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 182 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 183 MLX5_CMD_OP_CREATE_TIR = 0x900, 184 MLX5_CMD_OP_MODIFY_TIR = 0x901, 185 MLX5_CMD_OP_DESTROY_TIR = 0x902, 186 MLX5_CMD_OP_QUERY_TIR = 0x903, 187 MLX5_CMD_OP_CREATE_SQ = 0x904, 188 MLX5_CMD_OP_MODIFY_SQ = 0x905, 189 MLX5_CMD_OP_DESTROY_SQ = 0x906, 190 MLX5_CMD_OP_QUERY_SQ = 0x907, 191 MLX5_CMD_OP_CREATE_RQ = 0x908, 192 MLX5_CMD_OP_MODIFY_RQ = 0x909, 193 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 194 MLX5_CMD_OP_QUERY_RQ = 0x90b, 195 MLX5_CMD_OP_CREATE_RMP = 0x90c, 196 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 197 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 198 MLX5_CMD_OP_QUERY_RMP = 0x90f, 199 MLX5_CMD_OP_CREATE_TIS = 0x912, 200 MLX5_CMD_OP_MODIFY_TIS = 0x913, 201 MLX5_CMD_OP_DESTROY_TIS = 0x914, 202 MLX5_CMD_OP_QUERY_TIS = 0x915, 203 MLX5_CMD_OP_CREATE_RQT = 0x916, 204 MLX5_CMD_OP_MODIFY_RQT = 0x917, 205 MLX5_CMD_OP_DESTROY_RQT = 0x918, 206 MLX5_CMD_OP_QUERY_RQT = 0x919, 207 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 208 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 209 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 210 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 211 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 212 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 213 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 214 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 215 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 216 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 217 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 218 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 219 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 220 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 221 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 222 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 223 MLX5_CMD_OP_MAX 224 }; 225 226 struct mlx5_ifc_flow_table_fields_supported_bits { 227 u8 outer_dmac[0x1]; 228 u8 outer_smac[0x1]; 229 u8 outer_ether_type[0x1]; 230 u8 reserved_at_3[0x1]; 231 u8 outer_first_prio[0x1]; 232 u8 outer_first_cfi[0x1]; 233 u8 outer_first_vid[0x1]; 234 u8 reserved_at_7[0x1]; 235 u8 outer_second_prio[0x1]; 236 u8 outer_second_cfi[0x1]; 237 u8 outer_second_vid[0x1]; 238 u8 reserved_at_b[0x1]; 239 u8 outer_sip[0x1]; 240 u8 outer_dip[0x1]; 241 u8 outer_frag[0x1]; 242 u8 outer_ip_protocol[0x1]; 243 u8 outer_ip_ecn[0x1]; 244 u8 outer_ip_dscp[0x1]; 245 u8 outer_udp_sport[0x1]; 246 u8 outer_udp_dport[0x1]; 247 u8 outer_tcp_sport[0x1]; 248 u8 outer_tcp_dport[0x1]; 249 u8 outer_tcp_flags[0x1]; 250 u8 outer_gre_protocol[0x1]; 251 u8 outer_gre_key[0x1]; 252 u8 outer_vxlan_vni[0x1]; 253 u8 reserved_at_1a[0x5]; 254 u8 source_eswitch_port[0x1]; 255 256 u8 inner_dmac[0x1]; 257 u8 inner_smac[0x1]; 258 u8 inner_ether_type[0x1]; 259 u8 reserved_at_23[0x1]; 260 u8 inner_first_prio[0x1]; 261 u8 inner_first_cfi[0x1]; 262 u8 inner_first_vid[0x1]; 263 u8 reserved_at_27[0x1]; 264 u8 inner_second_prio[0x1]; 265 u8 inner_second_cfi[0x1]; 266 u8 inner_second_vid[0x1]; 267 u8 reserved_at_2b[0x1]; 268 u8 inner_sip[0x1]; 269 u8 inner_dip[0x1]; 270 u8 inner_frag[0x1]; 271 u8 inner_ip_protocol[0x1]; 272 u8 inner_ip_ecn[0x1]; 273 u8 inner_ip_dscp[0x1]; 274 u8 inner_udp_sport[0x1]; 275 u8 inner_udp_dport[0x1]; 276 u8 inner_tcp_sport[0x1]; 277 u8 inner_tcp_dport[0x1]; 278 u8 inner_tcp_flags[0x1]; 279 u8 reserved_at_37[0x9]; 280 281 u8 reserved_at_40[0x40]; 282 }; 283 284 struct mlx5_ifc_flow_table_prop_layout_bits { 285 u8 ft_support[0x1]; 286 u8 reserved_at_1[0x1]; 287 u8 flow_counter[0x1]; 288 u8 flow_modify_en[0x1]; 289 u8 modify_root[0x1]; 290 u8 identified_miss_table_mode[0x1]; 291 u8 flow_table_modify[0x1]; 292 u8 encap[0x1]; 293 u8 decap[0x1]; 294 u8 reserved_at_9[0x17]; 295 296 u8 reserved_at_20[0x2]; 297 u8 log_max_ft_size[0x6]; 298 u8 reserved_at_28[0x10]; 299 u8 max_ft_level[0x8]; 300 301 u8 reserved_at_40[0x20]; 302 303 u8 reserved_at_60[0x18]; 304 u8 log_max_ft_num[0x8]; 305 306 u8 reserved_at_80[0x18]; 307 u8 log_max_destination[0x8]; 308 309 u8 reserved_at_a0[0x18]; 310 u8 log_max_flow[0x8]; 311 312 u8 reserved_at_c0[0x40]; 313 314 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 315 316 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 317 }; 318 319 struct mlx5_ifc_odp_per_transport_service_cap_bits { 320 u8 send[0x1]; 321 u8 receive[0x1]; 322 u8 write[0x1]; 323 u8 read[0x1]; 324 u8 reserved_at_4[0x1]; 325 u8 srq_receive[0x1]; 326 u8 reserved_at_6[0x1a]; 327 }; 328 329 struct mlx5_ifc_ipv4_layout_bits { 330 u8 reserved_at_0[0x60]; 331 332 u8 ipv4[0x20]; 333 }; 334 335 struct mlx5_ifc_ipv6_layout_bits { 336 u8 ipv6[16][0x8]; 337 }; 338 339 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 340 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 341 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 342 u8 reserved_at_0[0x80]; 343 }; 344 345 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 346 u8 smac_47_16[0x20]; 347 348 u8 smac_15_0[0x10]; 349 u8 ethertype[0x10]; 350 351 u8 dmac_47_16[0x20]; 352 353 u8 dmac_15_0[0x10]; 354 u8 first_prio[0x3]; 355 u8 first_cfi[0x1]; 356 u8 first_vid[0xc]; 357 358 u8 ip_protocol[0x8]; 359 u8 ip_dscp[0x6]; 360 u8 ip_ecn[0x2]; 361 u8 vlan_tag[0x1]; 362 u8 reserved_at_91[0x1]; 363 u8 frag[0x1]; 364 u8 reserved_at_93[0x4]; 365 u8 tcp_flags[0x9]; 366 367 u8 tcp_sport[0x10]; 368 u8 tcp_dport[0x10]; 369 370 u8 reserved_at_c0[0x20]; 371 372 u8 udp_sport[0x10]; 373 u8 udp_dport[0x10]; 374 375 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 376 377 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 378 }; 379 380 struct mlx5_ifc_fte_match_set_misc_bits { 381 u8 reserved_at_0[0x8]; 382 u8 source_sqn[0x18]; 383 384 u8 reserved_at_20[0x10]; 385 u8 source_port[0x10]; 386 387 u8 outer_second_prio[0x3]; 388 u8 outer_second_cfi[0x1]; 389 u8 outer_second_vid[0xc]; 390 u8 inner_second_prio[0x3]; 391 u8 inner_second_cfi[0x1]; 392 u8 inner_second_vid[0xc]; 393 394 u8 outer_second_vlan_tag[0x1]; 395 u8 inner_second_vlan_tag[0x1]; 396 u8 reserved_at_62[0xe]; 397 u8 gre_protocol[0x10]; 398 399 u8 gre_key_h[0x18]; 400 u8 gre_key_l[0x8]; 401 402 u8 vxlan_vni[0x18]; 403 u8 reserved_at_b8[0x8]; 404 405 u8 reserved_at_c0[0x20]; 406 407 u8 reserved_at_e0[0xc]; 408 u8 outer_ipv6_flow_label[0x14]; 409 410 u8 reserved_at_100[0xc]; 411 u8 inner_ipv6_flow_label[0x14]; 412 413 u8 reserved_at_120[0xe0]; 414 }; 415 416 struct mlx5_ifc_cmd_pas_bits { 417 u8 pa_h[0x20]; 418 419 u8 pa_l[0x14]; 420 u8 reserved_at_34[0xc]; 421 }; 422 423 struct mlx5_ifc_uint64_bits { 424 u8 hi[0x20]; 425 426 u8 lo[0x20]; 427 }; 428 429 enum { 430 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 431 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 432 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 433 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 434 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 435 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 436 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 437 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 438 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 439 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 440 }; 441 442 struct mlx5_ifc_ads_bits { 443 u8 fl[0x1]; 444 u8 free_ar[0x1]; 445 u8 reserved_at_2[0xe]; 446 u8 pkey_index[0x10]; 447 448 u8 reserved_at_20[0x8]; 449 u8 grh[0x1]; 450 u8 mlid[0x7]; 451 u8 rlid[0x10]; 452 453 u8 ack_timeout[0x5]; 454 u8 reserved_at_45[0x3]; 455 u8 src_addr_index[0x8]; 456 u8 reserved_at_50[0x4]; 457 u8 stat_rate[0x4]; 458 u8 hop_limit[0x8]; 459 460 u8 reserved_at_60[0x4]; 461 u8 tclass[0x8]; 462 u8 flow_label[0x14]; 463 464 u8 rgid_rip[16][0x8]; 465 466 u8 reserved_at_100[0x4]; 467 u8 f_dscp[0x1]; 468 u8 f_ecn[0x1]; 469 u8 reserved_at_106[0x1]; 470 u8 f_eth_prio[0x1]; 471 u8 ecn[0x2]; 472 u8 dscp[0x6]; 473 u8 udp_sport[0x10]; 474 475 u8 dei_cfi[0x1]; 476 u8 eth_prio[0x3]; 477 u8 sl[0x4]; 478 u8 port[0x8]; 479 u8 rmac_47_32[0x10]; 480 481 u8 rmac_31_0[0x20]; 482 }; 483 484 struct mlx5_ifc_flow_table_nic_cap_bits { 485 u8 nic_rx_multi_path_tirs[0x1]; 486 u8 nic_rx_multi_path_tirs_fts[0x1]; 487 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 488 u8 reserved_at_3[0x1fd]; 489 490 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 491 492 u8 reserved_at_400[0x200]; 493 494 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 495 496 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 497 498 u8 reserved_at_a00[0x200]; 499 500 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 501 502 u8 reserved_at_e00[0x7200]; 503 }; 504 505 struct mlx5_ifc_flow_table_eswitch_cap_bits { 506 u8 reserved_at_0[0x200]; 507 508 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 509 510 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 511 512 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 513 514 u8 reserved_at_800[0x7800]; 515 }; 516 517 struct mlx5_ifc_e_switch_cap_bits { 518 u8 vport_svlan_strip[0x1]; 519 u8 vport_cvlan_strip[0x1]; 520 u8 vport_svlan_insert[0x1]; 521 u8 vport_cvlan_insert_if_not_exist[0x1]; 522 u8 vport_cvlan_insert_overwrite[0x1]; 523 u8 reserved_at_5[0x19]; 524 u8 nic_vport_node_guid_modify[0x1]; 525 u8 nic_vport_port_guid_modify[0x1]; 526 527 u8 vxlan_encap_decap[0x1]; 528 u8 nvgre_encap_decap[0x1]; 529 u8 reserved_at_22[0x9]; 530 u8 log_max_encap_headers[0x5]; 531 u8 reserved_2b[0x6]; 532 u8 max_encap_header_size[0xa]; 533 534 u8 reserved_40[0x7c0]; 535 536 }; 537 538 struct mlx5_ifc_qos_cap_bits { 539 u8 packet_pacing[0x1]; 540 u8 reserved_0[0x1f]; 541 u8 reserved_1[0x20]; 542 u8 packet_pacing_max_rate[0x20]; 543 u8 packet_pacing_min_rate[0x20]; 544 u8 reserved_2[0x10]; 545 u8 packet_pacing_rate_table_size[0x10]; 546 u8 reserved_3[0x760]; 547 }; 548 549 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 550 u8 csum_cap[0x1]; 551 u8 vlan_cap[0x1]; 552 u8 lro_cap[0x1]; 553 u8 lro_psh_flag[0x1]; 554 u8 lro_time_stamp[0x1]; 555 u8 reserved_at_5[0x3]; 556 u8 self_lb_en_modifiable[0x1]; 557 u8 reserved_at_9[0x2]; 558 u8 max_lso_cap[0x5]; 559 u8 reserved_at_10[0x2]; 560 u8 wqe_inline_mode[0x2]; 561 u8 rss_ind_tbl_cap[0x4]; 562 u8 reg_umr_sq[0x1]; 563 u8 scatter_fcs[0x1]; 564 u8 reserved_at_1a[0x1]; 565 u8 tunnel_lso_const_out_ip_id[0x1]; 566 u8 reserved_at_1c[0x2]; 567 u8 tunnel_statless_gre[0x1]; 568 u8 tunnel_stateless_vxlan[0x1]; 569 570 u8 reserved_at_20[0x20]; 571 572 u8 reserved_at_40[0x10]; 573 u8 lro_min_mss_size[0x10]; 574 575 u8 reserved_at_60[0x120]; 576 577 u8 lro_timer_supported_periods[4][0x20]; 578 579 u8 reserved_at_200[0x600]; 580 }; 581 582 struct mlx5_ifc_roce_cap_bits { 583 u8 roce_apm[0x1]; 584 u8 reserved_at_1[0x1f]; 585 586 u8 reserved_at_20[0x60]; 587 588 u8 reserved_at_80[0xc]; 589 u8 l3_type[0x4]; 590 u8 reserved_at_90[0x8]; 591 u8 roce_version[0x8]; 592 593 u8 reserved_at_a0[0x10]; 594 u8 r_roce_dest_udp_port[0x10]; 595 596 u8 r_roce_max_src_udp_port[0x10]; 597 u8 r_roce_min_src_udp_port[0x10]; 598 599 u8 reserved_at_e0[0x10]; 600 u8 roce_address_table_size[0x10]; 601 602 u8 reserved_at_100[0x700]; 603 }; 604 605 enum { 606 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 607 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 608 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 609 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 610 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 611 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 612 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 613 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 614 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 615 }; 616 617 enum { 618 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 619 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 620 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 621 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 622 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 623 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 624 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 625 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 626 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 627 }; 628 629 struct mlx5_ifc_atomic_caps_bits { 630 u8 reserved_at_0[0x40]; 631 632 u8 atomic_req_8B_endianess_mode[0x2]; 633 u8 reserved_at_42[0x4]; 634 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 635 636 u8 reserved_at_47[0x19]; 637 638 u8 reserved_at_60[0x20]; 639 640 u8 reserved_at_80[0x10]; 641 u8 atomic_operations[0x10]; 642 643 u8 reserved_at_a0[0x10]; 644 u8 atomic_size_qp[0x10]; 645 646 u8 reserved_at_c0[0x10]; 647 u8 atomic_size_dc[0x10]; 648 649 u8 reserved_at_e0[0x720]; 650 }; 651 652 struct mlx5_ifc_odp_cap_bits { 653 u8 reserved_at_0[0x40]; 654 655 u8 sig[0x1]; 656 u8 reserved_at_41[0x1f]; 657 658 u8 reserved_at_60[0x20]; 659 660 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 661 662 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 663 664 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 665 666 u8 reserved_at_e0[0x720]; 667 }; 668 669 struct mlx5_ifc_calc_op { 670 u8 reserved_at_0[0x10]; 671 u8 reserved_at_10[0x9]; 672 u8 op_swap_endianness[0x1]; 673 u8 op_min[0x1]; 674 u8 op_xor[0x1]; 675 u8 op_or[0x1]; 676 u8 op_and[0x1]; 677 u8 op_max[0x1]; 678 u8 op_add[0x1]; 679 }; 680 681 struct mlx5_ifc_vector_calc_cap_bits { 682 u8 calc_matrix[0x1]; 683 u8 reserved_at_1[0x1f]; 684 u8 reserved_at_20[0x8]; 685 u8 max_vec_count[0x8]; 686 u8 reserved_at_30[0xd]; 687 u8 max_chunk_size[0x3]; 688 struct mlx5_ifc_calc_op calc0; 689 struct mlx5_ifc_calc_op calc1; 690 struct mlx5_ifc_calc_op calc2; 691 struct mlx5_ifc_calc_op calc3; 692 693 u8 reserved_at_e0[0x720]; 694 }; 695 696 enum { 697 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 698 MLX5_WQ_TYPE_CYCLIC = 0x1, 699 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 700 }; 701 702 enum { 703 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 704 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 705 }; 706 707 enum { 708 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 709 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 710 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 711 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 712 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 713 }; 714 715 enum { 716 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 717 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 718 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 719 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 720 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 721 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 722 }; 723 724 enum { 725 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 726 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 727 }; 728 729 enum { 730 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 731 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 732 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 733 }; 734 735 enum { 736 MLX5_CAP_PORT_TYPE_IB = 0x0, 737 MLX5_CAP_PORT_TYPE_ETH = 0x1, 738 }; 739 740 struct mlx5_ifc_cmd_hca_cap_bits { 741 u8 reserved_at_0[0x80]; 742 743 u8 log_max_srq_sz[0x8]; 744 u8 log_max_qp_sz[0x8]; 745 u8 reserved_at_90[0xb]; 746 u8 log_max_qp[0x5]; 747 748 u8 reserved_at_a0[0xb]; 749 u8 log_max_srq[0x5]; 750 u8 reserved_at_b0[0x10]; 751 752 u8 reserved_at_c0[0x8]; 753 u8 log_max_cq_sz[0x8]; 754 u8 reserved_at_d0[0xb]; 755 u8 log_max_cq[0x5]; 756 757 u8 log_max_eq_sz[0x8]; 758 u8 reserved_at_e8[0x2]; 759 u8 log_max_mkey[0x6]; 760 u8 reserved_at_f0[0xc]; 761 u8 log_max_eq[0x4]; 762 763 u8 max_indirection[0x8]; 764 u8 reserved_at_108[0x1]; 765 u8 log_max_mrw_sz[0x7]; 766 u8 reserved_at_110[0x2]; 767 u8 log_max_bsf_list_size[0x6]; 768 u8 reserved_at_118[0x2]; 769 u8 log_max_klm_list_size[0x6]; 770 771 u8 reserved_at_120[0xa]; 772 u8 log_max_ra_req_dc[0x6]; 773 u8 reserved_at_130[0xa]; 774 u8 log_max_ra_res_dc[0x6]; 775 776 u8 reserved_at_140[0xa]; 777 u8 log_max_ra_req_qp[0x6]; 778 u8 reserved_at_150[0xa]; 779 u8 log_max_ra_res_qp[0x6]; 780 781 u8 pad_cap[0x1]; 782 u8 cc_query_allowed[0x1]; 783 u8 cc_modify_allowed[0x1]; 784 u8 reserved_at_163[0xd]; 785 u8 gid_table_size[0x10]; 786 787 u8 out_of_seq_cnt[0x1]; 788 u8 vport_counters[0x1]; 789 u8 retransmission_q_counters[0x1]; 790 u8 reserved_at_183[0x1]; 791 u8 modify_rq_counter_set_id[0x1]; 792 u8 reserved_at_185[0x1]; 793 u8 max_qp_cnt[0xa]; 794 u8 pkey_table_size[0x10]; 795 796 u8 vport_group_manager[0x1]; 797 u8 vhca_group_manager[0x1]; 798 u8 ib_virt[0x1]; 799 u8 eth_virt[0x1]; 800 u8 reserved_at_1a4[0x1]; 801 u8 ets[0x1]; 802 u8 nic_flow_table[0x1]; 803 u8 eswitch_flow_table[0x1]; 804 u8 early_vf_enable[0x1]; 805 u8 reserved_at_1a9[0x2]; 806 u8 local_ca_ack_delay[0x5]; 807 u8 reserved_at_1af[0x2]; 808 u8 ports_check[0x1]; 809 u8 reserved_at_1b2[0x1]; 810 u8 disable_link_up[0x1]; 811 u8 beacon_led[0x1]; 812 u8 port_type[0x2]; 813 u8 num_ports[0x8]; 814 815 u8 reserved_at_1c0[0x3]; 816 u8 log_max_msg[0x5]; 817 u8 reserved_at_1c8[0x4]; 818 u8 max_tc[0x4]; 819 u8 reserved_at_1d0[0x1]; 820 u8 dcbx[0x1]; 821 u8 reserved_at_1d2[0x4]; 822 u8 rol_s[0x1]; 823 u8 rol_g[0x1]; 824 u8 reserved_at_1d8[0x1]; 825 u8 wol_s[0x1]; 826 u8 wol_g[0x1]; 827 u8 wol_a[0x1]; 828 u8 wol_b[0x1]; 829 u8 wol_m[0x1]; 830 u8 wol_u[0x1]; 831 u8 wol_p[0x1]; 832 833 u8 stat_rate_support[0x10]; 834 u8 reserved_at_1f0[0xc]; 835 u8 cqe_version[0x4]; 836 837 u8 compact_address_vector[0x1]; 838 u8 striding_rq[0x1]; 839 u8 reserved_at_201[0x2]; 840 u8 ipoib_basic_offloads[0x1]; 841 u8 reserved_at_205[0xa]; 842 u8 drain_sigerr[0x1]; 843 u8 cmdif_checksum[0x2]; 844 u8 sigerr_cqe[0x1]; 845 u8 reserved_at_213[0x1]; 846 u8 wq_signature[0x1]; 847 u8 sctr_data_cqe[0x1]; 848 u8 reserved_at_216[0x1]; 849 u8 sho[0x1]; 850 u8 tph[0x1]; 851 u8 rf[0x1]; 852 u8 dct[0x1]; 853 u8 qos[0x1]; 854 u8 eth_net_offloads[0x1]; 855 u8 roce[0x1]; 856 u8 atomic[0x1]; 857 u8 reserved_at_21f[0x1]; 858 859 u8 cq_oi[0x1]; 860 u8 cq_resize[0x1]; 861 u8 cq_moderation[0x1]; 862 u8 reserved_at_223[0x3]; 863 u8 cq_eq_remap[0x1]; 864 u8 pg[0x1]; 865 u8 block_lb_mc[0x1]; 866 u8 reserved_at_229[0x1]; 867 u8 scqe_break_moderation[0x1]; 868 u8 cq_period_start_from_cqe[0x1]; 869 u8 cd[0x1]; 870 u8 reserved_at_22d[0x1]; 871 u8 apm[0x1]; 872 u8 vector_calc[0x1]; 873 u8 umr_ptr_rlky[0x1]; 874 u8 imaicl[0x1]; 875 u8 reserved_at_232[0x4]; 876 u8 qkv[0x1]; 877 u8 pkv[0x1]; 878 u8 set_deth_sqpn[0x1]; 879 u8 reserved_at_239[0x3]; 880 u8 xrc[0x1]; 881 u8 ud[0x1]; 882 u8 uc[0x1]; 883 u8 rc[0x1]; 884 885 u8 reserved_at_240[0xa]; 886 u8 uar_sz[0x6]; 887 u8 reserved_at_250[0x8]; 888 u8 log_pg_sz[0x8]; 889 890 u8 bf[0x1]; 891 u8 reserved_at_261[0x1]; 892 u8 pad_tx_eth_packet[0x1]; 893 u8 reserved_at_263[0x8]; 894 u8 log_bf_reg_size[0x5]; 895 896 u8 reserved_at_270[0xb]; 897 u8 lag_master[0x1]; 898 u8 num_lag_ports[0x4]; 899 900 u8 reserved_at_280[0x10]; 901 u8 max_wqe_sz_sq[0x10]; 902 903 u8 reserved_at_2a0[0x10]; 904 u8 max_wqe_sz_rq[0x10]; 905 906 u8 reserved_at_2c0[0x10]; 907 u8 max_wqe_sz_sq_dc[0x10]; 908 909 u8 reserved_at_2e0[0x7]; 910 u8 max_qp_mcg[0x19]; 911 912 u8 reserved_at_300[0x18]; 913 u8 log_max_mcg[0x8]; 914 915 u8 reserved_at_320[0x3]; 916 u8 log_max_transport_domain[0x5]; 917 u8 reserved_at_328[0x3]; 918 u8 log_max_pd[0x5]; 919 u8 reserved_at_330[0xb]; 920 u8 log_max_xrcd[0x5]; 921 922 u8 reserved_at_340[0x8]; 923 u8 log_max_flow_counter_bulk[0x8]; 924 u8 max_flow_counter[0x10]; 925 926 927 u8 reserved_at_360[0x3]; 928 u8 log_max_rq[0x5]; 929 u8 reserved_at_368[0x3]; 930 u8 log_max_sq[0x5]; 931 u8 reserved_at_370[0x3]; 932 u8 log_max_tir[0x5]; 933 u8 reserved_at_378[0x3]; 934 u8 log_max_tis[0x5]; 935 936 u8 basic_cyclic_rcv_wqe[0x1]; 937 u8 reserved_at_381[0x2]; 938 u8 log_max_rmp[0x5]; 939 u8 reserved_at_388[0x3]; 940 u8 log_max_rqt[0x5]; 941 u8 reserved_at_390[0x3]; 942 u8 log_max_rqt_size[0x5]; 943 u8 reserved_at_398[0x3]; 944 u8 log_max_tis_per_sq[0x5]; 945 946 u8 reserved_at_3a0[0x3]; 947 u8 log_max_stride_sz_rq[0x5]; 948 u8 reserved_at_3a8[0x3]; 949 u8 log_min_stride_sz_rq[0x5]; 950 u8 reserved_at_3b0[0x3]; 951 u8 log_max_stride_sz_sq[0x5]; 952 u8 reserved_at_3b8[0x3]; 953 u8 log_min_stride_sz_sq[0x5]; 954 955 u8 reserved_at_3c0[0x1b]; 956 u8 log_max_wq_sz[0x5]; 957 958 u8 nic_vport_change_event[0x1]; 959 u8 reserved_at_3e1[0xa]; 960 u8 log_max_vlan_list[0x5]; 961 u8 reserved_at_3f0[0x3]; 962 u8 log_max_current_mc_list[0x5]; 963 u8 reserved_at_3f8[0x3]; 964 u8 log_max_current_uc_list[0x5]; 965 966 u8 reserved_at_400[0x80]; 967 968 u8 reserved_at_480[0x3]; 969 u8 log_max_l2_table[0x5]; 970 u8 reserved_at_488[0x8]; 971 u8 log_uar_page_sz[0x10]; 972 973 u8 reserved_at_4a0[0x20]; 974 u8 device_frequency_mhz[0x20]; 975 u8 device_frequency_khz[0x20]; 976 977 u8 reserved_at_500[0x80]; 978 979 u8 reserved_at_580[0x3f]; 980 u8 cqe_compression[0x1]; 981 982 u8 cqe_compression_timeout[0x10]; 983 u8 cqe_compression_max_num[0x10]; 984 985 u8 reserved_at_5e0[0x10]; 986 u8 tag_matching[0x1]; 987 u8 rndv_offload_rc[0x1]; 988 u8 rndv_offload_dc[0x1]; 989 u8 log_tag_matching_list_sz[0x5]; 990 u8 reserved_at_5e8[0x3]; 991 u8 log_max_xrq[0x5]; 992 993 u8 reserved_at_5f0[0x200]; 994 }; 995 996 enum mlx5_flow_destination_type { 997 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 998 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 999 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1000 1001 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1002 }; 1003 1004 struct mlx5_ifc_dest_format_struct_bits { 1005 u8 destination_type[0x8]; 1006 u8 destination_id[0x18]; 1007 1008 u8 reserved_at_20[0x20]; 1009 }; 1010 1011 struct mlx5_ifc_flow_counter_list_bits { 1012 u8 clear[0x1]; 1013 u8 num_of_counters[0xf]; 1014 u8 flow_counter_id[0x10]; 1015 1016 u8 reserved_at_20[0x20]; 1017 }; 1018 1019 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1020 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1021 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1022 u8 reserved_at_0[0x40]; 1023 }; 1024 1025 struct mlx5_ifc_fte_match_param_bits { 1026 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1027 1028 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1029 1030 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1031 1032 u8 reserved_at_600[0xa00]; 1033 }; 1034 1035 enum { 1036 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1037 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1038 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1039 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1040 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1041 }; 1042 1043 struct mlx5_ifc_rx_hash_field_select_bits { 1044 u8 l3_prot_type[0x1]; 1045 u8 l4_prot_type[0x1]; 1046 u8 selected_fields[0x1e]; 1047 }; 1048 1049 enum { 1050 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1051 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1052 }; 1053 1054 enum { 1055 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1056 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1057 }; 1058 1059 struct mlx5_ifc_wq_bits { 1060 u8 wq_type[0x4]; 1061 u8 wq_signature[0x1]; 1062 u8 end_padding_mode[0x2]; 1063 u8 cd_slave[0x1]; 1064 u8 reserved_at_8[0x18]; 1065 1066 u8 hds_skip_first_sge[0x1]; 1067 u8 log2_hds_buf_size[0x3]; 1068 u8 reserved_at_24[0x7]; 1069 u8 page_offset[0x5]; 1070 u8 lwm[0x10]; 1071 1072 u8 reserved_at_40[0x8]; 1073 u8 pd[0x18]; 1074 1075 u8 reserved_at_60[0x8]; 1076 u8 uar_page[0x18]; 1077 1078 u8 dbr_addr[0x40]; 1079 1080 u8 hw_counter[0x20]; 1081 1082 u8 sw_counter[0x20]; 1083 1084 u8 reserved_at_100[0xc]; 1085 u8 log_wq_stride[0x4]; 1086 u8 reserved_at_110[0x3]; 1087 u8 log_wq_pg_sz[0x5]; 1088 u8 reserved_at_118[0x3]; 1089 u8 log_wq_sz[0x5]; 1090 1091 u8 reserved_at_120[0x15]; 1092 u8 log_wqe_num_of_strides[0x3]; 1093 u8 two_byte_shift_en[0x1]; 1094 u8 reserved_at_139[0x4]; 1095 u8 log_wqe_stride_size[0x3]; 1096 1097 u8 reserved_at_140[0x4c0]; 1098 1099 struct mlx5_ifc_cmd_pas_bits pas[0]; 1100 }; 1101 1102 struct mlx5_ifc_rq_num_bits { 1103 u8 reserved_at_0[0x8]; 1104 u8 rq_num[0x18]; 1105 }; 1106 1107 struct mlx5_ifc_mac_address_layout_bits { 1108 u8 reserved_at_0[0x10]; 1109 u8 mac_addr_47_32[0x10]; 1110 1111 u8 mac_addr_31_0[0x20]; 1112 }; 1113 1114 struct mlx5_ifc_vlan_layout_bits { 1115 u8 reserved_at_0[0x14]; 1116 u8 vlan[0x0c]; 1117 1118 u8 reserved_at_20[0x20]; 1119 }; 1120 1121 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1122 u8 reserved_at_0[0xa0]; 1123 1124 u8 min_time_between_cnps[0x20]; 1125 1126 u8 reserved_at_c0[0x12]; 1127 u8 cnp_dscp[0x6]; 1128 u8 reserved_at_d8[0x5]; 1129 u8 cnp_802p_prio[0x3]; 1130 1131 u8 reserved_at_e0[0x720]; 1132 }; 1133 1134 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1135 u8 reserved_at_0[0x60]; 1136 1137 u8 reserved_at_60[0x4]; 1138 u8 clamp_tgt_rate[0x1]; 1139 u8 reserved_at_65[0x3]; 1140 u8 clamp_tgt_rate_after_time_inc[0x1]; 1141 u8 reserved_at_69[0x17]; 1142 1143 u8 reserved_at_80[0x20]; 1144 1145 u8 rpg_time_reset[0x20]; 1146 1147 u8 rpg_byte_reset[0x20]; 1148 1149 u8 rpg_threshold[0x20]; 1150 1151 u8 rpg_max_rate[0x20]; 1152 1153 u8 rpg_ai_rate[0x20]; 1154 1155 u8 rpg_hai_rate[0x20]; 1156 1157 u8 rpg_gd[0x20]; 1158 1159 u8 rpg_min_dec_fac[0x20]; 1160 1161 u8 rpg_min_rate[0x20]; 1162 1163 u8 reserved_at_1c0[0xe0]; 1164 1165 u8 rate_to_set_on_first_cnp[0x20]; 1166 1167 u8 dce_tcp_g[0x20]; 1168 1169 u8 dce_tcp_rtt[0x20]; 1170 1171 u8 rate_reduce_monitor_period[0x20]; 1172 1173 u8 reserved_at_320[0x20]; 1174 1175 u8 initial_alpha_value[0x20]; 1176 1177 u8 reserved_at_360[0x4a0]; 1178 }; 1179 1180 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1181 u8 reserved_at_0[0x80]; 1182 1183 u8 rppp_max_rps[0x20]; 1184 1185 u8 rpg_time_reset[0x20]; 1186 1187 u8 rpg_byte_reset[0x20]; 1188 1189 u8 rpg_threshold[0x20]; 1190 1191 u8 rpg_max_rate[0x20]; 1192 1193 u8 rpg_ai_rate[0x20]; 1194 1195 u8 rpg_hai_rate[0x20]; 1196 1197 u8 rpg_gd[0x20]; 1198 1199 u8 rpg_min_dec_fac[0x20]; 1200 1201 u8 rpg_min_rate[0x20]; 1202 1203 u8 reserved_at_1c0[0x640]; 1204 }; 1205 1206 enum { 1207 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1208 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1209 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1210 }; 1211 1212 struct mlx5_ifc_resize_field_select_bits { 1213 u8 resize_field_select[0x20]; 1214 }; 1215 1216 enum { 1217 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1218 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1219 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1220 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1221 }; 1222 1223 struct mlx5_ifc_modify_field_select_bits { 1224 u8 modify_field_select[0x20]; 1225 }; 1226 1227 struct mlx5_ifc_field_select_r_roce_np_bits { 1228 u8 field_select_r_roce_np[0x20]; 1229 }; 1230 1231 struct mlx5_ifc_field_select_r_roce_rp_bits { 1232 u8 field_select_r_roce_rp[0x20]; 1233 }; 1234 1235 enum { 1236 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1237 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1238 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1239 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1240 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1241 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1242 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1243 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1244 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1245 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1246 }; 1247 1248 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1249 u8 field_select_8021qaurp[0x20]; 1250 }; 1251 1252 struct mlx5_ifc_phys_layer_cntrs_bits { 1253 u8 time_since_last_clear_high[0x20]; 1254 1255 u8 time_since_last_clear_low[0x20]; 1256 1257 u8 symbol_errors_high[0x20]; 1258 1259 u8 symbol_errors_low[0x20]; 1260 1261 u8 sync_headers_errors_high[0x20]; 1262 1263 u8 sync_headers_errors_low[0x20]; 1264 1265 u8 edpl_bip_errors_lane0_high[0x20]; 1266 1267 u8 edpl_bip_errors_lane0_low[0x20]; 1268 1269 u8 edpl_bip_errors_lane1_high[0x20]; 1270 1271 u8 edpl_bip_errors_lane1_low[0x20]; 1272 1273 u8 edpl_bip_errors_lane2_high[0x20]; 1274 1275 u8 edpl_bip_errors_lane2_low[0x20]; 1276 1277 u8 edpl_bip_errors_lane3_high[0x20]; 1278 1279 u8 edpl_bip_errors_lane3_low[0x20]; 1280 1281 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1282 1283 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1284 1285 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1286 1287 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1288 1289 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1290 1291 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1292 1293 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1294 1295 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1296 1297 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1298 1299 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1300 1301 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1302 1303 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1304 1305 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1306 1307 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1308 1309 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1310 1311 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1312 1313 u8 rs_fec_corrected_blocks_high[0x20]; 1314 1315 u8 rs_fec_corrected_blocks_low[0x20]; 1316 1317 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1318 1319 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1320 1321 u8 rs_fec_no_errors_blocks_high[0x20]; 1322 1323 u8 rs_fec_no_errors_blocks_low[0x20]; 1324 1325 u8 rs_fec_single_error_blocks_high[0x20]; 1326 1327 u8 rs_fec_single_error_blocks_low[0x20]; 1328 1329 u8 rs_fec_corrected_symbols_total_high[0x20]; 1330 1331 u8 rs_fec_corrected_symbols_total_low[0x20]; 1332 1333 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1334 1335 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1336 1337 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1338 1339 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1340 1341 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1342 1343 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1344 1345 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1346 1347 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1348 1349 u8 link_down_events[0x20]; 1350 1351 u8 successful_recovery_events[0x20]; 1352 1353 u8 reserved_at_640[0x180]; 1354 }; 1355 1356 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1357 u8 symbol_error_counter[0x10]; 1358 1359 u8 link_error_recovery_counter[0x8]; 1360 1361 u8 link_downed_counter[0x8]; 1362 1363 u8 port_rcv_errors[0x10]; 1364 1365 u8 port_rcv_remote_physical_errors[0x10]; 1366 1367 u8 port_rcv_switch_relay_errors[0x10]; 1368 1369 u8 port_xmit_discards[0x10]; 1370 1371 u8 port_xmit_constraint_errors[0x8]; 1372 1373 u8 port_rcv_constraint_errors[0x8]; 1374 1375 u8 reserved_at_70[0x8]; 1376 1377 u8 link_overrun_errors[0x8]; 1378 1379 u8 reserved_at_80[0x10]; 1380 1381 u8 vl_15_dropped[0x10]; 1382 1383 u8 reserved_at_a0[0xa0]; 1384 }; 1385 1386 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1387 u8 transmit_queue_high[0x20]; 1388 1389 u8 transmit_queue_low[0x20]; 1390 1391 u8 reserved_at_40[0x780]; 1392 }; 1393 1394 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1395 u8 rx_octets_high[0x20]; 1396 1397 u8 rx_octets_low[0x20]; 1398 1399 u8 reserved_at_40[0xc0]; 1400 1401 u8 rx_frames_high[0x20]; 1402 1403 u8 rx_frames_low[0x20]; 1404 1405 u8 tx_octets_high[0x20]; 1406 1407 u8 tx_octets_low[0x20]; 1408 1409 u8 reserved_at_180[0xc0]; 1410 1411 u8 tx_frames_high[0x20]; 1412 1413 u8 tx_frames_low[0x20]; 1414 1415 u8 rx_pause_high[0x20]; 1416 1417 u8 rx_pause_low[0x20]; 1418 1419 u8 rx_pause_duration_high[0x20]; 1420 1421 u8 rx_pause_duration_low[0x20]; 1422 1423 u8 tx_pause_high[0x20]; 1424 1425 u8 tx_pause_low[0x20]; 1426 1427 u8 tx_pause_duration_high[0x20]; 1428 1429 u8 tx_pause_duration_low[0x20]; 1430 1431 u8 rx_pause_transition_high[0x20]; 1432 1433 u8 rx_pause_transition_low[0x20]; 1434 1435 u8 reserved_at_3c0[0x400]; 1436 }; 1437 1438 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1439 u8 port_transmit_wait_high[0x20]; 1440 1441 u8 port_transmit_wait_low[0x20]; 1442 1443 u8 reserved_at_40[0x780]; 1444 }; 1445 1446 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1447 u8 dot3stats_alignment_errors_high[0x20]; 1448 1449 u8 dot3stats_alignment_errors_low[0x20]; 1450 1451 u8 dot3stats_fcs_errors_high[0x20]; 1452 1453 u8 dot3stats_fcs_errors_low[0x20]; 1454 1455 u8 dot3stats_single_collision_frames_high[0x20]; 1456 1457 u8 dot3stats_single_collision_frames_low[0x20]; 1458 1459 u8 dot3stats_multiple_collision_frames_high[0x20]; 1460 1461 u8 dot3stats_multiple_collision_frames_low[0x20]; 1462 1463 u8 dot3stats_sqe_test_errors_high[0x20]; 1464 1465 u8 dot3stats_sqe_test_errors_low[0x20]; 1466 1467 u8 dot3stats_deferred_transmissions_high[0x20]; 1468 1469 u8 dot3stats_deferred_transmissions_low[0x20]; 1470 1471 u8 dot3stats_late_collisions_high[0x20]; 1472 1473 u8 dot3stats_late_collisions_low[0x20]; 1474 1475 u8 dot3stats_excessive_collisions_high[0x20]; 1476 1477 u8 dot3stats_excessive_collisions_low[0x20]; 1478 1479 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1480 1481 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1482 1483 u8 dot3stats_carrier_sense_errors_high[0x20]; 1484 1485 u8 dot3stats_carrier_sense_errors_low[0x20]; 1486 1487 u8 dot3stats_frame_too_longs_high[0x20]; 1488 1489 u8 dot3stats_frame_too_longs_low[0x20]; 1490 1491 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1492 1493 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1494 1495 u8 dot3stats_symbol_errors_high[0x20]; 1496 1497 u8 dot3stats_symbol_errors_low[0x20]; 1498 1499 u8 dot3control_in_unknown_opcodes_high[0x20]; 1500 1501 u8 dot3control_in_unknown_opcodes_low[0x20]; 1502 1503 u8 dot3in_pause_frames_high[0x20]; 1504 1505 u8 dot3in_pause_frames_low[0x20]; 1506 1507 u8 dot3out_pause_frames_high[0x20]; 1508 1509 u8 dot3out_pause_frames_low[0x20]; 1510 1511 u8 reserved_at_400[0x3c0]; 1512 }; 1513 1514 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1515 u8 ether_stats_drop_events_high[0x20]; 1516 1517 u8 ether_stats_drop_events_low[0x20]; 1518 1519 u8 ether_stats_octets_high[0x20]; 1520 1521 u8 ether_stats_octets_low[0x20]; 1522 1523 u8 ether_stats_pkts_high[0x20]; 1524 1525 u8 ether_stats_pkts_low[0x20]; 1526 1527 u8 ether_stats_broadcast_pkts_high[0x20]; 1528 1529 u8 ether_stats_broadcast_pkts_low[0x20]; 1530 1531 u8 ether_stats_multicast_pkts_high[0x20]; 1532 1533 u8 ether_stats_multicast_pkts_low[0x20]; 1534 1535 u8 ether_stats_crc_align_errors_high[0x20]; 1536 1537 u8 ether_stats_crc_align_errors_low[0x20]; 1538 1539 u8 ether_stats_undersize_pkts_high[0x20]; 1540 1541 u8 ether_stats_undersize_pkts_low[0x20]; 1542 1543 u8 ether_stats_oversize_pkts_high[0x20]; 1544 1545 u8 ether_stats_oversize_pkts_low[0x20]; 1546 1547 u8 ether_stats_fragments_high[0x20]; 1548 1549 u8 ether_stats_fragments_low[0x20]; 1550 1551 u8 ether_stats_jabbers_high[0x20]; 1552 1553 u8 ether_stats_jabbers_low[0x20]; 1554 1555 u8 ether_stats_collisions_high[0x20]; 1556 1557 u8 ether_stats_collisions_low[0x20]; 1558 1559 u8 ether_stats_pkts64octets_high[0x20]; 1560 1561 u8 ether_stats_pkts64octets_low[0x20]; 1562 1563 u8 ether_stats_pkts65to127octets_high[0x20]; 1564 1565 u8 ether_stats_pkts65to127octets_low[0x20]; 1566 1567 u8 ether_stats_pkts128to255octets_high[0x20]; 1568 1569 u8 ether_stats_pkts128to255octets_low[0x20]; 1570 1571 u8 ether_stats_pkts256to511octets_high[0x20]; 1572 1573 u8 ether_stats_pkts256to511octets_low[0x20]; 1574 1575 u8 ether_stats_pkts512to1023octets_high[0x20]; 1576 1577 u8 ether_stats_pkts512to1023octets_low[0x20]; 1578 1579 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1580 1581 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1582 1583 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1584 1585 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1586 1587 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1588 1589 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1590 1591 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1592 1593 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1594 1595 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1596 1597 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1598 1599 u8 reserved_at_540[0x280]; 1600 }; 1601 1602 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1603 u8 if_in_octets_high[0x20]; 1604 1605 u8 if_in_octets_low[0x20]; 1606 1607 u8 if_in_ucast_pkts_high[0x20]; 1608 1609 u8 if_in_ucast_pkts_low[0x20]; 1610 1611 u8 if_in_discards_high[0x20]; 1612 1613 u8 if_in_discards_low[0x20]; 1614 1615 u8 if_in_errors_high[0x20]; 1616 1617 u8 if_in_errors_low[0x20]; 1618 1619 u8 if_in_unknown_protos_high[0x20]; 1620 1621 u8 if_in_unknown_protos_low[0x20]; 1622 1623 u8 if_out_octets_high[0x20]; 1624 1625 u8 if_out_octets_low[0x20]; 1626 1627 u8 if_out_ucast_pkts_high[0x20]; 1628 1629 u8 if_out_ucast_pkts_low[0x20]; 1630 1631 u8 if_out_discards_high[0x20]; 1632 1633 u8 if_out_discards_low[0x20]; 1634 1635 u8 if_out_errors_high[0x20]; 1636 1637 u8 if_out_errors_low[0x20]; 1638 1639 u8 if_in_multicast_pkts_high[0x20]; 1640 1641 u8 if_in_multicast_pkts_low[0x20]; 1642 1643 u8 if_in_broadcast_pkts_high[0x20]; 1644 1645 u8 if_in_broadcast_pkts_low[0x20]; 1646 1647 u8 if_out_multicast_pkts_high[0x20]; 1648 1649 u8 if_out_multicast_pkts_low[0x20]; 1650 1651 u8 if_out_broadcast_pkts_high[0x20]; 1652 1653 u8 if_out_broadcast_pkts_low[0x20]; 1654 1655 u8 reserved_at_340[0x480]; 1656 }; 1657 1658 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1659 u8 a_frames_transmitted_ok_high[0x20]; 1660 1661 u8 a_frames_transmitted_ok_low[0x20]; 1662 1663 u8 a_frames_received_ok_high[0x20]; 1664 1665 u8 a_frames_received_ok_low[0x20]; 1666 1667 u8 a_frame_check_sequence_errors_high[0x20]; 1668 1669 u8 a_frame_check_sequence_errors_low[0x20]; 1670 1671 u8 a_alignment_errors_high[0x20]; 1672 1673 u8 a_alignment_errors_low[0x20]; 1674 1675 u8 a_octets_transmitted_ok_high[0x20]; 1676 1677 u8 a_octets_transmitted_ok_low[0x20]; 1678 1679 u8 a_octets_received_ok_high[0x20]; 1680 1681 u8 a_octets_received_ok_low[0x20]; 1682 1683 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1684 1685 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1686 1687 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1688 1689 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1690 1691 u8 a_multicast_frames_received_ok_high[0x20]; 1692 1693 u8 a_multicast_frames_received_ok_low[0x20]; 1694 1695 u8 a_broadcast_frames_received_ok_high[0x20]; 1696 1697 u8 a_broadcast_frames_received_ok_low[0x20]; 1698 1699 u8 a_in_range_length_errors_high[0x20]; 1700 1701 u8 a_in_range_length_errors_low[0x20]; 1702 1703 u8 a_out_of_range_length_field_high[0x20]; 1704 1705 u8 a_out_of_range_length_field_low[0x20]; 1706 1707 u8 a_frame_too_long_errors_high[0x20]; 1708 1709 u8 a_frame_too_long_errors_low[0x20]; 1710 1711 u8 a_symbol_error_during_carrier_high[0x20]; 1712 1713 u8 a_symbol_error_during_carrier_low[0x20]; 1714 1715 u8 a_mac_control_frames_transmitted_high[0x20]; 1716 1717 u8 a_mac_control_frames_transmitted_low[0x20]; 1718 1719 u8 a_mac_control_frames_received_high[0x20]; 1720 1721 u8 a_mac_control_frames_received_low[0x20]; 1722 1723 u8 a_unsupported_opcodes_received_high[0x20]; 1724 1725 u8 a_unsupported_opcodes_received_low[0x20]; 1726 1727 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1728 1729 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1730 1731 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1732 1733 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1734 1735 u8 reserved_at_4c0[0x300]; 1736 }; 1737 1738 struct mlx5_ifc_cmd_inter_comp_event_bits { 1739 u8 command_completion_vector[0x20]; 1740 1741 u8 reserved_at_20[0xc0]; 1742 }; 1743 1744 struct mlx5_ifc_stall_vl_event_bits { 1745 u8 reserved_at_0[0x18]; 1746 u8 port_num[0x1]; 1747 u8 reserved_at_19[0x3]; 1748 u8 vl[0x4]; 1749 1750 u8 reserved_at_20[0xa0]; 1751 }; 1752 1753 struct mlx5_ifc_db_bf_congestion_event_bits { 1754 u8 event_subtype[0x8]; 1755 u8 reserved_at_8[0x8]; 1756 u8 congestion_level[0x8]; 1757 u8 reserved_at_18[0x8]; 1758 1759 u8 reserved_at_20[0xa0]; 1760 }; 1761 1762 struct mlx5_ifc_gpio_event_bits { 1763 u8 reserved_at_0[0x60]; 1764 1765 u8 gpio_event_hi[0x20]; 1766 1767 u8 gpio_event_lo[0x20]; 1768 1769 u8 reserved_at_a0[0x40]; 1770 }; 1771 1772 struct mlx5_ifc_port_state_change_event_bits { 1773 u8 reserved_at_0[0x40]; 1774 1775 u8 port_num[0x4]; 1776 u8 reserved_at_44[0x1c]; 1777 1778 u8 reserved_at_60[0x80]; 1779 }; 1780 1781 struct mlx5_ifc_dropped_packet_logged_bits { 1782 u8 reserved_at_0[0xe0]; 1783 }; 1784 1785 enum { 1786 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1787 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1788 }; 1789 1790 struct mlx5_ifc_cq_error_bits { 1791 u8 reserved_at_0[0x8]; 1792 u8 cqn[0x18]; 1793 1794 u8 reserved_at_20[0x20]; 1795 1796 u8 reserved_at_40[0x18]; 1797 u8 syndrome[0x8]; 1798 1799 u8 reserved_at_60[0x80]; 1800 }; 1801 1802 struct mlx5_ifc_rdma_page_fault_event_bits { 1803 u8 bytes_committed[0x20]; 1804 1805 u8 r_key[0x20]; 1806 1807 u8 reserved_at_40[0x10]; 1808 u8 packet_len[0x10]; 1809 1810 u8 rdma_op_len[0x20]; 1811 1812 u8 rdma_va[0x40]; 1813 1814 u8 reserved_at_c0[0x5]; 1815 u8 rdma[0x1]; 1816 u8 write[0x1]; 1817 u8 requestor[0x1]; 1818 u8 qp_number[0x18]; 1819 }; 1820 1821 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1822 u8 bytes_committed[0x20]; 1823 1824 u8 reserved_at_20[0x10]; 1825 u8 wqe_index[0x10]; 1826 1827 u8 reserved_at_40[0x10]; 1828 u8 len[0x10]; 1829 1830 u8 reserved_at_60[0x60]; 1831 1832 u8 reserved_at_c0[0x5]; 1833 u8 rdma[0x1]; 1834 u8 write_read[0x1]; 1835 u8 requestor[0x1]; 1836 u8 qpn[0x18]; 1837 }; 1838 1839 struct mlx5_ifc_qp_events_bits { 1840 u8 reserved_at_0[0xa0]; 1841 1842 u8 type[0x8]; 1843 u8 reserved_at_a8[0x18]; 1844 1845 u8 reserved_at_c0[0x8]; 1846 u8 qpn_rqn_sqn[0x18]; 1847 }; 1848 1849 struct mlx5_ifc_dct_events_bits { 1850 u8 reserved_at_0[0xc0]; 1851 1852 u8 reserved_at_c0[0x8]; 1853 u8 dct_number[0x18]; 1854 }; 1855 1856 struct mlx5_ifc_comp_event_bits { 1857 u8 reserved_at_0[0xc0]; 1858 1859 u8 reserved_at_c0[0x8]; 1860 u8 cq_number[0x18]; 1861 }; 1862 1863 enum { 1864 MLX5_QPC_STATE_RST = 0x0, 1865 MLX5_QPC_STATE_INIT = 0x1, 1866 MLX5_QPC_STATE_RTR = 0x2, 1867 MLX5_QPC_STATE_RTS = 0x3, 1868 MLX5_QPC_STATE_SQER = 0x4, 1869 MLX5_QPC_STATE_ERR = 0x6, 1870 MLX5_QPC_STATE_SQD = 0x7, 1871 MLX5_QPC_STATE_SUSPENDED = 0x9, 1872 }; 1873 1874 enum { 1875 MLX5_QPC_ST_RC = 0x0, 1876 MLX5_QPC_ST_UC = 0x1, 1877 MLX5_QPC_ST_UD = 0x2, 1878 MLX5_QPC_ST_XRC = 0x3, 1879 MLX5_QPC_ST_DCI = 0x5, 1880 MLX5_QPC_ST_QP0 = 0x7, 1881 MLX5_QPC_ST_QP1 = 0x8, 1882 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1883 MLX5_QPC_ST_REG_UMR = 0xc, 1884 }; 1885 1886 enum { 1887 MLX5_QPC_PM_STATE_ARMED = 0x0, 1888 MLX5_QPC_PM_STATE_REARM = 0x1, 1889 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1890 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 1891 }; 1892 1893 enum { 1894 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1895 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1896 }; 1897 1898 enum { 1899 MLX5_QPC_MTU_256_BYTES = 0x1, 1900 MLX5_QPC_MTU_512_BYTES = 0x2, 1901 MLX5_QPC_MTU_1K_BYTES = 0x3, 1902 MLX5_QPC_MTU_2K_BYTES = 0x4, 1903 MLX5_QPC_MTU_4K_BYTES = 0x5, 1904 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1905 }; 1906 1907 enum { 1908 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1909 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1910 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1911 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1912 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1913 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1914 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1915 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1916 }; 1917 1918 enum { 1919 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1920 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1921 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1922 }; 1923 1924 enum { 1925 MLX5_QPC_CS_RES_DISABLE = 0x0, 1926 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1927 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1928 }; 1929 1930 struct mlx5_ifc_qpc_bits { 1931 u8 state[0x4]; 1932 u8 lag_tx_port_affinity[0x4]; 1933 u8 st[0x8]; 1934 u8 reserved_at_10[0x3]; 1935 u8 pm_state[0x2]; 1936 u8 reserved_at_15[0x7]; 1937 u8 end_padding_mode[0x2]; 1938 u8 reserved_at_1e[0x2]; 1939 1940 u8 wq_signature[0x1]; 1941 u8 block_lb_mc[0x1]; 1942 u8 atomic_like_write_en[0x1]; 1943 u8 latency_sensitive[0x1]; 1944 u8 reserved_at_24[0x1]; 1945 u8 drain_sigerr[0x1]; 1946 u8 reserved_at_26[0x2]; 1947 u8 pd[0x18]; 1948 1949 u8 mtu[0x3]; 1950 u8 log_msg_max[0x5]; 1951 u8 reserved_at_48[0x1]; 1952 u8 log_rq_size[0x4]; 1953 u8 log_rq_stride[0x3]; 1954 u8 no_sq[0x1]; 1955 u8 log_sq_size[0x4]; 1956 u8 reserved_at_55[0x6]; 1957 u8 rlky[0x1]; 1958 u8 ulp_stateless_offload_mode[0x4]; 1959 1960 u8 counter_set_id[0x8]; 1961 u8 uar_page[0x18]; 1962 1963 u8 reserved_at_80[0x8]; 1964 u8 user_index[0x18]; 1965 1966 u8 reserved_at_a0[0x3]; 1967 u8 log_page_size[0x5]; 1968 u8 remote_qpn[0x18]; 1969 1970 struct mlx5_ifc_ads_bits primary_address_path; 1971 1972 struct mlx5_ifc_ads_bits secondary_address_path; 1973 1974 u8 log_ack_req_freq[0x4]; 1975 u8 reserved_at_384[0x4]; 1976 u8 log_sra_max[0x3]; 1977 u8 reserved_at_38b[0x2]; 1978 u8 retry_count[0x3]; 1979 u8 rnr_retry[0x3]; 1980 u8 reserved_at_393[0x1]; 1981 u8 fre[0x1]; 1982 u8 cur_rnr_retry[0x3]; 1983 u8 cur_retry_count[0x3]; 1984 u8 reserved_at_39b[0x5]; 1985 1986 u8 reserved_at_3a0[0x20]; 1987 1988 u8 reserved_at_3c0[0x8]; 1989 u8 next_send_psn[0x18]; 1990 1991 u8 reserved_at_3e0[0x8]; 1992 u8 cqn_snd[0x18]; 1993 1994 u8 reserved_at_400[0x8]; 1995 u8 deth_sqpn[0x18]; 1996 1997 u8 reserved_at_420[0x20]; 1998 1999 u8 reserved_at_440[0x8]; 2000 u8 last_acked_psn[0x18]; 2001 2002 u8 reserved_at_460[0x8]; 2003 u8 ssn[0x18]; 2004 2005 u8 reserved_at_480[0x8]; 2006 u8 log_rra_max[0x3]; 2007 u8 reserved_at_48b[0x1]; 2008 u8 atomic_mode[0x4]; 2009 u8 rre[0x1]; 2010 u8 rwe[0x1]; 2011 u8 rae[0x1]; 2012 u8 reserved_at_493[0x1]; 2013 u8 page_offset[0x6]; 2014 u8 reserved_at_49a[0x3]; 2015 u8 cd_slave_receive[0x1]; 2016 u8 cd_slave_send[0x1]; 2017 u8 cd_master[0x1]; 2018 2019 u8 reserved_at_4a0[0x3]; 2020 u8 min_rnr_nak[0x5]; 2021 u8 next_rcv_psn[0x18]; 2022 2023 u8 reserved_at_4c0[0x8]; 2024 u8 xrcd[0x18]; 2025 2026 u8 reserved_at_4e0[0x8]; 2027 u8 cqn_rcv[0x18]; 2028 2029 u8 dbr_addr[0x40]; 2030 2031 u8 q_key[0x20]; 2032 2033 u8 reserved_at_560[0x5]; 2034 u8 rq_type[0x3]; 2035 u8 srqn_rmpn_xrqn[0x18]; 2036 2037 u8 reserved_at_580[0x8]; 2038 u8 rmsn[0x18]; 2039 2040 u8 hw_sq_wqebb_counter[0x10]; 2041 u8 sw_sq_wqebb_counter[0x10]; 2042 2043 u8 hw_rq_counter[0x20]; 2044 2045 u8 sw_rq_counter[0x20]; 2046 2047 u8 reserved_at_600[0x20]; 2048 2049 u8 reserved_at_620[0xf]; 2050 u8 cgs[0x1]; 2051 u8 cs_req[0x8]; 2052 u8 cs_res[0x8]; 2053 2054 u8 dc_access_key[0x40]; 2055 2056 u8 reserved_at_680[0xc0]; 2057 }; 2058 2059 struct mlx5_ifc_roce_addr_layout_bits { 2060 u8 source_l3_address[16][0x8]; 2061 2062 u8 reserved_at_80[0x3]; 2063 u8 vlan_valid[0x1]; 2064 u8 vlan_id[0xc]; 2065 u8 source_mac_47_32[0x10]; 2066 2067 u8 source_mac_31_0[0x20]; 2068 2069 u8 reserved_at_c0[0x14]; 2070 u8 roce_l3_type[0x4]; 2071 u8 roce_version[0x8]; 2072 2073 u8 reserved_at_e0[0x20]; 2074 }; 2075 2076 union mlx5_ifc_hca_cap_union_bits { 2077 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2078 struct mlx5_ifc_odp_cap_bits odp_cap; 2079 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2080 struct mlx5_ifc_roce_cap_bits roce_cap; 2081 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2082 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2083 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2084 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2085 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2086 struct mlx5_ifc_qos_cap_bits qos_cap; 2087 u8 reserved_at_0[0x8000]; 2088 }; 2089 2090 enum { 2091 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2092 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2093 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2094 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2095 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10, 2096 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2097 }; 2098 2099 struct mlx5_ifc_flow_context_bits { 2100 u8 reserved_at_0[0x20]; 2101 2102 u8 group_id[0x20]; 2103 2104 u8 reserved_at_40[0x8]; 2105 u8 flow_tag[0x18]; 2106 2107 u8 reserved_at_60[0x10]; 2108 u8 action[0x10]; 2109 2110 u8 reserved_at_80[0x8]; 2111 u8 destination_list_size[0x18]; 2112 2113 u8 reserved_at_a0[0x8]; 2114 u8 flow_counter_list_size[0x18]; 2115 2116 u8 encap_id[0x20]; 2117 2118 u8 reserved_at_e0[0x120]; 2119 2120 struct mlx5_ifc_fte_match_param_bits match_value; 2121 2122 u8 reserved_at_1200[0x600]; 2123 2124 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2125 }; 2126 2127 enum { 2128 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2129 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2130 }; 2131 2132 struct mlx5_ifc_xrc_srqc_bits { 2133 u8 state[0x4]; 2134 u8 log_xrc_srq_size[0x4]; 2135 u8 reserved_at_8[0x18]; 2136 2137 u8 wq_signature[0x1]; 2138 u8 cont_srq[0x1]; 2139 u8 reserved_at_22[0x1]; 2140 u8 rlky[0x1]; 2141 u8 basic_cyclic_rcv_wqe[0x1]; 2142 u8 log_rq_stride[0x3]; 2143 u8 xrcd[0x18]; 2144 2145 u8 page_offset[0x6]; 2146 u8 reserved_at_46[0x2]; 2147 u8 cqn[0x18]; 2148 2149 u8 reserved_at_60[0x20]; 2150 2151 u8 user_index_equal_xrc_srqn[0x1]; 2152 u8 reserved_at_81[0x1]; 2153 u8 log_page_size[0x6]; 2154 u8 user_index[0x18]; 2155 2156 u8 reserved_at_a0[0x20]; 2157 2158 u8 reserved_at_c0[0x8]; 2159 u8 pd[0x18]; 2160 2161 u8 lwm[0x10]; 2162 u8 wqe_cnt[0x10]; 2163 2164 u8 reserved_at_100[0x40]; 2165 2166 u8 db_record_addr_h[0x20]; 2167 2168 u8 db_record_addr_l[0x1e]; 2169 u8 reserved_at_17e[0x2]; 2170 2171 u8 reserved_at_180[0x80]; 2172 }; 2173 2174 struct mlx5_ifc_traffic_counter_bits { 2175 u8 packets[0x40]; 2176 2177 u8 octets[0x40]; 2178 }; 2179 2180 struct mlx5_ifc_tisc_bits { 2181 u8 strict_lag_tx_port_affinity[0x1]; 2182 u8 reserved_at_1[0x3]; 2183 u8 lag_tx_port_affinity[0x04]; 2184 2185 u8 reserved_at_8[0x4]; 2186 u8 prio[0x4]; 2187 u8 reserved_at_10[0x10]; 2188 2189 u8 reserved_at_20[0x100]; 2190 2191 u8 reserved_at_120[0x8]; 2192 u8 transport_domain[0x18]; 2193 2194 u8 reserved_at_140[0x3c0]; 2195 }; 2196 2197 enum { 2198 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2199 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2200 }; 2201 2202 enum { 2203 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2204 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2205 }; 2206 2207 enum { 2208 MLX5_RX_HASH_FN_NONE = 0x0, 2209 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2210 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2211 }; 2212 2213 enum { 2214 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 2215 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 2216 }; 2217 2218 struct mlx5_ifc_tirc_bits { 2219 u8 reserved_at_0[0x20]; 2220 2221 u8 disp_type[0x4]; 2222 u8 reserved_at_24[0x1c]; 2223 2224 u8 reserved_at_40[0x40]; 2225 2226 u8 reserved_at_80[0x4]; 2227 u8 lro_timeout_period_usecs[0x10]; 2228 u8 lro_enable_mask[0x4]; 2229 u8 lro_max_ip_payload_size[0x8]; 2230 2231 u8 reserved_at_a0[0x40]; 2232 2233 u8 reserved_at_e0[0x8]; 2234 u8 inline_rqn[0x18]; 2235 2236 u8 rx_hash_symmetric[0x1]; 2237 u8 reserved_at_101[0x1]; 2238 u8 tunneled_offload_en[0x1]; 2239 u8 reserved_at_103[0x5]; 2240 u8 indirect_table[0x18]; 2241 2242 u8 rx_hash_fn[0x4]; 2243 u8 reserved_at_124[0x2]; 2244 u8 self_lb_block[0x2]; 2245 u8 transport_domain[0x18]; 2246 2247 u8 rx_hash_toeplitz_key[10][0x20]; 2248 2249 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2250 2251 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2252 2253 u8 reserved_at_2c0[0x4c0]; 2254 }; 2255 2256 enum { 2257 MLX5_SRQC_STATE_GOOD = 0x0, 2258 MLX5_SRQC_STATE_ERROR = 0x1, 2259 }; 2260 2261 struct mlx5_ifc_srqc_bits { 2262 u8 state[0x4]; 2263 u8 log_srq_size[0x4]; 2264 u8 reserved_at_8[0x18]; 2265 2266 u8 wq_signature[0x1]; 2267 u8 cont_srq[0x1]; 2268 u8 reserved_at_22[0x1]; 2269 u8 rlky[0x1]; 2270 u8 reserved_at_24[0x1]; 2271 u8 log_rq_stride[0x3]; 2272 u8 xrcd[0x18]; 2273 2274 u8 page_offset[0x6]; 2275 u8 reserved_at_46[0x2]; 2276 u8 cqn[0x18]; 2277 2278 u8 reserved_at_60[0x20]; 2279 2280 u8 reserved_at_80[0x2]; 2281 u8 log_page_size[0x6]; 2282 u8 reserved_at_88[0x18]; 2283 2284 u8 reserved_at_a0[0x20]; 2285 2286 u8 reserved_at_c0[0x8]; 2287 u8 pd[0x18]; 2288 2289 u8 lwm[0x10]; 2290 u8 wqe_cnt[0x10]; 2291 2292 u8 reserved_at_100[0x40]; 2293 2294 u8 dbr_addr[0x40]; 2295 2296 u8 reserved_at_180[0x80]; 2297 }; 2298 2299 enum { 2300 MLX5_SQC_STATE_RST = 0x0, 2301 MLX5_SQC_STATE_RDY = 0x1, 2302 MLX5_SQC_STATE_ERR = 0x3, 2303 }; 2304 2305 struct mlx5_ifc_sqc_bits { 2306 u8 rlky[0x1]; 2307 u8 cd_master[0x1]; 2308 u8 fre[0x1]; 2309 u8 flush_in_error_en[0x1]; 2310 u8 reserved_at_4[0x1]; 2311 u8 min_wqe_inline_mode[0x3]; 2312 u8 state[0x4]; 2313 u8 reg_umr[0x1]; 2314 u8 reserved_at_d[0x13]; 2315 2316 u8 reserved_at_20[0x8]; 2317 u8 user_index[0x18]; 2318 2319 u8 reserved_at_40[0x8]; 2320 u8 cqn[0x18]; 2321 2322 u8 reserved_at_60[0x90]; 2323 2324 u8 packet_pacing_rate_limit_index[0x10]; 2325 u8 tis_lst_sz[0x10]; 2326 u8 reserved_at_110[0x10]; 2327 2328 u8 reserved_at_120[0x40]; 2329 2330 u8 reserved_at_160[0x8]; 2331 u8 tis_num_0[0x18]; 2332 2333 struct mlx5_ifc_wq_bits wq; 2334 }; 2335 2336 struct mlx5_ifc_rqtc_bits { 2337 u8 reserved_at_0[0xa0]; 2338 2339 u8 reserved_at_a0[0x10]; 2340 u8 rqt_max_size[0x10]; 2341 2342 u8 reserved_at_c0[0x10]; 2343 u8 rqt_actual_size[0x10]; 2344 2345 u8 reserved_at_e0[0x6a0]; 2346 2347 struct mlx5_ifc_rq_num_bits rq_num[0]; 2348 }; 2349 2350 enum { 2351 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2352 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2353 }; 2354 2355 enum { 2356 MLX5_RQC_STATE_RST = 0x0, 2357 MLX5_RQC_STATE_RDY = 0x1, 2358 MLX5_RQC_STATE_ERR = 0x3, 2359 }; 2360 2361 struct mlx5_ifc_rqc_bits { 2362 u8 rlky[0x1]; 2363 u8 reserved_at_1[0x1]; 2364 u8 scatter_fcs[0x1]; 2365 u8 vsd[0x1]; 2366 u8 mem_rq_type[0x4]; 2367 u8 state[0x4]; 2368 u8 reserved_at_c[0x1]; 2369 u8 flush_in_error_en[0x1]; 2370 u8 reserved_at_e[0x12]; 2371 2372 u8 reserved_at_20[0x8]; 2373 u8 user_index[0x18]; 2374 2375 u8 reserved_at_40[0x8]; 2376 u8 cqn[0x18]; 2377 2378 u8 counter_set_id[0x8]; 2379 u8 reserved_at_68[0x18]; 2380 2381 u8 reserved_at_80[0x8]; 2382 u8 rmpn[0x18]; 2383 2384 u8 reserved_at_a0[0xe0]; 2385 2386 struct mlx5_ifc_wq_bits wq; 2387 }; 2388 2389 enum { 2390 MLX5_RMPC_STATE_RDY = 0x1, 2391 MLX5_RMPC_STATE_ERR = 0x3, 2392 }; 2393 2394 struct mlx5_ifc_rmpc_bits { 2395 u8 reserved_at_0[0x8]; 2396 u8 state[0x4]; 2397 u8 reserved_at_c[0x14]; 2398 2399 u8 basic_cyclic_rcv_wqe[0x1]; 2400 u8 reserved_at_21[0x1f]; 2401 2402 u8 reserved_at_40[0x140]; 2403 2404 struct mlx5_ifc_wq_bits wq; 2405 }; 2406 2407 struct mlx5_ifc_nic_vport_context_bits { 2408 u8 reserved_at_0[0x5]; 2409 u8 min_wqe_inline_mode[0x3]; 2410 u8 reserved_at_8[0x17]; 2411 u8 roce_en[0x1]; 2412 2413 u8 arm_change_event[0x1]; 2414 u8 reserved_at_21[0x1a]; 2415 u8 event_on_mtu[0x1]; 2416 u8 event_on_promisc_change[0x1]; 2417 u8 event_on_vlan_change[0x1]; 2418 u8 event_on_mc_address_change[0x1]; 2419 u8 event_on_uc_address_change[0x1]; 2420 2421 u8 reserved_at_40[0xf0]; 2422 2423 u8 mtu[0x10]; 2424 2425 u8 system_image_guid[0x40]; 2426 u8 port_guid[0x40]; 2427 u8 node_guid[0x40]; 2428 2429 u8 reserved_at_200[0x140]; 2430 u8 qkey_violation_counter[0x10]; 2431 u8 reserved_at_350[0x430]; 2432 2433 u8 promisc_uc[0x1]; 2434 u8 promisc_mc[0x1]; 2435 u8 promisc_all[0x1]; 2436 u8 reserved_at_783[0x2]; 2437 u8 allowed_list_type[0x3]; 2438 u8 reserved_at_788[0xc]; 2439 u8 allowed_list_size[0xc]; 2440 2441 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2442 2443 u8 reserved_at_7e0[0x20]; 2444 2445 u8 current_uc_mac_address[0][0x40]; 2446 }; 2447 2448 enum { 2449 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2450 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2451 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2452 }; 2453 2454 struct mlx5_ifc_mkc_bits { 2455 u8 reserved_at_0[0x1]; 2456 u8 free[0x1]; 2457 u8 reserved_at_2[0xd]; 2458 u8 small_fence_on_rdma_read_response[0x1]; 2459 u8 umr_en[0x1]; 2460 u8 a[0x1]; 2461 u8 rw[0x1]; 2462 u8 rr[0x1]; 2463 u8 lw[0x1]; 2464 u8 lr[0x1]; 2465 u8 access_mode[0x2]; 2466 u8 reserved_at_18[0x8]; 2467 2468 u8 qpn[0x18]; 2469 u8 mkey_7_0[0x8]; 2470 2471 u8 reserved_at_40[0x20]; 2472 2473 u8 length64[0x1]; 2474 u8 bsf_en[0x1]; 2475 u8 sync_umr[0x1]; 2476 u8 reserved_at_63[0x2]; 2477 u8 expected_sigerr_count[0x1]; 2478 u8 reserved_at_66[0x1]; 2479 u8 en_rinval[0x1]; 2480 u8 pd[0x18]; 2481 2482 u8 start_addr[0x40]; 2483 2484 u8 len[0x40]; 2485 2486 u8 bsf_octword_size[0x20]; 2487 2488 u8 reserved_at_120[0x80]; 2489 2490 u8 translations_octword_size[0x20]; 2491 2492 u8 reserved_at_1c0[0x1b]; 2493 u8 log_page_size[0x5]; 2494 2495 u8 reserved_at_1e0[0x20]; 2496 }; 2497 2498 struct mlx5_ifc_pkey_bits { 2499 u8 reserved_at_0[0x10]; 2500 u8 pkey[0x10]; 2501 }; 2502 2503 struct mlx5_ifc_array128_auto_bits { 2504 u8 array128_auto[16][0x8]; 2505 }; 2506 2507 struct mlx5_ifc_hca_vport_context_bits { 2508 u8 field_select[0x20]; 2509 2510 u8 reserved_at_20[0xe0]; 2511 2512 u8 sm_virt_aware[0x1]; 2513 u8 has_smi[0x1]; 2514 u8 has_raw[0x1]; 2515 u8 grh_required[0x1]; 2516 u8 reserved_at_104[0xc]; 2517 u8 port_physical_state[0x4]; 2518 u8 vport_state_policy[0x4]; 2519 u8 port_state[0x4]; 2520 u8 vport_state[0x4]; 2521 2522 u8 reserved_at_120[0x20]; 2523 2524 u8 system_image_guid[0x40]; 2525 2526 u8 port_guid[0x40]; 2527 2528 u8 node_guid[0x40]; 2529 2530 u8 cap_mask1[0x20]; 2531 2532 u8 cap_mask1_field_select[0x20]; 2533 2534 u8 cap_mask2[0x20]; 2535 2536 u8 cap_mask2_field_select[0x20]; 2537 2538 u8 reserved_at_280[0x80]; 2539 2540 u8 lid[0x10]; 2541 u8 reserved_at_310[0x4]; 2542 u8 init_type_reply[0x4]; 2543 u8 lmc[0x3]; 2544 u8 subnet_timeout[0x5]; 2545 2546 u8 sm_lid[0x10]; 2547 u8 sm_sl[0x4]; 2548 u8 reserved_at_334[0xc]; 2549 2550 u8 qkey_violation_counter[0x10]; 2551 u8 pkey_violation_counter[0x10]; 2552 2553 u8 reserved_at_360[0xca0]; 2554 }; 2555 2556 struct mlx5_ifc_esw_vport_context_bits { 2557 u8 reserved_at_0[0x3]; 2558 u8 vport_svlan_strip[0x1]; 2559 u8 vport_cvlan_strip[0x1]; 2560 u8 vport_svlan_insert[0x1]; 2561 u8 vport_cvlan_insert[0x2]; 2562 u8 reserved_at_8[0x18]; 2563 2564 u8 reserved_at_20[0x20]; 2565 2566 u8 svlan_cfi[0x1]; 2567 u8 svlan_pcp[0x3]; 2568 u8 svlan_id[0xc]; 2569 u8 cvlan_cfi[0x1]; 2570 u8 cvlan_pcp[0x3]; 2571 u8 cvlan_id[0xc]; 2572 2573 u8 reserved_at_60[0x7a0]; 2574 }; 2575 2576 enum { 2577 MLX5_EQC_STATUS_OK = 0x0, 2578 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2579 }; 2580 2581 enum { 2582 MLX5_EQC_ST_ARMED = 0x9, 2583 MLX5_EQC_ST_FIRED = 0xa, 2584 }; 2585 2586 struct mlx5_ifc_eqc_bits { 2587 u8 status[0x4]; 2588 u8 reserved_at_4[0x9]; 2589 u8 ec[0x1]; 2590 u8 oi[0x1]; 2591 u8 reserved_at_f[0x5]; 2592 u8 st[0x4]; 2593 u8 reserved_at_18[0x8]; 2594 2595 u8 reserved_at_20[0x20]; 2596 2597 u8 reserved_at_40[0x14]; 2598 u8 page_offset[0x6]; 2599 u8 reserved_at_5a[0x6]; 2600 2601 u8 reserved_at_60[0x3]; 2602 u8 log_eq_size[0x5]; 2603 u8 uar_page[0x18]; 2604 2605 u8 reserved_at_80[0x20]; 2606 2607 u8 reserved_at_a0[0x18]; 2608 u8 intr[0x8]; 2609 2610 u8 reserved_at_c0[0x3]; 2611 u8 log_page_size[0x5]; 2612 u8 reserved_at_c8[0x18]; 2613 2614 u8 reserved_at_e0[0x60]; 2615 2616 u8 reserved_at_140[0x8]; 2617 u8 consumer_counter[0x18]; 2618 2619 u8 reserved_at_160[0x8]; 2620 u8 producer_counter[0x18]; 2621 2622 u8 reserved_at_180[0x80]; 2623 }; 2624 2625 enum { 2626 MLX5_DCTC_STATE_ACTIVE = 0x0, 2627 MLX5_DCTC_STATE_DRAINING = 0x1, 2628 MLX5_DCTC_STATE_DRAINED = 0x2, 2629 }; 2630 2631 enum { 2632 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2633 MLX5_DCTC_CS_RES_NA = 0x1, 2634 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2635 }; 2636 2637 enum { 2638 MLX5_DCTC_MTU_256_BYTES = 0x1, 2639 MLX5_DCTC_MTU_512_BYTES = 0x2, 2640 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2641 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2642 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2643 }; 2644 2645 struct mlx5_ifc_dctc_bits { 2646 u8 reserved_at_0[0x4]; 2647 u8 state[0x4]; 2648 u8 reserved_at_8[0x18]; 2649 2650 u8 reserved_at_20[0x8]; 2651 u8 user_index[0x18]; 2652 2653 u8 reserved_at_40[0x8]; 2654 u8 cqn[0x18]; 2655 2656 u8 counter_set_id[0x8]; 2657 u8 atomic_mode[0x4]; 2658 u8 rre[0x1]; 2659 u8 rwe[0x1]; 2660 u8 rae[0x1]; 2661 u8 atomic_like_write_en[0x1]; 2662 u8 latency_sensitive[0x1]; 2663 u8 rlky[0x1]; 2664 u8 free_ar[0x1]; 2665 u8 reserved_at_73[0xd]; 2666 2667 u8 reserved_at_80[0x8]; 2668 u8 cs_res[0x8]; 2669 u8 reserved_at_90[0x3]; 2670 u8 min_rnr_nak[0x5]; 2671 u8 reserved_at_98[0x8]; 2672 2673 u8 reserved_at_a0[0x8]; 2674 u8 srqn_xrqn[0x18]; 2675 2676 u8 reserved_at_c0[0x8]; 2677 u8 pd[0x18]; 2678 2679 u8 tclass[0x8]; 2680 u8 reserved_at_e8[0x4]; 2681 u8 flow_label[0x14]; 2682 2683 u8 dc_access_key[0x40]; 2684 2685 u8 reserved_at_140[0x5]; 2686 u8 mtu[0x3]; 2687 u8 port[0x8]; 2688 u8 pkey_index[0x10]; 2689 2690 u8 reserved_at_160[0x8]; 2691 u8 my_addr_index[0x8]; 2692 u8 reserved_at_170[0x8]; 2693 u8 hop_limit[0x8]; 2694 2695 u8 dc_access_key_violation_count[0x20]; 2696 2697 u8 reserved_at_1a0[0x14]; 2698 u8 dei_cfi[0x1]; 2699 u8 eth_prio[0x3]; 2700 u8 ecn[0x2]; 2701 u8 dscp[0x6]; 2702 2703 u8 reserved_at_1c0[0x40]; 2704 }; 2705 2706 enum { 2707 MLX5_CQC_STATUS_OK = 0x0, 2708 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2709 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2710 }; 2711 2712 enum { 2713 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 2714 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 2715 }; 2716 2717 enum { 2718 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 2719 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 2720 MLX5_CQC_ST_FIRED = 0xa, 2721 }; 2722 2723 enum { 2724 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2725 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2726 MLX5_CQ_PERIOD_NUM_MODES 2727 }; 2728 2729 struct mlx5_ifc_cqc_bits { 2730 u8 status[0x4]; 2731 u8 reserved_at_4[0x4]; 2732 u8 cqe_sz[0x3]; 2733 u8 cc[0x1]; 2734 u8 reserved_at_c[0x1]; 2735 u8 scqe_break_moderation_en[0x1]; 2736 u8 oi[0x1]; 2737 u8 cq_period_mode[0x2]; 2738 u8 cqe_comp_en[0x1]; 2739 u8 mini_cqe_res_format[0x2]; 2740 u8 st[0x4]; 2741 u8 reserved_at_18[0x8]; 2742 2743 u8 reserved_at_20[0x20]; 2744 2745 u8 reserved_at_40[0x14]; 2746 u8 page_offset[0x6]; 2747 u8 reserved_at_5a[0x6]; 2748 2749 u8 reserved_at_60[0x3]; 2750 u8 log_cq_size[0x5]; 2751 u8 uar_page[0x18]; 2752 2753 u8 reserved_at_80[0x4]; 2754 u8 cq_period[0xc]; 2755 u8 cq_max_count[0x10]; 2756 2757 u8 reserved_at_a0[0x18]; 2758 u8 c_eqn[0x8]; 2759 2760 u8 reserved_at_c0[0x3]; 2761 u8 log_page_size[0x5]; 2762 u8 reserved_at_c8[0x18]; 2763 2764 u8 reserved_at_e0[0x20]; 2765 2766 u8 reserved_at_100[0x8]; 2767 u8 last_notified_index[0x18]; 2768 2769 u8 reserved_at_120[0x8]; 2770 u8 last_solicit_index[0x18]; 2771 2772 u8 reserved_at_140[0x8]; 2773 u8 consumer_counter[0x18]; 2774 2775 u8 reserved_at_160[0x8]; 2776 u8 producer_counter[0x18]; 2777 2778 u8 reserved_at_180[0x40]; 2779 2780 u8 dbr_addr[0x40]; 2781 }; 2782 2783 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2784 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2785 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2786 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2787 u8 reserved_at_0[0x800]; 2788 }; 2789 2790 struct mlx5_ifc_query_adapter_param_block_bits { 2791 u8 reserved_at_0[0xc0]; 2792 2793 u8 reserved_at_c0[0x8]; 2794 u8 ieee_vendor_id[0x18]; 2795 2796 u8 reserved_at_e0[0x10]; 2797 u8 vsd_vendor_id[0x10]; 2798 2799 u8 vsd[208][0x8]; 2800 2801 u8 vsd_contd_psid[16][0x8]; 2802 }; 2803 2804 enum { 2805 MLX5_XRQC_STATE_GOOD = 0x0, 2806 MLX5_XRQC_STATE_ERROR = 0x1, 2807 }; 2808 2809 enum { 2810 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 2811 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 2812 }; 2813 2814 enum { 2815 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 2816 }; 2817 2818 struct mlx5_ifc_tag_matching_topology_context_bits { 2819 u8 log_matching_list_sz[0x4]; 2820 u8 reserved_at_4[0xc]; 2821 u8 append_next_index[0x10]; 2822 2823 u8 sw_phase_cnt[0x10]; 2824 u8 hw_phase_cnt[0x10]; 2825 2826 u8 reserved_at_40[0x40]; 2827 }; 2828 2829 struct mlx5_ifc_xrqc_bits { 2830 u8 state[0x4]; 2831 u8 rlkey[0x1]; 2832 u8 reserved_at_5[0xf]; 2833 u8 topology[0x4]; 2834 u8 reserved_at_18[0x4]; 2835 u8 offload[0x4]; 2836 2837 u8 reserved_at_20[0x8]; 2838 u8 user_index[0x18]; 2839 2840 u8 reserved_at_40[0x8]; 2841 u8 cqn[0x18]; 2842 2843 u8 reserved_at_60[0xa0]; 2844 2845 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 2846 2847 u8 reserved_at_180[0x200]; 2848 2849 struct mlx5_ifc_wq_bits wq; 2850 }; 2851 2852 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2853 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2854 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2855 u8 reserved_at_0[0x20]; 2856 }; 2857 2858 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2859 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2860 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2861 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2862 u8 reserved_at_0[0x20]; 2863 }; 2864 2865 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 2866 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 2867 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 2868 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 2869 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 2870 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 2871 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 2872 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 2873 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 2874 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 2875 u8 reserved_at_0[0x7c0]; 2876 }; 2877 2878 union mlx5_ifc_event_auto_bits { 2879 struct mlx5_ifc_comp_event_bits comp_event; 2880 struct mlx5_ifc_dct_events_bits dct_events; 2881 struct mlx5_ifc_qp_events_bits qp_events; 2882 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 2883 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 2884 struct mlx5_ifc_cq_error_bits cq_error; 2885 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 2886 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 2887 struct mlx5_ifc_gpio_event_bits gpio_event; 2888 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 2889 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 2890 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 2891 u8 reserved_at_0[0xe0]; 2892 }; 2893 2894 struct mlx5_ifc_health_buffer_bits { 2895 u8 reserved_at_0[0x100]; 2896 2897 u8 assert_existptr[0x20]; 2898 2899 u8 assert_callra[0x20]; 2900 2901 u8 reserved_at_140[0x40]; 2902 2903 u8 fw_version[0x20]; 2904 2905 u8 hw_id[0x20]; 2906 2907 u8 reserved_at_1c0[0x20]; 2908 2909 u8 irisc_index[0x8]; 2910 u8 synd[0x8]; 2911 u8 ext_synd[0x10]; 2912 }; 2913 2914 struct mlx5_ifc_register_loopback_control_bits { 2915 u8 no_lb[0x1]; 2916 u8 reserved_at_1[0x7]; 2917 u8 port[0x8]; 2918 u8 reserved_at_10[0x10]; 2919 2920 u8 reserved_at_20[0x60]; 2921 }; 2922 2923 struct mlx5_ifc_teardown_hca_out_bits { 2924 u8 status[0x8]; 2925 u8 reserved_at_8[0x18]; 2926 2927 u8 syndrome[0x20]; 2928 2929 u8 reserved_at_40[0x40]; 2930 }; 2931 2932 enum { 2933 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 2934 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1, 2935 }; 2936 2937 struct mlx5_ifc_teardown_hca_in_bits { 2938 u8 opcode[0x10]; 2939 u8 reserved_at_10[0x10]; 2940 2941 u8 reserved_at_20[0x10]; 2942 u8 op_mod[0x10]; 2943 2944 u8 reserved_at_40[0x10]; 2945 u8 profile[0x10]; 2946 2947 u8 reserved_at_60[0x20]; 2948 }; 2949 2950 struct mlx5_ifc_sqerr2rts_qp_out_bits { 2951 u8 status[0x8]; 2952 u8 reserved_at_8[0x18]; 2953 2954 u8 syndrome[0x20]; 2955 2956 u8 reserved_at_40[0x40]; 2957 }; 2958 2959 struct mlx5_ifc_sqerr2rts_qp_in_bits { 2960 u8 opcode[0x10]; 2961 u8 reserved_at_10[0x10]; 2962 2963 u8 reserved_at_20[0x10]; 2964 u8 op_mod[0x10]; 2965 2966 u8 reserved_at_40[0x8]; 2967 u8 qpn[0x18]; 2968 2969 u8 reserved_at_60[0x20]; 2970 2971 u8 opt_param_mask[0x20]; 2972 2973 u8 reserved_at_a0[0x20]; 2974 2975 struct mlx5_ifc_qpc_bits qpc; 2976 2977 u8 reserved_at_800[0x80]; 2978 }; 2979 2980 struct mlx5_ifc_sqd2rts_qp_out_bits { 2981 u8 status[0x8]; 2982 u8 reserved_at_8[0x18]; 2983 2984 u8 syndrome[0x20]; 2985 2986 u8 reserved_at_40[0x40]; 2987 }; 2988 2989 struct mlx5_ifc_sqd2rts_qp_in_bits { 2990 u8 opcode[0x10]; 2991 u8 reserved_at_10[0x10]; 2992 2993 u8 reserved_at_20[0x10]; 2994 u8 op_mod[0x10]; 2995 2996 u8 reserved_at_40[0x8]; 2997 u8 qpn[0x18]; 2998 2999 u8 reserved_at_60[0x20]; 3000 3001 u8 opt_param_mask[0x20]; 3002 3003 u8 reserved_at_a0[0x20]; 3004 3005 struct mlx5_ifc_qpc_bits qpc; 3006 3007 u8 reserved_at_800[0x80]; 3008 }; 3009 3010 struct mlx5_ifc_set_roce_address_out_bits { 3011 u8 status[0x8]; 3012 u8 reserved_at_8[0x18]; 3013 3014 u8 syndrome[0x20]; 3015 3016 u8 reserved_at_40[0x40]; 3017 }; 3018 3019 struct mlx5_ifc_set_roce_address_in_bits { 3020 u8 opcode[0x10]; 3021 u8 reserved_at_10[0x10]; 3022 3023 u8 reserved_at_20[0x10]; 3024 u8 op_mod[0x10]; 3025 3026 u8 roce_address_index[0x10]; 3027 u8 reserved_at_50[0x10]; 3028 3029 u8 reserved_at_60[0x20]; 3030 3031 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3032 }; 3033 3034 struct mlx5_ifc_set_mad_demux_out_bits { 3035 u8 status[0x8]; 3036 u8 reserved_at_8[0x18]; 3037 3038 u8 syndrome[0x20]; 3039 3040 u8 reserved_at_40[0x40]; 3041 }; 3042 3043 enum { 3044 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3045 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3046 }; 3047 3048 struct mlx5_ifc_set_mad_demux_in_bits { 3049 u8 opcode[0x10]; 3050 u8 reserved_at_10[0x10]; 3051 3052 u8 reserved_at_20[0x10]; 3053 u8 op_mod[0x10]; 3054 3055 u8 reserved_at_40[0x20]; 3056 3057 u8 reserved_at_60[0x6]; 3058 u8 demux_mode[0x2]; 3059 u8 reserved_at_68[0x18]; 3060 }; 3061 3062 struct mlx5_ifc_set_l2_table_entry_out_bits { 3063 u8 status[0x8]; 3064 u8 reserved_at_8[0x18]; 3065 3066 u8 syndrome[0x20]; 3067 3068 u8 reserved_at_40[0x40]; 3069 }; 3070 3071 struct mlx5_ifc_set_l2_table_entry_in_bits { 3072 u8 opcode[0x10]; 3073 u8 reserved_at_10[0x10]; 3074 3075 u8 reserved_at_20[0x10]; 3076 u8 op_mod[0x10]; 3077 3078 u8 reserved_at_40[0x60]; 3079 3080 u8 reserved_at_a0[0x8]; 3081 u8 table_index[0x18]; 3082 3083 u8 reserved_at_c0[0x20]; 3084 3085 u8 reserved_at_e0[0x13]; 3086 u8 vlan_valid[0x1]; 3087 u8 vlan[0xc]; 3088 3089 struct mlx5_ifc_mac_address_layout_bits mac_address; 3090 3091 u8 reserved_at_140[0xc0]; 3092 }; 3093 3094 struct mlx5_ifc_set_issi_out_bits { 3095 u8 status[0x8]; 3096 u8 reserved_at_8[0x18]; 3097 3098 u8 syndrome[0x20]; 3099 3100 u8 reserved_at_40[0x40]; 3101 }; 3102 3103 struct mlx5_ifc_set_issi_in_bits { 3104 u8 opcode[0x10]; 3105 u8 reserved_at_10[0x10]; 3106 3107 u8 reserved_at_20[0x10]; 3108 u8 op_mod[0x10]; 3109 3110 u8 reserved_at_40[0x10]; 3111 u8 current_issi[0x10]; 3112 3113 u8 reserved_at_60[0x20]; 3114 }; 3115 3116 struct mlx5_ifc_set_hca_cap_out_bits { 3117 u8 status[0x8]; 3118 u8 reserved_at_8[0x18]; 3119 3120 u8 syndrome[0x20]; 3121 3122 u8 reserved_at_40[0x40]; 3123 }; 3124 3125 struct mlx5_ifc_set_hca_cap_in_bits { 3126 u8 opcode[0x10]; 3127 u8 reserved_at_10[0x10]; 3128 3129 u8 reserved_at_20[0x10]; 3130 u8 op_mod[0x10]; 3131 3132 u8 reserved_at_40[0x40]; 3133 3134 union mlx5_ifc_hca_cap_union_bits capability; 3135 }; 3136 3137 enum { 3138 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3139 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3140 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3141 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3142 }; 3143 3144 struct mlx5_ifc_set_fte_out_bits { 3145 u8 status[0x8]; 3146 u8 reserved_at_8[0x18]; 3147 3148 u8 syndrome[0x20]; 3149 3150 u8 reserved_at_40[0x40]; 3151 }; 3152 3153 struct mlx5_ifc_set_fte_in_bits { 3154 u8 opcode[0x10]; 3155 u8 reserved_at_10[0x10]; 3156 3157 u8 reserved_at_20[0x10]; 3158 u8 op_mod[0x10]; 3159 3160 u8 other_vport[0x1]; 3161 u8 reserved_at_41[0xf]; 3162 u8 vport_number[0x10]; 3163 3164 u8 reserved_at_60[0x20]; 3165 3166 u8 table_type[0x8]; 3167 u8 reserved_at_88[0x18]; 3168 3169 u8 reserved_at_a0[0x8]; 3170 u8 table_id[0x18]; 3171 3172 u8 reserved_at_c0[0x18]; 3173 u8 modify_enable_mask[0x8]; 3174 3175 u8 reserved_at_e0[0x20]; 3176 3177 u8 flow_index[0x20]; 3178 3179 u8 reserved_at_120[0xe0]; 3180 3181 struct mlx5_ifc_flow_context_bits flow_context; 3182 }; 3183 3184 struct mlx5_ifc_rts2rts_qp_out_bits { 3185 u8 status[0x8]; 3186 u8 reserved_at_8[0x18]; 3187 3188 u8 syndrome[0x20]; 3189 3190 u8 reserved_at_40[0x40]; 3191 }; 3192 3193 struct mlx5_ifc_rts2rts_qp_in_bits { 3194 u8 opcode[0x10]; 3195 u8 reserved_at_10[0x10]; 3196 3197 u8 reserved_at_20[0x10]; 3198 u8 op_mod[0x10]; 3199 3200 u8 reserved_at_40[0x8]; 3201 u8 qpn[0x18]; 3202 3203 u8 reserved_at_60[0x20]; 3204 3205 u8 opt_param_mask[0x20]; 3206 3207 u8 reserved_at_a0[0x20]; 3208 3209 struct mlx5_ifc_qpc_bits qpc; 3210 3211 u8 reserved_at_800[0x80]; 3212 }; 3213 3214 struct mlx5_ifc_rtr2rts_qp_out_bits { 3215 u8 status[0x8]; 3216 u8 reserved_at_8[0x18]; 3217 3218 u8 syndrome[0x20]; 3219 3220 u8 reserved_at_40[0x40]; 3221 }; 3222 3223 struct mlx5_ifc_rtr2rts_qp_in_bits { 3224 u8 opcode[0x10]; 3225 u8 reserved_at_10[0x10]; 3226 3227 u8 reserved_at_20[0x10]; 3228 u8 op_mod[0x10]; 3229 3230 u8 reserved_at_40[0x8]; 3231 u8 qpn[0x18]; 3232 3233 u8 reserved_at_60[0x20]; 3234 3235 u8 opt_param_mask[0x20]; 3236 3237 u8 reserved_at_a0[0x20]; 3238 3239 struct mlx5_ifc_qpc_bits qpc; 3240 3241 u8 reserved_at_800[0x80]; 3242 }; 3243 3244 struct mlx5_ifc_rst2init_qp_out_bits { 3245 u8 status[0x8]; 3246 u8 reserved_at_8[0x18]; 3247 3248 u8 syndrome[0x20]; 3249 3250 u8 reserved_at_40[0x40]; 3251 }; 3252 3253 struct mlx5_ifc_rst2init_qp_in_bits { 3254 u8 opcode[0x10]; 3255 u8 reserved_at_10[0x10]; 3256 3257 u8 reserved_at_20[0x10]; 3258 u8 op_mod[0x10]; 3259 3260 u8 reserved_at_40[0x8]; 3261 u8 qpn[0x18]; 3262 3263 u8 reserved_at_60[0x20]; 3264 3265 u8 opt_param_mask[0x20]; 3266 3267 u8 reserved_at_a0[0x20]; 3268 3269 struct mlx5_ifc_qpc_bits qpc; 3270 3271 u8 reserved_at_800[0x80]; 3272 }; 3273 3274 struct mlx5_ifc_query_xrq_out_bits { 3275 u8 status[0x8]; 3276 u8 reserved_at_8[0x18]; 3277 3278 u8 syndrome[0x20]; 3279 3280 u8 reserved_at_40[0x40]; 3281 3282 struct mlx5_ifc_xrqc_bits xrq_context; 3283 }; 3284 3285 struct mlx5_ifc_query_xrq_in_bits { 3286 u8 opcode[0x10]; 3287 u8 reserved_at_10[0x10]; 3288 3289 u8 reserved_at_20[0x10]; 3290 u8 op_mod[0x10]; 3291 3292 u8 reserved_at_40[0x8]; 3293 u8 xrqn[0x18]; 3294 3295 u8 reserved_at_60[0x20]; 3296 }; 3297 3298 struct mlx5_ifc_query_xrc_srq_out_bits { 3299 u8 status[0x8]; 3300 u8 reserved_at_8[0x18]; 3301 3302 u8 syndrome[0x20]; 3303 3304 u8 reserved_at_40[0x40]; 3305 3306 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3307 3308 u8 reserved_at_280[0x600]; 3309 3310 u8 pas[0][0x40]; 3311 }; 3312 3313 struct mlx5_ifc_query_xrc_srq_in_bits { 3314 u8 opcode[0x10]; 3315 u8 reserved_at_10[0x10]; 3316 3317 u8 reserved_at_20[0x10]; 3318 u8 op_mod[0x10]; 3319 3320 u8 reserved_at_40[0x8]; 3321 u8 xrc_srqn[0x18]; 3322 3323 u8 reserved_at_60[0x20]; 3324 }; 3325 3326 enum { 3327 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3328 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3329 }; 3330 3331 struct mlx5_ifc_query_vport_state_out_bits { 3332 u8 status[0x8]; 3333 u8 reserved_at_8[0x18]; 3334 3335 u8 syndrome[0x20]; 3336 3337 u8 reserved_at_40[0x20]; 3338 3339 u8 reserved_at_60[0x18]; 3340 u8 admin_state[0x4]; 3341 u8 state[0x4]; 3342 }; 3343 3344 enum { 3345 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3346 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3347 }; 3348 3349 struct mlx5_ifc_query_vport_state_in_bits { 3350 u8 opcode[0x10]; 3351 u8 reserved_at_10[0x10]; 3352 3353 u8 reserved_at_20[0x10]; 3354 u8 op_mod[0x10]; 3355 3356 u8 other_vport[0x1]; 3357 u8 reserved_at_41[0xf]; 3358 u8 vport_number[0x10]; 3359 3360 u8 reserved_at_60[0x20]; 3361 }; 3362 3363 struct mlx5_ifc_query_vport_counter_out_bits { 3364 u8 status[0x8]; 3365 u8 reserved_at_8[0x18]; 3366 3367 u8 syndrome[0x20]; 3368 3369 u8 reserved_at_40[0x40]; 3370 3371 struct mlx5_ifc_traffic_counter_bits received_errors; 3372 3373 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3374 3375 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3376 3377 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3378 3379 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3380 3381 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3382 3383 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3384 3385 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3386 3387 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3388 3389 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3390 3391 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3392 3393 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3394 3395 u8 reserved_at_680[0xa00]; 3396 }; 3397 3398 enum { 3399 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3400 }; 3401 3402 struct mlx5_ifc_query_vport_counter_in_bits { 3403 u8 opcode[0x10]; 3404 u8 reserved_at_10[0x10]; 3405 3406 u8 reserved_at_20[0x10]; 3407 u8 op_mod[0x10]; 3408 3409 u8 other_vport[0x1]; 3410 u8 reserved_at_41[0xb]; 3411 u8 port_num[0x4]; 3412 u8 vport_number[0x10]; 3413 3414 u8 reserved_at_60[0x60]; 3415 3416 u8 clear[0x1]; 3417 u8 reserved_at_c1[0x1f]; 3418 3419 u8 reserved_at_e0[0x20]; 3420 }; 3421 3422 struct mlx5_ifc_query_tis_out_bits { 3423 u8 status[0x8]; 3424 u8 reserved_at_8[0x18]; 3425 3426 u8 syndrome[0x20]; 3427 3428 u8 reserved_at_40[0x40]; 3429 3430 struct mlx5_ifc_tisc_bits tis_context; 3431 }; 3432 3433 struct mlx5_ifc_query_tis_in_bits { 3434 u8 opcode[0x10]; 3435 u8 reserved_at_10[0x10]; 3436 3437 u8 reserved_at_20[0x10]; 3438 u8 op_mod[0x10]; 3439 3440 u8 reserved_at_40[0x8]; 3441 u8 tisn[0x18]; 3442 3443 u8 reserved_at_60[0x20]; 3444 }; 3445 3446 struct mlx5_ifc_query_tir_out_bits { 3447 u8 status[0x8]; 3448 u8 reserved_at_8[0x18]; 3449 3450 u8 syndrome[0x20]; 3451 3452 u8 reserved_at_40[0xc0]; 3453 3454 struct mlx5_ifc_tirc_bits tir_context; 3455 }; 3456 3457 struct mlx5_ifc_query_tir_in_bits { 3458 u8 opcode[0x10]; 3459 u8 reserved_at_10[0x10]; 3460 3461 u8 reserved_at_20[0x10]; 3462 u8 op_mod[0x10]; 3463 3464 u8 reserved_at_40[0x8]; 3465 u8 tirn[0x18]; 3466 3467 u8 reserved_at_60[0x20]; 3468 }; 3469 3470 struct mlx5_ifc_query_srq_out_bits { 3471 u8 status[0x8]; 3472 u8 reserved_at_8[0x18]; 3473 3474 u8 syndrome[0x20]; 3475 3476 u8 reserved_at_40[0x40]; 3477 3478 struct mlx5_ifc_srqc_bits srq_context_entry; 3479 3480 u8 reserved_at_280[0x600]; 3481 3482 u8 pas[0][0x40]; 3483 }; 3484 3485 struct mlx5_ifc_query_srq_in_bits { 3486 u8 opcode[0x10]; 3487 u8 reserved_at_10[0x10]; 3488 3489 u8 reserved_at_20[0x10]; 3490 u8 op_mod[0x10]; 3491 3492 u8 reserved_at_40[0x8]; 3493 u8 srqn[0x18]; 3494 3495 u8 reserved_at_60[0x20]; 3496 }; 3497 3498 struct mlx5_ifc_query_sq_out_bits { 3499 u8 status[0x8]; 3500 u8 reserved_at_8[0x18]; 3501 3502 u8 syndrome[0x20]; 3503 3504 u8 reserved_at_40[0xc0]; 3505 3506 struct mlx5_ifc_sqc_bits sq_context; 3507 }; 3508 3509 struct mlx5_ifc_query_sq_in_bits { 3510 u8 opcode[0x10]; 3511 u8 reserved_at_10[0x10]; 3512 3513 u8 reserved_at_20[0x10]; 3514 u8 op_mod[0x10]; 3515 3516 u8 reserved_at_40[0x8]; 3517 u8 sqn[0x18]; 3518 3519 u8 reserved_at_60[0x20]; 3520 }; 3521 3522 struct mlx5_ifc_query_special_contexts_out_bits { 3523 u8 status[0x8]; 3524 u8 reserved_at_8[0x18]; 3525 3526 u8 syndrome[0x20]; 3527 3528 u8 dump_fill_mkey[0x20]; 3529 3530 u8 resd_lkey[0x20]; 3531 }; 3532 3533 struct mlx5_ifc_query_special_contexts_in_bits { 3534 u8 opcode[0x10]; 3535 u8 reserved_at_10[0x10]; 3536 3537 u8 reserved_at_20[0x10]; 3538 u8 op_mod[0x10]; 3539 3540 u8 reserved_at_40[0x40]; 3541 }; 3542 3543 struct mlx5_ifc_query_rqt_out_bits { 3544 u8 status[0x8]; 3545 u8 reserved_at_8[0x18]; 3546 3547 u8 syndrome[0x20]; 3548 3549 u8 reserved_at_40[0xc0]; 3550 3551 struct mlx5_ifc_rqtc_bits rqt_context; 3552 }; 3553 3554 struct mlx5_ifc_query_rqt_in_bits { 3555 u8 opcode[0x10]; 3556 u8 reserved_at_10[0x10]; 3557 3558 u8 reserved_at_20[0x10]; 3559 u8 op_mod[0x10]; 3560 3561 u8 reserved_at_40[0x8]; 3562 u8 rqtn[0x18]; 3563 3564 u8 reserved_at_60[0x20]; 3565 }; 3566 3567 struct mlx5_ifc_query_rq_out_bits { 3568 u8 status[0x8]; 3569 u8 reserved_at_8[0x18]; 3570 3571 u8 syndrome[0x20]; 3572 3573 u8 reserved_at_40[0xc0]; 3574 3575 struct mlx5_ifc_rqc_bits rq_context; 3576 }; 3577 3578 struct mlx5_ifc_query_rq_in_bits { 3579 u8 opcode[0x10]; 3580 u8 reserved_at_10[0x10]; 3581 3582 u8 reserved_at_20[0x10]; 3583 u8 op_mod[0x10]; 3584 3585 u8 reserved_at_40[0x8]; 3586 u8 rqn[0x18]; 3587 3588 u8 reserved_at_60[0x20]; 3589 }; 3590 3591 struct mlx5_ifc_query_roce_address_out_bits { 3592 u8 status[0x8]; 3593 u8 reserved_at_8[0x18]; 3594 3595 u8 syndrome[0x20]; 3596 3597 u8 reserved_at_40[0x40]; 3598 3599 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3600 }; 3601 3602 struct mlx5_ifc_query_roce_address_in_bits { 3603 u8 opcode[0x10]; 3604 u8 reserved_at_10[0x10]; 3605 3606 u8 reserved_at_20[0x10]; 3607 u8 op_mod[0x10]; 3608 3609 u8 roce_address_index[0x10]; 3610 u8 reserved_at_50[0x10]; 3611 3612 u8 reserved_at_60[0x20]; 3613 }; 3614 3615 struct mlx5_ifc_query_rmp_out_bits { 3616 u8 status[0x8]; 3617 u8 reserved_at_8[0x18]; 3618 3619 u8 syndrome[0x20]; 3620 3621 u8 reserved_at_40[0xc0]; 3622 3623 struct mlx5_ifc_rmpc_bits rmp_context; 3624 }; 3625 3626 struct mlx5_ifc_query_rmp_in_bits { 3627 u8 opcode[0x10]; 3628 u8 reserved_at_10[0x10]; 3629 3630 u8 reserved_at_20[0x10]; 3631 u8 op_mod[0x10]; 3632 3633 u8 reserved_at_40[0x8]; 3634 u8 rmpn[0x18]; 3635 3636 u8 reserved_at_60[0x20]; 3637 }; 3638 3639 struct mlx5_ifc_query_qp_out_bits { 3640 u8 status[0x8]; 3641 u8 reserved_at_8[0x18]; 3642 3643 u8 syndrome[0x20]; 3644 3645 u8 reserved_at_40[0x40]; 3646 3647 u8 opt_param_mask[0x20]; 3648 3649 u8 reserved_at_a0[0x20]; 3650 3651 struct mlx5_ifc_qpc_bits qpc; 3652 3653 u8 reserved_at_800[0x80]; 3654 3655 u8 pas[0][0x40]; 3656 }; 3657 3658 struct mlx5_ifc_query_qp_in_bits { 3659 u8 opcode[0x10]; 3660 u8 reserved_at_10[0x10]; 3661 3662 u8 reserved_at_20[0x10]; 3663 u8 op_mod[0x10]; 3664 3665 u8 reserved_at_40[0x8]; 3666 u8 qpn[0x18]; 3667 3668 u8 reserved_at_60[0x20]; 3669 }; 3670 3671 struct mlx5_ifc_query_q_counter_out_bits { 3672 u8 status[0x8]; 3673 u8 reserved_at_8[0x18]; 3674 3675 u8 syndrome[0x20]; 3676 3677 u8 reserved_at_40[0x40]; 3678 3679 u8 rx_write_requests[0x20]; 3680 3681 u8 reserved_at_a0[0x20]; 3682 3683 u8 rx_read_requests[0x20]; 3684 3685 u8 reserved_at_e0[0x20]; 3686 3687 u8 rx_atomic_requests[0x20]; 3688 3689 u8 reserved_at_120[0x20]; 3690 3691 u8 rx_dct_connect[0x20]; 3692 3693 u8 reserved_at_160[0x20]; 3694 3695 u8 out_of_buffer[0x20]; 3696 3697 u8 reserved_at_1a0[0x20]; 3698 3699 u8 out_of_sequence[0x20]; 3700 3701 u8 reserved_at_1e0[0x20]; 3702 3703 u8 duplicate_request[0x20]; 3704 3705 u8 reserved_at_220[0x20]; 3706 3707 u8 rnr_nak_retry_err[0x20]; 3708 3709 u8 reserved_at_260[0x20]; 3710 3711 u8 packet_seq_err[0x20]; 3712 3713 u8 reserved_at_2a0[0x20]; 3714 3715 u8 implied_nak_seq_err[0x20]; 3716 3717 u8 reserved_at_2e0[0x20]; 3718 3719 u8 local_ack_timeout_err[0x20]; 3720 3721 u8 reserved_at_320[0x4e0]; 3722 }; 3723 3724 struct mlx5_ifc_query_q_counter_in_bits { 3725 u8 opcode[0x10]; 3726 u8 reserved_at_10[0x10]; 3727 3728 u8 reserved_at_20[0x10]; 3729 u8 op_mod[0x10]; 3730 3731 u8 reserved_at_40[0x80]; 3732 3733 u8 clear[0x1]; 3734 u8 reserved_at_c1[0x1f]; 3735 3736 u8 reserved_at_e0[0x18]; 3737 u8 counter_set_id[0x8]; 3738 }; 3739 3740 struct mlx5_ifc_query_pages_out_bits { 3741 u8 status[0x8]; 3742 u8 reserved_at_8[0x18]; 3743 3744 u8 syndrome[0x20]; 3745 3746 u8 reserved_at_40[0x10]; 3747 u8 function_id[0x10]; 3748 3749 u8 num_pages[0x20]; 3750 }; 3751 3752 enum { 3753 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 3754 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 3755 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 3756 }; 3757 3758 struct mlx5_ifc_query_pages_in_bits { 3759 u8 opcode[0x10]; 3760 u8 reserved_at_10[0x10]; 3761 3762 u8 reserved_at_20[0x10]; 3763 u8 op_mod[0x10]; 3764 3765 u8 reserved_at_40[0x10]; 3766 u8 function_id[0x10]; 3767 3768 u8 reserved_at_60[0x20]; 3769 }; 3770 3771 struct mlx5_ifc_query_nic_vport_context_out_bits { 3772 u8 status[0x8]; 3773 u8 reserved_at_8[0x18]; 3774 3775 u8 syndrome[0x20]; 3776 3777 u8 reserved_at_40[0x40]; 3778 3779 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 3780 }; 3781 3782 struct mlx5_ifc_query_nic_vport_context_in_bits { 3783 u8 opcode[0x10]; 3784 u8 reserved_at_10[0x10]; 3785 3786 u8 reserved_at_20[0x10]; 3787 u8 op_mod[0x10]; 3788 3789 u8 other_vport[0x1]; 3790 u8 reserved_at_41[0xf]; 3791 u8 vport_number[0x10]; 3792 3793 u8 reserved_at_60[0x5]; 3794 u8 allowed_list_type[0x3]; 3795 u8 reserved_at_68[0x18]; 3796 }; 3797 3798 struct mlx5_ifc_query_mkey_out_bits { 3799 u8 status[0x8]; 3800 u8 reserved_at_8[0x18]; 3801 3802 u8 syndrome[0x20]; 3803 3804 u8 reserved_at_40[0x40]; 3805 3806 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 3807 3808 u8 reserved_at_280[0x600]; 3809 3810 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 3811 3812 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 3813 }; 3814 3815 struct mlx5_ifc_query_mkey_in_bits { 3816 u8 opcode[0x10]; 3817 u8 reserved_at_10[0x10]; 3818 3819 u8 reserved_at_20[0x10]; 3820 u8 op_mod[0x10]; 3821 3822 u8 reserved_at_40[0x8]; 3823 u8 mkey_index[0x18]; 3824 3825 u8 pg_access[0x1]; 3826 u8 reserved_at_61[0x1f]; 3827 }; 3828 3829 struct mlx5_ifc_query_mad_demux_out_bits { 3830 u8 status[0x8]; 3831 u8 reserved_at_8[0x18]; 3832 3833 u8 syndrome[0x20]; 3834 3835 u8 reserved_at_40[0x40]; 3836 3837 u8 mad_dumux_parameters_block[0x20]; 3838 }; 3839 3840 struct mlx5_ifc_query_mad_demux_in_bits { 3841 u8 opcode[0x10]; 3842 u8 reserved_at_10[0x10]; 3843 3844 u8 reserved_at_20[0x10]; 3845 u8 op_mod[0x10]; 3846 3847 u8 reserved_at_40[0x40]; 3848 }; 3849 3850 struct mlx5_ifc_query_l2_table_entry_out_bits { 3851 u8 status[0x8]; 3852 u8 reserved_at_8[0x18]; 3853 3854 u8 syndrome[0x20]; 3855 3856 u8 reserved_at_40[0xa0]; 3857 3858 u8 reserved_at_e0[0x13]; 3859 u8 vlan_valid[0x1]; 3860 u8 vlan[0xc]; 3861 3862 struct mlx5_ifc_mac_address_layout_bits mac_address; 3863 3864 u8 reserved_at_140[0xc0]; 3865 }; 3866 3867 struct mlx5_ifc_query_l2_table_entry_in_bits { 3868 u8 opcode[0x10]; 3869 u8 reserved_at_10[0x10]; 3870 3871 u8 reserved_at_20[0x10]; 3872 u8 op_mod[0x10]; 3873 3874 u8 reserved_at_40[0x60]; 3875 3876 u8 reserved_at_a0[0x8]; 3877 u8 table_index[0x18]; 3878 3879 u8 reserved_at_c0[0x140]; 3880 }; 3881 3882 struct mlx5_ifc_query_issi_out_bits { 3883 u8 status[0x8]; 3884 u8 reserved_at_8[0x18]; 3885 3886 u8 syndrome[0x20]; 3887 3888 u8 reserved_at_40[0x10]; 3889 u8 current_issi[0x10]; 3890 3891 u8 reserved_at_60[0xa0]; 3892 3893 u8 reserved_at_100[76][0x8]; 3894 u8 supported_issi_dw0[0x20]; 3895 }; 3896 3897 struct mlx5_ifc_query_issi_in_bits { 3898 u8 opcode[0x10]; 3899 u8 reserved_at_10[0x10]; 3900 3901 u8 reserved_at_20[0x10]; 3902 u8 op_mod[0x10]; 3903 3904 u8 reserved_at_40[0x40]; 3905 }; 3906 3907 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 3908 u8 status[0x8]; 3909 u8 reserved_at_8[0x18]; 3910 3911 u8 syndrome[0x20]; 3912 3913 u8 reserved_at_40[0x40]; 3914 3915 struct mlx5_ifc_pkey_bits pkey[0]; 3916 }; 3917 3918 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 3919 u8 opcode[0x10]; 3920 u8 reserved_at_10[0x10]; 3921 3922 u8 reserved_at_20[0x10]; 3923 u8 op_mod[0x10]; 3924 3925 u8 other_vport[0x1]; 3926 u8 reserved_at_41[0xb]; 3927 u8 port_num[0x4]; 3928 u8 vport_number[0x10]; 3929 3930 u8 reserved_at_60[0x10]; 3931 u8 pkey_index[0x10]; 3932 }; 3933 3934 enum { 3935 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 3936 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 3937 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 3938 }; 3939 3940 struct mlx5_ifc_query_hca_vport_gid_out_bits { 3941 u8 status[0x8]; 3942 u8 reserved_at_8[0x18]; 3943 3944 u8 syndrome[0x20]; 3945 3946 u8 reserved_at_40[0x20]; 3947 3948 u8 gids_num[0x10]; 3949 u8 reserved_at_70[0x10]; 3950 3951 struct mlx5_ifc_array128_auto_bits gid[0]; 3952 }; 3953 3954 struct mlx5_ifc_query_hca_vport_gid_in_bits { 3955 u8 opcode[0x10]; 3956 u8 reserved_at_10[0x10]; 3957 3958 u8 reserved_at_20[0x10]; 3959 u8 op_mod[0x10]; 3960 3961 u8 other_vport[0x1]; 3962 u8 reserved_at_41[0xb]; 3963 u8 port_num[0x4]; 3964 u8 vport_number[0x10]; 3965 3966 u8 reserved_at_60[0x10]; 3967 u8 gid_index[0x10]; 3968 }; 3969 3970 struct mlx5_ifc_query_hca_vport_context_out_bits { 3971 u8 status[0x8]; 3972 u8 reserved_at_8[0x18]; 3973 3974 u8 syndrome[0x20]; 3975 3976 u8 reserved_at_40[0x40]; 3977 3978 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 3979 }; 3980 3981 struct mlx5_ifc_query_hca_vport_context_in_bits { 3982 u8 opcode[0x10]; 3983 u8 reserved_at_10[0x10]; 3984 3985 u8 reserved_at_20[0x10]; 3986 u8 op_mod[0x10]; 3987 3988 u8 other_vport[0x1]; 3989 u8 reserved_at_41[0xb]; 3990 u8 port_num[0x4]; 3991 u8 vport_number[0x10]; 3992 3993 u8 reserved_at_60[0x20]; 3994 }; 3995 3996 struct mlx5_ifc_query_hca_cap_out_bits { 3997 u8 status[0x8]; 3998 u8 reserved_at_8[0x18]; 3999 4000 u8 syndrome[0x20]; 4001 4002 u8 reserved_at_40[0x40]; 4003 4004 union mlx5_ifc_hca_cap_union_bits capability; 4005 }; 4006 4007 struct mlx5_ifc_query_hca_cap_in_bits { 4008 u8 opcode[0x10]; 4009 u8 reserved_at_10[0x10]; 4010 4011 u8 reserved_at_20[0x10]; 4012 u8 op_mod[0x10]; 4013 4014 u8 reserved_at_40[0x40]; 4015 }; 4016 4017 struct mlx5_ifc_query_flow_table_out_bits { 4018 u8 status[0x8]; 4019 u8 reserved_at_8[0x18]; 4020 4021 u8 syndrome[0x20]; 4022 4023 u8 reserved_at_40[0x80]; 4024 4025 u8 reserved_at_c0[0x8]; 4026 u8 level[0x8]; 4027 u8 reserved_at_d0[0x8]; 4028 u8 log_size[0x8]; 4029 4030 u8 reserved_at_e0[0x120]; 4031 }; 4032 4033 struct mlx5_ifc_query_flow_table_in_bits { 4034 u8 opcode[0x10]; 4035 u8 reserved_at_10[0x10]; 4036 4037 u8 reserved_at_20[0x10]; 4038 u8 op_mod[0x10]; 4039 4040 u8 reserved_at_40[0x40]; 4041 4042 u8 table_type[0x8]; 4043 u8 reserved_at_88[0x18]; 4044 4045 u8 reserved_at_a0[0x8]; 4046 u8 table_id[0x18]; 4047 4048 u8 reserved_at_c0[0x140]; 4049 }; 4050 4051 struct mlx5_ifc_query_fte_out_bits { 4052 u8 status[0x8]; 4053 u8 reserved_at_8[0x18]; 4054 4055 u8 syndrome[0x20]; 4056 4057 u8 reserved_at_40[0x1c0]; 4058 4059 struct mlx5_ifc_flow_context_bits flow_context; 4060 }; 4061 4062 struct mlx5_ifc_query_fte_in_bits { 4063 u8 opcode[0x10]; 4064 u8 reserved_at_10[0x10]; 4065 4066 u8 reserved_at_20[0x10]; 4067 u8 op_mod[0x10]; 4068 4069 u8 reserved_at_40[0x40]; 4070 4071 u8 table_type[0x8]; 4072 u8 reserved_at_88[0x18]; 4073 4074 u8 reserved_at_a0[0x8]; 4075 u8 table_id[0x18]; 4076 4077 u8 reserved_at_c0[0x40]; 4078 4079 u8 flow_index[0x20]; 4080 4081 u8 reserved_at_120[0xe0]; 4082 }; 4083 4084 enum { 4085 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4086 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4087 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4088 }; 4089 4090 struct mlx5_ifc_query_flow_group_out_bits { 4091 u8 status[0x8]; 4092 u8 reserved_at_8[0x18]; 4093 4094 u8 syndrome[0x20]; 4095 4096 u8 reserved_at_40[0xa0]; 4097 4098 u8 start_flow_index[0x20]; 4099 4100 u8 reserved_at_100[0x20]; 4101 4102 u8 end_flow_index[0x20]; 4103 4104 u8 reserved_at_140[0xa0]; 4105 4106 u8 reserved_at_1e0[0x18]; 4107 u8 match_criteria_enable[0x8]; 4108 4109 struct mlx5_ifc_fte_match_param_bits match_criteria; 4110 4111 u8 reserved_at_1200[0xe00]; 4112 }; 4113 4114 struct mlx5_ifc_query_flow_group_in_bits { 4115 u8 opcode[0x10]; 4116 u8 reserved_at_10[0x10]; 4117 4118 u8 reserved_at_20[0x10]; 4119 u8 op_mod[0x10]; 4120 4121 u8 reserved_at_40[0x40]; 4122 4123 u8 table_type[0x8]; 4124 u8 reserved_at_88[0x18]; 4125 4126 u8 reserved_at_a0[0x8]; 4127 u8 table_id[0x18]; 4128 4129 u8 group_id[0x20]; 4130 4131 u8 reserved_at_e0[0x120]; 4132 }; 4133 4134 struct mlx5_ifc_query_flow_counter_out_bits { 4135 u8 status[0x8]; 4136 u8 reserved_at_8[0x18]; 4137 4138 u8 syndrome[0x20]; 4139 4140 u8 reserved_at_40[0x40]; 4141 4142 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4143 }; 4144 4145 struct mlx5_ifc_query_flow_counter_in_bits { 4146 u8 opcode[0x10]; 4147 u8 reserved_at_10[0x10]; 4148 4149 u8 reserved_at_20[0x10]; 4150 u8 op_mod[0x10]; 4151 4152 u8 reserved_at_40[0x80]; 4153 4154 u8 clear[0x1]; 4155 u8 reserved_at_c1[0xf]; 4156 u8 num_of_counters[0x10]; 4157 4158 u8 reserved_at_e0[0x10]; 4159 u8 flow_counter_id[0x10]; 4160 }; 4161 4162 struct mlx5_ifc_query_esw_vport_context_out_bits { 4163 u8 status[0x8]; 4164 u8 reserved_at_8[0x18]; 4165 4166 u8 syndrome[0x20]; 4167 4168 u8 reserved_at_40[0x40]; 4169 4170 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4171 }; 4172 4173 struct mlx5_ifc_query_esw_vport_context_in_bits { 4174 u8 opcode[0x10]; 4175 u8 reserved_at_10[0x10]; 4176 4177 u8 reserved_at_20[0x10]; 4178 u8 op_mod[0x10]; 4179 4180 u8 other_vport[0x1]; 4181 u8 reserved_at_41[0xf]; 4182 u8 vport_number[0x10]; 4183 4184 u8 reserved_at_60[0x20]; 4185 }; 4186 4187 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4188 u8 status[0x8]; 4189 u8 reserved_at_8[0x18]; 4190 4191 u8 syndrome[0x20]; 4192 4193 u8 reserved_at_40[0x40]; 4194 }; 4195 4196 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4197 u8 reserved_at_0[0x1c]; 4198 u8 vport_cvlan_insert[0x1]; 4199 u8 vport_svlan_insert[0x1]; 4200 u8 vport_cvlan_strip[0x1]; 4201 u8 vport_svlan_strip[0x1]; 4202 }; 4203 4204 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4205 u8 opcode[0x10]; 4206 u8 reserved_at_10[0x10]; 4207 4208 u8 reserved_at_20[0x10]; 4209 u8 op_mod[0x10]; 4210 4211 u8 other_vport[0x1]; 4212 u8 reserved_at_41[0xf]; 4213 u8 vport_number[0x10]; 4214 4215 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4216 4217 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4218 }; 4219 4220 struct mlx5_ifc_query_eq_out_bits { 4221 u8 status[0x8]; 4222 u8 reserved_at_8[0x18]; 4223 4224 u8 syndrome[0x20]; 4225 4226 u8 reserved_at_40[0x40]; 4227 4228 struct mlx5_ifc_eqc_bits eq_context_entry; 4229 4230 u8 reserved_at_280[0x40]; 4231 4232 u8 event_bitmask[0x40]; 4233 4234 u8 reserved_at_300[0x580]; 4235 4236 u8 pas[0][0x40]; 4237 }; 4238 4239 struct mlx5_ifc_query_eq_in_bits { 4240 u8 opcode[0x10]; 4241 u8 reserved_at_10[0x10]; 4242 4243 u8 reserved_at_20[0x10]; 4244 u8 op_mod[0x10]; 4245 4246 u8 reserved_at_40[0x18]; 4247 u8 eq_number[0x8]; 4248 4249 u8 reserved_at_60[0x20]; 4250 }; 4251 4252 struct mlx5_ifc_encap_header_in_bits { 4253 u8 reserved_at_0[0x5]; 4254 u8 header_type[0x3]; 4255 u8 reserved_at_8[0xe]; 4256 u8 encap_header_size[0xa]; 4257 4258 u8 reserved_at_20[0x10]; 4259 u8 encap_header[2][0x8]; 4260 4261 u8 more_encap_header[0][0x8]; 4262 }; 4263 4264 struct mlx5_ifc_query_encap_header_out_bits { 4265 u8 status[0x8]; 4266 u8 reserved_at_8[0x18]; 4267 4268 u8 syndrome[0x20]; 4269 4270 u8 reserved_at_40[0xa0]; 4271 4272 struct mlx5_ifc_encap_header_in_bits encap_header[0]; 4273 }; 4274 4275 struct mlx5_ifc_query_encap_header_in_bits { 4276 u8 opcode[0x10]; 4277 u8 reserved_at_10[0x10]; 4278 4279 u8 reserved_at_20[0x10]; 4280 u8 op_mod[0x10]; 4281 4282 u8 encap_id[0x20]; 4283 4284 u8 reserved_at_60[0xa0]; 4285 }; 4286 4287 struct mlx5_ifc_alloc_encap_header_out_bits { 4288 u8 status[0x8]; 4289 u8 reserved_at_8[0x18]; 4290 4291 u8 syndrome[0x20]; 4292 4293 u8 encap_id[0x20]; 4294 4295 u8 reserved_at_60[0x20]; 4296 }; 4297 4298 struct mlx5_ifc_alloc_encap_header_in_bits { 4299 u8 opcode[0x10]; 4300 u8 reserved_at_10[0x10]; 4301 4302 u8 reserved_at_20[0x10]; 4303 u8 op_mod[0x10]; 4304 4305 u8 reserved_at_40[0xa0]; 4306 4307 struct mlx5_ifc_encap_header_in_bits encap_header; 4308 }; 4309 4310 struct mlx5_ifc_dealloc_encap_header_out_bits { 4311 u8 status[0x8]; 4312 u8 reserved_at_8[0x18]; 4313 4314 u8 syndrome[0x20]; 4315 4316 u8 reserved_at_40[0x40]; 4317 }; 4318 4319 struct mlx5_ifc_dealloc_encap_header_in_bits { 4320 u8 opcode[0x10]; 4321 u8 reserved_at_10[0x10]; 4322 4323 u8 reserved_20[0x10]; 4324 u8 op_mod[0x10]; 4325 4326 u8 encap_id[0x20]; 4327 4328 u8 reserved_60[0x20]; 4329 }; 4330 4331 struct mlx5_ifc_query_dct_out_bits { 4332 u8 status[0x8]; 4333 u8 reserved_at_8[0x18]; 4334 4335 u8 syndrome[0x20]; 4336 4337 u8 reserved_at_40[0x40]; 4338 4339 struct mlx5_ifc_dctc_bits dct_context_entry; 4340 4341 u8 reserved_at_280[0x180]; 4342 }; 4343 4344 struct mlx5_ifc_query_dct_in_bits { 4345 u8 opcode[0x10]; 4346 u8 reserved_at_10[0x10]; 4347 4348 u8 reserved_at_20[0x10]; 4349 u8 op_mod[0x10]; 4350 4351 u8 reserved_at_40[0x8]; 4352 u8 dctn[0x18]; 4353 4354 u8 reserved_at_60[0x20]; 4355 }; 4356 4357 struct mlx5_ifc_query_cq_out_bits { 4358 u8 status[0x8]; 4359 u8 reserved_at_8[0x18]; 4360 4361 u8 syndrome[0x20]; 4362 4363 u8 reserved_at_40[0x40]; 4364 4365 struct mlx5_ifc_cqc_bits cq_context; 4366 4367 u8 reserved_at_280[0x600]; 4368 4369 u8 pas[0][0x40]; 4370 }; 4371 4372 struct mlx5_ifc_query_cq_in_bits { 4373 u8 opcode[0x10]; 4374 u8 reserved_at_10[0x10]; 4375 4376 u8 reserved_at_20[0x10]; 4377 u8 op_mod[0x10]; 4378 4379 u8 reserved_at_40[0x8]; 4380 u8 cqn[0x18]; 4381 4382 u8 reserved_at_60[0x20]; 4383 }; 4384 4385 struct mlx5_ifc_query_cong_status_out_bits { 4386 u8 status[0x8]; 4387 u8 reserved_at_8[0x18]; 4388 4389 u8 syndrome[0x20]; 4390 4391 u8 reserved_at_40[0x20]; 4392 4393 u8 enable[0x1]; 4394 u8 tag_enable[0x1]; 4395 u8 reserved_at_62[0x1e]; 4396 }; 4397 4398 struct mlx5_ifc_query_cong_status_in_bits { 4399 u8 opcode[0x10]; 4400 u8 reserved_at_10[0x10]; 4401 4402 u8 reserved_at_20[0x10]; 4403 u8 op_mod[0x10]; 4404 4405 u8 reserved_at_40[0x18]; 4406 u8 priority[0x4]; 4407 u8 cong_protocol[0x4]; 4408 4409 u8 reserved_at_60[0x20]; 4410 }; 4411 4412 struct mlx5_ifc_query_cong_statistics_out_bits { 4413 u8 status[0x8]; 4414 u8 reserved_at_8[0x18]; 4415 4416 u8 syndrome[0x20]; 4417 4418 u8 reserved_at_40[0x40]; 4419 4420 u8 cur_flows[0x20]; 4421 4422 u8 sum_flows[0x20]; 4423 4424 u8 cnp_ignored_high[0x20]; 4425 4426 u8 cnp_ignored_low[0x20]; 4427 4428 u8 cnp_handled_high[0x20]; 4429 4430 u8 cnp_handled_low[0x20]; 4431 4432 u8 reserved_at_140[0x100]; 4433 4434 u8 time_stamp_high[0x20]; 4435 4436 u8 time_stamp_low[0x20]; 4437 4438 u8 accumulators_period[0x20]; 4439 4440 u8 ecn_marked_roce_packets_high[0x20]; 4441 4442 u8 ecn_marked_roce_packets_low[0x20]; 4443 4444 u8 cnps_sent_high[0x20]; 4445 4446 u8 cnps_sent_low[0x20]; 4447 4448 u8 reserved_at_320[0x560]; 4449 }; 4450 4451 struct mlx5_ifc_query_cong_statistics_in_bits { 4452 u8 opcode[0x10]; 4453 u8 reserved_at_10[0x10]; 4454 4455 u8 reserved_at_20[0x10]; 4456 u8 op_mod[0x10]; 4457 4458 u8 clear[0x1]; 4459 u8 reserved_at_41[0x1f]; 4460 4461 u8 reserved_at_60[0x20]; 4462 }; 4463 4464 struct mlx5_ifc_query_cong_params_out_bits { 4465 u8 status[0x8]; 4466 u8 reserved_at_8[0x18]; 4467 4468 u8 syndrome[0x20]; 4469 4470 u8 reserved_at_40[0x40]; 4471 4472 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4473 }; 4474 4475 struct mlx5_ifc_query_cong_params_in_bits { 4476 u8 opcode[0x10]; 4477 u8 reserved_at_10[0x10]; 4478 4479 u8 reserved_at_20[0x10]; 4480 u8 op_mod[0x10]; 4481 4482 u8 reserved_at_40[0x1c]; 4483 u8 cong_protocol[0x4]; 4484 4485 u8 reserved_at_60[0x20]; 4486 }; 4487 4488 struct mlx5_ifc_query_adapter_out_bits { 4489 u8 status[0x8]; 4490 u8 reserved_at_8[0x18]; 4491 4492 u8 syndrome[0x20]; 4493 4494 u8 reserved_at_40[0x40]; 4495 4496 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 4497 }; 4498 4499 struct mlx5_ifc_query_adapter_in_bits { 4500 u8 opcode[0x10]; 4501 u8 reserved_at_10[0x10]; 4502 4503 u8 reserved_at_20[0x10]; 4504 u8 op_mod[0x10]; 4505 4506 u8 reserved_at_40[0x40]; 4507 }; 4508 4509 struct mlx5_ifc_qp_2rst_out_bits { 4510 u8 status[0x8]; 4511 u8 reserved_at_8[0x18]; 4512 4513 u8 syndrome[0x20]; 4514 4515 u8 reserved_at_40[0x40]; 4516 }; 4517 4518 struct mlx5_ifc_qp_2rst_in_bits { 4519 u8 opcode[0x10]; 4520 u8 reserved_at_10[0x10]; 4521 4522 u8 reserved_at_20[0x10]; 4523 u8 op_mod[0x10]; 4524 4525 u8 reserved_at_40[0x8]; 4526 u8 qpn[0x18]; 4527 4528 u8 reserved_at_60[0x20]; 4529 }; 4530 4531 struct mlx5_ifc_qp_2err_out_bits { 4532 u8 status[0x8]; 4533 u8 reserved_at_8[0x18]; 4534 4535 u8 syndrome[0x20]; 4536 4537 u8 reserved_at_40[0x40]; 4538 }; 4539 4540 struct mlx5_ifc_qp_2err_in_bits { 4541 u8 opcode[0x10]; 4542 u8 reserved_at_10[0x10]; 4543 4544 u8 reserved_at_20[0x10]; 4545 u8 op_mod[0x10]; 4546 4547 u8 reserved_at_40[0x8]; 4548 u8 qpn[0x18]; 4549 4550 u8 reserved_at_60[0x20]; 4551 }; 4552 4553 struct mlx5_ifc_page_fault_resume_out_bits { 4554 u8 status[0x8]; 4555 u8 reserved_at_8[0x18]; 4556 4557 u8 syndrome[0x20]; 4558 4559 u8 reserved_at_40[0x40]; 4560 }; 4561 4562 struct mlx5_ifc_page_fault_resume_in_bits { 4563 u8 opcode[0x10]; 4564 u8 reserved_at_10[0x10]; 4565 4566 u8 reserved_at_20[0x10]; 4567 u8 op_mod[0x10]; 4568 4569 u8 error[0x1]; 4570 u8 reserved_at_41[0x4]; 4571 u8 rdma[0x1]; 4572 u8 read_write[0x1]; 4573 u8 req_res[0x1]; 4574 u8 qpn[0x18]; 4575 4576 u8 reserved_at_60[0x20]; 4577 }; 4578 4579 struct mlx5_ifc_nop_out_bits { 4580 u8 status[0x8]; 4581 u8 reserved_at_8[0x18]; 4582 4583 u8 syndrome[0x20]; 4584 4585 u8 reserved_at_40[0x40]; 4586 }; 4587 4588 struct mlx5_ifc_nop_in_bits { 4589 u8 opcode[0x10]; 4590 u8 reserved_at_10[0x10]; 4591 4592 u8 reserved_at_20[0x10]; 4593 u8 op_mod[0x10]; 4594 4595 u8 reserved_at_40[0x40]; 4596 }; 4597 4598 struct mlx5_ifc_modify_vport_state_out_bits { 4599 u8 status[0x8]; 4600 u8 reserved_at_8[0x18]; 4601 4602 u8 syndrome[0x20]; 4603 4604 u8 reserved_at_40[0x40]; 4605 }; 4606 4607 struct mlx5_ifc_modify_vport_state_in_bits { 4608 u8 opcode[0x10]; 4609 u8 reserved_at_10[0x10]; 4610 4611 u8 reserved_at_20[0x10]; 4612 u8 op_mod[0x10]; 4613 4614 u8 other_vport[0x1]; 4615 u8 reserved_at_41[0xf]; 4616 u8 vport_number[0x10]; 4617 4618 u8 reserved_at_60[0x18]; 4619 u8 admin_state[0x4]; 4620 u8 reserved_at_7c[0x4]; 4621 }; 4622 4623 struct mlx5_ifc_modify_tis_out_bits { 4624 u8 status[0x8]; 4625 u8 reserved_at_8[0x18]; 4626 4627 u8 syndrome[0x20]; 4628 4629 u8 reserved_at_40[0x40]; 4630 }; 4631 4632 struct mlx5_ifc_modify_tis_bitmask_bits { 4633 u8 reserved_at_0[0x20]; 4634 4635 u8 reserved_at_20[0x1d]; 4636 u8 lag_tx_port_affinity[0x1]; 4637 u8 strict_lag_tx_port_affinity[0x1]; 4638 u8 prio[0x1]; 4639 }; 4640 4641 struct mlx5_ifc_modify_tis_in_bits { 4642 u8 opcode[0x10]; 4643 u8 reserved_at_10[0x10]; 4644 4645 u8 reserved_at_20[0x10]; 4646 u8 op_mod[0x10]; 4647 4648 u8 reserved_at_40[0x8]; 4649 u8 tisn[0x18]; 4650 4651 u8 reserved_at_60[0x20]; 4652 4653 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 4654 4655 u8 reserved_at_c0[0x40]; 4656 4657 struct mlx5_ifc_tisc_bits ctx; 4658 }; 4659 4660 struct mlx5_ifc_modify_tir_bitmask_bits { 4661 u8 reserved_at_0[0x20]; 4662 4663 u8 reserved_at_20[0x1b]; 4664 u8 self_lb_en[0x1]; 4665 u8 reserved_at_3c[0x1]; 4666 u8 hash[0x1]; 4667 u8 reserved_at_3e[0x1]; 4668 u8 lro[0x1]; 4669 }; 4670 4671 struct mlx5_ifc_modify_tir_out_bits { 4672 u8 status[0x8]; 4673 u8 reserved_at_8[0x18]; 4674 4675 u8 syndrome[0x20]; 4676 4677 u8 reserved_at_40[0x40]; 4678 }; 4679 4680 struct mlx5_ifc_modify_tir_in_bits { 4681 u8 opcode[0x10]; 4682 u8 reserved_at_10[0x10]; 4683 4684 u8 reserved_at_20[0x10]; 4685 u8 op_mod[0x10]; 4686 4687 u8 reserved_at_40[0x8]; 4688 u8 tirn[0x18]; 4689 4690 u8 reserved_at_60[0x20]; 4691 4692 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 4693 4694 u8 reserved_at_c0[0x40]; 4695 4696 struct mlx5_ifc_tirc_bits ctx; 4697 }; 4698 4699 struct mlx5_ifc_modify_sq_out_bits { 4700 u8 status[0x8]; 4701 u8 reserved_at_8[0x18]; 4702 4703 u8 syndrome[0x20]; 4704 4705 u8 reserved_at_40[0x40]; 4706 }; 4707 4708 struct mlx5_ifc_modify_sq_in_bits { 4709 u8 opcode[0x10]; 4710 u8 reserved_at_10[0x10]; 4711 4712 u8 reserved_at_20[0x10]; 4713 u8 op_mod[0x10]; 4714 4715 u8 sq_state[0x4]; 4716 u8 reserved_at_44[0x4]; 4717 u8 sqn[0x18]; 4718 4719 u8 reserved_at_60[0x20]; 4720 4721 u8 modify_bitmask[0x40]; 4722 4723 u8 reserved_at_c0[0x40]; 4724 4725 struct mlx5_ifc_sqc_bits ctx; 4726 }; 4727 4728 struct mlx5_ifc_modify_rqt_out_bits { 4729 u8 status[0x8]; 4730 u8 reserved_at_8[0x18]; 4731 4732 u8 syndrome[0x20]; 4733 4734 u8 reserved_at_40[0x40]; 4735 }; 4736 4737 struct mlx5_ifc_rqt_bitmask_bits { 4738 u8 reserved_at_0[0x20]; 4739 4740 u8 reserved_at_20[0x1f]; 4741 u8 rqn_list[0x1]; 4742 }; 4743 4744 struct mlx5_ifc_modify_rqt_in_bits { 4745 u8 opcode[0x10]; 4746 u8 reserved_at_10[0x10]; 4747 4748 u8 reserved_at_20[0x10]; 4749 u8 op_mod[0x10]; 4750 4751 u8 reserved_at_40[0x8]; 4752 u8 rqtn[0x18]; 4753 4754 u8 reserved_at_60[0x20]; 4755 4756 struct mlx5_ifc_rqt_bitmask_bits bitmask; 4757 4758 u8 reserved_at_c0[0x40]; 4759 4760 struct mlx5_ifc_rqtc_bits ctx; 4761 }; 4762 4763 struct mlx5_ifc_modify_rq_out_bits { 4764 u8 status[0x8]; 4765 u8 reserved_at_8[0x18]; 4766 4767 u8 syndrome[0x20]; 4768 4769 u8 reserved_at_40[0x40]; 4770 }; 4771 4772 enum { 4773 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 4774 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 4775 }; 4776 4777 struct mlx5_ifc_modify_rq_in_bits { 4778 u8 opcode[0x10]; 4779 u8 reserved_at_10[0x10]; 4780 4781 u8 reserved_at_20[0x10]; 4782 u8 op_mod[0x10]; 4783 4784 u8 rq_state[0x4]; 4785 u8 reserved_at_44[0x4]; 4786 u8 rqn[0x18]; 4787 4788 u8 reserved_at_60[0x20]; 4789 4790 u8 modify_bitmask[0x40]; 4791 4792 u8 reserved_at_c0[0x40]; 4793 4794 struct mlx5_ifc_rqc_bits ctx; 4795 }; 4796 4797 struct mlx5_ifc_modify_rmp_out_bits { 4798 u8 status[0x8]; 4799 u8 reserved_at_8[0x18]; 4800 4801 u8 syndrome[0x20]; 4802 4803 u8 reserved_at_40[0x40]; 4804 }; 4805 4806 struct mlx5_ifc_rmp_bitmask_bits { 4807 u8 reserved_at_0[0x20]; 4808 4809 u8 reserved_at_20[0x1f]; 4810 u8 lwm[0x1]; 4811 }; 4812 4813 struct mlx5_ifc_modify_rmp_in_bits { 4814 u8 opcode[0x10]; 4815 u8 reserved_at_10[0x10]; 4816 4817 u8 reserved_at_20[0x10]; 4818 u8 op_mod[0x10]; 4819 4820 u8 rmp_state[0x4]; 4821 u8 reserved_at_44[0x4]; 4822 u8 rmpn[0x18]; 4823 4824 u8 reserved_at_60[0x20]; 4825 4826 struct mlx5_ifc_rmp_bitmask_bits bitmask; 4827 4828 u8 reserved_at_c0[0x40]; 4829 4830 struct mlx5_ifc_rmpc_bits ctx; 4831 }; 4832 4833 struct mlx5_ifc_modify_nic_vport_context_out_bits { 4834 u8 status[0x8]; 4835 u8 reserved_at_8[0x18]; 4836 4837 u8 syndrome[0x20]; 4838 4839 u8 reserved_at_40[0x40]; 4840 }; 4841 4842 struct mlx5_ifc_modify_nic_vport_field_select_bits { 4843 u8 reserved_at_0[0x16]; 4844 u8 node_guid[0x1]; 4845 u8 port_guid[0x1]; 4846 u8 min_inline[0x1]; 4847 u8 mtu[0x1]; 4848 u8 change_event[0x1]; 4849 u8 promisc[0x1]; 4850 u8 permanent_address[0x1]; 4851 u8 addresses_list[0x1]; 4852 u8 roce_en[0x1]; 4853 u8 reserved_at_1f[0x1]; 4854 }; 4855 4856 struct mlx5_ifc_modify_nic_vport_context_in_bits { 4857 u8 opcode[0x10]; 4858 u8 reserved_at_10[0x10]; 4859 4860 u8 reserved_at_20[0x10]; 4861 u8 op_mod[0x10]; 4862 4863 u8 other_vport[0x1]; 4864 u8 reserved_at_41[0xf]; 4865 u8 vport_number[0x10]; 4866 4867 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 4868 4869 u8 reserved_at_80[0x780]; 4870 4871 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4872 }; 4873 4874 struct mlx5_ifc_modify_hca_vport_context_out_bits { 4875 u8 status[0x8]; 4876 u8 reserved_at_8[0x18]; 4877 4878 u8 syndrome[0x20]; 4879 4880 u8 reserved_at_40[0x40]; 4881 }; 4882 4883 struct mlx5_ifc_modify_hca_vport_context_in_bits { 4884 u8 opcode[0x10]; 4885 u8 reserved_at_10[0x10]; 4886 4887 u8 reserved_at_20[0x10]; 4888 u8 op_mod[0x10]; 4889 4890 u8 other_vport[0x1]; 4891 u8 reserved_at_41[0xb]; 4892 u8 port_num[0x4]; 4893 u8 vport_number[0x10]; 4894 4895 u8 reserved_at_60[0x20]; 4896 4897 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4898 }; 4899 4900 struct mlx5_ifc_modify_cq_out_bits { 4901 u8 status[0x8]; 4902 u8 reserved_at_8[0x18]; 4903 4904 u8 syndrome[0x20]; 4905 4906 u8 reserved_at_40[0x40]; 4907 }; 4908 4909 enum { 4910 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 4911 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 4912 }; 4913 4914 struct mlx5_ifc_modify_cq_in_bits { 4915 u8 opcode[0x10]; 4916 u8 reserved_at_10[0x10]; 4917 4918 u8 reserved_at_20[0x10]; 4919 u8 op_mod[0x10]; 4920 4921 u8 reserved_at_40[0x8]; 4922 u8 cqn[0x18]; 4923 4924 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 4925 4926 struct mlx5_ifc_cqc_bits cq_context; 4927 4928 u8 reserved_at_280[0x600]; 4929 4930 u8 pas[0][0x40]; 4931 }; 4932 4933 struct mlx5_ifc_modify_cong_status_out_bits { 4934 u8 status[0x8]; 4935 u8 reserved_at_8[0x18]; 4936 4937 u8 syndrome[0x20]; 4938 4939 u8 reserved_at_40[0x40]; 4940 }; 4941 4942 struct mlx5_ifc_modify_cong_status_in_bits { 4943 u8 opcode[0x10]; 4944 u8 reserved_at_10[0x10]; 4945 4946 u8 reserved_at_20[0x10]; 4947 u8 op_mod[0x10]; 4948 4949 u8 reserved_at_40[0x18]; 4950 u8 priority[0x4]; 4951 u8 cong_protocol[0x4]; 4952 4953 u8 enable[0x1]; 4954 u8 tag_enable[0x1]; 4955 u8 reserved_at_62[0x1e]; 4956 }; 4957 4958 struct mlx5_ifc_modify_cong_params_out_bits { 4959 u8 status[0x8]; 4960 u8 reserved_at_8[0x18]; 4961 4962 u8 syndrome[0x20]; 4963 4964 u8 reserved_at_40[0x40]; 4965 }; 4966 4967 struct mlx5_ifc_modify_cong_params_in_bits { 4968 u8 opcode[0x10]; 4969 u8 reserved_at_10[0x10]; 4970 4971 u8 reserved_at_20[0x10]; 4972 u8 op_mod[0x10]; 4973 4974 u8 reserved_at_40[0x1c]; 4975 u8 cong_protocol[0x4]; 4976 4977 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 4978 4979 u8 reserved_at_80[0x80]; 4980 4981 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4982 }; 4983 4984 struct mlx5_ifc_manage_pages_out_bits { 4985 u8 status[0x8]; 4986 u8 reserved_at_8[0x18]; 4987 4988 u8 syndrome[0x20]; 4989 4990 u8 output_num_entries[0x20]; 4991 4992 u8 reserved_at_60[0x20]; 4993 4994 u8 pas[0][0x40]; 4995 }; 4996 4997 enum { 4998 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 4999 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5000 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5001 }; 5002 5003 struct mlx5_ifc_manage_pages_in_bits { 5004 u8 opcode[0x10]; 5005 u8 reserved_at_10[0x10]; 5006 5007 u8 reserved_at_20[0x10]; 5008 u8 op_mod[0x10]; 5009 5010 u8 reserved_at_40[0x10]; 5011 u8 function_id[0x10]; 5012 5013 u8 input_num_entries[0x20]; 5014 5015 u8 pas[0][0x40]; 5016 }; 5017 5018 struct mlx5_ifc_mad_ifc_out_bits { 5019 u8 status[0x8]; 5020 u8 reserved_at_8[0x18]; 5021 5022 u8 syndrome[0x20]; 5023 5024 u8 reserved_at_40[0x40]; 5025 5026 u8 response_mad_packet[256][0x8]; 5027 }; 5028 5029 struct mlx5_ifc_mad_ifc_in_bits { 5030 u8 opcode[0x10]; 5031 u8 reserved_at_10[0x10]; 5032 5033 u8 reserved_at_20[0x10]; 5034 u8 op_mod[0x10]; 5035 5036 u8 remote_lid[0x10]; 5037 u8 reserved_at_50[0x8]; 5038 u8 port[0x8]; 5039 5040 u8 reserved_at_60[0x20]; 5041 5042 u8 mad[256][0x8]; 5043 }; 5044 5045 struct mlx5_ifc_init_hca_out_bits { 5046 u8 status[0x8]; 5047 u8 reserved_at_8[0x18]; 5048 5049 u8 syndrome[0x20]; 5050 5051 u8 reserved_at_40[0x40]; 5052 }; 5053 5054 struct mlx5_ifc_init_hca_in_bits { 5055 u8 opcode[0x10]; 5056 u8 reserved_at_10[0x10]; 5057 5058 u8 reserved_at_20[0x10]; 5059 u8 op_mod[0x10]; 5060 5061 u8 reserved_at_40[0x40]; 5062 }; 5063 5064 struct mlx5_ifc_init2rtr_qp_out_bits { 5065 u8 status[0x8]; 5066 u8 reserved_at_8[0x18]; 5067 5068 u8 syndrome[0x20]; 5069 5070 u8 reserved_at_40[0x40]; 5071 }; 5072 5073 struct mlx5_ifc_init2rtr_qp_in_bits { 5074 u8 opcode[0x10]; 5075 u8 reserved_at_10[0x10]; 5076 5077 u8 reserved_at_20[0x10]; 5078 u8 op_mod[0x10]; 5079 5080 u8 reserved_at_40[0x8]; 5081 u8 qpn[0x18]; 5082 5083 u8 reserved_at_60[0x20]; 5084 5085 u8 opt_param_mask[0x20]; 5086 5087 u8 reserved_at_a0[0x20]; 5088 5089 struct mlx5_ifc_qpc_bits qpc; 5090 5091 u8 reserved_at_800[0x80]; 5092 }; 5093 5094 struct mlx5_ifc_init2init_qp_out_bits { 5095 u8 status[0x8]; 5096 u8 reserved_at_8[0x18]; 5097 5098 u8 syndrome[0x20]; 5099 5100 u8 reserved_at_40[0x40]; 5101 }; 5102 5103 struct mlx5_ifc_init2init_qp_in_bits { 5104 u8 opcode[0x10]; 5105 u8 reserved_at_10[0x10]; 5106 5107 u8 reserved_at_20[0x10]; 5108 u8 op_mod[0x10]; 5109 5110 u8 reserved_at_40[0x8]; 5111 u8 qpn[0x18]; 5112 5113 u8 reserved_at_60[0x20]; 5114 5115 u8 opt_param_mask[0x20]; 5116 5117 u8 reserved_at_a0[0x20]; 5118 5119 struct mlx5_ifc_qpc_bits qpc; 5120 5121 u8 reserved_at_800[0x80]; 5122 }; 5123 5124 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5125 u8 status[0x8]; 5126 u8 reserved_at_8[0x18]; 5127 5128 u8 syndrome[0x20]; 5129 5130 u8 reserved_at_40[0x40]; 5131 5132 u8 packet_headers_log[128][0x8]; 5133 5134 u8 packet_syndrome[64][0x8]; 5135 }; 5136 5137 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5138 u8 opcode[0x10]; 5139 u8 reserved_at_10[0x10]; 5140 5141 u8 reserved_at_20[0x10]; 5142 u8 op_mod[0x10]; 5143 5144 u8 reserved_at_40[0x40]; 5145 }; 5146 5147 struct mlx5_ifc_gen_eqe_in_bits { 5148 u8 opcode[0x10]; 5149 u8 reserved_at_10[0x10]; 5150 5151 u8 reserved_at_20[0x10]; 5152 u8 op_mod[0x10]; 5153 5154 u8 reserved_at_40[0x18]; 5155 u8 eq_number[0x8]; 5156 5157 u8 reserved_at_60[0x20]; 5158 5159 u8 eqe[64][0x8]; 5160 }; 5161 5162 struct mlx5_ifc_gen_eq_out_bits { 5163 u8 status[0x8]; 5164 u8 reserved_at_8[0x18]; 5165 5166 u8 syndrome[0x20]; 5167 5168 u8 reserved_at_40[0x40]; 5169 }; 5170 5171 struct mlx5_ifc_enable_hca_out_bits { 5172 u8 status[0x8]; 5173 u8 reserved_at_8[0x18]; 5174 5175 u8 syndrome[0x20]; 5176 5177 u8 reserved_at_40[0x20]; 5178 }; 5179 5180 struct mlx5_ifc_enable_hca_in_bits { 5181 u8 opcode[0x10]; 5182 u8 reserved_at_10[0x10]; 5183 5184 u8 reserved_at_20[0x10]; 5185 u8 op_mod[0x10]; 5186 5187 u8 reserved_at_40[0x10]; 5188 u8 function_id[0x10]; 5189 5190 u8 reserved_at_60[0x20]; 5191 }; 5192 5193 struct mlx5_ifc_drain_dct_out_bits { 5194 u8 status[0x8]; 5195 u8 reserved_at_8[0x18]; 5196 5197 u8 syndrome[0x20]; 5198 5199 u8 reserved_at_40[0x40]; 5200 }; 5201 5202 struct mlx5_ifc_drain_dct_in_bits { 5203 u8 opcode[0x10]; 5204 u8 reserved_at_10[0x10]; 5205 5206 u8 reserved_at_20[0x10]; 5207 u8 op_mod[0x10]; 5208 5209 u8 reserved_at_40[0x8]; 5210 u8 dctn[0x18]; 5211 5212 u8 reserved_at_60[0x20]; 5213 }; 5214 5215 struct mlx5_ifc_disable_hca_out_bits { 5216 u8 status[0x8]; 5217 u8 reserved_at_8[0x18]; 5218 5219 u8 syndrome[0x20]; 5220 5221 u8 reserved_at_40[0x20]; 5222 }; 5223 5224 struct mlx5_ifc_disable_hca_in_bits { 5225 u8 opcode[0x10]; 5226 u8 reserved_at_10[0x10]; 5227 5228 u8 reserved_at_20[0x10]; 5229 u8 op_mod[0x10]; 5230 5231 u8 reserved_at_40[0x10]; 5232 u8 function_id[0x10]; 5233 5234 u8 reserved_at_60[0x20]; 5235 }; 5236 5237 struct mlx5_ifc_detach_from_mcg_out_bits { 5238 u8 status[0x8]; 5239 u8 reserved_at_8[0x18]; 5240 5241 u8 syndrome[0x20]; 5242 5243 u8 reserved_at_40[0x40]; 5244 }; 5245 5246 struct mlx5_ifc_detach_from_mcg_in_bits { 5247 u8 opcode[0x10]; 5248 u8 reserved_at_10[0x10]; 5249 5250 u8 reserved_at_20[0x10]; 5251 u8 op_mod[0x10]; 5252 5253 u8 reserved_at_40[0x8]; 5254 u8 qpn[0x18]; 5255 5256 u8 reserved_at_60[0x20]; 5257 5258 u8 multicast_gid[16][0x8]; 5259 }; 5260 5261 struct mlx5_ifc_destroy_xrq_out_bits { 5262 u8 status[0x8]; 5263 u8 reserved_at_8[0x18]; 5264 5265 u8 syndrome[0x20]; 5266 5267 u8 reserved_at_40[0x40]; 5268 }; 5269 5270 struct mlx5_ifc_destroy_xrq_in_bits { 5271 u8 opcode[0x10]; 5272 u8 reserved_at_10[0x10]; 5273 5274 u8 reserved_at_20[0x10]; 5275 u8 op_mod[0x10]; 5276 5277 u8 reserved_at_40[0x8]; 5278 u8 xrqn[0x18]; 5279 5280 u8 reserved_at_60[0x20]; 5281 }; 5282 5283 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5284 u8 status[0x8]; 5285 u8 reserved_at_8[0x18]; 5286 5287 u8 syndrome[0x20]; 5288 5289 u8 reserved_at_40[0x40]; 5290 }; 5291 5292 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5293 u8 opcode[0x10]; 5294 u8 reserved_at_10[0x10]; 5295 5296 u8 reserved_at_20[0x10]; 5297 u8 op_mod[0x10]; 5298 5299 u8 reserved_at_40[0x8]; 5300 u8 xrc_srqn[0x18]; 5301 5302 u8 reserved_at_60[0x20]; 5303 }; 5304 5305 struct mlx5_ifc_destroy_tis_out_bits { 5306 u8 status[0x8]; 5307 u8 reserved_at_8[0x18]; 5308 5309 u8 syndrome[0x20]; 5310 5311 u8 reserved_at_40[0x40]; 5312 }; 5313 5314 struct mlx5_ifc_destroy_tis_in_bits { 5315 u8 opcode[0x10]; 5316 u8 reserved_at_10[0x10]; 5317 5318 u8 reserved_at_20[0x10]; 5319 u8 op_mod[0x10]; 5320 5321 u8 reserved_at_40[0x8]; 5322 u8 tisn[0x18]; 5323 5324 u8 reserved_at_60[0x20]; 5325 }; 5326 5327 struct mlx5_ifc_destroy_tir_out_bits { 5328 u8 status[0x8]; 5329 u8 reserved_at_8[0x18]; 5330 5331 u8 syndrome[0x20]; 5332 5333 u8 reserved_at_40[0x40]; 5334 }; 5335 5336 struct mlx5_ifc_destroy_tir_in_bits { 5337 u8 opcode[0x10]; 5338 u8 reserved_at_10[0x10]; 5339 5340 u8 reserved_at_20[0x10]; 5341 u8 op_mod[0x10]; 5342 5343 u8 reserved_at_40[0x8]; 5344 u8 tirn[0x18]; 5345 5346 u8 reserved_at_60[0x20]; 5347 }; 5348 5349 struct mlx5_ifc_destroy_srq_out_bits { 5350 u8 status[0x8]; 5351 u8 reserved_at_8[0x18]; 5352 5353 u8 syndrome[0x20]; 5354 5355 u8 reserved_at_40[0x40]; 5356 }; 5357 5358 struct mlx5_ifc_destroy_srq_in_bits { 5359 u8 opcode[0x10]; 5360 u8 reserved_at_10[0x10]; 5361 5362 u8 reserved_at_20[0x10]; 5363 u8 op_mod[0x10]; 5364 5365 u8 reserved_at_40[0x8]; 5366 u8 srqn[0x18]; 5367 5368 u8 reserved_at_60[0x20]; 5369 }; 5370 5371 struct mlx5_ifc_destroy_sq_out_bits { 5372 u8 status[0x8]; 5373 u8 reserved_at_8[0x18]; 5374 5375 u8 syndrome[0x20]; 5376 5377 u8 reserved_at_40[0x40]; 5378 }; 5379 5380 struct mlx5_ifc_destroy_sq_in_bits { 5381 u8 opcode[0x10]; 5382 u8 reserved_at_10[0x10]; 5383 5384 u8 reserved_at_20[0x10]; 5385 u8 op_mod[0x10]; 5386 5387 u8 reserved_at_40[0x8]; 5388 u8 sqn[0x18]; 5389 5390 u8 reserved_at_60[0x20]; 5391 }; 5392 5393 struct mlx5_ifc_destroy_rqt_out_bits { 5394 u8 status[0x8]; 5395 u8 reserved_at_8[0x18]; 5396 5397 u8 syndrome[0x20]; 5398 5399 u8 reserved_at_40[0x40]; 5400 }; 5401 5402 struct mlx5_ifc_destroy_rqt_in_bits { 5403 u8 opcode[0x10]; 5404 u8 reserved_at_10[0x10]; 5405 5406 u8 reserved_at_20[0x10]; 5407 u8 op_mod[0x10]; 5408 5409 u8 reserved_at_40[0x8]; 5410 u8 rqtn[0x18]; 5411 5412 u8 reserved_at_60[0x20]; 5413 }; 5414 5415 struct mlx5_ifc_destroy_rq_out_bits { 5416 u8 status[0x8]; 5417 u8 reserved_at_8[0x18]; 5418 5419 u8 syndrome[0x20]; 5420 5421 u8 reserved_at_40[0x40]; 5422 }; 5423 5424 struct mlx5_ifc_destroy_rq_in_bits { 5425 u8 opcode[0x10]; 5426 u8 reserved_at_10[0x10]; 5427 5428 u8 reserved_at_20[0x10]; 5429 u8 op_mod[0x10]; 5430 5431 u8 reserved_at_40[0x8]; 5432 u8 rqn[0x18]; 5433 5434 u8 reserved_at_60[0x20]; 5435 }; 5436 5437 struct mlx5_ifc_destroy_rmp_out_bits { 5438 u8 status[0x8]; 5439 u8 reserved_at_8[0x18]; 5440 5441 u8 syndrome[0x20]; 5442 5443 u8 reserved_at_40[0x40]; 5444 }; 5445 5446 struct mlx5_ifc_destroy_rmp_in_bits { 5447 u8 opcode[0x10]; 5448 u8 reserved_at_10[0x10]; 5449 5450 u8 reserved_at_20[0x10]; 5451 u8 op_mod[0x10]; 5452 5453 u8 reserved_at_40[0x8]; 5454 u8 rmpn[0x18]; 5455 5456 u8 reserved_at_60[0x20]; 5457 }; 5458 5459 struct mlx5_ifc_destroy_qp_out_bits { 5460 u8 status[0x8]; 5461 u8 reserved_at_8[0x18]; 5462 5463 u8 syndrome[0x20]; 5464 5465 u8 reserved_at_40[0x40]; 5466 }; 5467 5468 struct mlx5_ifc_destroy_qp_in_bits { 5469 u8 opcode[0x10]; 5470 u8 reserved_at_10[0x10]; 5471 5472 u8 reserved_at_20[0x10]; 5473 u8 op_mod[0x10]; 5474 5475 u8 reserved_at_40[0x8]; 5476 u8 qpn[0x18]; 5477 5478 u8 reserved_at_60[0x20]; 5479 }; 5480 5481 struct mlx5_ifc_destroy_psv_out_bits { 5482 u8 status[0x8]; 5483 u8 reserved_at_8[0x18]; 5484 5485 u8 syndrome[0x20]; 5486 5487 u8 reserved_at_40[0x40]; 5488 }; 5489 5490 struct mlx5_ifc_destroy_psv_in_bits { 5491 u8 opcode[0x10]; 5492 u8 reserved_at_10[0x10]; 5493 5494 u8 reserved_at_20[0x10]; 5495 u8 op_mod[0x10]; 5496 5497 u8 reserved_at_40[0x8]; 5498 u8 psvn[0x18]; 5499 5500 u8 reserved_at_60[0x20]; 5501 }; 5502 5503 struct mlx5_ifc_destroy_mkey_out_bits { 5504 u8 status[0x8]; 5505 u8 reserved_at_8[0x18]; 5506 5507 u8 syndrome[0x20]; 5508 5509 u8 reserved_at_40[0x40]; 5510 }; 5511 5512 struct mlx5_ifc_destroy_mkey_in_bits { 5513 u8 opcode[0x10]; 5514 u8 reserved_at_10[0x10]; 5515 5516 u8 reserved_at_20[0x10]; 5517 u8 op_mod[0x10]; 5518 5519 u8 reserved_at_40[0x8]; 5520 u8 mkey_index[0x18]; 5521 5522 u8 reserved_at_60[0x20]; 5523 }; 5524 5525 struct mlx5_ifc_destroy_flow_table_out_bits { 5526 u8 status[0x8]; 5527 u8 reserved_at_8[0x18]; 5528 5529 u8 syndrome[0x20]; 5530 5531 u8 reserved_at_40[0x40]; 5532 }; 5533 5534 struct mlx5_ifc_destroy_flow_table_in_bits { 5535 u8 opcode[0x10]; 5536 u8 reserved_at_10[0x10]; 5537 5538 u8 reserved_at_20[0x10]; 5539 u8 op_mod[0x10]; 5540 5541 u8 other_vport[0x1]; 5542 u8 reserved_at_41[0xf]; 5543 u8 vport_number[0x10]; 5544 5545 u8 reserved_at_60[0x20]; 5546 5547 u8 table_type[0x8]; 5548 u8 reserved_at_88[0x18]; 5549 5550 u8 reserved_at_a0[0x8]; 5551 u8 table_id[0x18]; 5552 5553 u8 reserved_at_c0[0x140]; 5554 }; 5555 5556 struct mlx5_ifc_destroy_flow_group_out_bits { 5557 u8 status[0x8]; 5558 u8 reserved_at_8[0x18]; 5559 5560 u8 syndrome[0x20]; 5561 5562 u8 reserved_at_40[0x40]; 5563 }; 5564 5565 struct mlx5_ifc_destroy_flow_group_in_bits { 5566 u8 opcode[0x10]; 5567 u8 reserved_at_10[0x10]; 5568 5569 u8 reserved_at_20[0x10]; 5570 u8 op_mod[0x10]; 5571 5572 u8 other_vport[0x1]; 5573 u8 reserved_at_41[0xf]; 5574 u8 vport_number[0x10]; 5575 5576 u8 reserved_at_60[0x20]; 5577 5578 u8 table_type[0x8]; 5579 u8 reserved_at_88[0x18]; 5580 5581 u8 reserved_at_a0[0x8]; 5582 u8 table_id[0x18]; 5583 5584 u8 group_id[0x20]; 5585 5586 u8 reserved_at_e0[0x120]; 5587 }; 5588 5589 struct mlx5_ifc_destroy_eq_out_bits { 5590 u8 status[0x8]; 5591 u8 reserved_at_8[0x18]; 5592 5593 u8 syndrome[0x20]; 5594 5595 u8 reserved_at_40[0x40]; 5596 }; 5597 5598 struct mlx5_ifc_destroy_eq_in_bits { 5599 u8 opcode[0x10]; 5600 u8 reserved_at_10[0x10]; 5601 5602 u8 reserved_at_20[0x10]; 5603 u8 op_mod[0x10]; 5604 5605 u8 reserved_at_40[0x18]; 5606 u8 eq_number[0x8]; 5607 5608 u8 reserved_at_60[0x20]; 5609 }; 5610 5611 struct mlx5_ifc_destroy_dct_out_bits { 5612 u8 status[0x8]; 5613 u8 reserved_at_8[0x18]; 5614 5615 u8 syndrome[0x20]; 5616 5617 u8 reserved_at_40[0x40]; 5618 }; 5619 5620 struct mlx5_ifc_destroy_dct_in_bits { 5621 u8 opcode[0x10]; 5622 u8 reserved_at_10[0x10]; 5623 5624 u8 reserved_at_20[0x10]; 5625 u8 op_mod[0x10]; 5626 5627 u8 reserved_at_40[0x8]; 5628 u8 dctn[0x18]; 5629 5630 u8 reserved_at_60[0x20]; 5631 }; 5632 5633 struct mlx5_ifc_destroy_cq_out_bits { 5634 u8 status[0x8]; 5635 u8 reserved_at_8[0x18]; 5636 5637 u8 syndrome[0x20]; 5638 5639 u8 reserved_at_40[0x40]; 5640 }; 5641 5642 struct mlx5_ifc_destroy_cq_in_bits { 5643 u8 opcode[0x10]; 5644 u8 reserved_at_10[0x10]; 5645 5646 u8 reserved_at_20[0x10]; 5647 u8 op_mod[0x10]; 5648 5649 u8 reserved_at_40[0x8]; 5650 u8 cqn[0x18]; 5651 5652 u8 reserved_at_60[0x20]; 5653 }; 5654 5655 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 5656 u8 status[0x8]; 5657 u8 reserved_at_8[0x18]; 5658 5659 u8 syndrome[0x20]; 5660 5661 u8 reserved_at_40[0x40]; 5662 }; 5663 5664 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 5665 u8 opcode[0x10]; 5666 u8 reserved_at_10[0x10]; 5667 5668 u8 reserved_at_20[0x10]; 5669 u8 op_mod[0x10]; 5670 5671 u8 reserved_at_40[0x20]; 5672 5673 u8 reserved_at_60[0x10]; 5674 u8 vxlan_udp_port[0x10]; 5675 }; 5676 5677 struct mlx5_ifc_delete_l2_table_entry_out_bits { 5678 u8 status[0x8]; 5679 u8 reserved_at_8[0x18]; 5680 5681 u8 syndrome[0x20]; 5682 5683 u8 reserved_at_40[0x40]; 5684 }; 5685 5686 struct mlx5_ifc_delete_l2_table_entry_in_bits { 5687 u8 opcode[0x10]; 5688 u8 reserved_at_10[0x10]; 5689 5690 u8 reserved_at_20[0x10]; 5691 u8 op_mod[0x10]; 5692 5693 u8 reserved_at_40[0x60]; 5694 5695 u8 reserved_at_a0[0x8]; 5696 u8 table_index[0x18]; 5697 5698 u8 reserved_at_c0[0x140]; 5699 }; 5700 5701 struct mlx5_ifc_delete_fte_out_bits { 5702 u8 status[0x8]; 5703 u8 reserved_at_8[0x18]; 5704 5705 u8 syndrome[0x20]; 5706 5707 u8 reserved_at_40[0x40]; 5708 }; 5709 5710 struct mlx5_ifc_delete_fte_in_bits { 5711 u8 opcode[0x10]; 5712 u8 reserved_at_10[0x10]; 5713 5714 u8 reserved_at_20[0x10]; 5715 u8 op_mod[0x10]; 5716 5717 u8 other_vport[0x1]; 5718 u8 reserved_at_41[0xf]; 5719 u8 vport_number[0x10]; 5720 5721 u8 reserved_at_60[0x20]; 5722 5723 u8 table_type[0x8]; 5724 u8 reserved_at_88[0x18]; 5725 5726 u8 reserved_at_a0[0x8]; 5727 u8 table_id[0x18]; 5728 5729 u8 reserved_at_c0[0x40]; 5730 5731 u8 flow_index[0x20]; 5732 5733 u8 reserved_at_120[0xe0]; 5734 }; 5735 5736 struct mlx5_ifc_dealloc_xrcd_out_bits { 5737 u8 status[0x8]; 5738 u8 reserved_at_8[0x18]; 5739 5740 u8 syndrome[0x20]; 5741 5742 u8 reserved_at_40[0x40]; 5743 }; 5744 5745 struct mlx5_ifc_dealloc_xrcd_in_bits { 5746 u8 opcode[0x10]; 5747 u8 reserved_at_10[0x10]; 5748 5749 u8 reserved_at_20[0x10]; 5750 u8 op_mod[0x10]; 5751 5752 u8 reserved_at_40[0x8]; 5753 u8 xrcd[0x18]; 5754 5755 u8 reserved_at_60[0x20]; 5756 }; 5757 5758 struct mlx5_ifc_dealloc_uar_out_bits { 5759 u8 status[0x8]; 5760 u8 reserved_at_8[0x18]; 5761 5762 u8 syndrome[0x20]; 5763 5764 u8 reserved_at_40[0x40]; 5765 }; 5766 5767 struct mlx5_ifc_dealloc_uar_in_bits { 5768 u8 opcode[0x10]; 5769 u8 reserved_at_10[0x10]; 5770 5771 u8 reserved_at_20[0x10]; 5772 u8 op_mod[0x10]; 5773 5774 u8 reserved_at_40[0x8]; 5775 u8 uar[0x18]; 5776 5777 u8 reserved_at_60[0x20]; 5778 }; 5779 5780 struct mlx5_ifc_dealloc_transport_domain_out_bits { 5781 u8 status[0x8]; 5782 u8 reserved_at_8[0x18]; 5783 5784 u8 syndrome[0x20]; 5785 5786 u8 reserved_at_40[0x40]; 5787 }; 5788 5789 struct mlx5_ifc_dealloc_transport_domain_in_bits { 5790 u8 opcode[0x10]; 5791 u8 reserved_at_10[0x10]; 5792 5793 u8 reserved_at_20[0x10]; 5794 u8 op_mod[0x10]; 5795 5796 u8 reserved_at_40[0x8]; 5797 u8 transport_domain[0x18]; 5798 5799 u8 reserved_at_60[0x20]; 5800 }; 5801 5802 struct mlx5_ifc_dealloc_q_counter_out_bits { 5803 u8 status[0x8]; 5804 u8 reserved_at_8[0x18]; 5805 5806 u8 syndrome[0x20]; 5807 5808 u8 reserved_at_40[0x40]; 5809 }; 5810 5811 struct mlx5_ifc_dealloc_q_counter_in_bits { 5812 u8 opcode[0x10]; 5813 u8 reserved_at_10[0x10]; 5814 5815 u8 reserved_at_20[0x10]; 5816 u8 op_mod[0x10]; 5817 5818 u8 reserved_at_40[0x18]; 5819 u8 counter_set_id[0x8]; 5820 5821 u8 reserved_at_60[0x20]; 5822 }; 5823 5824 struct mlx5_ifc_dealloc_pd_out_bits { 5825 u8 status[0x8]; 5826 u8 reserved_at_8[0x18]; 5827 5828 u8 syndrome[0x20]; 5829 5830 u8 reserved_at_40[0x40]; 5831 }; 5832 5833 struct mlx5_ifc_dealloc_pd_in_bits { 5834 u8 opcode[0x10]; 5835 u8 reserved_at_10[0x10]; 5836 5837 u8 reserved_at_20[0x10]; 5838 u8 op_mod[0x10]; 5839 5840 u8 reserved_at_40[0x8]; 5841 u8 pd[0x18]; 5842 5843 u8 reserved_at_60[0x20]; 5844 }; 5845 5846 struct mlx5_ifc_dealloc_flow_counter_out_bits { 5847 u8 status[0x8]; 5848 u8 reserved_at_8[0x18]; 5849 5850 u8 syndrome[0x20]; 5851 5852 u8 reserved_at_40[0x40]; 5853 }; 5854 5855 struct mlx5_ifc_dealloc_flow_counter_in_bits { 5856 u8 opcode[0x10]; 5857 u8 reserved_at_10[0x10]; 5858 5859 u8 reserved_at_20[0x10]; 5860 u8 op_mod[0x10]; 5861 5862 u8 reserved_at_40[0x10]; 5863 u8 flow_counter_id[0x10]; 5864 5865 u8 reserved_at_60[0x20]; 5866 }; 5867 5868 struct mlx5_ifc_create_xrq_out_bits { 5869 u8 status[0x8]; 5870 u8 reserved_at_8[0x18]; 5871 5872 u8 syndrome[0x20]; 5873 5874 u8 reserved_at_40[0x8]; 5875 u8 xrqn[0x18]; 5876 5877 u8 reserved_at_60[0x20]; 5878 }; 5879 5880 struct mlx5_ifc_create_xrq_in_bits { 5881 u8 opcode[0x10]; 5882 u8 reserved_at_10[0x10]; 5883 5884 u8 reserved_at_20[0x10]; 5885 u8 op_mod[0x10]; 5886 5887 u8 reserved_at_40[0x40]; 5888 5889 struct mlx5_ifc_xrqc_bits xrq_context; 5890 }; 5891 5892 struct mlx5_ifc_create_xrc_srq_out_bits { 5893 u8 status[0x8]; 5894 u8 reserved_at_8[0x18]; 5895 5896 u8 syndrome[0x20]; 5897 5898 u8 reserved_at_40[0x8]; 5899 u8 xrc_srqn[0x18]; 5900 5901 u8 reserved_at_60[0x20]; 5902 }; 5903 5904 struct mlx5_ifc_create_xrc_srq_in_bits { 5905 u8 opcode[0x10]; 5906 u8 reserved_at_10[0x10]; 5907 5908 u8 reserved_at_20[0x10]; 5909 u8 op_mod[0x10]; 5910 5911 u8 reserved_at_40[0x40]; 5912 5913 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5914 5915 u8 reserved_at_280[0x600]; 5916 5917 u8 pas[0][0x40]; 5918 }; 5919 5920 struct mlx5_ifc_create_tis_out_bits { 5921 u8 status[0x8]; 5922 u8 reserved_at_8[0x18]; 5923 5924 u8 syndrome[0x20]; 5925 5926 u8 reserved_at_40[0x8]; 5927 u8 tisn[0x18]; 5928 5929 u8 reserved_at_60[0x20]; 5930 }; 5931 5932 struct mlx5_ifc_create_tis_in_bits { 5933 u8 opcode[0x10]; 5934 u8 reserved_at_10[0x10]; 5935 5936 u8 reserved_at_20[0x10]; 5937 u8 op_mod[0x10]; 5938 5939 u8 reserved_at_40[0xc0]; 5940 5941 struct mlx5_ifc_tisc_bits ctx; 5942 }; 5943 5944 struct mlx5_ifc_create_tir_out_bits { 5945 u8 status[0x8]; 5946 u8 reserved_at_8[0x18]; 5947 5948 u8 syndrome[0x20]; 5949 5950 u8 reserved_at_40[0x8]; 5951 u8 tirn[0x18]; 5952 5953 u8 reserved_at_60[0x20]; 5954 }; 5955 5956 struct mlx5_ifc_create_tir_in_bits { 5957 u8 opcode[0x10]; 5958 u8 reserved_at_10[0x10]; 5959 5960 u8 reserved_at_20[0x10]; 5961 u8 op_mod[0x10]; 5962 5963 u8 reserved_at_40[0xc0]; 5964 5965 struct mlx5_ifc_tirc_bits ctx; 5966 }; 5967 5968 struct mlx5_ifc_create_srq_out_bits { 5969 u8 status[0x8]; 5970 u8 reserved_at_8[0x18]; 5971 5972 u8 syndrome[0x20]; 5973 5974 u8 reserved_at_40[0x8]; 5975 u8 srqn[0x18]; 5976 5977 u8 reserved_at_60[0x20]; 5978 }; 5979 5980 struct mlx5_ifc_create_srq_in_bits { 5981 u8 opcode[0x10]; 5982 u8 reserved_at_10[0x10]; 5983 5984 u8 reserved_at_20[0x10]; 5985 u8 op_mod[0x10]; 5986 5987 u8 reserved_at_40[0x40]; 5988 5989 struct mlx5_ifc_srqc_bits srq_context_entry; 5990 5991 u8 reserved_at_280[0x600]; 5992 5993 u8 pas[0][0x40]; 5994 }; 5995 5996 struct mlx5_ifc_create_sq_out_bits { 5997 u8 status[0x8]; 5998 u8 reserved_at_8[0x18]; 5999 6000 u8 syndrome[0x20]; 6001 6002 u8 reserved_at_40[0x8]; 6003 u8 sqn[0x18]; 6004 6005 u8 reserved_at_60[0x20]; 6006 }; 6007 6008 struct mlx5_ifc_create_sq_in_bits { 6009 u8 opcode[0x10]; 6010 u8 reserved_at_10[0x10]; 6011 6012 u8 reserved_at_20[0x10]; 6013 u8 op_mod[0x10]; 6014 6015 u8 reserved_at_40[0xc0]; 6016 6017 struct mlx5_ifc_sqc_bits ctx; 6018 }; 6019 6020 struct mlx5_ifc_create_rqt_out_bits { 6021 u8 status[0x8]; 6022 u8 reserved_at_8[0x18]; 6023 6024 u8 syndrome[0x20]; 6025 6026 u8 reserved_at_40[0x8]; 6027 u8 rqtn[0x18]; 6028 6029 u8 reserved_at_60[0x20]; 6030 }; 6031 6032 struct mlx5_ifc_create_rqt_in_bits { 6033 u8 opcode[0x10]; 6034 u8 reserved_at_10[0x10]; 6035 6036 u8 reserved_at_20[0x10]; 6037 u8 op_mod[0x10]; 6038 6039 u8 reserved_at_40[0xc0]; 6040 6041 struct mlx5_ifc_rqtc_bits rqt_context; 6042 }; 6043 6044 struct mlx5_ifc_create_rq_out_bits { 6045 u8 status[0x8]; 6046 u8 reserved_at_8[0x18]; 6047 6048 u8 syndrome[0x20]; 6049 6050 u8 reserved_at_40[0x8]; 6051 u8 rqn[0x18]; 6052 6053 u8 reserved_at_60[0x20]; 6054 }; 6055 6056 struct mlx5_ifc_create_rq_in_bits { 6057 u8 opcode[0x10]; 6058 u8 reserved_at_10[0x10]; 6059 6060 u8 reserved_at_20[0x10]; 6061 u8 op_mod[0x10]; 6062 6063 u8 reserved_at_40[0xc0]; 6064 6065 struct mlx5_ifc_rqc_bits ctx; 6066 }; 6067 6068 struct mlx5_ifc_create_rmp_out_bits { 6069 u8 status[0x8]; 6070 u8 reserved_at_8[0x18]; 6071 6072 u8 syndrome[0x20]; 6073 6074 u8 reserved_at_40[0x8]; 6075 u8 rmpn[0x18]; 6076 6077 u8 reserved_at_60[0x20]; 6078 }; 6079 6080 struct mlx5_ifc_create_rmp_in_bits { 6081 u8 opcode[0x10]; 6082 u8 reserved_at_10[0x10]; 6083 6084 u8 reserved_at_20[0x10]; 6085 u8 op_mod[0x10]; 6086 6087 u8 reserved_at_40[0xc0]; 6088 6089 struct mlx5_ifc_rmpc_bits ctx; 6090 }; 6091 6092 struct mlx5_ifc_create_qp_out_bits { 6093 u8 status[0x8]; 6094 u8 reserved_at_8[0x18]; 6095 6096 u8 syndrome[0x20]; 6097 6098 u8 reserved_at_40[0x8]; 6099 u8 qpn[0x18]; 6100 6101 u8 reserved_at_60[0x20]; 6102 }; 6103 6104 struct mlx5_ifc_create_qp_in_bits { 6105 u8 opcode[0x10]; 6106 u8 reserved_at_10[0x10]; 6107 6108 u8 reserved_at_20[0x10]; 6109 u8 op_mod[0x10]; 6110 6111 u8 reserved_at_40[0x40]; 6112 6113 u8 opt_param_mask[0x20]; 6114 6115 u8 reserved_at_a0[0x20]; 6116 6117 struct mlx5_ifc_qpc_bits qpc; 6118 6119 u8 reserved_at_800[0x80]; 6120 6121 u8 pas[0][0x40]; 6122 }; 6123 6124 struct mlx5_ifc_create_psv_out_bits { 6125 u8 status[0x8]; 6126 u8 reserved_at_8[0x18]; 6127 6128 u8 syndrome[0x20]; 6129 6130 u8 reserved_at_40[0x40]; 6131 6132 u8 reserved_at_80[0x8]; 6133 u8 psv0_index[0x18]; 6134 6135 u8 reserved_at_a0[0x8]; 6136 u8 psv1_index[0x18]; 6137 6138 u8 reserved_at_c0[0x8]; 6139 u8 psv2_index[0x18]; 6140 6141 u8 reserved_at_e0[0x8]; 6142 u8 psv3_index[0x18]; 6143 }; 6144 6145 struct mlx5_ifc_create_psv_in_bits { 6146 u8 opcode[0x10]; 6147 u8 reserved_at_10[0x10]; 6148 6149 u8 reserved_at_20[0x10]; 6150 u8 op_mod[0x10]; 6151 6152 u8 num_psv[0x4]; 6153 u8 reserved_at_44[0x4]; 6154 u8 pd[0x18]; 6155 6156 u8 reserved_at_60[0x20]; 6157 }; 6158 6159 struct mlx5_ifc_create_mkey_out_bits { 6160 u8 status[0x8]; 6161 u8 reserved_at_8[0x18]; 6162 6163 u8 syndrome[0x20]; 6164 6165 u8 reserved_at_40[0x8]; 6166 u8 mkey_index[0x18]; 6167 6168 u8 reserved_at_60[0x20]; 6169 }; 6170 6171 struct mlx5_ifc_create_mkey_in_bits { 6172 u8 opcode[0x10]; 6173 u8 reserved_at_10[0x10]; 6174 6175 u8 reserved_at_20[0x10]; 6176 u8 op_mod[0x10]; 6177 6178 u8 reserved_at_40[0x20]; 6179 6180 u8 pg_access[0x1]; 6181 u8 reserved_at_61[0x1f]; 6182 6183 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6184 6185 u8 reserved_at_280[0x80]; 6186 6187 u8 translations_octword_actual_size[0x20]; 6188 6189 u8 reserved_at_320[0x560]; 6190 6191 u8 klm_pas_mtt[0][0x20]; 6192 }; 6193 6194 struct mlx5_ifc_create_flow_table_out_bits { 6195 u8 status[0x8]; 6196 u8 reserved_at_8[0x18]; 6197 6198 u8 syndrome[0x20]; 6199 6200 u8 reserved_at_40[0x8]; 6201 u8 table_id[0x18]; 6202 6203 u8 reserved_at_60[0x20]; 6204 }; 6205 6206 struct mlx5_ifc_create_flow_table_in_bits { 6207 u8 opcode[0x10]; 6208 u8 reserved_at_10[0x10]; 6209 6210 u8 reserved_at_20[0x10]; 6211 u8 op_mod[0x10]; 6212 6213 u8 other_vport[0x1]; 6214 u8 reserved_at_41[0xf]; 6215 u8 vport_number[0x10]; 6216 6217 u8 reserved_at_60[0x20]; 6218 6219 u8 table_type[0x8]; 6220 u8 reserved_at_88[0x18]; 6221 6222 u8 reserved_at_a0[0x20]; 6223 6224 u8 encap_en[0x1]; 6225 u8 decap_en[0x1]; 6226 u8 reserved_at_c2[0x2]; 6227 u8 table_miss_mode[0x4]; 6228 u8 level[0x8]; 6229 u8 reserved_at_d0[0x8]; 6230 u8 log_size[0x8]; 6231 6232 u8 reserved_at_e0[0x8]; 6233 u8 table_miss_id[0x18]; 6234 6235 u8 reserved_at_100[0x8]; 6236 u8 lag_master_next_table_id[0x18]; 6237 6238 u8 reserved_at_120[0x80]; 6239 }; 6240 6241 struct mlx5_ifc_create_flow_group_out_bits { 6242 u8 status[0x8]; 6243 u8 reserved_at_8[0x18]; 6244 6245 u8 syndrome[0x20]; 6246 6247 u8 reserved_at_40[0x8]; 6248 u8 group_id[0x18]; 6249 6250 u8 reserved_at_60[0x20]; 6251 }; 6252 6253 enum { 6254 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6255 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6256 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6257 }; 6258 6259 struct mlx5_ifc_create_flow_group_in_bits { 6260 u8 opcode[0x10]; 6261 u8 reserved_at_10[0x10]; 6262 6263 u8 reserved_at_20[0x10]; 6264 u8 op_mod[0x10]; 6265 6266 u8 other_vport[0x1]; 6267 u8 reserved_at_41[0xf]; 6268 u8 vport_number[0x10]; 6269 6270 u8 reserved_at_60[0x20]; 6271 6272 u8 table_type[0x8]; 6273 u8 reserved_at_88[0x18]; 6274 6275 u8 reserved_at_a0[0x8]; 6276 u8 table_id[0x18]; 6277 6278 u8 reserved_at_c0[0x20]; 6279 6280 u8 start_flow_index[0x20]; 6281 6282 u8 reserved_at_100[0x20]; 6283 6284 u8 end_flow_index[0x20]; 6285 6286 u8 reserved_at_140[0xa0]; 6287 6288 u8 reserved_at_1e0[0x18]; 6289 u8 match_criteria_enable[0x8]; 6290 6291 struct mlx5_ifc_fte_match_param_bits match_criteria; 6292 6293 u8 reserved_at_1200[0xe00]; 6294 }; 6295 6296 struct mlx5_ifc_create_eq_out_bits { 6297 u8 status[0x8]; 6298 u8 reserved_at_8[0x18]; 6299 6300 u8 syndrome[0x20]; 6301 6302 u8 reserved_at_40[0x18]; 6303 u8 eq_number[0x8]; 6304 6305 u8 reserved_at_60[0x20]; 6306 }; 6307 6308 struct mlx5_ifc_create_eq_in_bits { 6309 u8 opcode[0x10]; 6310 u8 reserved_at_10[0x10]; 6311 6312 u8 reserved_at_20[0x10]; 6313 u8 op_mod[0x10]; 6314 6315 u8 reserved_at_40[0x40]; 6316 6317 struct mlx5_ifc_eqc_bits eq_context_entry; 6318 6319 u8 reserved_at_280[0x40]; 6320 6321 u8 event_bitmask[0x40]; 6322 6323 u8 reserved_at_300[0x580]; 6324 6325 u8 pas[0][0x40]; 6326 }; 6327 6328 struct mlx5_ifc_create_dct_out_bits { 6329 u8 status[0x8]; 6330 u8 reserved_at_8[0x18]; 6331 6332 u8 syndrome[0x20]; 6333 6334 u8 reserved_at_40[0x8]; 6335 u8 dctn[0x18]; 6336 6337 u8 reserved_at_60[0x20]; 6338 }; 6339 6340 struct mlx5_ifc_create_dct_in_bits { 6341 u8 opcode[0x10]; 6342 u8 reserved_at_10[0x10]; 6343 6344 u8 reserved_at_20[0x10]; 6345 u8 op_mod[0x10]; 6346 6347 u8 reserved_at_40[0x40]; 6348 6349 struct mlx5_ifc_dctc_bits dct_context_entry; 6350 6351 u8 reserved_at_280[0x180]; 6352 }; 6353 6354 struct mlx5_ifc_create_cq_out_bits { 6355 u8 status[0x8]; 6356 u8 reserved_at_8[0x18]; 6357 6358 u8 syndrome[0x20]; 6359 6360 u8 reserved_at_40[0x8]; 6361 u8 cqn[0x18]; 6362 6363 u8 reserved_at_60[0x20]; 6364 }; 6365 6366 struct mlx5_ifc_create_cq_in_bits { 6367 u8 opcode[0x10]; 6368 u8 reserved_at_10[0x10]; 6369 6370 u8 reserved_at_20[0x10]; 6371 u8 op_mod[0x10]; 6372 6373 u8 reserved_at_40[0x40]; 6374 6375 struct mlx5_ifc_cqc_bits cq_context; 6376 6377 u8 reserved_at_280[0x600]; 6378 6379 u8 pas[0][0x40]; 6380 }; 6381 6382 struct mlx5_ifc_config_int_moderation_out_bits { 6383 u8 status[0x8]; 6384 u8 reserved_at_8[0x18]; 6385 6386 u8 syndrome[0x20]; 6387 6388 u8 reserved_at_40[0x4]; 6389 u8 min_delay[0xc]; 6390 u8 int_vector[0x10]; 6391 6392 u8 reserved_at_60[0x20]; 6393 }; 6394 6395 enum { 6396 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 6397 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 6398 }; 6399 6400 struct mlx5_ifc_config_int_moderation_in_bits { 6401 u8 opcode[0x10]; 6402 u8 reserved_at_10[0x10]; 6403 6404 u8 reserved_at_20[0x10]; 6405 u8 op_mod[0x10]; 6406 6407 u8 reserved_at_40[0x4]; 6408 u8 min_delay[0xc]; 6409 u8 int_vector[0x10]; 6410 6411 u8 reserved_at_60[0x20]; 6412 }; 6413 6414 struct mlx5_ifc_attach_to_mcg_out_bits { 6415 u8 status[0x8]; 6416 u8 reserved_at_8[0x18]; 6417 6418 u8 syndrome[0x20]; 6419 6420 u8 reserved_at_40[0x40]; 6421 }; 6422 6423 struct mlx5_ifc_attach_to_mcg_in_bits { 6424 u8 opcode[0x10]; 6425 u8 reserved_at_10[0x10]; 6426 6427 u8 reserved_at_20[0x10]; 6428 u8 op_mod[0x10]; 6429 6430 u8 reserved_at_40[0x8]; 6431 u8 qpn[0x18]; 6432 6433 u8 reserved_at_60[0x20]; 6434 6435 u8 multicast_gid[16][0x8]; 6436 }; 6437 6438 struct mlx5_ifc_arm_xrq_out_bits { 6439 u8 status[0x8]; 6440 u8 reserved_at_8[0x18]; 6441 6442 u8 syndrome[0x20]; 6443 6444 u8 reserved_at_40[0x40]; 6445 }; 6446 6447 struct mlx5_ifc_arm_xrq_in_bits { 6448 u8 opcode[0x10]; 6449 u8 reserved_at_10[0x10]; 6450 6451 u8 reserved_at_20[0x10]; 6452 u8 op_mod[0x10]; 6453 6454 u8 reserved_at_40[0x8]; 6455 u8 xrqn[0x18]; 6456 6457 u8 reserved_at_60[0x10]; 6458 u8 lwm[0x10]; 6459 }; 6460 6461 struct mlx5_ifc_arm_xrc_srq_out_bits { 6462 u8 status[0x8]; 6463 u8 reserved_at_8[0x18]; 6464 6465 u8 syndrome[0x20]; 6466 6467 u8 reserved_at_40[0x40]; 6468 }; 6469 6470 enum { 6471 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 6472 }; 6473 6474 struct mlx5_ifc_arm_xrc_srq_in_bits { 6475 u8 opcode[0x10]; 6476 u8 reserved_at_10[0x10]; 6477 6478 u8 reserved_at_20[0x10]; 6479 u8 op_mod[0x10]; 6480 6481 u8 reserved_at_40[0x8]; 6482 u8 xrc_srqn[0x18]; 6483 6484 u8 reserved_at_60[0x10]; 6485 u8 lwm[0x10]; 6486 }; 6487 6488 struct mlx5_ifc_arm_rq_out_bits { 6489 u8 status[0x8]; 6490 u8 reserved_at_8[0x18]; 6491 6492 u8 syndrome[0x20]; 6493 6494 u8 reserved_at_40[0x40]; 6495 }; 6496 6497 enum { 6498 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 6499 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 6500 }; 6501 6502 struct mlx5_ifc_arm_rq_in_bits { 6503 u8 opcode[0x10]; 6504 u8 reserved_at_10[0x10]; 6505 6506 u8 reserved_at_20[0x10]; 6507 u8 op_mod[0x10]; 6508 6509 u8 reserved_at_40[0x8]; 6510 u8 srq_number[0x18]; 6511 6512 u8 reserved_at_60[0x10]; 6513 u8 lwm[0x10]; 6514 }; 6515 6516 struct mlx5_ifc_arm_dct_out_bits { 6517 u8 status[0x8]; 6518 u8 reserved_at_8[0x18]; 6519 6520 u8 syndrome[0x20]; 6521 6522 u8 reserved_at_40[0x40]; 6523 }; 6524 6525 struct mlx5_ifc_arm_dct_in_bits { 6526 u8 opcode[0x10]; 6527 u8 reserved_at_10[0x10]; 6528 6529 u8 reserved_at_20[0x10]; 6530 u8 op_mod[0x10]; 6531 6532 u8 reserved_at_40[0x8]; 6533 u8 dct_number[0x18]; 6534 6535 u8 reserved_at_60[0x20]; 6536 }; 6537 6538 struct mlx5_ifc_alloc_xrcd_out_bits { 6539 u8 status[0x8]; 6540 u8 reserved_at_8[0x18]; 6541 6542 u8 syndrome[0x20]; 6543 6544 u8 reserved_at_40[0x8]; 6545 u8 xrcd[0x18]; 6546 6547 u8 reserved_at_60[0x20]; 6548 }; 6549 6550 struct mlx5_ifc_alloc_xrcd_in_bits { 6551 u8 opcode[0x10]; 6552 u8 reserved_at_10[0x10]; 6553 6554 u8 reserved_at_20[0x10]; 6555 u8 op_mod[0x10]; 6556 6557 u8 reserved_at_40[0x40]; 6558 }; 6559 6560 struct mlx5_ifc_alloc_uar_out_bits { 6561 u8 status[0x8]; 6562 u8 reserved_at_8[0x18]; 6563 6564 u8 syndrome[0x20]; 6565 6566 u8 reserved_at_40[0x8]; 6567 u8 uar[0x18]; 6568 6569 u8 reserved_at_60[0x20]; 6570 }; 6571 6572 struct mlx5_ifc_alloc_uar_in_bits { 6573 u8 opcode[0x10]; 6574 u8 reserved_at_10[0x10]; 6575 6576 u8 reserved_at_20[0x10]; 6577 u8 op_mod[0x10]; 6578 6579 u8 reserved_at_40[0x40]; 6580 }; 6581 6582 struct mlx5_ifc_alloc_transport_domain_out_bits { 6583 u8 status[0x8]; 6584 u8 reserved_at_8[0x18]; 6585 6586 u8 syndrome[0x20]; 6587 6588 u8 reserved_at_40[0x8]; 6589 u8 transport_domain[0x18]; 6590 6591 u8 reserved_at_60[0x20]; 6592 }; 6593 6594 struct mlx5_ifc_alloc_transport_domain_in_bits { 6595 u8 opcode[0x10]; 6596 u8 reserved_at_10[0x10]; 6597 6598 u8 reserved_at_20[0x10]; 6599 u8 op_mod[0x10]; 6600 6601 u8 reserved_at_40[0x40]; 6602 }; 6603 6604 struct mlx5_ifc_alloc_q_counter_out_bits { 6605 u8 status[0x8]; 6606 u8 reserved_at_8[0x18]; 6607 6608 u8 syndrome[0x20]; 6609 6610 u8 reserved_at_40[0x18]; 6611 u8 counter_set_id[0x8]; 6612 6613 u8 reserved_at_60[0x20]; 6614 }; 6615 6616 struct mlx5_ifc_alloc_q_counter_in_bits { 6617 u8 opcode[0x10]; 6618 u8 reserved_at_10[0x10]; 6619 6620 u8 reserved_at_20[0x10]; 6621 u8 op_mod[0x10]; 6622 6623 u8 reserved_at_40[0x40]; 6624 }; 6625 6626 struct mlx5_ifc_alloc_pd_out_bits { 6627 u8 status[0x8]; 6628 u8 reserved_at_8[0x18]; 6629 6630 u8 syndrome[0x20]; 6631 6632 u8 reserved_at_40[0x8]; 6633 u8 pd[0x18]; 6634 6635 u8 reserved_at_60[0x20]; 6636 }; 6637 6638 struct mlx5_ifc_alloc_pd_in_bits { 6639 u8 opcode[0x10]; 6640 u8 reserved_at_10[0x10]; 6641 6642 u8 reserved_at_20[0x10]; 6643 u8 op_mod[0x10]; 6644 6645 u8 reserved_at_40[0x40]; 6646 }; 6647 6648 struct mlx5_ifc_alloc_flow_counter_out_bits { 6649 u8 status[0x8]; 6650 u8 reserved_at_8[0x18]; 6651 6652 u8 syndrome[0x20]; 6653 6654 u8 reserved_at_40[0x10]; 6655 u8 flow_counter_id[0x10]; 6656 6657 u8 reserved_at_60[0x20]; 6658 }; 6659 6660 struct mlx5_ifc_alloc_flow_counter_in_bits { 6661 u8 opcode[0x10]; 6662 u8 reserved_at_10[0x10]; 6663 6664 u8 reserved_at_20[0x10]; 6665 u8 op_mod[0x10]; 6666 6667 u8 reserved_at_40[0x40]; 6668 }; 6669 6670 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 6671 u8 status[0x8]; 6672 u8 reserved_at_8[0x18]; 6673 6674 u8 syndrome[0x20]; 6675 6676 u8 reserved_at_40[0x40]; 6677 }; 6678 6679 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 6680 u8 opcode[0x10]; 6681 u8 reserved_at_10[0x10]; 6682 6683 u8 reserved_at_20[0x10]; 6684 u8 op_mod[0x10]; 6685 6686 u8 reserved_at_40[0x20]; 6687 6688 u8 reserved_at_60[0x10]; 6689 u8 vxlan_udp_port[0x10]; 6690 }; 6691 6692 struct mlx5_ifc_set_rate_limit_out_bits { 6693 u8 status[0x8]; 6694 u8 reserved_at_8[0x18]; 6695 6696 u8 syndrome[0x20]; 6697 6698 u8 reserved_at_40[0x40]; 6699 }; 6700 6701 struct mlx5_ifc_set_rate_limit_in_bits { 6702 u8 opcode[0x10]; 6703 u8 reserved_at_10[0x10]; 6704 6705 u8 reserved_at_20[0x10]; 6706 u8 op_mod[0x10]; 6707 6708 u8 reserved_at_40[0x10]; 6709 u8 rate_limit_index[0x10]; 6710 6711 u8 reserved_at_60[0x20]; 6712 6713 u8 rate_limit[0x20]; 6714 }; 6715 6716 struct mlx5_ifc_access_register_out_bits { 6717 u8 status[0x8]; 6718 u8 reserved_at_8[0x18]; 6719 6720 u8 syndrome[0x20]; 6721 6722 u8 reserved_at_40[0x40]; 6723 6724 u8 register_data[0][0x20]; 6725 }; 6726 6727 enum { 6728 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 6729 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 6730 }; 6731 6732 struct mlx5_ifc_access_register_in_bits { 6733 u8 opcode[0x10]; 6734 u8 reserved_at_10[0x10]; 6735 6736 u8 reserved_at_20[0x10]; 6737 u8 op_mod[0x10]; 6738 6739 u8 reserved_at_40[0x10]; 6740 u8 register_id[0x10]; 6741 6742 u8 argument[0x20]; 6743 6744 u8 register_data[0][0x20]; 6745 }; 6746 6747 struct mlx5_ifc_sltp_reg_bits { 6748 u8 status[0x4]; 6749 u8 version[0x4]; 6750 u8 local_port[0x8]; 6751 u8 pnat[0x2]; 6752 u8 reserved_at_12[0x2]; 6753 u8 lane[0x4]; 6754 u8 reserved_at_18[0x8]; 6755 6756 u8 reserved_at_20[0x20]; 6757 6758 u8 reserved_at_40[0x7]; 6759 u8 polarity[0x1]; 6760 u8 ob_tap0[0x8]; 6761 u8 ob_tap1[0x8]; 6762 u8 ob_tap2[0x8]; 6763 6764 u8 reserved_at_60[0xc]; 6765 u8 ob_preemp_mode[0x4]; 6766 u8 ob_reg[0x8]; 6767 u8 ob_bias[0x8]; 6768 6769 u8 reserved_at_80[0x20]; 6770 }; 6771 6772 struct mlx5_ifc_slrg_reg_bits { 6773 u8 status[0x4]; 6774 u8 version[0x4]; 6775 u8 local_port[0x8]; 6776 u8 pnat[0x2]; 6777 u8 reserved_at_12[0x2]; 6778 u8 lane[0x4]; 6779 u8 reserved_at_18[0x8]; 6780 6781 u8 time_to_link_up[0x10]; 6782 u8 reserved_at_30[0xc]; 6783 u8 grade_lane_speed[0x4]; 6784 6785 u8 grade_version[0x8]; 6786 u8 grade[0x18]; 6787 6788 u8 reserved_at_60[0x4]; 6789 u8 height_grade_type[0x4]; 6790 u8 height_grade[0x18]; 6791 6792 u8 height_dz[0x10]; 6793 u8 height_dv[0x10]; 6794 6795 u8 reserved_at_a0[0x10]; 6796 u8 height_sigma[0x10]; 6797 6798 u8 reserved_at_c0[0x20]; 6799 6800 u8 reserved_at_e0[0x4]; 6801 u8 phase_grade_type[0x4]; 6802 u8 phase_grade[0x18]; 6803 6804 u8 reserved_at_100[0x8]; 6805 u8 phase_eo_pos[0x8]; 6806 u8 reserved_at_110[0x8]; 6807 u8 phase_eo_neg[0x8]; 6808 6809 u8 ffe_set_tested[0x10]; 6810 u8 test_errors_per_lane[0x10]; 6811 }; 6812 6813 struct mlx5_ifc_pvlc_reg_bits { 6814 u8 reserved_at_0[0x8]; 6815 u8 local_port[0x8]; 6816 u8 reserved_at_10[0x10]; 6817 6818 u8 reserved_at_20[0x1c]; 6819 u8 vl_hw_cap[0x4]; 6820 6821 u8 reserved_at_40[0x1c]; 6822 u8 vl_admin[0x4]; 6823 6824 u8 reserved_at_60[0x1c]; 6825 u8 vl_operational[0x4]; 6826 }; 6827 6828 struct mlx5_ifc_pude_reg_bits { 6829 u8 swid[0x8]; 6830 u8 local_port[0x8]; 6831 u8 reserved_at_10[0x4]; 6832 u8 admin_status[0x4]; 6833 u8 reserved_at_18[0x4]; 6834 u8 oper_status[0x4]; 6835 6836 u8 reserved_at_20[0x60]; 6837 }; 6838 6839 struct mlx5_ifc_ptys_reg_bits { 6840 u8 reserved_at_0[0x1]; 6841 u8 an_disable_admin[0x1]; 6842 u8 an_disable_cap[0x1]; 6843 u8 reserved_at_3[0x5]; 6844 u8 local_port[0x8]; 6845 u8 reserved_at_10[0xd]; 6846 u8 proto_mask[0x3]; 6847 6848 u8 an_status[0x4]; 6849 u8 reserved_at_24[0x3c]; 6850 6851 u8 eth_proto_capability[0x20]; 6852 6853 u8 ib_link_width_capability[0x10]; 6854 u8 ib_proto_capability[0x10]; 6855 6856 u8 reserved_at_a0[0x20]; 6857 6858 u8 eth_proto_admin[0x20]; 6859 6860 u8 ib_link_width_admin[0x10]; 6861 u8 ib_proto_admin[0x10]; 6862 6863 u8 reserved_at_100[0x20]; 6864 6865 u8 eth_proto_oper[0x20]; 6866 6867 u8 ib_link_width_oper[0x10]; 6868 u8 ib_proto_oper[0x10]; 6869 6870 u8 reserved_at_160[0x20]; 6871 6872 u8 eth_proto_lp_advertise[0x20]; 6873 6874 u8 reserved_at_1a0[0x60]; 6875 }; 6876 6877 struct mlx5_ifc_mlcr_reg_bits { 6878 u8 reserved_at_0[0x8]; 6879 u8 local_port[0x8]; 6880 u8 reserved_at_10[0x20]; 6881 6882 u8 beacon_duration[0x10]; 6883 u8 reserved_at_40[0x10]; 6884 6885 u8 beacon_remain[0x10]; 6886 }; 6887 6888 struct mlx5_ifc_ptas_reg_bits { 6889 u8 reserved_at_0[0x20]; 6890 6891 u8 algorithm_options[0x10]; 6892 u8 reserved_at_30[0x4]; 6893 u8 repetitions_mode[0x4]; 6894 u8 num_of_repetitions[0x8]; 6895 6896 u8 grade_version[0x8]; 6897 u8 height_grade_type[0x4]; 6898 u8 phase_grade_type[0x4]; 6899 u8 height_grade_weight[0x8]; 6900 u8 phase_grade_weight[0x8]; 6901 6902 u8 gisim_measure_bits[0x10]; 6903 u8 adaptive_tap_measure_bits[0x10]; 6904 6905 u8 ber_bath_high_error_threshold[0x10]; 6906 u8 ber_bath_mid_error_threshold[0x10]; 6907 6908 u8 ber_bath_low_error_threshold[0x10]; 6909 u8 one_ratio_high_threshold[0x10]; 6910 6911 u8 one_ratio_high_mid_threshold[0x10]; 6912 u8 one_ratio_low_mid_threshold[0x10]; 6913 6914 u8 one_ratio_low_threshold[0x10]; 6915 u8 ndeo_error_threshold[0x10]; 6916 6917 u8 mixer_offset_step_size[0x10]; 6918 u8 reserved_at_110[0x8]; 6919 u8 mix90_phase_for_voltage_bath[0x8]; 6920 6921 u8 mixer_offset_start[0x10]; 6922 u8 mixer_offset_end[0x10]; 6923 6924 u8 reserved_at_140[0x15]; 6925 u8 ber_test_time[0xb]; 6926 }; 6927 6928 struct mlx5_ifc_pspa_reg_bits { 6929 u8 swid[0x8]; 6930 u8 local_port[0x8]; 6931 u8 sub_port[0x8]; 6932 u8 reserved_at_18[0x8]; 6933 6934 u8 reserved_at_20[0x20]; 6935 }; 6936 6937 struct mlx5_ifc_pqdr_reg_bits { 6938 u8 reserved_at_0[0x8]; 6939 u8 local_port[0x8]; 6940 u8 reserved_at_10[0x5]; 6941 u8 prio[0x3]; 6942 u8 reserved_at_18[0x6]; 6943 u8 mode[0x2]; 6944 6945 u8 reserved_at_20[0x20]; 6946 6947 u8 reserved_at_40[0x10]; 6948 u8 min_threshold[0x10]; 6949 6950 u8 reserved_at_60[0x10]; 6951 u8 max_threshold[0x10]; 6952 6953 u8 reserved_at_80[0x10]; 6954 u8 mark_probability_denominator[0x10]; 6955 6956 u8 reserved_at_a0[0x60]; 6957 }; 6958 6959 struct mlx5_ifc_ppsc_reg_bits { 6960 u8 reserved_at_0[0x8]; 6961 u8 local_port[0x8]; 6962 u8 reserved_at_10[0x10]; 6963 6964 u8 reserved_at_20[0x60]; 6965 6966 u8 reserved_at_80[0x1c]; 6967 u8 wrps_admin[0x4]; 6968 6969 u8 reserved_at_a0[0x1c]; 6970 u8 wrps_status[0x4]; 6971 6972 u8 reserved_at_c0[0x8]; 6973 u8 up_threshold[0x8]; 6974 u8 reserved_at_d0[0x8]; 6975 u8 down_threshold[0x8]; 6976 6977 u8 reserved_at_e0[0x20]; 6978 6979 u8 reserved_at_100[0x1c]; 6980 u8 srps_admin[0x4]; 6981 6982 u8 reserved_at_120[0x1c]; 6983 u8 srps_status[0x4]; 6984 6985 u8 reserved_at_140[0x40]; 6986 }; 6987 6988 struct mlx5_ifc_pplr_reg_bits { 6989 u8 reserved_at_0[0x8]; 6990 u8 local_port[0x8]; 6991 u8 reserved_at_10[0x10]; 6992 6993 u8 reserved_at_20[0x8]; 6994 u8 lb_cap[0x8]; 6995 u8 reserved_at_30[0x8]; 6996 u8 lb_en[0x8]; 6997 }; 6998 6999 struct mlx5_ifc_pplm_reg_bits { 7000 u8 reserved_at_0[0x8]; 7001 u8 local_port[0x8]; 7002 u8 reserved_at_10[0x10]; 7003 7004 u8 reserved_at_20[0x20]; 7005 7006 u8 port_profile_mode[0x8]; 7007 u8 static_port_profile[0x8]; 7008 u8 active_port_profile[0x8]; 7009 u8 reserved_at_58[0x8]; 7010 7011 u8 retransmission_active[0x8]; 7012 u8 fec_mode_active[0x18]; 7013 7014 u8 reserved_at_80[0x20]; 7015 }; 7016 7017 struct mlx5_ifc_ppcnt_reg_bits { 7018 u8 swid[0x8]; 7019 u8 local_port[0x8]; 7020 u8 pnat[0x2]; 7021 u8 reserved_at_12[0x8]; 7022 u8 grp[0x6]; 7023 7024 u8 clr[0x1]; 7025 u8 reserved_at_21[0x1c]; 7026 u8 prio_tc[0x3]; 7027 7028 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7029 }; 7030 7031 struct mlx5_ifc_ppad_reg_bits { 7032 u8 reserved_at_0[0x3]; 7033 u8 single_mac[0x1]; 7034 u8 reserved_at_4[0x4]; 7035 u8 local_port[0x8]; 7036 u8 mac_47_32[0x10]; 7037 7038 u8 mac_31_0[0x20]; 7039 7040 u8 reserved_at_40[0x40]; 7041 }; 7042 7043 struct mlx5_ifc_pmtu_reg_bits { 7044 u8 reserved_at_0[0x8]; 7045 u8 local_port[0x8]; 7046 u8 reserved_at_10[0x10]; 7047 7048 u8 max_mtu[0x10]; 7049 u8 reserved_at_30[0x10]; 7050 7051 u8 admin_mtu[0x10]; 7052 u8 reserved_at_50[0x10]; 7053 7054 u8 oper_mtu[0x10]; 7055 u8 reserved_at_70[0x10]; 7056 }; 7057 7058 struct mlx5_ifc_pmpr_reg_bits { 7059 u8 reserved_at_0[0x8]; 7060 u8 module[0x8]; 7061 u8 reserved_at_10[0x10]; 7062 7063 u8 reserved_at_20[0x18]; 7064 u8 attenuation_5g[0x8]; 7065 7066 u8 reserved_at_40[0x18]; 7067 u8 attenuation_7g[0x8]; 7068 7069 u8 reserved_at_60[0x18]; 7070 u8 attenuation_12g[0x8]; 7071 }; 7072 7073 struct mlx5_ifc_pmpe_reg_bits { 7074 u8 reserved_at_0[0x8]; 7075 u8 module[0x8]; 7076 u8 reserved_at_10[0xc]; 7077 u8 module_status[0x4]; 7078 7079 u8 reserved_at_20[0x60]; 7080 }; 7081 7082 struct mlx5_ifc_pmpc_reg_bits { 7083 u8 module_state_updated[32][0x8]; 7084 }; 7085 7086 struct mlx5_ifc_pmlpn_reg_bits { 7087 u8 reserved_at_0[0x4]; 7088 u8 mlpn_status[0x4]; 7089 u8 local_port[0x8]; 7090 u8 reserved_at_10[0x10]; 7091 7092 u8 e[0x1]; 7093 u8 reserved_at_21[0x1f]; 7094 }; 7095 7096 struct mlx5_ifc_pmlp_reg_bits { 7097 u8 rxtx[0x1]; 7098 u8 reserved_at_1[0x7]; 7099 u8 local_port[0x8]; 7100 u8 reserved_at_10[0x8]; 7101 u8 width[0x8]; 7102 7103 u8 lane0_module_mapping[0x20]; 7104 7105 u8 lane1_module_mapping[0x20]; 7106 7107 u8 lane2_module_mapping[0x20]; 7108 7109 u8 lane3_module_mapping[0x20]; 7110 7111 u8 reserved_at_a0[0x160]; 7112 }; 7113 7114 struct mlx5_ifc_pmaos_reg_bits { 7115 u8 reserved_at_0[0x8]; 7116 u8 module[0x8]; 7117 u8 reserved_at_10[0x4]; 7118 u8 admin_status[0x4]; 7119 u8 reserved_at_18[0x4]; 7120 u8 oper_status[0x4]; 7121 7122 u8 ase[0x1]; 7123 u8 ee[0x1]; 7124 u8 reserved_at_22[0x1c]; 7125 u8 e[0x2]; 7126 7127 u8 reserved_at_40[0x40]; 7128 }; 7129 7130 struct mlx5_ifc_plpc_reg_bits { 7131 u8 reserved_at_0[0x4]; 7132 u8 profile_id[0xc]; 7133 u8 reserved_at_10[0x4]; 7134 u8 proto_mask[0x4]; 7135 u8 reserved_at_18[0x8]; 7136 7137 u8 reserved_at_20[0x10]; 7138 u8 lane_speed[0x10]; 7139 7140 u8 reserved_at_40[0x17]; 7141 u8 lpbf[0x1]; 7142 u8 fec_mode_policy[0x8]; 7143 7144 u8 retransmission_capability[0x8]; 7145 u8 fec_mode_capability[0x18]; 7146 7147 u8 retransmission_support_admin[0x8]; 7148 u8 fec_mode_support_admin[0x18]; 7149 7150 u8 retransmission_request_admin[0x8]; 7151 u8 fec_mode_request_admin[0x18]; 7152 7153 u8 reserved_at_c0[0x80]; 7154 }; 7155 7156 struct mlx5_ifc_plib_reg_bits { 7157 u8 reserved_at_0[0x8]; 7158 u8 local_port[0x8]; 7159 u8 reserved_at_10[0x8]; 7160 u8 ib_port[0x8]; 7161 7162 u8 reserved_at_20[0x60]; 7163 }; 7164 7165 struct mlx5_ifc_plbf_reg_bits { 7166 u8 reserved_at_0[0x8]; 7167 u8 local_port[0x8]; 7168 u8 reserved_at_10[0xd]; 7169 u8 lbf_mode[0x3]; 7170 7171 u8 reserved_at_20[0x20]; 7172 }; 7173 7174 struct mlx5_ifc_pipg_reg_bits { 7175 u8 reserved_at_0[0x8]; 7176 u8 local_port[0x8]; 7177 u8 reserved_at_10[0x10]; 7178 7179 u8 dic[0x1]; 7180 u8 reserved_at_21[0x19]; 7181 u8 ipg[0x4]; 7182 u8 reserved_at_3e[0x2]; 7183 }; 7184 7185 struct mlx5_ifc_pifr_reg_bits { 7186 u8 reserved_at_0[0x8]; 7187 u8 local_port[0x8]; 7188 u8 reserved_at_10[0x10]; 7189 7190 u8 reserved_at_20[0xe0]; 7191 7192 u8 port_filter[8][0x20]; 7193 7194 u8 port_filter_update_en[8][0x20]; 7195 }; 7196 7197 struct mlx5_ifc_pfcc_reg_bits { 7198 u8 reserved_at_0[0x8]; 7199 u8 local_port[0x8]; 7200 u8 reserved_at_10[0x10]; 7201 7202 u8 ppan[0x4]; 7203 u8 reserved_at_24[0x4]; 7204 u8 prio_mask_tx[0x8]; 7205 u8 reserved_at_30[0x8]; 7206 u8 prio_mask_rx[0x8]; 7207 7208 u8 pptx[0x1]; 7209 u8 aptx[0x1]; 7210 u8 reserved_at_42[0x6]; 7211 u8 pfctx[0x8]; 7212 u8 reserved_at_50[0x10]; 7213 7214 u8 pprx[0x1]; 7215 u8 aprx[0x1]; 7216 u8 reserved_at_62[0x6]; 7217 u8 pfcrx[0x8]; 7218 u8 reserved_at_70[0x10]; 7219 7220 u8 reserved_at_80[0x80]; 7221 }; 7222 7223 struct mlx5_ifc_pelc_reg_bits { 7224 u8 op[0x4]; 7225 u8 reserved_at_4[0x4]; 7226 u8 local_port[0x8]; 7227 u8 reserved_at_10[0x10]; 7228 7229 u8 op_admin[0x8]; 7230 u8 op_capability[0x8]; 7231 u8 op_request[0x8]; 7232 u8 op_active[0x8]; 7233 7234 u8 admin[0x40]; 7235 7236 u8 capability[0x40]; 7237 7238 u8 request[0x40]; 7239 7240 u8 active[0x40]; 7241 7242 u8 reserved_at_140[0x80]; 7243 }; 7244 7245 struct mlx5_ifc_peir_reg_bits { 7246 u8 reserved_at_0[0x8]; 7247 u8 local_port[0x8]; 7248 u8 reserved_at_10[0x10]; 7249 7250 u8 reserved_at_20[0xc]; 7251 u8 error_count[0x4]; 7252 u8 reserved_at_30[0x10]; 7253 7254 u8 reserved_at_40[0xc]; 7255 u8 lane[0x4]; 7256 u8 reserved_at_50[0x8]; 7257 u8 error_type[0x8]; 7258 }; 7259 7260 struct mlx5_ifc_pcap_reg_bits { 7261 u8 reserved_at_0[0x8]; 7262 u8 local_port[0x8]; 7263 u8 reserved_at_10[0x10]; 7264 7265 u8 port_capability_mask[4][0x20]; 7266 }; 7267 7268 struct mlx5_ifc_paos_reg_bits { 7269 u8 swid[0x8]; 7270 u8 local_port[0x8]; 7271 u8 reserved_at_10[0x4]; 7272 u8 admin_status[0x4]; 7273 u8 reserved_at_18[0x4]; 7274 u8 oper_status[0x4]; 7275 7276 u8 ase[0x1]; 7277 u8 ee[0x1]; 7278 u8 reserved_at_22[0x1c]; 7279 u8 e[0x2]; 7280 7281 u8 reserved_at_40[0x40]; 7282 }; 7283 7284 struct mlx5_ifc_pamp_reg_bits { 7285 u8 reserved_at_0[0x8]; 7286 u8 opamp_group[0x8]; 7287 u8 reserved_at_10[0xc]; 7288 u8 opamp_group_type[0x4]; 7289 7290 u8 start_index[0x10]; 7291 u8 reserved_at_30[0x4]; 7292 u8 num_of_indices[0xc]; 7293 7294 u8 index_data[18][0x10]; 7295 }; 7296 7297 struct mlx5_ifc_pcmr_reg_bits { 7298 u8 reserved_at_0[0x8]; 7299 u8 local_port[0x8]; 7300 u8 reserved_at_10[0x2e]; 7301 u8 fcs_cap[0x1]; 7302 u8 reserved_at_3f[0x1f]; 7303 u8 fcs_chk[0x1]; 7304 u8 reserved_at_5f[0x1]; 7305 }; 7306 7307 struct mlx5_ifc_lane_2_module_mapping_bits { 7308 u8 reserved_at_0[0x6]; 7309 u8 rx_lane[0x2]; 7310 u8 reserved_at_8[0x6]; 7311 u8 tx_lane[0x2]; 7312 u8 reserved_at_10[0x8]; 7313 u8 module[0x8]; 7314 }; 7315 7316 struct mlx5_ifc_bufferx_reg_bits { 7317 u8 reserved_at_0[0x6]; 7318 u8 lossy[0x1]; 7319 u8 epsb[0x1]; 7320 u8 reserved_at_8[0xc]; 7321 u8 size[0xc]; 7322 7323 u8 xoff_threshold[0x10]; 7324 u8 xon_threshold[0x10]; 7325 }; 7326 7327 struct mlx5_ifc_set_node_in_bits { 7328 u8 node_description[64][0x8]; 7329 }; 7330 7331 struct mlx5_ifc_register_power_settings_bits { 7332 u8 reserved_at_0[0x18]; 7333 u8 power_settings_level[0x8]; 7334 7335 u8 reserved_at_20[0x60]; 7336 }; 7337 7338 struct mlx5_ifc_register_host_endianness_bits { 7339 u8 he[0x1]; 7340 u8 reserved_at_1[0x1f]; 7341 7342 u8 reserved_at_20[0x60]; 7343 }; 7344 7345 struct mlx5_ifc_umr_pointer_desc_argument_bits { 7346 u8 reserved_at_0[0x20]; 7347 7348 u8 mkey[0x20]; 7349 7350 u8 addressh_63_32[0x20]; 7351 7352 u8 addressl_31_0[0x20]; 7353 }; 7354 7355 struct mlx5_ifc_ud_adrs_vector_bits { 7356 u8 dc_key[0x40]; 7357 7358 u8 ext[0x1]; 7359 u8 reserved_at_41[0x7]; 7360 u8 destination_qp_dct[0x18]; 7361 7362 u8 static_rate[0x4]; 7363 u8 sl_eth_prio[0x4]; 7364 u8 fl[0x1]; 7365 u8 mlid[0x7]; 7366 u8 rlid_udp_sport[0x10]; 7367 7368 u8 reserved_at_80[0x20]; 7369 7370 u8 rmac_47_16[0x20]; 7371 7372 u8 rmac_15_0[0x10]; 7373 u8 tclass[0x8]; 7374 u8 hop_limit[0x8]; 7375 7376 u8 reserved_at_e0[0x1]; 7377 u8 grh[0x1]; 7378 u8 reserved_at_e2[0x2]; 7379 u8 src_addr_index[0x8]; 7380 u8 flow_label[0x14]; 7381 7382 u8 rgid_rip[16][0x8]; 7383 }; 7384 7385 struct mlx5_ifc_pages_req_event_bits { 7386 u8 reserved_at_0[0x10]; 7387 u8 function_id[0x10]; 7388 7389 u8 num_pages[0x20]; 7390 7391 u8 reserved_at_40[0xa0]; 7392 }; 7393 7394 struct mlx5_ifc_eqe_bits { 7395 u8 reserved_at_0[0x8]; 7396 u8 event_type[0x8]; 7397 u8 reserved_at_10[0x8]; 7398 u8 event_sub_type[0x8]; 7399 7400 u8 reserved_at_20[0xe0]; 7401 7402 union mlx5_ifc_event_auto_bits event_data; 7403 7404 u8 reserved_at_1e0[0x10]; 7405 u8 signature[0x8]; 7406 u8 reserved_at_1f8[0x7]; 7407 u8 owner[0x1]; 7408 }; 7409 7410 enum { 7411 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 7412 }; 7413 7414 struct mlx5_ifc_cmd_queue_entry_bits { 7415 u8 type[0x8]; 7416 u8 reserved_at_8[0x18]; 7417 7418 u8 input_length[0x20]; 7419 7420 u8 input_mailbox_pointer_63_32[0x20]; 7421 7422 u8 input_mailbox_pointer_31_9[0x17]; 7423 u8 reserved_at_77[0x9]; 7424 7425 u8 command_input_inline_data[16][0x8]; 7426 7427 u8 command_output_inline_data[16][0x8]; 7428 7429 u8 output_mailbox_pointer_63_32[0x20]; 7430 7431 u8 output_mailbox_pointer_31_9[0x17]; 7432 u8 reserved_at_1b7[0x9]; 7433 7434 u8 output_length[0x20]; 7435 7436 u8 token[0x8]; 7437 u8 signature[0x8]; 7438 u8 reserved_at_1f0[0x8]; 7439 u8 status[0x7]; 7440 u8 ownership[0x1]; 7441 }; 7442 7443 struct mlx5_ifc_cmd_out_bits { 7444 u8 status[0x8]; 7445 u8 reserved_at_8[0x18]; 7446 7447 u8 syndrome[0x20]; 7448 7449 u8 command_output[0x20]; 7450 }; 7451 7452 struct mlx5_ifc_cmd_in_bits { 7453 u8 opcode[0x10]; 7454 u8 reserved_at_10[0x10]; 7455 7456 u8 reserved_at_20[0x10]; 7457 u8 op_mod[0x10]; 7458 7459 u8 command[0][0x20]; 7460 }; 7461 7462 struct mlx5_ifc_cmd_if_box_bits { 7463 u8 mailbox_data[512][0x8]; 7464 7465 u8 reserved_at_1000[0x180]; 7466 7467 u8 next_pointer_63_32[0x20]; 7468 7469 u8 next_pointer_31_10[0x16]; 7470 u8 reserved_at_11b6[0xa]; 7471 7472 u8 block_number[0x20]; 7473 7474 u8 reserved_at_11e0[0x8]; 7475 u8 token[0x8]; 7476 u8 ctrl_signature[0x8]; 7477 u8 signature[0x8]; 7478 }; 7479 7480 struct mlx5_ifc_mtt_bits { 7481 u8 ptag_63_32[0x20]; 7482 7483 u8 ptag_31_8[0x18]; 7484 u8 reserved_at_38[0x6]; 7485 u8 wr_en[0x1]; 7486 u8 rd_en[0x1]; 7487 }; 7488 7489 struct mlx5_ifc_query_wol_rol_out_bits { 7490 u8 status[0x8]; 7491 u8 reserved_at_8[0x18]; 7492 7493 u8 syndrome[0x20]; 7494 7495 u8 reserved_at_40[0x10]; 7496 u8 rol_mode[0x8]; 7497 u8 wol_mode[0x8]; 7498 7499 u8 reserved_at_60[0x20]; 7500 }; 7501 7502 struct mlx5_ifc_query_wol_rol_in_bits { 7503 u8 opcode[0x10]; 7504 u8 reserved_at_10[0x10]; 7505 7506 u8 reserved_at_20[0x10]; 7507 u8 op_mod[0x10]; 7508 7509 u8 reserved_at_40[0x40]; 7510 }; 7511 7512 struct mlx5_ifc_set_wol_rol_out_bits { 7513 u8 status[0x8]; 7514 u8 reserved_at_8[0x18]; 7515 7516 u8 syndrome[0x20]; 7517 7518 u8 reserved_at_40[0x40]; 7519 }; 7520 7521 struct mlx5_ifc_set_wol_rol_in_bits { 7522 u8 opcode[0x10]; 7523 u8 reserved_at_10[0x10]; 7524 7525 u8 reserved_at_20[0x10]; 7526 u8 op_mod[0x10]; 7527 7528 u8 rol_mode_valid[0x1]; 7529 u8 wol_mode_valid[0x1]; 7530 u8 reserved_at_42[0xe]; 7531 u8 rol_mode[0x8]; 7532 u8 wol_mode[0x8]; 7533 7534 u8 reserved_at_60[0x20]; 7535 }; 7536 7537 enum { 7538 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 7539 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 7540 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 7541 }; 7542 7543 enum { 7544 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 7545 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 7546 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 7547 }; 7548 7549 enum { 7550 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 7551 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 7552 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 7553 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 7554 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 7555 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 7556 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 7557 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 7558 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 7559 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 7560 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 7561 }; 7562 7563 struct mlx5_ifc_initial_seg_bits { 7564 u8 fw_rev_minor[0x10]; 7565 u8 fw_rev_major[0x10]; 7566 7567 u8 cmd_interface_rev[0x10]; 7568 u8 fw_rev_subminor[0x10]; 7569 7570 u8 reserved_at_40[0x40]; 7571 7572 u8 cmdq_phy_addr_63_32[0x20]; 7573 7574 u8 cmdq_phy_addr_31_12[0x14]; 7575 u8 reserved_at_b4[0x2]; 7576 u8 nic_interface[0x2]; 7577 u8 log_cmdq_size[0x4]; 7578 u8 log_cmdq_stride[0x4]; 7579 7580 u8 command_doorbell_vector[0x20]; 7581 7582 u8 reserved_at_e0[0xf00]; 7583 7584 u8 initializing[0x1]; 7585 u8 reserved_at_fe1[0x4]; 7586 u8 nic_interface_supported[0x3]; 7587 u8 reserved_at_fe8[0x18]; 7588 7589 struct mlx5_ifc_health_buffer_bits health_buffer; 7590 7591 u8 no_dram_nic_offset[0x20]; 7592 7593 u8 reserved_at_1220[0x6e40]; 7594 7595 u8 reserved_at_8060[0x1f]; 7596 u8 clear_int[0x1]; 7597 7598 u8 health_syndrome[0x8]; 7599 u8 health_counter[0x18]; 7600 7601 u8 reserved_at_80a0[0x17fc0]; 7602 }; 7603 7604 union mlx5_ifc_ports_control_registers_document_bits { 7605 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 7606 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 7607 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 7608 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 7609 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 7610 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 7611 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 7612 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 7613 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 7614 struct mlx5_ifc_pamp_reg_bits pamp_reg; 7615 struct mlx5_ifc_paos_reg_bits paos_reg; 7616 struct mlx5_ifc_pcap_reg_bits pcap_reg; 7617 struct mlx5_ifc_peir_reg_bits peir_reg; 7618 struct mlx5_ifc_pelc_reg_bits pelc_reg; 7619 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 7620 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 7621 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 7622 struct mlx5_ifc_pifr_reg_bits pifr_reg; 7623 struct mlx5_ifc_pipg_reg_bits pipg_reg; 7624 struct mlx5_ifc_plbf_reg_bits plbf_reg; 7625 struct mlx5_ifc_plib_reg_bits plib_reg; 7626 struct mlx5_ifc_plpc_reg_bits plpc_reg; 7627 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 7628 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 7629 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 7630 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 7631 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 7632 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 7633 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 7634 struct mlx5_ifc_ppad_reg_bits ppad_reg; 7635 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 7636 struct mlx5_ifc_pplm_reg_bits pplm_reg; 7637 struct mlx5_ifc_pplr_reg_bits pplr_reg; 7638 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 7639 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 7640 struct mlx5_ifc_pspa_reg_bits pspa_reg; 7641 struct mlx5_ifc_ptas_reg_bits ptas_reg; 7642 struct mlx5_ifc_ptys_reg_bits ptys_reg; 7643 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 7644 struct mlx5_ifc_pude_reg_bits pude_reg; 7645 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 7646 struct mlx5_ifc_slrg_reg_bits slrg_reg; 7647 struct mlx5_ifc_sltp_reg_bits sltp_reg; 7648 u8 reserved_at_0[0x60e0]; 7649 }; 7650 7651 union mlx5_ifc_debug_enhancements_document_bits { 7652 struct mlx5_ifc_health_buffer_bits health_buffer; 7653 u8 reserved_at_0[0x200]; 7654 }; 7655 7656 union mlx5_ifc_uplink_pci_interface_document_bits { 7657 struct mlx5_ifc_initial_seg_bits initial_seg; 7658 u8 reserved_at_0[0x20060]; 7659 }; 7660 7661 struct mlx5_ifc_set_flow_table_root_out_bits { 7662 u8 status[0x8]; 7663 u8 reserved_at_8[0x18]; 7664 7665 u8 syndrome[0x20]; 7666 7667 u8 reserved_at_40[0x40]; 7668 }; 7669 7670 struct mlx5_ifc_set_flow_table_root_in_bits { 7671 u8 opcode[0x10]; 7672 u8 reserved_at_10[0x10]; 7673 7674 u8 reserved_at_20[0x10]; 7675 u8 op_mod[0x10]; 7676 7677 u8 other_vport[0x1]; 7678 u8 reserved_at_41[0xf]; 7679 u8 vport_number[0x10]; 7680 7681 u8 reserved_at_60[0x20]; 7682 7683 u8 table_type[0x8]; 7684 u8 reserved_at_88[0x18]; 7685 7686 u8 reserved_at_a0[0x8]; 7687 u8 table_id[0x18]; 7688 7689 u8 reserved_at_c0[0x140]; 7690 }; 7691 7692 enum { 7693 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 7694 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 7695 }; 7696 7697 struct mlx5_ifc_modify_flow_table_out_bits { 7698 u8 status[0x8]; 7699 u8 reserved_at_8[0x18]; 7700 7701 u8 syndrome[0x20]; 7702 7703 u8 reserved_at_40[0x40]; 7704 }; 7705 7706 struct mlx5_ifc_modify_flow_table_in_bits { 7707 u8 opcode[0x10]; 7708 u8 reserved_at_10[0x10]; 7709 7710 u8 reserved_at_20[0x10]; 7711 u8 op_mod[0x10]; 7712 7713 u8 other_vport[0x1]; 7714 u8 reserved_at_41[0xf]; 7715 u8 vport_number[0x10]; 7716 7717 u8 reserved_at_60[0x10]; 7718 u8 modify_field_select[0x10]; 7719 7720 u8 table_type[0x8]; 7721 u8 reserved_at_88[0x18]; 7722 7723 u8 reserved_at_a0[0x8]; 7724 u8 table_id[0x18]; 7725 7726 u8 reserved_at_c0[0x4]; 7727 u8 table_miss_mode[0x4]; 7728 u8 reserved_at_c8[0x18]; 7729 7730 u8 reserved_at_e0[0x8]; 7731 u8 table_miss_id[0x18]; 7732 7733 u8 reserved_at_100[0x8]; 7734 u8 lag_master_next_table_id[0x18]; 7735 7736 u8 reserved_at_120[0x80]; 7737 }; 7738 7739 struct mlx5_ifc_ets_tcn_config_reg_bits { 7740 u8 g[0x1]; 7741 u8 b[0x1]; 7742 u8 r[0x1]; 7743 u8 reserved_at_3[0x9]; 7744 u8 group[0x4]; 7745 u8 reserved_at_10[0x9]; 7746 u8 bw_allocation[0x7]; 7747 7748 u8 reserved_at_20[0xc]; 7749 u8 max_bw_units[0x4]; 7750 u8 reserved_at_30[0x8]; 7751 u8 max_bw_value[0x8]; 7752 }; 7753 7754 struct mlx5_ifc_ets_global_config_reg_bits { 7755 u8 reserved_at_0[0x2]; 7756 u8 r[0x1]; 7757 u8 reserved_at_3[0x1d]; 7758 7759 u8 reserved_at_20[0xc]; 7760 u8 max_bw_units[0x4]; 7761 u8 reserved_at_30[0x8]; 7762 u8 max_bw_value[0x8]; 7763 }; 7764 7765 struct mlx5_ifc_qetc_reg_bits { 7766 u8 reserved_at_0[0x8]; 7767 u8 port_number[0x8]; 7768 u8 reserved_at_10[0x30]; 7769 7770 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 7771 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 7772 }; 7773 7774 struct mlx5_ifc_qtct_reg_bits { 7775 u8 reserved_at_0[0x8]; 7776 u8 port_number[0x8]; 7777 u8 reserved_at_10[0xd]; 7778 u8 prio[0x3]; 7779 7780 u8 reserved_at_20[0x1d]; 7781 u8 tclass[0x3]; 7782 }; 7783 7784 struct mlx5_ifc_mcia_reg_bits { 7785 u8 l[0x1]; 7786 u8 reserved_at_1[0x7]; 7787 u8 module[0x8]; 7788 u8 reserved_at_10[0x8]; 7789 u8 status[0x8]; 7790 7791 u8 i2c_device_address[0x8]; 7792 u8 page_number[0x8]; 7793 u8 device_address[0x10]; 7794 7795 u8 reserved_at_40[0x10]; 7796 u8 size[0x10]; 7797 7798 u8 reserved_at_60[0x20]; 7799 7800 u8 dword_0[0x20]; 7801 u8 dword_1[0x20]; 7802 u8 dword_2[0x20]; 7803 u8 dword_3[0x20]; 7804 u8 dword_4[0x20]; 7805 u8 dword_5[0x20]; 7806 u8 dword_6[0x20]; 7807 u8 dword_7[0x20]; 7808 u8 dword_8[0x20]; 7809 u8 dword_9[0x20]; 7810 u8 dword_10[0x20]; 7811 u8 dword_11[0x20]; 7812 }; 7813 7814 struct mlx5_ifc_dcbx_param_bits { 7815 u8 dcbx_cee_cap[0x1]; 7816 u8 dcbx_ieee_cap[0x1]; 7817 u8 dcbx_standby_cap[0x1]; 7818 u8 reserved_at_0[0x5]; 7819 u8 port_number[0x8]; 7820 u8 reserved_at_10[0xa]; 7821 u8 max_application_table_size[6]; 7822 u8 reserved_at_20[0x15]; 7823 u8 version_oper[0x3]; 7824 u8 reserved_at_38[5]; 7825 u8 version_admin[0x3]; 7826 u8 willing_admin[0x1]; 7827 u8 reserved_at_41[0x3]; 7828 u8 pfc_cap_oper[0x4]; 7829 u8 reserved_at_48[0x4]; 7830 u8 pfc_cap_admin[0x4]; 7831 u8 reserved_at_50[0x4]; 7832 u8 num_of_tc_oper[0x4]; 7833 u8 reserved_at_58[0x4]; 7834 u8 num_of_tc_admin[0x4]; 7835 u8 remote_willing[0x1]; 7836 u8 reserved_at_61[3]; 7837 u8 remote_pfc_cap[4]; 7838 u8 reserved_at_68[0x14]; 7839 u8 remote_num_of_tc[0x4]; 7840 u8 reserved_at_80[0x18]; 7841 u8 error[0x8]; 7842 u8 reserved_at_a0[0x160]; 7843 }; 7844 7845 struct mlx5_ifc_lagc_bits { 7846 u8 reserved_at_0[0x1d]; 7847 u8 lag_state[0x3]; 7848 7849 u8 reserved_at_20[0x14]; 7850 u8 tx_remap_affinity_2[0x4]; 7851 u8 reserved_at_38[0x4]; 7852 u8 tx_remap_affinity_1[0x4]; 7853 }; 7854 7855 struct mlx5_ifc_create_lag_out_bits { 7856 u8 status[0x8]; 7857 u8 reserved_at_8[0x18]; 7858 7859 u8 syndrome[0x20]; 7860 7861 u8 reserved_at_40[0x40]; 7862 }; 7863 7864 struct mlx5_ifc_create_lag_in_bits { 7865 u8 opcode[0x10]; 7866 u8 reserved_at_10[0x10]; 7867 7868 u8 reserved_at_20[0x10]; 7869 u8 op_mod[0x10]; 7870 7871 struct mlx5_ifc_lagc_bits ctx; 7872 }; 7873 7874 struct mlx5_ifc_modify_lag_out_bits { 7875 u8 status[0x8]; 7876 u8 reserved_at_8[0x18]; 7877 7878 u8 syndrome[0x20]; 7879 7880 u8 reserved_at_40[0x40]; 7881 }; 7882 7883 struct mlx5_ifc_modify_lag_in_bits { 7884 u8 opcode[0x10]; 7885 u8 reserved_at_10[0x10]; 7886 7887 u8 reserved_at_20[0x10]; 7888 u8 op_mod[0x10]; 7889 7890 u8 reserved_at_40[0x20]; 7891 u8 field_select[0x20]; 7892 7893 struct mlx5_ifc_lagc_bits ctx; 7894 }; 7895 7896 struct mlx5_ifc_query_lag_out_bits { 7897 u8 status[0x8]; 7898 u8 reserved_at_8[0x18]; 7899 7900 u8 syndrome[0x20]; 7901 7902 u8 reserved_at_40[0x40]; 7903 7904 struct mlx5_ifc_lagc_bits ctx; 7905 }; 7906 7907 struct mlx5_ifc_query_lag_in_bits { 7908 u8 opcode[0x10]; 7909 u8 reserved_at_10[0x10]; 7910 7911 u8 reserved_at_20[0x10]; 7912 u8 op_mod[0x10]; 7913 7914 u8 reserved_at_40[0x40]; 7915 }; 7916 7917 struct mlx5_ifc_destroy_lag_out_bits { 7918 u8 status[0x8]; 7919 u8 reserved_at_8[0x18]; 7920 7921 u8 syndrome[0x20]; 7922 7923 u8 reserved_at_40[0x40]; 7924 }; 7925 7926 struct mlx5_ifc_destroy_lag_in_bits { 7927 u8 opcode[0x10]; 7928 u8 reserved_at_10[0x10]; 7929 7930 u8 reserved_at_20[0x10]; 7931 u8 op_mod[0x10]; 7932 7933 u8 reserved_at_40[0x40]; 7934 }; 7935 7936 struct mlx5_ifc_create_vport_lag_out_bits { 7937 u8 status[0x8]; 7938 u8 reserved_at_8[0x18]; 7939 7940 u8 syndrome[0x20]; 7941 7942 u8 reserved_at_40[0x40]; 7943 }; 7944 7945 struct mlx5_ifc_create_vport_lag_in_bits { 7946 u8 opcode[0x10]; 7947 u8 reserved_at_10[0x10]; 7948 7949 u8 reserved_at_20[0x10]; 7950 u8 op_mod[0x10]; 7951 7952 u8 reserved_at_40[0x40]; 7953 }; 7954 7955 struct mlx5_ifc_destroy_vport_lag_out_bits { 7956 u8 status[0x8]; 7957 u8 reserved_at_8[0x18]; 7958 7959 u8 syndrome[0x20]; 7960 7961 u8 reserved_at_40[0x40]; 7962 }; 7963 7964 struct mlx5_ifc_destroy_vport_lag_in_bits { 7965 u8 opcode[0x10]; 7966 u8 reserved_at_10[0x10]; 7967 7968 u8 reserved_at_20[0x10]; 7969 u8 op_mod[0x10]; 7970 7971 u8 reserved_at_40[0x40]; 7972 }; 7973 7974 #endif /* MLX5_IFC_H */ 7975